]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blob - drivers/gpio/gpio-vf610.c
gpio: vf610: Simplify vf610_gpio_set()
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpio / gpio-vf610.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Freescale vf610 GPIO support through PORT and GPIO
4 *
5 * Copyright (c) 2014 Toradex AG.
6 *
7 * Author: Stefan Agner <stefan@agner.ch>.
8 */
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/err.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/platform_device.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
22
23 #define VF610_GPIO_PER_PORT 32
24
25 struct fsl_gpio_soc_data {
26 /* SoCs has a Port Data Direction Register (PDDR) */
27 bool have_paddr;
28 };
29
30 struct vf610_gpio_port {
31 struct gpio_chip gc;
32 struct irq_chip ic;
33 void __iomem *base;
34 void __iomem *gpio_base;
35 const struct fsl_gpio_soc_data *sdata;
36 u8 irqc[VF610_GPIO_PER_PORT];
37 struct clk *clk_port;
38 struct clk *clk_gpio;
39 int irq;
40 };
41
42 #define GPIO_PDOR 0x00
43 #define GPIO_PSOR 0x04
44 #define GPIO_PCOR 0x08
45 #define GPIO_PTOR 0x0c
46 #define GPIO_PDIR 0x10
47 #define GPIO_PDDR 0x14
48
49 #define PORT_PCR(n) ((n) * 0x4)
50 #define PORT_PCR_IRQC_OFFSET 16
51
52 #define PORT_ISFR 0xa0
53 #define PORT_DFER 0xc0
54 #define PORT_DFCR 0xc4
55 #define PORT_DFWR 0xc8
56
57 #define PORT_INT_OFF 0x0
58 #define PORT_INT_LOGIC_ZERO 0x8
59 #define PORT_INT_RISING_EDGE 0x9
60 #define PORT_INT_FALLING_EDGE 0xa
61 #define PORT_INT_EITHER_EDGE 0xb
62 #define PORT_INT_LOGIC_ONE 0xc
63
64 static const struct fsl_gpio_soc_data imx_data = {
65 .have_paddr = true,
66 };
67
68 static const struct of_device_id vf610_gpio_dt_ids[] = {
69 { .compatible = "fsl,vf610-gpio", .data = NULL, },
70 { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, },
71 { /* sentinel */ }
72 };
73
74 static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
75 {
76 writel_relaxed(val, reg);
77 }
78
79 static inline u32 vf610_gpio_readl(void __iomem *reg)
80 {
81 return readl_relaxed(reg);
82 }
83
84 static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
85 {
86 struct vf610_gpio_port *port = gpiochip_get_data(gc);
87 unsigned long mask = BIT(gpio);
88 void __iomem *addr;
89
90 if (port->sdata && port->sdata->have_paddr) {
91 mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
92 addr = mask ? port->gpio_base + GPIO_PDOR :
93 port->gpio_base + GPIO_PDIR;
94 return !!(vf610_gpio_readl(addr) & BIT(gpio));
95 } else {
96 return !!(vf610_gpio_readl(port->gpio_base + GPIO_PDIR)
97 & BIT(gpio));
98 }
99 }
100
101 static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
102 {
103 struct vf610_gpio_port *port = gpiochip_get_data(gc);
104 unsigned long mask = BIT(gpio);
105 unsigned long offset = val ? GPIO_PSOR : GPIO_PCOR;
106
107 vf610_gpio_writel(mask, port->gpio_base + offset);
108 }
109
110 static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
111 {
112 struct vf610_gpio_port *port = gpiochip_get_data(chip);
113 unsigned long mask = BIT(gpio);
114 u32 val;
115
116 if (port->sdata && port->sdata->have_paddr) {
117 val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
118 val &= ~mask;
119 vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
120 }
121
122 return pinctrl_gpio_direction_input(chip->base + gpio);
123 }
124
125 static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
126 int value)
127 {
128 struct vf610_gpio_port *port = gpiochip_get_data(chip);
129 unsigned long mask = BIT(gpio);
130
131 if (port->sdata && port->sdata->have_paddr)
132 vf610_gpio_writel(mask, port->gpio_base + GPIO_PDDR);
133
134 vf610_gpio_set(chip, gpio, value);
135
136 return pinctrl_gpio_direction_output(chip->base + gpio);
137 }
138
139 static void vf610_gpio_irq_handler(struct irq_desc *desc)
140 {
141 struct vf610_gpio_port *port =
142 gpiochip_get_data(irq_desc_get_handler_data(desc));
143 struct irq_chip *chip = irq_desc_get_chip(desc);
144 int pin;
145 unsigned long irq_isfr;
146
147 chained_irq_enter(chip, desc);
148
149 irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);
150
151 for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
152 vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
153
154 generic_handle_irq(irq_find_mapping(port->gc.irq.domain, pin));
155 }
156
157 chained_irq_exit(chip, desc);
158 }
159
160 static void vf610_gpio_irq_ack(struct irq_data *d)
161 {
162 struct vf610_gpio_port *port =
163 gpiochip_get_data(irq_data_get_irq_chip_data(d));
164 int gpio = d->hwirq;
165
166 vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
167 }
168
169 static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
170 {
171 struct vf610_gpio_port *port =
172 gpiochip_get_data(irq_data_get_irq_chip_data(d));
173 u8 irqc;
174
175 switch (type) {
176 case IRQ_TYPE_EDGE_RISING:
177 irqc = PORT_INT_RISING_EDGE;
178 break;
179 case IRQ_TYPE_EDGE_FALLING:
180 irqc = PORT_INT_FALLING_EDGE;
181 break;
182 case IRQ_TYPE_EDGE_BOTH:
183 irqc = PORT_INT_EITHER_EDGE;
184 break;
185 case IRQ_TYPE_LEVEL_LOW:
186 irqc = PORT_INT_LOGIC_ZERO;
187 break;
188 case IRQ_TYPE_LEVEL_HIGH:
189 irqc = PORT_INT_LOGIC_ONE;
190 break;
191 default:
192 return -EINVAL;
193 }
194
195 port->irqc[d->hwirq] = irqc;
196
197 if (type & IRQ_TYPE_LEVEL_MASK)
198 irq_set_handler_locked(d, handle_level_irq);
199 else
200 irq_set_handler_locked(d, handle_edge_irq);
201
202 return 0;
203 }
204
205 static void vf610_gpio_irq_mask(struct irq_data *d)
206 {
207 struct vf610_gpio_port *port =
208 gpiochip_get_data(irq_data_get_irq_chip_data(d));
209 void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);
210
211 vf610_gpio_writel(0, pcr_base);
212 }
213
214 static void vf610_gpio_irq_unmask(struct irq_data *d)
215 {
216 struct vf610_gpio_port *port =
217 gpiochip_get_data(irq_data_get_irq_chip_data(d));
218 void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);
219
220 vf610_gpio_writel(port->irqc[d->hwirq] << PORT_PCR_IRQC_OFFSET,
221 pcr_base);
222 }
223
224 static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
225 {
226 struct vf610_gpio_port *port =
227 gpiochip_get_data(irq_data_get_irq_chip_data(d));
228
229 if (enable)
230 enable_irq_wake(port->irq);
231 else
232 disable_irq_wake(port->irq);
233
234 return 0;
235 }
236
237 static int vf610_gpio_probe(struct platform_device *pdev)
238 {
239 struct device *dev = &pdev->dev;
240 struct device_node *np = dev->of_node;
241 struct vf610_gpio_port *port;
242 struct resource *iores;
243 struct gpio_chip *gc;
244 struct irq_chip *ic;
245 int i;
246 int ret;
247
248 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
249 if (!port)
250 return -ENOMEM;
251
252 port->sdata = of_device_get_match_data(dev);
253 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
254 port->base = devm_ioremap_resource(dev, iores);
255 if (IS_ERR(port->base))
256 return PTR_ERR(port->base);
257
258 iores = platform_get_resource(pdev, IORESOURCE_MEM, 1);
259 port->gpio_base = devm_ioremap_resource(dev, iores);
260 if (IS_ERR(port->gpio_base))
261 return PTR_ERR(port->gpio_base);
262
263 port->irq = platform_get_irq(pdev, 0);
264 if (port->irq < 0)
265 return port->irq;
266
267 port->clk_port = devm_clk_get(&pdev->dev, "port");
268 if (!IS_ERR(port->clk_port)) {
269 ret = clk_prepare_enable(port->clk_port);
270 if (ret)
271 return ret;
272 } else if (port->clk_port == ERR_PTR(-EPROBE_DEFER)) {
273 /*
274 * Percolate deferrals, for anything else,
275 * just live without the clocking.
276 */
277 return PTR_ERR(port->clk_port);
278 }
279
280 port->clk_gpio = devm_clk_get(&pdev->dev, "gpio");
281 if (!IS_ERR(port->clk_gpio)) {
282 ret = clk_prepare_enable(port->clk_gpio);
283 if (ret) {
284 clk_disable_unprepare(port->clk_port);
285 return ret;
286 }
287 } else if (port->clk_gpio == ERR_PTR(-EPROBE_DEFER)) {
288 clk_disable_unprepare(port->clk_port);
289 return PTR_ERR(port->clk_gpio);
290 }
291
292 platform_set_drvdata(pdev, port);
293
294 gc = &port->gc;
295 gc->of_node = np;
296 gc->parent = dev;
297 gc->label = "vf610-gpio";
298 gc->ngpio = VF610_GPIO_PER_PORT;
299 gc->base = of_alias_get_id(np, "gpio") * VF610_GPIO_PER_PORT;
300
301 gc->request = gpiochip_generic_request;
302 gc->free = gpiochip_generic_free;
303 gc->direction_input = vf610_gpio_direction_input;
304 gc->get = vf610_gpio_get;
305 gc->direction_output = vf610_gpio_direction_output;
306 gc->set = vf610_gpio_set;
307
308 ic = &port->ic;
309 ic->name = "gpio-vf610";
310 ic->irq_ack = vf610_gpio_irq_ack;
311 ic->irq_mask = vf610_gpio_irq_mask;
312 ic->irq_unmask = vf610_gpio_irq_unmask;
313 ic->irq_set_type = vf610_gpio_irq_set_type;
314 ic->irq_set_wake = vf610_gpio_irq_set_wake;
315
316 ret = gpiochip_add_data(gc, port);
317 if (ret < 0)
318 return ret;
319
320 /* Mask all GPIO interrupts */
321 for (i = 0; i < gc->ngpio; i++)
322 vf610_gpio_writel(0, port->base + PORT_PCR(i));
323
324 /* Clear the interrupt status register for all GPIO's */
325 vf610_gpio_writel(~0, port->base + PORT_ISFR);
326
327 ret = gpiochip_irqchip_add(gc, ic, 0, handle_edge_irq, IRQ_TYPE_NONE);
328 if (ret) {
329 dev_err(dev, "failed to add irqchip\n");
330 gpiochip_remove(gc);
331 return ret;
332 }
333 gpiochip_set_chained_irqchip(gc, ic, port->irq,
334 vf610_gpio_irq_handler);
335
336 return 0;
337 }
338
339 static int vf610_gpio_remove(struct platform_device *pdev)
340 {
341 struct vf610_gpio_port *port = platform_get_drvdata(pdev);
342
343 gpiochip_remove(&port->gc);
344 if (!IS_ERR(port->clk_port))
345 clk_disable_unprepare(port->clk_port);
346 if (!IS_ERR(port->clk_gpio))
347 clk_disable_unprepare(port->clk_gpio);
348
349 return 0;
350 }
351
352 static struct platform_driver vf610_gpio_driver = {
353 .driver = {
354 .name = "gpio-vf610",
355 .of_match_table = vf610_gpio_dt_ids,
356 },
357 .probe = vf610_gpio_probe,
358 .remove = vf610_gpio_remove,
359 };
360
361 builtin_platform_driver(vf610_gpio_driver);