drivers/gpio/gpio-wcove.c

   1 /*
   2  * Intel Whiskey Cove PMIC GPIO Driver
   3  *
   4  * This driver is written based on gpio-crystalcove.c
   5  *
   6  * Copyright (C) 2016 Intel Corporation. All rights reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License version
  10  * 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/bitops.h>
  19 #include <linux/module.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/gpio/driver.h>
  22 #include <linux/mfd/intel_soc_pmic.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/regmap.h>
  25 #include <linux/seq_file.h>
  26
  27 /*
  28  * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks:
  29  * Bank 0: Pin 0 - 6
  30  * Bank 1: Pin 7 - 10
  31  * Bank 2: Pin 11 -12
  32  * Each pin has one output control register and one input control register.
  33  */
  34 #define BANK0_NR_PINS           7
  35 #define BANK1_NR_PINS           4
  36 #define BANK2_NR_PINS           2
  37 #define WCOVE_GPIO_NUM          (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS)
  38 #define WCOVE_VGPIO_NUM         94
  39 /* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */
  40 #define GPIO_OUT_CTRL_BASE      0x4e44
  41 /* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */
  42 #define GPIO_IN_CTRL_BASE       0x4e51
  43
  44 /*
  45  * GPIO interrupts are organized in two groups:
  46  * Group 0: Bank 0 pins (Pin 0 - 6)
  47  * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
  48  * Each group has two registers (one bit per pin): status and mask.
  49  */
  50 #define GROUP0_NR_IRQS          7
  51 #define GROUP1_NR_IRQS          6
  52 #define IRQ_MASK_BASE           0x4e19
  53 #define IRQ_STATUS_BASE         0x4e0b
  54 #define UPDATE_IRQ_TYPE         BIT(0)
  55 #define UPDATE_IRQ_MASK         BIT(1)
  56
  57 #define CTLI_INTCNT_DIS         (0 << 1)
  58 #define CTLI_INTCNT_NE          (1 << 1)
  59 #define CTLI_INTCNT_PE          (2 << 1)
  60 #define CTLI_INTCNT_BE          (3 << 1)
  61
  62 #define CTLO_DIR_IN             (0 << 5)
  63 #define CTLO_DIR_OUT            (1 << 5)
  64
  65 #define CTLO_DRV_MASK           (1 << 4)
  66 #define CTLO_DRV_OD             (0 << 4)
  67 #define CTLO_DRV_CMOS           (1 << 4)
  68
  69 #define CTLO_DRV_REN            (1 << 3)
  70
  71 #define CTLO_RVAL_2KDOWN        (0 << 1)
  72 #define CTLO_RVAL_2KUP          (1 << 1)
  73 #define CTLO_RVAL_50KDOWN       (2 << 1)
  74 #define CTLO_RVAL_50KUP         (3 << 1)
  75
  76 #define CTLO_INPUT_SET  (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
  77 #define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET)
  78
  79 enum ctrl_register {
  80         CTRL_IN,
  81         CTRL_OUT,
  82 };
  83
  84 /*
  85  * struct wcove_gpio - Whiskey Cove GPIO controller
  86  * @buslock: for bus lock/sync and unlock.
  87  * @chip: the abstract gpio_chip structure.
  88  * @dev: the gpio device
  89  * @regmap: the regmap from the parent device.
  90  * @regmap_irq_chip: the regmap of the gpio irq chip.
  91  * @update: pending IRQ setting update, to be written to the chip upon unlock.
  92  * @intcnt: the Interrupt Detect value to be written.
  93  * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
  94  */
  95 struct wcove_gpio {
  96         struct mutex buslock;
  97         struct gpio_chip chip;
  98         struct device *dev;
  99         struct regmap *regmap;
 100         struct regmap_irq_chip_data *regmap_irq_chip;
 101         int update;
 102         int intcnt;
 103         bool set_irq_mask;
 104 };
 105
 106 static inline unsigned int to_reg(int gpio, enum ctrl_register reg_type)
 107 {
 108         unsigned int reg;
 109         int bank;
 110
 111         if (gpio < BANK0_NR_PINS)
 112                 bank = 0;
 113         else if (gpio < BANK0_NR_PINS + BANK1_NR_PINS)
 114                 bank = 1;
 115         else
 116                 bank = 2;
 117
 118         if (reg_type == CTRL_IN)
 119                 reg = GPIO_IN_CTRL_BASE + bank;
 120         else
 121                 reg = GPIO_OUT_CTRL_BASE + bank;
 122
 123         return reg;
 124 }
 125
 126 static void wcove_update_irq_mask(struct wcove_gpio *wg, int gpio)
 127 {
 128         unsigned int reg, mask;
 129
 130         if (gpio < GROUP0_NR_IRQS) {
 131                 reg = IRQ_MASK_BASE;
 132                 mask = BIT(gpio % GROUP0_NR_IRQS);
 133         } else {
 134                 reg = IRQ_MASK_BASE + 1;
 135                 mask = BIT((gpio - GROUP0_NR_IRQS) % GROUP1_NR_IRQS);
 136         }
 137
 138         if (wg->set_irq_mask)
 139                 regmap_update_bits(wg->regmap, reg, mask, mask);
 140         else
 141                 regmap_update_bits(wg->regmap, reg, mask, 0);
 142 }
 143
 144 static void wcove_update_irq_ctrl(struct wcove_gpio *wg, int gpio)
 145 {
 146         unsigned int reg = to_reg(gpio, CTRL_IN);
 147
 148         regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt);
 149 }
 150
 151 static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
 152 {
 153         struct wcove_gpio *wg = gpiochip_get_data(chip);
 154
 155         return regmap_write(wg->regmap, to_reg(gpio, CTRL_OUT),
 156                             CTLO_INPUT_SET);
 157 }
 158
 159 static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
 160                                     int value)
 161 {
 162         struct wcove_gpio *wg = gpiochip_get_data(chip);
 163
 164         return regmap_write(wg->regmap, to_reg(gpio, CTRL_OUT),
 165                             CTLO_OUTPUT_SET | value);
 166 }
 167
 168 static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
 169 {
 170         struct wcove_gpio *wg = gpiochip_get_data(chip);
 171         unsigned int val;
 172         int ret;
 173
 174         ret = regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &val);
 175         if (ret)
 176                 return ret;
 177
 178         return !(val & CTLO_DIR_OUT);
 179 }
 180
 181 static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
 182 {
 183         struct wcove_gpio *wg = gpiochip_get_data(chip);
 184         unsigned int val;
 185         int ret;
 186
 187         ret = regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &val);
 188         if (ret)
 189                 return ret;
 190
 191         return val & 0x1;
 192 }
 193
 194 static void wcove_gpio_set(struct gpio_chip *chip,
 195                                  unsigned int gpio, int value)
 196 {
 197         struct wcove_gpio *wg = gpiochip_get_data(chip);
 198
 199         if (value)
 200                 regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT), 1, 1);
 201         else
 202                 regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT), 1, 0);
 203 }
 204
 205 static int wcove_gpio_set_config(struct gpio_chip *chip, unsigned int gpio,
 206                                  unsigned long config)
 207 {
 208         struct wcove_gpio *wg = gpiochip_get_data(chip);
 209
 210         switch (pinconf_to_config_param(config)) {
 211         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 212                 return regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT),
 213                                                 CTLO_DRV_MASK, CTLO_DRV_OD);
 214         case PIN_CONFIG_DRIVE_PUSH_PULL:
 215                 return regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT),
 216                                                 CTLO_DRV_MASK, CTLO_DRV_CMOS);
 217         default:
 218                 break;
 219         }
 220
 221         return -ENOTSUPP;
 222 }
 223
 224 static int wcove_irq_type(struct irq_data *data, unsigned int type)
 225 {
 226         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 227         struct wcove_gpio *wg = gpiochip_get_data(chip);
 228
 229         switch (type) {
 230         case IRQ_TYPE_NONE:
 231                 wg->intcnt = CTLI_INTCNT_DIS;
 232                 break;
 233         case IRQ_TYPE_EDGE_BOTH:
 234                 wg->intcnt = CTLI_INTCNT_BE;
 235                 break;
 236         case IRQ_TYPE_EDGE_RISING:
 237                 wg->intcnt = CTLI_INTCNT_PE;
 238                 break;
 239         case IRQ_TYPE_EDGE_FALLING:
 240                 wg->intcnt = CTLI_INTCNT_NE;
 241                 break;
 242         default:
 243                 return -EINVAL;
 244         }
 245
 246         wg->update |= UPDATE_IRQ_TYPE;
 247
 248         return 0;
 249 }
 250
 251 static void wcove_bus_lock(struct irq_data *data)
 252 {
 253         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 254         struct wcove_gpio *wg = gpiochip_get_data(chip);
 255
 256         mutex_lock(&wg->buslock);
 257 }
 258
 259 static void wcove_bus_sync_unlock(struct irq_data *data)
 260 {
 261         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 262         struct wcove_gpio *wg = gpiochip_get_data(chip);
 263         int gpio = data->hwirq;
 264
 265         if (wg->update & UPDATE_IRQ_TYPE)
 266                 wcove_update_irq_ctrl(wg, gpio);
 267         if (wg->update & UPDATE_IRQ_MASK)
 268                 wcove_update_irq_mask(wg, gpio);
 269         wg->update = 0;
 270
 271         mutex_unlock(&wg->buslock);
 272 }
 273
 274 static void wcove_irq_unmask(struct irq_data *data)
 275 {
 276         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 277         struct wcove_gpio *wg = gpiochip_get_data(chip);
 278
 279         wg->set_irq_mask = false;
 280         wg->update |= UPDATE_IRQ_MASK;
 281 }
 282
 283 static void wcove_irq_mask(struct irq_data *data)
 284 {
 285         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 286         struct wcove_gpio *wg = gpiochip_get_data(chip);
 287
 288         wg->set_irq_mask = true;
 289         wg->update |= UPDATE_IRQ_MASK;
 290 }
 291
 292 static struct irq_chip wcove_irqchip = {
 293         .name                   = "Whiskey Cove",
 294         .irq_mask               = wcove_irq_mask,
 295         .irq_unmask             = wcove_irq_unmask,
 296         .irq_set_type           = wcove_irq_type,
 297         .irq_bus_lock           = wcove_bus_lock,
 298         .irq_bus_sync_unlock    = wcove_bus_sync_unlock,
 299 };
 300
 301 static irqreturn_t wcove_gpio_irq_handler(int irq, void *data)
 302 {
 303         struct wcove_gpio *wg = (struct wcove_gpio *)data;
 304         unsigned int pending, virq, gpio, mask, offset;
 305         u8 p[2];
 306
 307         if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
 308                 dev_err(wg->dev, "Failed to read irq status register\n");
 309                 return IRQ_NONE;
 310         }
 311
 312         pending = p[0] | (p[1] << 8);
 313         if (!pending)
 314                 return IRQ_NONE;
 315
 316         /* Iterate until no interrupt is pending */
 317         while (pending) {
 318                 /* One iteration is for all pending bits */
 319                 for_each_set_bit(gpio, (const unsigned long *)&pending,
 320                                                  GROUP0_NR_IRQS) {
 321                         offset = (gpio > GROUP0_NR_IRQS) ? 1 : 0;
 322                         mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) :
 323                                                                 BIT(gpio);
 324                         virq = irq_find_mapping(wg->chip.irqdomain, gpio);
 325                         handle_nested_irq(virq);
 326                         regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset,
 327                                                                 mask, mask);
 328                 }
 329
 330                 /* Next iteration */
 331                 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
 332                         dev_err(wg->dev, "Failed to read irq status\n");
 333                         break;
 334                 }
 335
 336                 pending = p[0] | (p[1] << 8);
 337         }
 338
 339         return IRQ_HANDLED;
 340 }
 341
 342 static void wcove_gpio_dbg_show(struct seq_file *s,
 343                                       struct gpio_chip *chip)
 344 {
 345         unsigned int ctlo, ctli, irq_mask, irq_status;
 346         struct wcove_gpio *wg = gpiochip_get_data(chip);
 347         int gpio, offset, group, ret = 0;
 348
 349         for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) {
 350                 group = gpio < GROUP0_NR_IRQS ? 0 : 1;
 351                 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
 352                 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli);
 353                 ret += regmap_read(wg->regmap, IRQ_MASK_BASE + group,
 354                                                         &irq_mask);
 355                 ret += regmap_read(wg->regmap, IRQ_STATUS_BASE + group,
 356                                                         &irq_status);
 357                 if (ret) {
 358                         pr_err("Failed to read registers: ctrl out/in or irq status/mask\n");
 359                         break;
 360                 }
 361
 362                 offset = gpio % 8;
 363                 seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n",
 364                            gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
 365                            ctli & 0x1 ? "hi" : "lo",
 366                            ctli & CTLI_INTCNT_NE ? "fall" : "    ",
 367                            ctli & CTLI_INTCNT_PE ? "rise" : "    ",
 368                            ctlo,
 369                            irq_mask & BIT(offset) ? "mask  " : "unmask",
 370                            irq_status & BIT(offset) ? "pending" : "       ");
 371         }
 372 }
 373
 374 static int wcove_gpio_probe(struct platform_device *pdev)
 375 {
 376         struct intel_soc_pmic *pmic;
 377         struct wcove_gpio *wg;
 378         int virq, ret, irq;
 379         struct device *dev;
 380
 381         /*
 382          * This gpio platform device is created by a mfd device (see
 383          * drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information
 384          * shared by all sub-devices created by the mfd device, the regmap
 385          * pointer for instance, is stored as driver data of the mfd device
 386          * driver.
 387          */
 388         pmic = dev_get_drvdata(pdev->dev.parent);
 389         if (!pmic)
 390                 return -ENODEV;
 391
 392         irq = platform_get_irq(pdev, 0);
 393         if (irq < 0)
 394                 return irq;
 395
 396         dev = &pdev->dev;
 397
 398         wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL);
 399         if (!wg)
 400                 return -ENOMEM;
 401
 402         wg->regmap_irq_chip = pmic->irq_chip_data_level2;
 403
 404         platform_set_drvdata(pdev, wg);
 405
 406         mutex_init(&wg->buslock);
 407         wg->chip.label = KBUILD_MODNAME;
 408         wg->chip.direction_input = wcove_gpio_dir_in;
 409         wg->chip.direction_output = wcove_gpio_dir_out;
 410         wg->chip.get_direction = wcove_gpio_get_direction;
 411         wg->chip.get = wcove_gpio_get;
 412         wg->chip.set = wcove_gpio_set;
 413         wg->chip.set_config = wcove_gpio_set_config,
 414         wg->chip.base = -1;
 415         wg->chip.ngpio = WCOVE_VGPIO_NUM;
 416         wg->chip.can_sleep = true;
 417         wg->chip.parent = pdev->dev.parent;
 418         wg->chip.dbg_show = wcove_gpio_dbg_show;
 419         wg->dev = dev;
 420         wg->regmap = pmic->regmap;
 421
 422         ret = devm_gpiochip_add_data(dev, &wg->chip, wg);
 423         if (ret) {
 424                 dev_err(dev, "Failed to add gpiochip: %d\n", ret);
 425                 return ret;
 426         }
 427
 428         ret = gpiochip_irqchip_add_nested(&wg->chip, &wcove_irqchip, 0,
 429                                           handle_simple_irq, IRQ_TYPE_NONE);
 430         if (ret) {
 431                 dev_err(dev, "Failed to add irqchip: %d\n", ret);
 432                 return ret;
 433         }
 434
 435         virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq);
 436         if (virq < 0) {
 437                 dev_err(dev, "Failed to get virq by irq %d\n", irq);
 438                 return virq;
 439         }
 440
 441         ret = devm_request_threaded_irq(dev, virq, NULL,
 442                 wcove_gpio_irq_handler, IRQF_ONESHOT, pdev->name, wg);
 443         if (ret) {
 444                 dev_err(dev, "Failed to request irq %d\n", virq);
 445                 return ret;
 446         }
 447
 448         gpiochip_set_nested_irqchip(&wg->chip, &wcove_irqchip, virq);
 449
 450         return 0;
 451 }
 452
 453 /*
 454  * Whiskey Cove PMIC itself is a analog device(but with digital control
 455  * interface) providing power management support for other devices in
 456  * the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver.
 457  */
 458 static struct platform_driver wcove_gpio_driver = {
 459         .driver = {
 460                 .name = "bxt_wcove_gpio",
 461         },
 462         .probe = wcove_gpio_probe,
 463 };
 464
 465 module_platform_driver(wcove_gpio_driver);
 466
 467 MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>");
 468 MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>");
 469 MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver");
 470 MODULE_LICENSE("GPL v2");
 471 MODULE_ALIAS("platform:bxt_wcove_gpio");