2 * Intel Whiskey Cove PMIC GPIO Driver
4 * This driver is written based on gpio-crystalcove.c
6 * Copyright (C) 2016 Intel Corporation. All rights reserved.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License version
10 * 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/bitops.h>
19 #include <linux/interrupt.h>
20 #include <linux/gpio/driver.h>
21 #include <linux/mfd/intel_soc_pmic.h>
22 #include <linux/platform_device.h>
23 #include <linux/regmap.h>
24 #include <linux/seq_file.h>
27 * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks:
31 * Each pin has one output control register and one input control register.
33 #define BANK0_NR_PINS 7
34 #define BANK1_NR_PINS 4
35 #define BANK2_NR_PINS 2
36 #define WCOVE_GPIO_NUM (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS)
37 #define WCOVE_VGPIO_NUM 94
38 /* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */
39 #define GPIO_OUT_CTRL_BASE 0x4e44
40 /* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */
41 #define GPIO_IN_CTRL_BASE 0x4e51
44 * GPIO interrupts are organized in two groups:
45 * Group 0: Bank 0 pins (Pin 0 - 6)
46 * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
47 * Each group has two registers (one bit per pin): status and mask.
49 #define GROUP0_NR_IRQS 7
50 #define GROUP1_NR_IRQS 6
51 #define IRQ_MASK_BASE 0x4e19
52 #define IRQ_STATUS_BASE 0x4e0b
53 #define UPDATE_IRQ_TYPE BIT(0)
54 #define UPDATE_IRQ_MASK BIT(1)
56 #define CTLI_INTCNT_DIS (0 << 1)
57 #define CTLI_INTCNT_NE (1 << 1)
58 #define CTLI_INTCNT_PE (2 << 1)
59 #define CTLI_INTCNT_BE (3 << 1)
61 #define CTLO_DIR_IN (0 << 5)
62 #define CTLO_DIR_OUT (1 << 5)
64 #define CTLO_DRV_MASK (1 << 4)
65 #define CTLO_DRV_OD (0 << 4)
66 #define CTLO_DRV_CMOS (1 << 4)
68 #define CTLO_DRV_REN (1 << 3)
70 #define CTLO_RVAL_2KDOWN (0 << 1)
71 #define CTLO_RVAL_2KUP (1 << 1)
72 #define CTLO_RVAL_50KDOWN (2 << 1)
73 #define CTLO_RVAL_50KUP (3 << 1)
75 #define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
76 #define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET)
84 * struct wcove_gpio - Whiskey Cove GPIO controller
85 * @buslock: for bus lock/sync and unlock.
86 * @chip: the abstract gpio_chip structure.
87 * @dev: the gpio device
88 * @regmap: the regmap from the parent device.
89 * @regmap_irq_chip: the regmap of the gpio irq chip.
90 * @update: pending IRQ setting update, to be written to the chip upon unlock.
91 * @intcnt: the Interrupt Detect value to be written.
92 * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
96 struct gpio_chip chip
;
98 struct regmap
*regmap
;
99 struct regmap_irq_chip_data
*regmap_irq_chip
;
105 static inline unsigned int to_reg(int gpio
, enum ctrl_register reg_type
)
110 if (gpio
< BANK0_NR_PINS
)
112 else if (gpio
< BANK0_NR_PINS
+ BANK1_NR_PINS
)
117 if (reg_type
== CTRL_IN
)
118 reg
= GPIO_IN_CTRL_BASE
+ bank
;
120 reg
= GPIO_OUT_CTRL_BASE
+ bank
;
125 static void wcove_update_irq_mask(struct wcove_gpio
*wg
, int gpio
)
127 unsigned int reg
, mask
;
129 if (gpio
< GROUP0_NR_IRQS
) {
131 mask
= BIT(gpio
% GROUP0_NR_IRQS
);
133 reg
= IRQ_MASK_BASE
+ 1;
134 mask
= BIT((gpio
- GROUP0_NR_IRQS
) % GROUP1_NR_IRQS
);
137 if (wg
->set_irq_mask
)
138 regmap_update_bits(wg
->regmap
, reg
, mask
, mask
);
140 regmap_update_bits(wg
->regmap
, reg
, mask
, 0);
143 static void wcove_update_irq_ctrl(struct wcove_gpio
*wg
, int gpio
)
145 unsigned int reg
= to_reg(gpio
, CTRL_IN
);
147 regmap_update_bits(wg
->regmap
, reg
, CTLI_INTCNT_BE
, wg
->intcnt
);
150 static int wcove_gpio_dir_in(struct gpio_chip
*chip
, unsigned int gpio
)
152 struct wcove_gpio
*wg
= gpiochip_get_data(chip
);
154 return regmap_write(wg
->regmap
, to_reg(gpio
, CTRL_OUT
),
158 static int wcove_gpio_dir_out(struct gpio_chip
*chip
, unsigned int gpio
,
161 struct wcove_gpio
*wg
= gpiochip_get_data(chip
);
163 return regmap_write(wg
->regmap
, to_reg(gpio
, CTRL_OUT
),
164 CTLO_OUTPUT_SET
| value
);
167 static int wcove_gpio_get_direction(struct gpio_chip
*chip
, unsigned int gpio
)
169 struct wcove_gpio
*wg
= gpiochip_get_data(chip
);
173 ret
= regmap_read(wg
->regmap
, to_reg(gpio
, CTRL_OUT
), &val
);
177 return !(val
& CTLO_DIR_OUT
);
180 static int wcove_gpio_get(struct gpio_chip
*chip
, unsigned int gpio
)
182 struct wcove_gpio
*wg
= gpiochip_get_data(chip
);
186 ret
= regmap_read(wg
->regmap
, to_reg(gpio
, CTRL_IN
), &val
);
193 static void wcove_gpio_set(struct gpio_chip
*chip
,
194 unsigned int gpio
, int value
)
196 struct wcove_gpio
*wg
= gpiochip_get_data(chip
);
199 regmap_update_bits(wg
->regmap
, to_reg(gpio
, CTRL_OUT
), 1, 1);
201 regmap_update_bits(wg
->regmap
, to_reg(gpio
, CTRL_OUT
), 1, 0);
204 static int wcove_gpio_set_single_ended(struct gpio_chip
*chip
,
206 enum single_ended_mode mode
)
208 struct wcove_gpio
*wg
= gpiochip_get_data(chip
);
211 case LINE_MODE_OPEN_DRAIN
:
212 return regmap_update_bits(wg
->regmap
, to_reg(gpio
, CTRL_OUT
),
213 CTLO_DRV_MASK
, CTLO_DRV_OD
);
214 case LINE_MODE_PUSH_PULL
:
215 return regmap_update_bits(wg
->regmap
, to_reg(gpio
, CTRL_OUT
),
216 CTLO_DRV_MASK
, CTLO_DRV_CMOS
);
224 static int wcove_irq_type(struct irq_data
*data
, unsigned int type
)
226 struct gpio_chip
*chip
= irq_data_get_irq_chip_data(data
);
227 struct wcove_gpio
*wg
= gpiochip_get_data(chip
);
231 wg
->intcnt
= CTLI_INTCNT_DIS
;
233 case IRQ_TYPE_EDGE_BOTH
:
234 wg
->intcnt
= CTLI_INTCNT_BE
;
236 case IRQ_TYPE_EDGE_RISING
:
237 wg
->intcnt
= CTLI_INTCNT_PE
;
239 case IRQ_TYPE_EDGE_FALLING
:
240 wg
->intcnt
= CTLI_INTCNT_NE
;
246 wg
->update
|= UPDATE_IRQ_TYPE
;
251 static void wcove_bus_lock(struct irq_data
*data
)
253 struct gpio_chip
*chip
= irq_data_get_irq_chip_data(data
);
254 struct wcove_gpio
*wg
= gpiochip_get_data(chip
);
256 mutex_lock(&wg
->buslock
);
259 static void wcove_bus_sync_unlock(struct irq_data
*data
)
261 struct gpio_chip
*chip
= irq_data_get_irq_chip_data(data
);
262 struct wcove_gpio
*wg
= gpiochip_get_data(chip
);
263 int gpio
= data
->hwirq
;
265 if (wg
->update
& UPDATE_IRQ_TYPE
)
266 wcove_update_irq_ctrl(wg
, gpio
);
267 if (wg
->update
& UPDATE_IRQ_MASK
)
268 wcove_update_irq_mask(wg
, gpio
);
271 mutex_unlock(&wg
->buslock
);
274 static void wcove_irq_unmask(struct irq_data
*data
)
276 struct gpio_chip
*chip
= irq_data_get_irq_chip_data(data
);
277 struct wcove_gpio
*wg
= gpiochip_get_data(chip
);
279 wg
->set_irq_mask
= false;
280 wg
->update
|= UPDATE_IRQ_MASK
;
283 static void wcove_irq_mask(struct irq_data
*data
)
285 struct gpio_chip
*chip
= irq_data_get_irq_chip_data(data
);
286 struct wcove_gpio
*wg
= gpiochip_get_data(chip
);
288 wg
->set_irq_mask
= true;
289 wg
->update
|= UPDATE_IRQ_MASK
;
292 static struct irq_chip wcove_irqchip
= {
293 .name
= "Whiskey Cove",
294 .irq_mask
= wcove_irq_mask
,
295 .irq_unmask
= wcove_irq_unmask
,
296 .irq_set_type
= wcove_irq_type
,
297 .irq_bus_lock
= wcove_bus_lock
,
298 .irq_bus_sync_unlock
= wcove_bus_sync_unlock
,
301 static irqreturn_t
wcove_gpio_irq_handler(int irq
, void *data
)
303 struct wcove_gpio
*wg
= (struct wcove_gpio
*)data
;
304 unsigned int pending
, virq
, gpio
, mask
, offset
;
307 if (regmap_bulk_read(wg
->regmap
, IRQ_STATUS_BASE
, p
, 2)) {
308 dev_err(wg
->dev
, "Failed to read irq status register\n");
312 pending
= p
[0] | (p
[1] << 8);
316 /* Iterate until no interrupt is pending */
318 /* One iteration is for all pending bits */
319 for_each_set_bit(gpio
, (const unsigned long *)&pending
,
321 offset
= (gpio
> GROUP0_NR_IRQS
) ? 1 : 0;
322 mask
= (offset
== 1) ? BIT(gpio
- GROUP0_NR_IRQS
) :
324 virq
= irq_find_mapping(wg
->chip
.irqdomain
, gpio
);
325 handle_nested_irq(virq
);
326 regmap_update_bits(wg
->regmap
, IRQ_STATUS_BASE
+ offset
,
331 if (regmap_bulk_read(wg
->regmap
, IRQ_STATUS_BASE
, p
, 2)) {
332 dev_err(wg
->dev
, "Failed to read irq status\n");
336 pending
= p
[0] | (p
[1] << 8);
342 static void wcove_gpio_dbg_show(struct seq_file
*s
,
343 struct gpio_chip
*chip
)
345 unsigned int ctlo
, ctli
, irq_mask
, irq_status
;
346 struct wcove_gpio
*wg
= gpiochip_get_data(chip
);
347 int gpio
, offset
, group
, ret
= 0;
349 for (gpio
= 0; gpio
< WCOVE_GPIO_NUM
; gpio
++) {
350 group
= gpio
< GROUP0_NR_IRQS
? 0 : 1;
351 ret
+= regmap_read(wg
->regmap
, to_reg(gpio
, CTRL_OUT
), &ctlo
);
352 ret
+= regmap_read(wg
->regmap
, to_reg(gpio
, CTRL_IN
), &ctli
);
353 ret
+= regmap_read(wg
->regmap
, IRQ_MASK_BASE
+ group
,
355 ret
+= regmap_read(wg
->regmap
, IRQ_STATUS_BASE
+ group
,
358 pr_err("Failed to read registers: ctrl out/in or irq status/mask\n");
363 seq_printf(s
, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n",
364 gpio
, ctlo
& CTLO_DIR_OUT
? "out" : "in ",
365 ctli
& 0x1 ? "hi" : "lo",
366 ctli
& CTLI_INTCNT_NE
? "fall" : " ",
367 ctli
& CTLI_INTCNT_PE
? "rise" : " ",
369 irq_mask
& BIT(offset
) ? "mask " : "unmask",
370 irq_status
& BIT(offset
) ? "pending" : " ");
374 static int wcove_gpio_probe(struct platform_device
*pdev
)
376 struct intel_soc_pmic
*pmic
;
377 struct wcove_gpio
*wg
;
382 * This gpio platform device is created by a mfd device (see
383 * drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information
384 * shared by all sub-devices created by the mfd device, the regmap
385 * pointer for instance, is stored as driver data of the mfd device
388 pmic
= dev_get_drvdata(pdev
->dev
.parent
);
392 irq
= platform_get_irq(pdev
, 0);
398 wg
= devm_kzalloc(dev
, sizeof(*wg
), GFP_KERNEL
);
402 wg
->regmap_irq_chip
= pmic
->irq_chip_data_level2
;
404 platform_set_drvdata(pdev
, wg
);
406 mutex_init(&wg
->buslock
);
407 wg
->chip
.label
= KBUILD_MODNAME
;
408 wg
->chip
.direction_input
= wcove_gpio_dir_in
;
409 wg
->chip
.direction_output
= wcove_gpio_dir_out
;
410 wg
->chip
.get_direction
= wcove_gpio_get_direction
;
411 wg
->chip
.get
= wcove_gpio_get
;
412 wg
->chip
.set
= wcove_gpio_set
;
413 wg
->chip
.set_single_ended
= wcove_gpio_set_single_ended
,
415 wg
->chip
.ngpio
= WCOVE_VGPIO_NUM
;
416 wg
->chip
.can_sleep
= true;
417 wg
->chip
.parent
= pdev
->dev
.parent
;
418 wg
->chip
.dbg_show
= wcove_gpio_dbg_show
;
420 wg
->regmap
= pmic
->regmap
;
422 ret
= devm_gpiochip_add_data(dev
, &wg
->chip
, wg
);
424 dev_err(dev
, "Failed to add gpiochip: %d\n", ret
);
428 ret
= gpiochip_irqchip_add(&wg
->chip
, &wcove_irqchip
, 0,
429 handle_simple_irq
, IRQ_TYPE_NONE
);
431 dev_err(dev
, "Failed to add irqchip: %d\n", ret
);
435 virq
= regmap_irq_get_virq(wg
->regmap_irq_chip
, irq
);
437 dev_err(dev
, "Failed to get virq by irq %d\n", irq
);
441 ret
= devm_request_threaded_irq(dev
, virq
, NULL
,
442 wcove_gpio_irq_handler
, IRQF_ONESHOT
, pdev
->name
, wg
);
444 dev_err(dev
, "Failed to request irq %d\n", virq
);
452 * Whiskey Cove PMIC itself is a analog device(but with digital control
453 * interface) providing power management support for other devices in
454 * the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver.
456 static struct platform_driver wcove_gpio_driver
= {
458 .name
= "bxt_wcove_gpio",
460 .probe
= wcove_gpio_probe
,
463 module_platform_driver(wcove_gpio_driver
);
465 MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>");
466 MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>");
467 MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver");
468 MODULE_LICENSE("GPL v2");
469 MODULE_ALIAS("platform:bxt_wcove_gpio");