drivers/gpio/gpio-zynq.c

   1 /*
   2  * Xilinx Zynq GPIO device driver
   3  *
   4  * Copyright (C) 2009 - 2014 Xilinx, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it under
   7  * the terms of the GNU General Public License as published by the Free Software
   8  * Foundation; either version 2 of the License, or (at your option) any later
   9  * version.
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/clk.h>
  14 #include <linux/gpio/driver.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/of.h>
  22
  23 #define DRIVER_NAME "zynq-gpio"
  24
  25 /* Maximum banks */
  26 #define ZYNQ_GPIO_MAX_BANK      4
  27 #define ZYNQMP_GPIO_MAX_BANK    6
  28
  29 #define ZYNQ_GPIO_BANK0_NGPIO   32
  30 #define ZYNQ_GPIO_BANK1_NGPIO   22
  31 #define ZYNQ_GPIO_BANK2_NGPIO   32
  32 #define ZYNQ_GPIO_BANK3_NGPIO   32
  33
  34 #define ZYNQMP_GPIO_BANK0_NGPIO 26
  35 #define ZYNQMP_GPIO_BANK1_NGPIO 26
  36 #define ZYNQMP_GPIO_BANK2_NGPIO 26
  37 #define ZYNQMP_GPIO_BANK3_NGPIO 32
  38 #define ZYNQMP_GPIO_BANK4_NGPIO 32
  39 #define ZYNQMP_GPIO_BANK5_NGPIO 32
  40
  41 #define ZYNQ_GPIO_NR_GPIOS      118
  42 #define ZYNQMP_GPIO_NR_GPIOS    174
  43
  44 #define ZYNQ_GPIO_BANK0_PIN_MIN(str)    0
  45 #define ZYNQ_GPIO_BANK0_PIN_MAX(str)    (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
  46                                         ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
  47 #define ZYNQ_GPIO_BANK1_PIN_MIN(str)    (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
  48 #define ZYNQ_GPIO_BANK1_PIN_MAX(str)    (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
  49                                         ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
  50 #define ZYNQ_GPIO_BANK2_PIN_MIN(str)    (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
  51 #define ZYNQ_GPIO_BANK2_PIN_MAX(str)    (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
  52                                         ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
  53 #define ZYNQ_GPIO_BANK3_PIN_MIN(str)    (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
  54 #define ZYNQ_GPIO_BANK3_PIN_MAX(str)    (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
  55                                         ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
  56 #define ZYNQ_GPIO_BANK4_PIN_MIN(str)    (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
  57 #define ZYNQ_GPIO_BANK4_PIN_MAX(str)    (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
  58                                         ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
  59 #define ZYNQ_GPIO_BANK5_PIN_MIN(str)    (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
  60 #define ZYNQ_GPIO_BANK5_PIN_MAX(str)    (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
  61                                         ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
  62
  63
  64 /* Register offsets for the GPIO device */
  65 /* LSW Mask & Data -WO */
  66 #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
  67 /* MSW Mask & Data -WO */
  68 #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
  69 /* Data Register-RW */
  70 #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK)  (0x060 + (4 * BANK))
  71 /* Direction mode reg-RW */
  72 #define ZYNQ_GPIO_DIRM_OFFSET(BANK)     (0x204 + (0x40 * BANK))
  73 /* Output enable reg-RW */
  74 #define ZYNQ_GPIO_OUTEN_OFFSET(BANK)    (0x208 + (0x40 * BANK))
  75 /* Interrupt mask reg-RO */
  76 #define ZYNQ_GPIO_INTMASK_OFFSET(BANK)  (0x20C + (0x40 * BANK))
  77 /* Interrupt enable reg-WO */
  78 #define ZYNQ_GPIO_INTEN_OFFSET(BANK)    (0x210 + (0x40 * BANK))
  79 /* Interrupt disable reg-WO */
  80 #define ZYNQ_GPIO_INTDIS_OFFSET(BANK)   (0x214 + (0x40 * BANK))
  81 /* Interrupt status reg-RO */
  82 #define ZYNQ_GPIO_INTSTS_OFFSET(BANK)   (0x218 + (0x40 * BANK))
  83 /* Interrupt type reg-RW */
  84 #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK)  (0x21C + (0x40 * BANK))
  85 /* Interrupt polarity reg-RW */
  86 #define ZYNQ_GPIO_INTPOL_OFFSET(BANK)   (0x220 + (0x40 * BANK))
  87 /* Interrupt on any, reg-RW */
  88 #define ZYNQ_GPIO_INTANY_OFFSET(BANK)   (0x224 + (0x40 * BANK))
  89
  90 /* Disable all interrupts mask */
  91 #define ZYNQ_GPIO_IXR_DISABLE_ALL       0xFFFFFFFF
  92
  93 /* Mid pin number of a bank */
  94 #define ZYNQ_GPIO_MID_PIN_NUM 16
  95
  96 /* GPIO upper 16 bit mask */
  97 #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
  98
  99 /* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */
 100 #define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)
 101
 102 /**
 103  * struct zynq_gpio - gpio device private data structure
 104  * @chip:       instance of the gpio_chip
 105  * @base_addr:  base address of the GPIO device
 106  * @clk:        clock resource for this controller
 107  * @irq:        interrupt for the GPIO device
 108  * @p_data:     pointer to platform data
 109  */
 110 struct zynq_gpio {
 111         struct gpio_chip chip;
 112         void __iomem *base_addr;
 113         struct clk *clk;
 114         int irq;
 115         const struct zynq_platform_data *p_data;
 116 };
 117
 118 /**
 119  * struct zynq_platform_data -  zynq gpio platform data structure
 120  * @label:      string to store in gpio->label
 121  * @ngpio:      max number of gpio pins
 122  * @max_bank:   maximum number of gpio banks
 123  * @bank_min:   this array represents bank's min pin
 124  * @bank_max:   this array represents bank's max pin
 125 */
 126 struct zynq_platform_data {
 127         const char *label;
 128         u32 quirks;
 129         u16 ngpio;
 130         int max_bank;
 131         int bank_min[ZYNQMP_GPIO_MAX_BANK];
 132         int bank_max[ZYNQMP_GPIO_MAX_BANK];
 133 };
 134
 135 static struct irq_chip zynq_gpio_level_irqchip;
 136 static struct irq_chip zynq_gpio_edge_irqchip;
 137
 138 /**
 139  * zynq_gpio_is_zynq - test if HW is zynq or zynqmp
 140  * @gpio:       Pointer to driver data struct
 141  *
 142  * Return: 0 if zynqmp, 1 if zynq.
 143  */
 144 static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)
 145 {
 146         return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);
 147 }
 148
 149 /**
 150  * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
 151  * for a given pin in the GPIO device
 152  * @pin_num:    gpio pin number within the device
 153  * @bank_num:   an output parameter used to return the bank number of the gpio
 154  *              pin
 155  * @bank_pin_num: an output parameter used to return pin number within a bank
 156  *                for the given gpio pin
 157  *
 158  * Returns the bank number and pin offset within the bank.
 159  */
 160 static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
 161                                           unsigned int *bank_num,
 162                                           unsigned int *bank_pin_num,
 163                                           struct zynq_gpio *gpio)
 164 {
 165         int bank;
 166
 167         for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
 168                 if ((pin_num >= gpio->p_data->bank_min[bank]) &&
 169                         (pin_num <= gpio->p_data->bank_max[bank])) {
 170                                 *bank_num = bank;
 171                                 *bank_pin_num = pin_num -
 172                                                 gpio->p_data->bank_min[bank];
 173                                 return;
 174                 }
 175         }
 176
 177         /* default */
 178         WARN(true, "invalid GPIO pin number: %u", pin_num);
 179         *bank_num = 0;
 180         *bank_pin_num = 0;
 181 }
 182
 183 /**
 184  * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
 185  * @chip:       gpio_chip instance to be worked on
 186  * @pin:        gpio pin number within the device
 187  *
 188  * This function reads the state of the specified pin of the GPIO device.
 189  *
 190  * Return: 0 if the pin is low, 1 if pin is high.
 191  */
 192 static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
 193 {
 194         u32 data;
 195         unsigned int bank_num, bank_pin_num;
 196         struct zynq_gpio *gpio = gpiochip_get_data(chip);
 197
 198         zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
 199
 200         data = readl_relaxed(gpio->base_addr +
 201                              ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
 202
 203         return (data >> bank_pin_num) & 1;
 204 }
 205
 206 /**
 207  * zynq_gpio_set_value - Modify the state of the pin with specified value
 208  * @chip:       gpio_chip instance to be worked on
 209  * @pin:        gpio pin number within the device
 210  * @state:      value used to modify the state of the specified pin
 211  *
 212  * This function calculates the register offset (i.e to lower 16 bits or
 213  * upper 16 bits) based on the given pin number and sets the state of a
 214  * gpio pin to the specified value. The state is either 0 or non-zero.
 215  */
 216 static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
 217                                 int state)
 218 {
 219         unsigned int reg_offset, bank_num, bank_pin_num;
 220         struct zynq_gpio *gpio = gpiochip_get_data(chip);
 221
 222         zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
 223
 224         if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
 225                 /* only 16 data bits in bit maskable reg */
 226                 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
 227                 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
 228         } else {
 229                 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
 230         }
 231
 232         /*
 233          * get the 32 bit value to be written to the mask/data register where
 234          * the upper 16 bits is the mask and lower 16 bits is the data
 235          */
 236         state = !!state;
 237         state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
 238                 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
 239
 240         writel_relaxed(state, gpio->base_addr + reg_offset);
 241 }
 242
 243 /**
 244  * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
 245  * @chip:       gpio_chip instance to be worked on
 246  * @pin:        gpio pin number within the device
 247  *
 248  * This function uses the read-modify-write sequence to set the direction of
 249  * the gpio pin as input.
 250  *
 251  * Return: 0 always
 252  */
 253 static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
 254 {
 255         u32 reg;
 256         unsigned int bank_num, bank_pin_num;
 257         struct zynq_gpio *gpio = gpiochip_get_data(chip);
 258
 259         zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
 260
 261         /*
 262          * On zynq bank 0 pins 7 and 8 are special and cannot be used
 263          * as inputs.
 264          */
 265         if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&
 266                 (bank_pin_num == 7 || bank_pin_num == 8))
 267                 return -EINVAL;
 268
 269         /* clear the bit in direction mode reg to set the pin as input */
 270         reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 271         reg &= ~BIT(bank_pin_num);
 272         writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 273
 274         return 0;
 275 }
 276
 277 /**
 278  * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
 279  * @chip:       gpio_chip instance to be worked on
 280  * @pin:        gpio pin number within the device
 281  * @state:      value to be written to specified pin
 282  *
 283  * This function sets the direction of specified GPIO pin as output, configures
 284  * the Output Enable register for the pin and uses zynq_gpio_set to set
 285  * the state of the pin to the value specified.
 286  *
 287  * Return: 0 always
 288  */
 289 static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
 290                              int state)
 291 {
 292         u32 reg;
 293         unsigned int bank_num, bank_pin_num;
 294         struct zynq_gpio *gpio = gpiochip_get_data(chip);
 295
 296         zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
 297
 298         /* set the GPIO pin as output */
 299         reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 300         reg |= BIT(bank_pin_num);
 301         writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 302
 303         /* configure the output enable reg for the pin */
 304         reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
 305         reg |= BIT(bank_pin_num);
 306         writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
 307
 308         /* set the state of the pin */
 309         zynq_gpio_set_value(chip, pin, state);
 310         return 0;
 311 }
 312
 313 /**
 314  * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
 315  * @irq_data:   per irq and chip data passed down to chip functions
 316  *
 317  * This function calculates gpio pin number from irq number and sets the
 318  * bit in the Interrupt Disable register of the corresponding bank to disable
 319  * interrupts for that pin.
 320  */
 321 static void zynq_gpio_irq_mask(struct irq_data *irq_data)
 322 {
 323         unsigned int device_pin_num, bank_num, bank_pin_num;
 324         struct zynq_gpio *gpio =
 325                 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
 326
 327         device_pin_num = irq_data->hwirq;
 328         zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
 329         writel_relaxed(BIT(bank_pin_num),
 330                        gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
 331 }
 332
 333 /**
 334  * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
 335  * @irq_data:   irq data containing irq number of gpio pin for the interrupt
 336  *              to enable
 337  *
 338  * This function calculates the gpio pin number from irq number and sets the
 339  * bit in the Interrupt Enable register of the corresponding bank to enable
 340  * interrupts for that pin.
 341  */
 342 static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
 343 {
 344         unsigned int device_pin_num, bank_num, bank_pin_num;
 345         struct zynq_gpio *gpio =
 346                 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
 347
 348         device_pin_num = irq_data->hwirq;
 349         zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
 350         writel_relaxed(BIT(bank_pin_num),
 351                        gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
 352 }
 353
 354 /**
 355  * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
 356  * @irq_data:   irq data containing irq number of gpio pin for the interrupt
 357  *              to ack
 358  *
 359  * This function calculates gpio pin number from irq number and sets the bit
 360  * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
 361  */
 362 static void zynq_gpio_irq_ack(struct irq_data *irq_data)
 363 {
 364         unsigned int device_pin_num, bank_num, bank_pin_num;
 365         struct zynq_gpio *gpio =
 366                 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
 367
 368         device_pin_num = irq_data->hwirq;
 369         zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
 370         writel_relaxed(BIT(bank_pin_num),
 371                        gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
 372 }
 373
 374 /**
 375  * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
 376  * @irq_data:   irq data containing irq number of gpio pin for the interrupt
 377  *              to enable
 378  *
 379  * Clears the INTSTS bit and unmasks the given interrupt.
 380  */
 381 static void zynq_gpio_irq_enable(struct irq_data *irq_data)
 382 {
 383         /*
 384          * The Zynq GPIO controller does not disable interrupt detection when
 385          * the interrupt is masked and only disables the propagation of the
 386          * interrupt. This means when the controller detects an interrupt
 387          * condition while the interrupt is logically disabled it will propagate
 388          * that interrupt event once the interrupt is enabled. This will cause
 389          * the interrupt consumer to see spurious interrupts to prevent this
 390          * first make sure that the interrupt is not asserted and then enable
 391          * it.
 392          */
 393         zynq_gpio_irq_ack(irq_data);
 394         zynq_gpio_irq_unmask(irq_data);
 395 }
 396
 397 /**
 398  * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
 399  * @irq_data:   irq data containing irq number of gpio pin
 400  * @type:       interrupt type that is to be set for the gpio pin
 401  *
 402  * This function gets the gpio pin number and its bank from the gpio pin number
 403  * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
 404  *
 405  * Return: 0, negative error otherwise.
 406  * TYPE-EDGE_RISING,  INT_TYPE - 1, INT_POLARITY - 1,  INT_ANY - 0;
 407  * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0,  INT_ANY - 0;
 408  * TYPE-EDGE_BOTH,    INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
 409  * TYPE-LEVEL_HIGH,   INT_TYPE - 0, INT_POLARITY - 1,  INT_ANY - NA;
 410  * TYPE-LEVEL_LOW,    INT_TYPE - 0, INT_POLARITY - 0,  INT_ANY - NA
 411  */
 412 static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
 413 {
 414         u32 int_type, int_pol, int_any;
 415         unsigned int device_pin_num, bank_num, bank_pin_num;
 416         struct zynq_gpio *gpio =
 417                 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
 418
 419         device_pin_num = irq_data->hwirq;
 420         zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
 421
 422         int_type = readl_relaxed(gpio->base_addr +
 423                                  ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
 424         int_pol = readl_relaxed(gpio->base_addr +
 425                                 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
 426         int_any = readl_relaxed(gpio->base_addr +
 427                                 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
 428
 429         /*
 430          * based on the type requested, configure the INT_TYPE, INT_POLARITY
 431          * and INT_ANY registers
 432          */
 433         switch (type) {
 434         case IRQ_TYPE_EDGE_RISING:
 435                 int_type |= BIT(bank_pin_num);
 436                 int_pol |= BIT(bank_pin_num);
 437                 int_any &= ~BIT(bank_pin_num);
 438                 break;
 439         case IRQ_TYPE_EDGE_FALLING:
 440                 int_type |= BIT(bank_pin_num);
 441                 int_pol &= ~BIT(bank_pin_num);
 442                 int_any &= ~BIT(bank_pin_num);
 443                 break;
 444         case IRQ_TYPE_EDGE_BOTH:
 445                 int_type |= BIT(bank_pin_num);
 446                 int_any |= BIT(bank_pin_num);
 447                 break;
 448         case IRQ_TYPE_LEVEL_HIGH:
 449                 int_type &= ~BIT(bank_pin_num);
 450                 int_pol |= BIT(bank_pin_num);
 451                 break;
 452         case IRQ_TYPE_LEVEL_LOW:
 453                 int_type &= ~BIT(bank_pin_num);
 454                 int_pol &= ~BIT(bank_pin_num);
 455                 break;
 456         default:
 457                 return -EINVAL;
 458         }
 459
 460         writel_relaxed(int_type,
 461                        gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
 462         writel_relaxed(int_pol,
 463                        gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
 464         writel_relaxed(int_any,
 465                        gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
 466
 467         if (type & IRQ_TYPE_LEVEL_MASK) {
 468                 irq_set_chip_handler_name_locked(irq_data,
 469                         &zynq_gpio_level_irqchip, handle_fasteoi_irq, NULL);
 470         } else {
 471                 irq_set_chip_handler_name_locked(irq_data,
 472                         &zynq_gpio_edge_irqchip, handle_level_irq, NULL);
 473         }
 474
 475         return 0;
 476 }
 477
 478 static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
 479 {
 480         struct zynq_gpio *gpio =
 481                 gpiochip_get_data(irq_data_get_irq_chip_data(data));
 482
 483         irq_set_irq_wake(gpio->irq, on);
 484
 485         return 0;
 486 }
 487
 488 /* irq chip descriptor */
 489 static struct irq_chip zynq_gpio_level_irqchip = {
 490         .name           = DRIVER_NAME,
 491         .irq_enable     = zynq_gpio_irq_enable,
 492         .irq_eoi        = zynq_gpio_irq_ack,
 493         .irq_mask       = zynq_gpio_irq_mask,
 494         .irq_unmask     = zynq_gpio_irq_unmask,
 495         .irq_set_type   = zynq_gpio_set_irq_type,
 496         .irq_set_wake   = zynq_gpio_set_wake,
 497         .flags          = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
 498                           IRQCHIP_MASK_ON_SUSPEND,
 499 };
 500
 501 static struct irq_chip zynq_gpio_edge_irqchip = {
 502         .name           = DRIVER_NAME,
 503         .irq_enable     = zynq_gpio_irq_enable,
 504         .irq_ack        = zynq_gpio_irq_ack,
 505         .irq_mask       = zynq_gpio_irq_mask,
 506         .irq_unmask     = zynq_gpio_irq_unmask,
 507         .irq_set_type   = zynq_gpio_set_irq_type,
 508         .irq_set_wake   = zynq_gpio_set_wake,
 509         .flags          = IRQCHIP_MASK_ON_SUSPEND,
 510 };
 511
 512 static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
 513                                       unsigned int bank_num,
 514                                       unsigned long pending)
 515 {
 516         unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
 517         struct irq_domain *irqdomain = gpio->chip.irqdomain;
 518         int offset;
 519
 520         if (!pending)
 521                 return;
 522
 523         for_each_set_bit(offset, &pending, 32) {
 524                 unsigned int gpio_irq;
 525
 526                 gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
 527                 generic_handle_irq(gpio_irq);
 528         }
 529 }
 530
 531 /**
 532  * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
 533  * @irq:        irq number of the gpio bank where interrupt has occurred
 534  * @desc:       irq descriptor instance of the 'irq'
 535  *
 536  * This function reads the Interrupt Status Register of each bank to get the
 537  * gpio pin number which has triggered an interrupt. It then acks the triggered
 538  * interrupt and calls the pin specific handler set by the higher layer
 539  * application for that pin.
 540  * Note: A bug is reported if no handler is set for the gpio pin.
 541  */
 542 static void zynq_gpio_irqhandler(struct irq_desc *desc)
 543 {
 544         u32 int_sts, int_enb;
 545         unsigned int bank_num;
 546         struct zynq_gpio *gpio =
 547                 gpiochip_get_data(irq_desc_get_handler_data(desc));
 548         struct irq_chip *irqchip = irq_desc_get_chip(desc);
 549
 550         chained_irq_enter(irqchip, desc);
 551
 552         for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
 553                 int_sts = readl_relaxed(gpio->base_addr +
 554                                         ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
 555                 int_enb = readl_relaxed(gpio->base_addr +
 556                                         ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
 557                 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
 558         }
 559
 560         chained_irq_exit(irqchip, desc);
 561 }
 562
 563 static int __maybe_unused zynq_gpio_suspend(struct device *dev)
 564 {
 565         struct platform_device *pdev = to_platform_device(dev);
 566         int irq = platform_get_irq(pdev, 0);
 567         struct irq_data *data = irq_get_irq_data(irq);
 568
 569         if (!irqd_is_wakeup_set(data))
 570                 return pm_runtime_force_suspend(dev);
 571
 572         return 0;
 573 }
 574
 575 static int __maybe_unused zynq_gpio_resume(struct device *dev)
 576 {
 577         struct platform_device *pdev = to_platform_device(dev);
 578         int irq = platform_get_irq(pdev, 0);
 579         struct irq_data *data = irq_get_irq_data(irq);
 580
 581         if (!irqd_is_wakeup_set(data))
 582                 return pm_runtime_force_resume(dev);
 583
 584         return 0;
 585 }
 586
 587 static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
 588 {
 589         struct platform_device *pdev = to_platform_device(dev);
 590         struct zynq_gpio *gpio = platform_get_drvdata(pdev);
 591
 592         clk_disable_unprepare(gpio->clk);
 593
 594         return 0;
 595 }
 596
 597 static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
 598 {
 599         struct platform_device *pdev = to_platform_device(dev);
 600         struct zynq_gpio *gpio = platform_get_drvdata(pdev);
 601
 602         return clk_prepare_enable(gpio->clk);
 603 }
 604
 605 static int zynq_gpio_request(struct gpio_chip *chip, unsigned offset)
 606 {
 607         int ret;
 608
 609         ret = pm_runtime_get_sync(chip->parent);
 610
 611         /*
 612          * If the device is already active pm_runtime_get() will return 1 on
 613          * success, but gpio_request still needs to return 0.
 614          */
 615         return ret < 0 ? ret : 0;
 616 }
 617
 618 static void zynq_gpio_free(struct gpio_chip *chip, unsigned offset)
 619 {
 620         pm_runtime_put(chip->parent);
 621 }
 622
 623 static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
 624         SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
 625         SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
 626                         zynq_gpio_runtime_resume, NULL)
 627 };
 628
 629 static const struct zynq_platform_data zynqmp_gpio_def = {
 630         .label = "zynqmp_gpio",
 631         .ngpio = ZYNQMP_GPIO_NR_GPIOS,
 632         .max_bank = ZYNQMP_GPIO_MAX_BANK,
 633         .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
 634         .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
 635         .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
 636         .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
 637         .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
 638         .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
 639         .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
 640         .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
 641         .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
 642         .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
 643         .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
 644         .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
 645 };
 646
 647 static const struct zynq_platform_data zynq_gpio_def = {
 648         .label = "zynq_gpio",
 649         .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ,
 650         .ngpio = ZYNQ_GPIO_NR_GPIOS,
 651         .max_bank = ZYNQ_GPIO_MAX_BANK,
 652         .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
 653         .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
 654         .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
 655         .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
 656         .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
 657         .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
 658         .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
 659         .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
 660 };
 661
 662 static const struct of_device_id zynq_gpio_of_match[] = {
 663         { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
 664         { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
 665         { /* end of table */ }
 666 };
 667 MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
 668
 669 /**
 670  * zynq_gpio_probe - Initialization method for a zynq_gpio device
 671  * @pdev:       platform device instance
 672  *
 673  * This function allocates memory resources for the gpio device and registers
 674  * all the banks of the device. It will also set up interrupts for the gpio
 675  * pins.
 676  * Note: Interrupts are disabled for all the banks during initialization.
 677  *
 678  * Return: 0 on success, negative error otherwise.
 679  */
 680 static int zynq_gpio_probe(struct platform_device *pdev)
 681 {
 682         int ret, bank_num;
 683         struct zynq_gpio *gpio;
 684         struct gpio_chip *chip;
 685         struct resource *res;
 686         const struct of_device_id *match;
 687
 688         gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
 689         if (!gpio)
 690                 return -ENOMEM;
 691
 692         match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
 693         if (!match) {
 694                 dev_err(&pdev->dev, "of_match_node() failed\n");
 695                 return -EINVAL;
 696         }
 697         gpio->p_data = match->data;
 698         platform_set_drvdata(pdev, gpio);
 699
 700         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 701         gpio->base_addr = devm_ioremap_resource(&pdev->dev, res);
 702         if (IS_ERR(gpio->base_addr))
 703                 return PTR_ERR(gpio->base_addr);
 704
 705         gpio->irq = platform_get_irq(pdev, 0);
 706         if (gpio->irq < 0) {
 707                 dev_err(&pdev->dev, "invalid IRQ\n");
 708                 return gpio->irq;
 709         }
 710
 711         /* configure the gpio chip */
 712         chip = &gpio->chip;
 713         chip->label = gpio->p_data->label;
 714         chip->owner = THIS_MODULE;
 715         chip->parent = &pdev->dev;
 716         chip->get = zynq_gpio_get_value;
 717         chip->set = zynq_gpio_set_value;
 718         chip->request = zynq_gpio_request;
 719         chip->free = zynq_gpio_free;
 720         chip->direction_input = zynq_gpio_dir_in;
 721         chip->direction_output = zynq_gpio_dir_out;
 722         chip->base = -1;
 723         chip->ngpio = gpio->p_data->ngpio;
 724
 725         /* Retrieve GPIO clock */
 726         gpio->clk = devm_clk_get(&pdev->dev, NULL);
 727         if (IS_ERR(gpio->clk)) {
 728                 dev_err(&pdev->dev, "input clock not found.\n");
 729                 return PTR_ERR(gpio->clk);
 730         }
 731         ret = clk_prepare_enable(gpio->clk);
 732         if (ret) {
 733                 dev_err(&pdev->dev, "Unable to enable clock.\n");
 734                 return ret;
 735         }
 736
 737         pm_runtime_set_active(&pdev->dev);
 738         pm_runtime_enable(&pdev->dev);
 739         ret = pm_runtime_get_sync(&pdev->dev);
 740         if (ret < 0)
 741                 goto err_pm_dis;
 742
 743         /* report a bug if gpio chip registration fails */
 744         ret = gpiochip_add_data(chip, gpio);
 745         if (ret) {
 746                 dev_err(&pdev->dev, "Failed to add gpio chip\n");
 747                 goto err_pm_put;
 748         }
 749
 750         /* disable interrupts for all banks */
 751         for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++)
 752                 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
 753                                ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
 754
 755         ret = gpiochip_irqchip_add(chip, &zynq_gpio_edge_irqchip, 0,
 756                                    handle_level_irq, IRQ_TYPE_NONE);
 757         if (ret) {
 758                 dev_err(&pdev->dev, "Failed to add irq chip\n");
 759                 goto err_rm_gpiochip;
 760         }
 761
 762         gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, gpio->irq,
 763                                      zynq_gpio_irqhandler);
 764
 765         pm_runtime_put(&pdev->dev);
 766
 767         return 0;
 768
 769 err_rm_gpiochip:
 770         gpiochip_remove(chip);
 771 err_pm_put:
 772         pm_runtime_put(&pdev->dev);
 773 err_pm_dis:
 774         pm_runtime_disable(&pdev->dev);
 775         clk_disable_unprepare(gpio->clk);
 776
 777         return ret;
 778 }
 779
 780 /**
 781  * zynq_gpio_remove - Driver removal function
 782  * @pdev:       platform device instance
 783  *
 784  * Return: 0 always
 785  */
 786 static int zynq_gpio_remove(struct platform_device *pdev)
 787 {
 788         struct zynq_gpio *gpio = platform_get_drvdata(pdev);
 789
 790         pm_runtime_get_sync(&pdev->dev);
 791         gpiochip_remove(&gpio->chip);
 792         clk_disable_unprepare(gpio->clk);
 793         device_set_wakeup_capable(&pdev->dev, 0);
 794         pm_runtime_disable(&pdev->dev);
 795         return 0;
 796 }
 797
 798 static struct platform_driver zynq_gpio_driver = {
 799         .driver = {
 800                 .name = DRIVER_NAME,
 801                 .pm = &zynq_gpio_dev_pm_ops,
 802                 .of_match_table = zynq_gpio_of_match,
 803         },
 804         .probe = zynq_gpio_probe,
 805         .remove = zynq_gpio_remove,
 806 };
 807
 808 /**
 809  * zynq_gpio_init - Initial driver registration call
 810  *
 811  * Return: value from platform_driver_register
 812  */
 813 static int __init zynq_gpio_init(void)
 814 {
 815         return platform_driver_register(&zynq_gpio_driver);
 816 }
 817 postcore_initcall(zynq_gpio_init);
 818
 819 static void __exit zynq_gpio_exit(void)
 820 {
 821         platform_driver_unregister(&zynq_gpio_driver);
 822 }
 823 module_exit(zynq_gpio_exit);
 824
 825 MODULE_AUTHOR("Xilinx Inc.");
 826 MODULE_DESCRIPTION("Zynq GPIO driver");
 827 MODULE_LICENSE("GPL");