drivers/gpio/langwell_gpio.c

   1 /* langwell_gpio.c Moorestown platform Langwell chip GPIO driver
   2  * Copyright (c) 2008 - 2009,  Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16  */
  17
  18 /* Supports:
  19  * Moorestown platform Langwell chip.
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/pci.h>
  24 #include <linux/kernel.h>
  25 #include <linux/delay.h>
  26 #include <linux/stddef.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/init.h>
  29 #include <linux/irq.h>
  30 #include <linux/io.h>
  31 #include <linux/gpio.h>
  32 #include <linux/slab.h>
  33
  34 struct lnw_gpio_register {
  35         u32     GPLR[2];
  36         u32     GPDR[2];
  37         u32     GPSR[2];
  38         u32     GPCR[2];
  39         u32     GRER[2];
  40         u32     GFER[2];
  41         u32     GEDR[2];
  42 };
  43
  44 struct lnw_gpio {
  45         struct gpio_chip                chip;
  46         struct lnw_gpio_register        *reg_base;
  47         spinlock_t                      lock;
  48         unsigned                        irq_base;
  49 };
  50
  51 static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
  52 {
  53         struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
  54         u8 reg = offset / 32;
  55         void __iomem *gplr;
  56
  57         gplr = (void __iomem *)(&lnw->reg_base->GPLR[reg]);
  58         return readl(gplr) & BIT(offset % 32);
  59 }
  60
  61 static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  62 {
  63         struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
  64         u8 reg = offset / 32;
  65         void __iomem *gpsr, *gpcr;
  66
  67         if (value) {
  68                 gpsr = (void __iomem *)(&lnw->reg_base->GPSR[reg]);
  69                 writel(BIT(offset % 32), gpsr);
  70         } else {
  71                 gpcr = (void __iomem *)(&lnw->reg_base->GPCR[reg]);
  72                 writel(BIT(offset % 32), gpcr);
  73         }
  74 }
  75
  76 static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  77 {
  78         struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
  79         u8 reg = offset / 32;
  80         u32 value;
  81         unsigned long flags;
  82         void __iomem *gpdr;
  83
  84         gpdr = (void __iomem *)(&lnw->reg_base->GPDR[reg]);
  85         spin_lock_irqsave(&lnw->lock, flags);
  86         value = readl(gpdr);
  87         value &= ~BIT(offset % 32);
  88         writel(value, gpdr);
  89         spin_unlock_irqrestore(&lnw->lock, flags);
  90         return 0;
  91 }
  92
  93 static int lnw_gpio_direction_output(struct gpio_chip *chip,
  94                         unsigned offset, int value)
  95 {
  96         struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
  97         u8 reg = offset / 32;
  98         unsigned long flags;
  99         void __iomem *gpdr;
 100
 101         lnw_gpio_set(chip, offset, value);
 102         gpdr = (void __iomem *)(&lnw->reg_base->GPDR[reg]);
 103         spin_lock_irqsave(&lnw->lock, flags);
 104         value = readl(gpdr);
 105         value |= BIT(offset % 32);;
 106         writel(value, gpdr);
 107         spin_unlock_irqrestore(&lnw->lock, flags);
 108         return 0;
 109 }
 110
 111 static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 112 {
 113         struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
 114         return lnw->irq_base + offset;
 115 }
 116
 117 static int lnw_irq_type(unsigned irq, unsigned type)
 118 {
 119         struct lnw_gpio *lnw = get_irq_chip_data(irq);
 120         u32 gpio = irq - lnw->irq_base;
 121         u8 reg = gpio / 32;
 122         unsigned long flags;
 123         u32 value;
 124         void __iomem *grer = (void __iomem *)(&lnw->reg_base->GRER[reg]);
 125         void __iomem *gfer = (void __iomem *)(&lnw->reg_base->GFER[reg]);
 126
 127         if (gpio >= lnw->chip.ngpio)
 128                 return -EINVAL;
 129         spin_lock_irqsave(&lnw->lock, flags);
 130         if (type & IRQ_TYPE_EDGE_RISING)
 131                 value = readl(grer) | BIT(gpio % 32);
 132         else
 133                 value = readl(grer) & (~BIT(gpio % 32));
 134         writel(value, grer);
 135
 136         if (type & IRQ_TYPE_EDGE_FALLING)
 137                 value = readl(gfer) | BIT(gpio % 32);
 138         else
 139                 value = readl(gfer) & (~BIT(gpio % 32));
 140         writel(value, gfer);
 141         spin_unlock_irqrestore(&lnw->lock, flags);
 142
 143         return 0;
 144 };
 145
 146 static void lnw_irq_unmask(unsigned irq)
 147 {
 148 };
 149
 150 static void lnw_irq_mask(unsigned irq)
 151 {
 152 };
 153
 154 static struct irq_chip lnw_irqchip = {
 155         .name           = "LNW-GPIO",
 156         .mask           = lnw_irq_mask,
 157         .unmask         = lnw_irq_unmask,
 158         .set_type       = lnw_irq_type,
 159 };
 160
 161 static struct pci_device_id lnw_gpio_ids[] = {
 162         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f) },
 163         { 0, }
 164 };
 165 MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
 166
 167 static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
 168 {
 169         struct lnw_gpio *lnw = (struct lnw_gpio *)get_irq_data(irq);
 170         u32 reg, gpio;
 171         void __iomem *gedr;
 172         u32 gedr_v;
 173
 174         /* check GPIO controller to check which pin triggered the interrupt */
 175         for (reg = 0; reg < lnw->chip.ngpio / 32; reg++) {
 176                 gedr = (void __iomem *)(&lnw->reg_base->GEDR[reg]);
 177                 gedr_v = readl(gedr);
 178                 if (!gedr_v)
 179                         continue;
 180                 for (gpio = reg*32; gpio < reg*32+32; gpio++)
 181                         if (gedr_v & BIT(gpio % 32)) {
 182                                 pr_debug("pin %d triggered\n", gpio);
 183                                 generic_handle_irq(lnw->irq_base + gpio);
 184                         }
 185                 /* clear the edge detect status bit */
 186                 writel(gedr_v, gedr);
 187         }
 188         desc->chip->eoi(irq);
 189 }
 190
 191 static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
 192                         const struct pci_device_id *id)
 193 {
 194         void *base;
 195         int i;
 196         resource_size_t start, len;
 197         struct lnw_gpio *lnw;
 198         u32 irq_base;
 199         u32 gpio_base;
 200         int retval = 0;
 201
 202         retval = pci_enable_device(pdev);
 203         if (retval)
 204                 goto done;
 205
 206         retval = pci_request_regions(pdev, "langwell_gpio");
 207         if (retval) {
 208                 dev_err(&pdev->dev, "error requesting resources\n");
 209                 goto err2;
 210         }
 211         /* get the irq_base from bar1 */
 212         start = pci_resource_start(pdev, 1);
 213         len = pci_resource_len(pdev, 1);
 214         base = ioremap_nocache(start, len);
 215         if (!base) {
 216                 dev_err(&pdev->dev, "error mapping bar1\n");
 217                 goto err3;
 218         }
 219         irq_base = *(u32 *)base;
 220         gpio_base = *((u32 *)base + 1);
 221         /* release the IO mapping, since we already get the info from bar1 */
 222         iounmap(base);
 223         /* get the register base from bar0 */
 224         start = pci_resource_start(pdev, 0);
 225         len = pci_resource_len(pdev, 0);
 226         base = ioremap_nocache(start, len);
 227         if (!base) {
 228                 dev_err(&pdev->dev, "error mapping bar0\n");
 229                 retval = -EFAULT;
 230                 goto err3;
 231         }
 232
 233         lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
 234         if (!lnw) {
 235                 dev_err(&pdev->dev, "can't allocate langwell_gpio chip data\n");
 236                 retval = -ENOMEM;
 237                 goto err4;
 238         }
 239         lnw->reg_base = base;
 240         lnw->irq_base = irq_base;
 241         lnw->chip.label = dev_name(&pdev->dev);
 242         lnw->chip.direction_input = lnw_gpio_direction_input;
 243         lnw->chip.direction_output = lnw_gpio_direction_output;
 244         lnw->chip.get = lnw_gpio_get;
 245         lnw->chip.set = lnw_gpio_set;
 246         lnw->chip.to_irq = lnw_gpio_to_irq;
 247         lnw->chip.base = gpio_base;
 248         lnw->chip.ngpio = 64;
 249         lnw->chip.can_sleep = 0;
 250         pci_set_drvdata(pdev, lnw);
 251         retval = gpiochip_add(&lnw->chip);
 252         if (retval) {
 253                 dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
 254                 goto err5;
 255         }
 256         set_irq_data(pdev->irq, lnw);
 257         set_irq_chained_handler(pdev->irq, lnw_irq_handler);
 258         for (i = 0; i < lnw->chip.ngpio; i++) {
 259                 set_irq_chip_and_handler_name(i + lnw->irq_base, &lnw_irqchip,
 260                                         handle_simple_irq, "demux");
 261                 set_irq_chip_data(i + lnw->irq_base, lnw);
 262         }
 263
 264         spin_lock_init(&lnw->lock);
 265         goto done;
 266 err5:
 267         kfree(lnw);
 268 err4:
 269         iounmap(base);
 270 err3:
 271         pci_release_regions(pdev);
 272 err2:
 273         pci_disable_device(pdev);
 274 done:
 275         return retval;
 276 }
 277
 278 static struct pci_driver lnw_gpio_driver = {
 279         .name           = "langwell_gpio",
 280         .id_table       = lnw_gpio_ids,
 281         .probe          = lnw_gpio_probe,
 282 };
 283
 284 static int __init lnw_gpio_init(void)
 285 {
 286         return pci_register_driver(&lnw_gpio_driver);
 287 }
 288
 289 device_initcall(lnw_gpio_init);