drivers/gpio/timbgpio.c

   1 /*
   2  * timbgpio.c timberdale FPGA GPIO driver
   3  * Copyright (c) 2009 Intel Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 /* Supports:
  20  * Timberdale FPGA GPIO
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/gpio.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/irq.h>
  27 #include <linux/io.h>
  28 #include <linux/timb_gpio.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/slab.h>
  31
  32 #define DRIVER_NAME "timb-gpio"
  33
  34 #define TGPIOVAL        0x00
  35 #define TGPIODIR        0x04
  36 #define TGPIO_IER       0x08
  37 #define TGPIO_ISR       0x0c
  38 #define TGPIO_IPR       0x10
  39 #define TGPIO_ICR       0x14
  40 #define TGPIO_FLR       0x18
  41 #define TGPIO_LVR       0x1c
  42 #define TGPIO_VER       0x20
  43 #define TGPIO_BFLR      0x24
  44
  45 struct timbgpio {
  46         void __iomem            *membase;
  47         spinlock_t              lock; /* mutual exclusion */
  48         struct gpio_chip        gpio;
  49         int                     irq_base;
  50 };
  51
  52 static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
  53         unsigned offset, bool enabled)
  54 {
  55         struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
  56         u32 reg;
  57
  58         spin_lock(&tgpio->lock);
  59         reg = ioread32(tgpio->membase + offset);
  60
  61         if (enabled)
  62                 reg |= (1 << index);
  63         else
  64                 reg &= ~(1 << index);
  65
  66         iowrite32(reg, tgpio->membase + offset);
  67         spin_unlock(&tgpio->lock);
  68
  69         return 0;
  70 }
  71
  72 static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
  73 {
  74         return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
  75 }
  76
  77 static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
  78 {
  79         struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
  80         u32 value;
  81
  82         value = ioread32(tgpio->membase + TGPIOVAL);
  83         return (value & (1 << nr)) ? 1 : 0;
  84 }
  85
  86 static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
  87                                                 unsigned nr, int val)
  88 {
  89         return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
  90 }
  91
  92 static void timbgpio_gpio_set(struct gpio_chip *gpio,
  93                                 unsigned nr, int val)
  94 {
  95         timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
  96 }
  97
  98 static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
  99 {
 100         struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
 101
 102         if (tgpio->irq_base <= 0)
 103                 return -EINVAL;
 104
 105         return tgpio->irq_base + offset;
 106 }
 107
 108 /*
 109  * GPIO IRQ
 110  */
 111 static void timbgpio_irq_disable(unsigned irq)
 112 {
 113         struct timbgpio *tgpio = get_irq_chip_data(irq);
 114         int offset = irq - tgpio->irq_base;
 115
 116         timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 0);
 117 }
 118
 119 static void timbgpio_irq_enable(unsigned irq)
 120 {
 121         struct timbgpio *tgpio = get_irq_chip_data(irq);
 122         int offset = irq - tgpio->irq_base;
 123
 124         timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 1);
 125 }
 126
 127 static int timbgpio_irq_type(unsigned irq, unsigned trigger)
 128 {
 129         struct timbgpio *tgpio = get_irq_chip_data(irq);
 130         int offset = irq - tgpio->irq_base;
 131         unsigned long flags;
 132         u32 lvr, flr, bflr = 0;
 133         u32 ver;
 134
 135         if (offset < 0 || offset > tgpio->gpio.ngpio)
 136                 return -EINVAL;
 137
 138         ver = ioread32(tgpio->membase + TGPIO_VER);
 139
 140         spin_lock_irqsave(&tgpio->lock, flags);
 141
 142         lvr = ioread32(tgpio->membase + TGPIO_LVR);
 143         flr = ioread32(tgpio->membase + TGPIO_FLR);
 144         if (ver > 2)
 145                 bflr = ioread32(tgpio->membase + TGPIO_BFLR);
 146
 147         if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 148                 bflr &= ~(1 << offset);
 149                 flr &= ~(1 << offset);
 150                 if (trigger & IRQ_TYPE_LEVEL_HIGH)
 151                         lvr |= 1 << offset;
 152                 else
 153                         lvr &= ~(1 << offset);
 154         }
 155
 156         if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
 157                 if (ver < 3)
 158                         return -EINVAL;
 159                 else {
 160                         flr |= 1 << offset;
 161                         bflr |= 1 << offset;
 162                 }
 163         } else {
 164                 bflr &= ~(1 << offset);
 165                 flr |= 1 << offset;
 166                 if (trigger & IRQ_TYPE_EDGE_FALLING)
 167                         lvr &= ~(1 << offset);
 168                 else
 169                         lvr |= 1 << offset;
 170         }
 171
 172         iowrite32(lvr, tgpio->membase + TGPIO_LVR);
 173         iowrite32(flr, tgpio->membase + TGPIO_FLR);
 174         if (ver > 2)
 175                 iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
 176
 177         iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
 178         spin_unlock_irqrestore(&tgpio->lock, flags);
 179
 180         return 0;
 181 }
 182
 183 static void timbgpio_irq(unsigned int irq, struct irq_desc *desc)
 184 {
 185         struct timbgpio *tgpio = get_irq_data(irq);
 186         unsigned long ipr;
 187         int offset;
 188
 189         desc->chip->ack(irq);
 190         ipr = ioread32(tgpio->membase + TGPIO_IPR);
 191         iowrite32(ipr, tgpio->membase + TGPIO_ICR);
 192
 193         for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
 194                 generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
 195 }
 196
 197 static struct irq_chip timbgpio_irqchip = {
 198         .name           = "GPIO",
 199         .enable         = timbgpio_irq_enable,
 200         .disable        = timbgpio_irq_disable,
 201         .set_type       = timbgpio_irq_type,
 202 };
 203
 204 static int __devinit timbgpio_probe(struct platform_device *pdev)
 205 {
 206         int err, i;
 207         struct gpio_chip *gc;
 208         struct timbgpio *tgpio;
 209         struct resource *iomem;
 210         struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
 211         int irq = platform_get_irq(pdev, 0);
 212
 213         if (!pdata || pdata->nr_pins > 32) {
 214                 err = -EINVAL;
 215                 goto err_mem;
 216         }
 217
 218         iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 219         if (!iomem) {
 220                 err = -EINVAL;
 221                 goto err_mem;
 222         }
 223
 224         tgpio = kzalloc(sizeof(*tgpio), GFP_KERNEL);
 225         if (!tgpio) {
 226                 err = -EINVAL;
 227                 goto err_mem;
 228         }
 229         tgpio->irq_base = pdata->irq_base;
 230
 231         spin_lock_init(&tgpio->lock);
 232
 233         if (!request_mem_region(iomem->start, resource_size(iomem),
 234                 DRIVER_NAME)) {
 235                 err = -EBUSY;
 236                 goto err_request;
 237         }
 238
 239         tgpio->membase = ioremap(iomem->start, resource_size(iomem));
 240         if (!tgpio->membase) {
 241                 err = -ENOMEM;
 242                 goto err_ioremap;
 243         }
 244
 245         gc = &tgpio->gpio;
 246
 247         gc->label = dev_name(&pdev->dev);
 248         gc->owner = THIS_MODULE;
 249         gc->dev = &pdev->dev;
 250         gc->direction_input = timbgpio_gpio_direction_input;
 251         gc->get = timbgpio_gpio_get;
 252         gc->direction_output = timbgpio_gpio_direction_output;
 253         gc->set = timbgpio_gpio_set;
 254         gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
 255         gc->dbg_show = NULL;
 256         gc->base = pdata->gpio_base;
 257         gc->ngpio = pdata->nr_pins;
 258         gc->can_sleep = 0;
 259
 260         err = gpiochip_add(gc);
 261         if (err)
 262                 goto err_chipadd;
 263
 264         platform_set_drvdata(pdev, tgpio);
 265
 266         /* make sure to disable interrupts */
 267         iowrite32(0x0, tgpio->membase + TGPIO_IER);
 268
 269         if (irq < 0 || tgpio->irq_base <= 0)
 270                 return 0;
 271
 272         for (i = 0; i < pdata->nr_pins; i++) {
 273                 set_irq_chip_and_handler_name(tgpio->irq_base + i,
 274                         &timbgpio_irqchip, handle_simple_irq, "mux");
 275                 set_irq_chip_data(tgpio->irq_base + i, tgpio);
 276 #ifdef CONFIG_ARM
 277                 set_irq_flags(tgpio->irq_base + i, IRQF_VALID | IRQF_PROBE);
 278 #endif
 279         }
 280
 281         set_irq_data(irq, tgpio);
 282         set_irq_chained_handler(irq, timbgpio_irq);
 283
 284         return 0;
 285
 286 err_chipadd:
 287         iounmap(tgpio->membase);
 288 err_ioremap:
 289         release_mem_region(iomem->start, resource_size(iomem));
 290 err_request:
 291         kfree(tgpio);
 292 err_mem:
 293         printk(KERN_ERR DRIVER_NAME": Failed to register GPIOs: %d\n", err);
 294
 295         return err;
 296 }
 297
 298 static int __devexit timbgpio_remove(struct platform_device *pdev)
 299 {
 300         int err;
 301         struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
 302         struct timbgpio *tgpio = platform_get_drvdata(pdev);
 303         struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 304         int irq = platform_get_irq(pdev, 0);
 305
 306         if (irq >= 0 && tgpio->irq_base > 0) {
 307                 int i;
 308                 for (i = 0; i < pdata->nr_pins; i++) {
 309                         set_irq_chip(tgpio->irq_base + i, NULL);
 310                         set_irq_chip_data(tgpio->irq_base + i, NULL);
 311                 }
 312
 313                 set_irq_handler(irq, NULL);
 314                 set_irq_data(irq, NULL);
 315         }
 316
 317         err = gpiochip_remove(&tgpio->gpio);
 318         if (err)
 319                 printk(KERN_ERR DRIVER_NAME": failed to remove gpio_chip\n");
 320
 321         iounmap(tgpio->membase);
 322         release_mem_region(iomem->start, resource_size(iomem));
 323         kfree(tgpio);
 324
 325         platform_set_drvdata(pdev, NULL);
 326
 327         return 0;
 328 }
 329
 330 static struct platform_driver timbgpio_platform_driver = {
 331         .driver = {
 332                 .name   = DRIVER_NAME,
 333                 .owner  = THIS_MODULE,
 334         },
 335         .probe          = timbgpio_probe,
 336         .remove         = timbgpio_remove,
 337 };
 338
 339 /*--------------------------------------------------------------------------*/
 340
 341 static int __init timbgpio_init(void)
 342 {
 343         return platform_driver_register(&timbgpio_platform_driver);
 344 }
 345
 346 static void __exit timbgpio_exit(void)
 347 {
 348         platform_driver_unregister(&timbgpio_platform_driver);
 349 }
 350
 351 module_init(timbgpio_init);
 352 module_exit(timbgpio_exit);
 353
 354 MODULE_DESCRIPTION("Timberdale GPIO driver");
 355 MODULE_LICENSE("GPL v2");
 356 MODULE_AUTHOR("Mocean Laboratories");
 357 MODULE_ALIAS("platform:"DRIVER_NAME);
 358