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Merge tag 'vmwgfx-next-160316' of git://people.freedesktop.org/~thomash/linux into...
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
38
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
44
45 #include <drm/drmP.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
48
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_gds.h"
55 #include "amd_powerplay.h"
56 #include "amdgpu_acp.h"
57
58 #include "gpu_scheduler.h"
59
60 /*
61 * Modules parameters.
62 */
63 extern int amdgpu_modeset;
64 extern int amdgpu_vram_limit;
65 extern int amdgpu_gart_size;
66 extern int amdgpu_benchmarking;
67 extern int amdgpu_testing;
68 extern int amdgpu_audio;
69 extern int amdgpu_disp_priority;
70 extern int amdgpu_hw_i2c;
71 extern int amdgpu_pcie_gen2;
72 extern int amdgpu_msi;
73 extern int amdgpu_lockup_timeout;
74 extern int amdgpu_dpm;
75 extern int amdgpu_smc_load_fw;
76 extern int amdgpu_aspm;
77 extern int amdgpu_runtime_pm;
78 extern unsigned amdgpu_ip_block_mask;
79 extern int amdgpu_bapm;
80 extern int amdgpu_deep_color;
81 extern int amdgpu_vm_size;
82 extern int amdgpu_vm_block_size;
83 extern int amdgpu_vm_fault_stop;
84 extern int amdgpu_vm_debug;
85 extern int amdgpu_sched_jobs;
86 extern int amdgpu_sched_hw_submission;
87 extern int amdgpu_powerplay;
88 extern unsigned amdgpu_pcie_gen_cap;
89 extern unsigned amdgpu_pcie_lane_cap;
90
91 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
92 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
93 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
94 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
95 #define AMDGPU_IB_POOL_SIZE 16
96 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
97 #define AMDGPUFB_CONN_LIMIT 4
98 #define AMDGPU_BIOS_NUM_SCRATCH 8
99
100 /* max number of rings */
101 #define AMDGPU_MAX_RINGS 16
102 #define AMDGPU_MAX_GFX_RINGS 1
103 #define AMDGPU_MAX_COMPUTE_RINGS 8
104 #define AMDGPU_MAX_VCE_RINGS 2
105
106 /* max number of IP instances */
107 #define AMDGPU_MAX_SDMA_INSTANCES 2
108
109 /* hardcode that limit for now */
110 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
111
112 /* hard reset data */
113 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
114
115 /* reset flags */
116 #define AMDGPU_RESET_GFX (1 << 0)
117 #define AMDGPU_RESET_COMPUTE (1 << 1)
118 #define AMDGPU_RESET_DMA (1 << 2)
119 #define AMDGPU_RESET_CP (1 << 3)
120 #define AMDGPU_RESET_GRBM (1 << 4)
121 #define AMDGPU_RESET_DMA1 (1 << 5)
122 #define AMDGPU_RESET_RLC (1 << 6)
123 #define AMDGPU_RESET_SEM (1 << 7)
124 #define AMDGPU_RESET_IH (1 << 8)
125 #define AMDGPU_RESET_VMC (1 << 9)
126 #define AMDGPU_RESET_MC (1 << 10)
127 #define AMDGPU_RESET_DISPLAY (1 << 11)
128 #define AMDGPU_RESET_UVD (1 << 12)
129 #define AMDGPU_RESET_VCE (1 << 13)
130 #define AMDGPU_RESET_VCE1 (1 << 14)
131
132 /* GFX current status */
133 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
134 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
135 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
136 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
137 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
138
139 /* max cursor sizes (in pixels) */
140 #define CIK_CURSOR_WIDTH 128
141 #define CIK_CURSOR_HEIGHT 128
142
143 struct amdgpu_device;
144 struct amdgpu_fence;
145 struct amdgpu_ib;
146 struct amdgpu_vm;
147 struct amdgpu_ring;
148 struct amdgpu_cs_parser;
149 struct amdgpu_job;
150 struct amdgpu_irq_src;
151 struct amdgpu_fpriv;
152
153 enum amdgpu_cp_irq {
154 AMDGPU_CP_IRQ_GFX_EOP = 0,
155 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
156 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
157 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
158 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
159 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
160 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
161 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
162 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
163
164 AMDGPU_CP_IRQ_LAST
165 };
166
167 enum amdgpu_sdma_irq {
168 AMDGPU_SDMA_IRQ_TRAP0 = 0,
169 AMDGPU_SDMA_IRQ_TRAP1,
170
171 AMDGPU_SDMA_IRQ_LAST
172 };
173
174 enum amdgpu_thermal_irq {
175 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
176 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
177
178 AMDGPU_THERMAL_IRQ_LAST
179 };
180
181 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
182 enum amd_ip_block_type block_type,
183 enum amd_clockgating_state state);
184 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
185 enum amd_ip_block_type block_type,
186 enum amd_powergating_state state);
187
188 struct amdgpu_ip_block_version {
189 enum amd_ip_block_type type;
190 u32 major;
191 u32 minor;
192 u32 rev;
193 const struct amd_ip_funcs *funcs;
194 };
195
196 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
197 enum amd_ip_block_type type,
198 u32 major, u32 minor);
199
200 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
201 struct amdgpu_device *adev,
202 enum amd_ip_block_type type);
203
204 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
205 struct amdgpu_buffer_funcs {
206 /* maximum bytes in a single operation */
207 uint32_t copy_max_bytes;
208
209 /* number of dw to reserve per operation */
210 unsigned copy_num_dw;
211
212 /* used for buffer migration */
213 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
214 /* src addr in bytes */
215 uint64_t src_offset,
216 /* dst addr in bytes */
217 uint64_t dst_offset,
218 /* number of byte to transfer */
219 uint32_t byte_count);
220
221 /* maximum bytes in a single operation */
222 uint32_t fill_max_bytes;
223
224 /* number of dw to reserve per operation */
225 unsigned fill_num_dw;
226
227 /* used for buffer clearing */
228 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
229 /* value to write to memory */
230 uint32_t src_data,
231 /* dst addr in bytes */
232 uint64_t dst_offset,
233 /* number of byte to fill */
234 uint32_t byte_count);
235 };
236
237 /* provided by hw blocks that can write ptes, e.g., sdma */
238 struct amdgpu_vm_pte_funcs {
239 /* copy pte entries from GART */
240 void (*copy_pte)(struct amdgpu_ib *ib,
241 uint64_t pe, uint64_t src,
242 unsigned count);
243 /* write pte one entry at a time with addr mapping */
244 void (*write_pte)(struct amdgpu_ib *ib,
245 const dma_addr_t *pages_addr, uint64_t pe,
246 uint64_t addr, unsigned count,
247 uint32_t incr, uint32_t flags);
248 /* for linear pte/pde updates without addr mapping */
249 void (*set_pte_pde)(struct amdgpu_ib *ib,
250 uint64_t pe,
251 uint64_t addr, unsigned count,
252 uint32_t incr, uint32_t flags);
253 };
254
255 /* provided by the gmc block */
256 struct amdgpu_gart_funcs {
257 /* flush the vm tlb via mmio */
258 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
259 uint32_t vmid);
260 /* write pte/pde updates using the cpu */
261 int (*set_pte_pde)(struct amdgpu_device *adev,
262 void *cpu_pt_addr, /* cpu addr of page table */
263 uint32_t gpu_page_idx, /* pte/pde to update */
264 uint64_t addr, /* addr to write into pte/pde */
265 uint32_t flags); /* access flags */
266 };
267
268 /* provided by the ih block */
269 struct amdgpu_ih_funcs {
270 /* ring read/write ptr handling, called from interrupt context */
271 u32 (*get_wptr)(struct amdgpu_device *adev);
272 void (*decode_iv)(struct amdgpu_device *adev,
273 struct amdgpu_iv_entry *entry);
274 void (*set_rptr)(struct amdgpu_device *adev);
275 };
276
277 /* provided by hw blocks that expose a ring buffer for commands */
278 struct amdgpu_ring_funcs {
279 /* ring read/write ptr handling */
280 u32 (*get_rptr)(struct amdgpu_ring *ring);
281 u32 (*get_wptr)(struct amdgpu_ring *ring);
282 void (*set_wptr)(struct amdgpu_ring *ring);
283 /* validating and patching of IBs */
284 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
285 /* command emit functions */
286 void (*emit_ib)(struct amdgpu_ring *ring,
287 struct amdgpu_ib *ib);
288 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
289 uint64_t seq, unsigned flags);
290 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
291 uint64_t pd_addr);
292 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
293 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
294 uint32_t gds_base, uint32_t gds_size,
295 uint32_t gws_base, uint32_t gws_size,
296 uint32_t oa_base, uint32_t oa_size);
297 /* testing functions */
298 int (*test_ring)(struct amdgpu_ring *ring);
299 int (*test_ib)(struct amdgpu_ring *ring);
300 /* insert NOP packets */
301 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
302 /* pad the indirect buffer to the necessary number of dw */
303 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
304 };
305
306 /*
307 * BIOS.
308 */
309 bool amdgpu_get_bios(struct amdgpu_device *adev);
310 bool amdgpu_read_bios(struct amdgpu_device *adev);
311
312 /*
313 * Dummy page
314 */
315 struct amdgpu_dummy_page {
316 struct page *page;
317 dma_addr_t addr;
318 };
319 int amdgpu_dummy_page_init(struct amdgpu_device *adev);
320 void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
321
322
323 /*
324 * Clocks
325 */
326
327 #define AMDGPU_MAX_PPLL 3
328
329 struct amdgpu_clock {
330 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
331 struct amdgpu_pll spll;
332 struct amdgpu_pll mpll;
333 /* 10 Khz units */
334 uint32_t default_mclk;
335 uint32_t default_sclk;
336 uint32_t default_dispclk;
337 uint32_t current_dispclk;
338 uint32_t dp_extclk;
339 uint32_t max_pixel_clock;
340 };
341
342 /*
343 * Fences.
344 */
345 struct amdgpu_fence_driver {
346 uint64_t gpu_addr;
347 volatile uint32_t *cpu_addr;
348 /* sync_seq is protected by ring emission lock */
349 uint64_t sync_seq;
350 atomic64_t last_seq;
351 bool initialized;
352 struct amdgpu_irq_src *irq_src;
353 unsigned irq_type;
354 struct timer_list fallback_timer;
355 wait_queue_head_t fence_queue;
356 };
357
358 /* some special values for the owner field */
359 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
360 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
361
362 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
363 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
364
365 struct amdgpu_fence {
366 struct fence base;
367
368 /* RB, DMA, etc. */
369 struct amdgpu_ring *ring;
370 uint64_t seq;
371
372 /* filp or special value for fence creator */
373 void *owner;
374
375 wait_queue_t fence_wake;
376 };
377
378 struct amdgpu_user_fence {
379 /* write-back bo */
380 struct amdgpu_bo *bo;
381 /* write-back address offset to bo start */
382 uint32_t offset;
383 };
384
385 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
386 void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
387 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
388
389 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
390 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
391 struct amdgpu_irq_src *irq_src,
392 unsigned irq_type);
393 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
394 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
395 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
396 struct amdgpu_fence **fence);
397 void amdgpu_fence_process(struct amdgpu_ring *ring);
398 int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
399 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
400 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
401
402 /*
403 * TTM.
404 */
405 struct amdgpu_mman {
406 struct ttm_bo_global_ref bo_global_ref;
407 struct drm_global_reference mem_global_ref;
408 struct ttm_bo_device bdev;
409 bool mem_global_referenced;
410 bool initialized;
411
412 #if defined(CONFIG_DEBUG_FS)
413 struct dentry *vram;
414 struct dentry *gtt;
415 #endif
416
417 /* buffer handling */
418 const struct amdgpu_buffer_funcs *buffer_funcs;
419 struct amdgpu_ring *buffer_funcs_ring;
420 /* Scheduler entity for buffer moves */
421 struct amd_sched_entity entity;
422 };
423
424 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
425 uint64_t src_offset,
426 uint64_t dst_offset,
427 uint32_t byte_count,
428 struct reservation_object *resv,
429 struct fence **fence);
430 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
431
432 struct amdgpu_bo_list_entry {
433 struct amdgpu_bo *robj;
434 struct ttm_validate_buffer tv;
435 struct amdgpu_bo_va *bo_va;
436 uint32_t priority;
437 };
438
439 struct amdgpu_bo_va_mapping {
440 struct list_head list;
441 struct interval_tree_node it;
442 uint64_t offset;
443 uint32_t flags;
444 };
445
446 /* bo virtual addresses in a specific vm */
447 struct amdgpu_bo_va {
448 struct mutex mutex;
449 /* protected by bo being reserved */
450 struct list_head bo_list;
451 struct fence *last_pt_update;
452 unsigned ref_count;
453
454 /* protected by vm mutex and spinlock */
455 struct list_head vm_status;
456
457 /* mappings for this bo_va */
458 struct list_head invalids;
459 struct list_head valids;
460
461 /* constant after initialization */
462 struct amdgpu_vm *vm;
463 struct amdgpu_bo *bo;
464 };
465
466 #define AMDGPU_GEM_DOMAIN_MAX 0x3
467
468 struct amdgpu_bo {
469 /* Protected by gem.mutex */
470 struct list_head list;
471 /* Protected by tbo.reserved */
472 u32 prefered_domains;
473 u32 allowed_domains;
474 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
475 struct ttm_placement placement;
476 struct ttm_buffer_object tbo;
477 struct ttm_bo_kmap_obj kmap;
478 u64 flags;
479 unsigned pin_count;
480 void *kptr;
481 u64 tiling_flags;
482 u64 metadata_flags;
483 void *metadata;
484 u32 metadata_size;
485 /* list of all virtual address to which this bo
486 * is associated to
487 */
488 struct list_head va;
489 /* Constant after initialization */
490 struct amdgpu_device *adev;
491 struct drm_gem_object gem_base;
492 struct amdgpu_bo *parent;
493
494 struct ttm_bo_kmap_obj dma_buf_vmap;
495 struct amdgpu_mn *mn;
496 struct list_head mn_list;
497 };
498 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
499
500 void amdgpu_gem_object_free(struct drm_gem_object *obj);
501 int amdgpu_gem_object_open(struct drm_gem_object *obj,
502 struct drm_file *file_priv);
503 void amdgpu_gem_object_close(struct drm_gem_object *obj,
504 struct drm_file *file_priv);
505 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
506 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
507 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
508 struct dma_buf_attachment *attach,
509 struct sg_table *sg);
510 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
511 struct drm_gem_object *gobj,
512 int flags);
513 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
514 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
515 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
516 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
517 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
518 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
519
520 /* sub-allocation manager, it has to be protected by another lock.
521 * By conception this is an helper for other part of the driver
522 * like the indirect buffer or semaphore, which both have their
523 * locking.
524 *
525 * Principe is simple, we keep a list of sub allocation in offset
526 * order (first entry has offset == 0, last entry has the highest
527 * offset).
528 *
529 * When allocating new object we first check if there is room at
530 * the end total_size - (last_object_offset + last_object_size) >=
531 * alloc_size. If so we allocate new object there.
532 *
533 * When there is not enough room at the end, we start waiting for
534 * each sub object until we reach object_offset+object_size >=
535 * alloc_size, this object then become the sub object we return.
536 *
537 * Alignment can't be bigger than page size.
538 *
539 * Hole are not considered for allocation to keep things simple.
540 * Assumption is that there won't be hole (all object on same
541 * alignment).
542 */
543 struct amdgpu_sa_manager {
544 wait_queue_head_t wq;
545 struct amdgpu_bo *bo;
546 struct list_head *hole;
547 struct list_head flist[AMDGPU_MAX_RINGS];
548 struct list_head olist;
549 unsigned size;
550 uint64_t gpu_addr;
551 void *cpu_ptr;
552 uint32_t domain;
553 uint32_t align;
554 };
555
556 /* sub-allocation buffer */
557 struct amdgpu_sa_bo {
558 struct list_head olist;
559 struct list_head flist;
560 struct amdgpu_sa_manager *manager;
561 unsigned soffset;
562 unsigned eoffset;
563 struct fence *fence;
564 };
565
566 /*
567 * GEM objects.
568 */
569 void amdgpu_gem_force_release(struct amdgpu_device *adev);
570 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
571 int alignment, u32 initial_domain,
572 u64 flags, bool kernel,
573 struct drm_gem_object **obj);
574
575 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
576 struct drm_device *dev,
577 struct drm_mode_create_dumb *args);
578 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
579 struct drm_device *dev,
580 uint32_t handle, uint64_t *offset_p);
581 /*
582 * Synchronization
583 */
584 struct amdgpu_sync {
585 DECLARE_HASHTABLE(fences, 4);
586 struct fence *last_vm_update;
587 };
588
589 void amdgpu_sync_create(struct amdgpu_sync *sync);
590 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
591 struct fence *f);
592 int amdgpu_sync_resv(struct amdgpu_device *adev,
593 struct amdgpu_sync *sync,
594 struct reservation_object *resv,
595 void *owner);
596 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
597 int amdgpu_sync_wait(struct amdgpu_sync *sync);
598 void amdgpu_sync_free(struct amdgpu_sync *sync);
599
600 /*
601 * GART structures, functions & helpers
602 */
603 struct amdgpu_mc;
604
605 #define AMDGPU_GPU_PAGE_SIZE 4096
606 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
607 #define AMDGPU_GPU_PAGE_SHIFT 12
608 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
609
610 struct amdgpu_gart {
611 dma_addr_t table_addr;
612 struct amdgpu_bo *robj;
613 void *ptr;
614 unsigned num_gpu_pages;
615 unsigned num_cpu_pages;
616 unsigned table_size;
617 struct page **pages;
618 dma_addr_t *pages_addr;
619 bool ready;
620 const struct amdgpu_gart_funcs *gart_funcs;
621 };
622
623 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
624 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
625 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
626 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
627 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
628 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
629 int amdgpu_gart_init(struct amdgpu_device *adev);
630 void amdgpu_gart_fini(struct amdgpu_device *adev);
631 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
632 int pages);
633 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
634 int pages, struct page **pagelist,
635 dma_addr_t *dma_addr, uint32_t flags);
636
637 /*
638 * GPU MC structures, functions & helpers
639 */
640 struct amdgpu_mc {
641 resource_size_t aper_size;
642 resource_size_t aper_base;
643 resource_size_t agp_base;
644 /* for some chips with <= 32MB we need to lie
645 * about vram size near mc fb location */
646 u64 mc_vram_size;
647 u64 visible_vram_size;
648 u64 gtt_size;
649 u64 gtt_start;
650 u64 gtt_end;
651 u64 vram_start;
652 u64 vram_end;
653 unsigned vram_width;
654 u64 real_vram_size;
655 int vram_mtrr;
656 u64 gtt_base_align;
657 u64 mc_mask;
658 const struct firmware *fw; /* MC firmware */
659 uint32_t fw_version;
660 struct amdgpu_irq_src vm_fault;
661 uint32_t vram_type;
662 };
663
664 /*
665 * GPU doorbell structures, functions & helpers
666 */
667 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
668 {
669 AMDGPU_DOORBELL_KIQ = 0x000,
670 AMDGPU_DOORBELL_HIQ = 0x001,
671 AMDGPU_DOORBELL_DIQ = 0x002,
672 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
673 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
674 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
675 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
676 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
677 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
678 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
679 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
680 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
681 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
682 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
683 AMDGPU_DOORBELL_IH = 0x1E8,
684 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
685 AMDGPU_DOORBELL_INVALID = 0xFFFF
686 } AMDGPU_DOORBELL_ASSIGNMENT;
687
688 struct amdgpu_doorbell {
689 /* doorbell mmio */
690 resource_size_t base;
691 resource_size_t size;
692 u32 __iomem *ptr;
693 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
694 };
695
696 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
697 phys_addr_t *aperture_base,
698 size_t *aperture_size,
699 size_t *start_offset);
700
701 /*
702 * IRQS.
703 */
704
705 struct amdgpu_flip_work {
706 struct work_struct flip_work;
707 struct work_struct unpin_work;
708 struct amdgpu_device *adev;
709 int crtc_id;
710 uint64_t base;
711 struct drm_pending_vblank_event *event;
712 struct amdgpu_bo *old_rbo;
713 struct fence *excl;
714 unsigned shared_count;
715 struct fence **shared;
716 struct fence_cb cb;
717 };
718
719
720 /*
721 * CP & rings.
722 */
723
724 struct amdgpu_ib {
725 struct amdgpu_sa_bo *sa_bo;
726 uint32_t length_dw;
727 uint64_t gpu_addr;
728 uint32_t *ptr;
729 struct amdgpu_fence *fence;
730 struct amdgpu_user_fence *user;
731 struct amdgpu_vm *vm;
732 unsigned vm_id;
733 uint64_t vm_pd_addr;
734 struct amdgpu_ctx *ctx;
735 uint32_t gds_base, gds_size;
736 uint32_t gws_base, gws_size;
737 uint32_t oa_base, oa_size;
738 uint32_t flags;
739 /* resulting sequence number */
740 uint64_t sequence;
741 };
742
743 enum amdgpu_ring_type {
744 AMDGPU_RING_TYPE_GFX,
745 AMDGPU_RING_TYPE_COMPUTE,
746 AMDGPU_RING_TYPE_SDMA,
747 AMDGPU_RING_TYPE_UVD,
748 AMDGPU_RING_TYPE_VCE
749 };
750
751 extern struct amd_sched_backend_ops amdgpu_sched_ops;
752
753 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
754 struct amdgpu_job **job);
755 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
756 struct amdgpu_job **job);
757 void amdgpu_job_free(struct amdgpu_job *job);
758 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
759 struct amd_sched_entity *entity, void *owner,
760 struct fence **f);
761
762 struct amdgpu_ring {
763 struct amdgpu_device *adev;
764 const struct amdgpu_ring_funcs *funcs;
765 struct amdgpu_fence_driver fence_drv;
766 struct amd_gpu_scheduler sched;
767
768 spinlock_t fence_lock;
769 struct amdgpu_bo *ring_obj;
770 volatile uint32_t *ring;
771 unsigned rptr_offs;
772 u64 next_rptr_gpu_addr;
773 volatile u32 *next_rptr_cpu_addr;
774 unsigned wptr;
775 unsigned wptr_old;
776 unsigned ring_size;
777 unsigned max_dw;
778 int count_dw;
779 uint64_t gpu_addr;
780 uint32_t align_mask;
781 uint32_t ptr_mask;
782 bool ready;
783 u32 nop;
784 u32 idx;
785 u32 me;
786 u32 pipe;
787 u32 queue;
788 struct amdgpu_bo *mqd_obj;
789 u32 doorbell_index;
790 bool use_doorbell;
791 unsigned wptr_offs;
792 unsigned next_rptr_offs;
793 unsigned fence_offs;
794 struct amdgpu_ctx *current_ctx;
795 enum amdgpu_ring_type type;
796 char name[16];
797 };
798
799 /*
800 * VM
801 */
802
803 /* maximum number of VMIDs */
804 #define AMDGPU_NUM_VM 16
805
806 /* number of entries in page table */
807 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
808
809 /* PTBs (Page Table Blocks) need to be aligned to 32K */
810 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
811 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
812 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
813
814 #define AMDGPU_PTE_VALID (1 << 0)
815 #define AMDGPU_PTE_SYSTEM (1 << 1)
816 #define AMDGPU_PTE_SNOOPED (1 << 2)
817
818 /* VI only */
819 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
820
821 #define AMDGPU_PTE_READABLE (1 << 5)
822 #define AMDGPU_PTE_WRITEABLE (1 << 6)
823
824 /* PTE (Page Table Entry) fragment field for different page sizes */
825 #define AMDGPU_PTE_FRAG_4KB (0 << 7)
826 #define AMDGPU_PTE_FRAG_64KB (4 << 7)
827 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
828
829 /* How to programm VM fault handling */
830 #define AMDGPU_VM_FAULT_STOP_NEVER 0
831 #define AMDGPU_VM_FAULT_STOP_FIRST 1
832 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
833
834 struct amdgpu_vm_pt {
835 struct amdgpu_bo_list_entry entry;
836 uint64_t addr;
837 };
838
839 struct amdgpu_vm_id {
840 struct amdgpu_vm_manager_id *mgr_id;
841 uint64_t pd_gpu_addr;
842 /* last flushed PD/PT update */
843 struct fence *flushed_updates;
844 };
845
846 struct amdgpu_vm {
847 /* tree of virtual addresses mapped */
848 spinlock_t it_lock;
849 struct rb_root va;
850
851 /* protecting invalidated */
852 spinlock_t status_lock;
853
854 /* BOs moved, but not yet updated in the PT */
855 struct list_head invalidated;
856
857 /* BOs cleared in the PT because of a move */
858 struct list_head cleared;
859
860 /* BO mappings freed, but not yet updated in the PT */
861 struct list_head freed;
862
863 /* contains the page directory */
864 struct amdgpu_bo *page_directory;
865 unsigned max_pde_used;
866 struct fence *page_directory_fence;
867
868 /* array of page tables, one for each page directory entry */
869 struct amdgpu_vm_pt *page_tables;
870
871 /* for id and flush management per ring */
872 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
873
874 /* protecting freed */
875 spinlock_t freed_lock;
876
877 /* Scheduler entity for page table updates */
878 struct amd_sched_entity entity;
879 };
880
881 struct amdgpu_vm_manager_id {
882 struct list_head list;
883 struct fence *active;
884 atomic_long_t owner;
885 };
886
887 struct amdgpu_vm_manager {
888 /* Handling of VMIDs */
889 struct mutex lock;
890 unsigned num_ids;
891 struct list_head ids_lru;
892 struct amdgpu_vm_manager_id ids[AMDGPU_NUM_VM];
893
894 uint32_t max_pfn;
895 /* vram base address for page table entry */
896 u64 vram_base_offset;
897 /* is vm enabled? */
898 bool enabled;
899 /* vm pte handling */
900 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
901 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
902 unsigned vm_pte_num_rings;
903 atomic_t vm_pte_next_ring;
904 };
905
906 void amdgpu_vm_manager_init(struct amdgpu_device *adev);
907 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
908 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
909 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
910 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
911 struct list_head *validated,
912 struct amdgpu_bo_list_entry *entry);
913 void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
914 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
915 struct amdgpu_vm *vm);
916 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
917 struct amdgpu_sync *sync, struct fence *fence,
918 unsigned *vm_id, uint64_t *vm_pd_addr);
919 void amdgpu_vm_flush(struct amdgpu_ring *ring,
920 unsigned vmid,
921 uint64_t pd_addr);
922 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
923 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
924 struct amdgpu_vm *vm);
925 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
926 struct amdgpu_vm *vm);
927 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
928 struct amdgpu_sync *sync);
929 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
930 struct amdgpu_bo_va *bo_va,
931 struct ttm_mem_reg *mem);
932 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
933 struct amdgpu_bo *bo);
934 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
935 struct amdgpu_bo *bo);
936 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
937 struct amdgpu_vm *vm,
938 struct amdgpu_bo *bo);
939 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
940 struct amdgpu_bo_va *bo_va,
941 uint64_t addr, uint64_t offset,
942 uint64_t size, uint32_t flags);
943 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
944 struct amdgpu_bo_va *bo_va,
945 uint64_t addr);
946 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
947 struct amdgpu_bo_va *bo_va);
948
949 /*
950 * context related structures
951 */
952
953 struct amdgpu_ctx_ring {
954 uint64_t sequence;
955 struct fence **fences;
956 struct amd_sched_entity entity;
957 };
958
959 struct amdgpu_ctx {
960 struct kref refcount;
961 struct amdgpu_device *adev;
962 unsigned reset_counter;
963 spinlock_t ring_lock;
964 struct fence **fences;
965 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
966 };
967
968 struct amdgpu_ctx_mgr {
969 struct amdgpu_device *adev;
970 struct mutex lock;
971 /* protected by lock */
972 struct idr ctx_handles;
973 };
974
975 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
976 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
977
978 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
979 struct fence *fence);
980 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
981 struct amdgpu_ring *ring, uint64_t seq);
982
983 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
984 struct drm_file *filp);
985
986 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
987 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
988
989 /*
990 * file private structure
991 */
992
993 struct amdgpu_fpriv {
994 struct amdgpu_vm vm;
995 struct mutex bo_list_lock;
996 struct idr bo_list_handles;
997 struct amdgpu_ctx_mgr ctx_mgr;
998 };
999
1000 /*
1001 * residency list
1002 */
1003
1004 struct amdgpu_bo_list {
1005 struct mutex lock;
1006 struct amdgpu_bo *gds_obj;
1007 struct amdgpu_bo *gws_obj;
1008 struct amdgpu_bo *oa_obj;
1009 bool has_userptr;
1010 unsigned num_entries;
1011 struct amdgpu_bo_list_entry *array;
1012 };
1013
1014 struct amdgpu_bo_list *
1015 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1016 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1017 struct list_head *validated);
1018 void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1019 void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1020
1021 /*
1022 * GFX stuff
1023 */
1024 #include "clearstate_defs.h"
1025
1026 struct amdgpu_rlc {
1027 /* for power gating */
1028 struct amdgpu_bo *save_restore_obj;
1029 uint64_t save_restore_gpu_addr;
1030 volatile uint32_t *sr_ptr;
1031 const u32 *reg_list;
1032 u32 reg_list_size;
1033 /* for clear state */
1034 struct amdgpu_bo *clear_state_obj;
1035 uint64_t clear_state_gpu_addr;
1036 volatile uint32_t *cs_ptr;
1037 const struct cs_section_def *cs_data;
1038 u32 clear_state_size;
1039 /* for cp tables */
1040 struct amdgpu_bo *cp_table_obj;
1041 uint64_t cp_table_gpu_addr;
1042 volatile uint32_t *cp_table_ptr;
1043 u32 cp_table_size;
1044 };
1045
1046 struct amdgpu_mec {
1047 struct amdgpu_bo *hpd_eop_obj;
1048 u64 hpd_eop_gpu_addr;
1049 u32 num_pipe;
1050 u32 num_mec;
1051 u32 num_queue;
1052 };
1053
1054 /*
1055 * GPU scratch registers structures, functions & helpers
1056 */
1057 struct amdgpu_scratch {
1058 unsigned num_reg;
1059 uint32_t reg_base;
1060 bool free[32];
1061 uint32_t reg[32];
1062 };
1063
1064 /*
1065 * GFX configurations
1066 */
1067 struct amdgpu_gca_config {
1068 unsigned max_shader_engines;
1069 unsigned max_tile_pipes;
1070 unsigned max_cu_per_sh;
1071 unsigned max_sh_per_se;
1072 unsigned max_backends_per_se;
1073 unsigned max_texture_channel_caches;
1074 unsigned max_gprs;
1075 unsigned max_gs_threads;
1076 unsigned max_hw_contexts;
1077 unsigned sc_prim_fifo_size_frontend;
1078 unsigned sc_prim_fifo_size_backend;
1079 unsigned sc_hiz_tile_fifo_size;
1080 unsigned sc_earlyz_tile_fifo_size;
1081
1082 unsigned num_tile_pipes;
1083 unsigned backend_enable_mask;
1084 unsigned mem_max_burst_length_bytes;
1085 unsigned mem_row_size_in_kb;
1086 unsigned shader_engine_tile_size;
1087 unsigned num_gpus;
1088 unsigned multi_gpu_tile_size;
1089 unsigned mc_arb_ramcfg;
1090 unsigned gb_addr_config;
1091 unsigned num_rbs;
1092
1093 uint32_t tile_mode_array[32];
1094 uint32_t macrotile_mode_array[16];
1095 };
1096
1097 struct amdgpu_gfx {
1098 struct mutex gpu_clock_mutex;
1099 struct amdgpu_gca_config config;
1100 struct amdgpu_rlc rlc;
1101 struct amdgpu_mec mec;
1102 struct amdgpu_scratch scratch;
1103 const struct firmware *me_fw; /* ME firmware */
1104 uint32_t me_fw_version;
1105 const struct firmware *pfp_fw; /* PFP firmware */
1106 uint32_t pfp_fw_version;
1107 const struct firmware *ce_fw; /* CE firmware */
1108 uint32_t ce_fw_version;
1109 const struct firmware *rlc_fw; /* RLC firmware */
1110 uint32_t rlc_fw_version;
1111 const struct firmware *mec_fw; /* MEC firmware */
1112 uint32_t mec_fw_version;
1113 const struct firmware *mec2_fw; /* MEC2 firmware */
1114 uint32_t mec2_fw_version;
1115 uint32_t me_feature_version;
1116 uint32_t ce_feature_version;
1117 uint32_t pfp_feature_version;
1118 uint32_t rlc_feature_version;
1119 uint32_t mec_feature_version;
1120 uint32_t mec2_feature_version;
1121 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1122 unsigned num_gfx_rings;
1123 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1124 unsigned num_compute_rings;
1125 struct amdgpu_irq_src eop_irq;
1126 struct amdgpu_irq_src priv_reg_irq;
1127 struct amdgpu_irq_src priv_inst_irq;
1128 /* gfx status */
1129 uint32_t gfx_current_status;
1130 /* ce ram size*/
1131 unsigned ce_ram_size;
1132 };
1133
1134 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
1135 unsigned size, struct amdgpu_ib *ib);
1136 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1137 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
1138 struct amdgpu_ib *ib, void *owner,
1139 struct fence *last_vm_update,
1140 struct fence **f);
1141 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1142 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1143 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1144 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1145 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
1146 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
1147 void amdgpu_ring_commit(struct amdgpu_ring *ring);
1148 void amdgpu_ring_undo(struct amdgpu_ring *ring);
1149 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1150 uint32_t **data);
1151 int amdgpu_ring_restore(struct amdgpu_ring *ring,
1152 unsigned size, uint32_t *data);
1153 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1154 unsigned ring_size, u32 nop, u32 align_mask,
1155 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1156 enum amdgpu_ring_type ring_type);
1157 void amdgpu_ring_fini(struct amdgpu_ring *ring);
1158 struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
1159
1160 /*
1161 * CS.
1162 */
1163 struct amdgpu_cs_chunk {
1164 uint32_t chunk_id;
1165 uint32_t length_dw;
1166 uint32_t *kdata;
1167 };
1168
1169 struct amdgpu_cs_parser {
1170 struct amdgpu_device *adev;
1171 struct drm_file *filp;
1172 struct amdgpu_ctx *ctx;
1173
1174 /* chunks */
1175 unsigned nchunks;
1176 struct amdgpu_cs_chunk *chunks;
1177
1178 /* scheduler job object */
1179 struct amdgpu_job *job;
1180
1181 /* buffer objects */
1182 struct ww_acquire_ctx ticket;
1183 struct amdgpu_bo_list *bo_list;
1184 struct amdgpu_bo_list_entry vm_pd;
1185 struct list_head validated;
1186 struct fence *fence;
1187 uint64_t bytes_moved_threshold;
1188 uint64_t bytes_moved;
1189
1190 /* user fence */
1191 struct amdgpu_bo_list_entry uf_entry;
1192 };
1193
1194 struct amdgpu_job {
1195 struct amd_sched_job base;
1196 struct amdgpu_device *adev;
1197 struct amdgpu_ring *ring;
1198 struct amdgpu_sync sync;
1199 struct amdgpu_ib *ibs;
1200 uint32_t num_ibs;
1201 void *owner;
1202 struct amdgpu_user_fence uf;
1203 };
1204 #define to_amdgpu_job(sched_job) \
1205 container_of((sched_job), struct amdgpu_job, base)
1206
1207 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1208 uint32_t ib_idx, int idx)
1209 {
1210 return p->job->ibs[ib_idx].ptr[idx];
1211 }
1212
1213 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1214 uint32_t ib_idx, int idx,
1215 uint32_t value)
1216 {
1217 p->job->ibs[ib_idx].ptr[idx] = value;
1218 }
1219
1220 /*
1221 * Writeback
1222 */
1223 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1224
1225 struct amdgpu_wb {
1226 struct amdgpu_bo *wb_obj;
1227 volatile uint32_t *wb;
1228 uint64_t gpu_addr;
1229 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1230 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1231 };
1232
1233 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1234 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1235
1236
1237
1238 enum amdgpu_int_thermal_type {
1239 THERMAL_TYPE_NONE,
1240 THERMAL_TYPE_EXTERNAL,
1241 THERMAL_TYPE_EXTERNAL_GPIO,
1242 THERMAL_TYPE_RV6XX,
1243 THERMAL_TYPE_RV770,
1244 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1245 THERMAL_TYPE_EVERGREEN,
1246 THERMAL_TYPE_SUMO,
1247 THERMAL_TYPE_NI,
1248 THERMAL_TYPE_SI,
1249 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1250 THERMAL_TYPE_CI,
1251 THERMAL_TYPE_KV,
1252 };
1253
1254 enum amdgpu_dpm_auto_throttle_src {
1255 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1256 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1257 };
1258
1259 enum amdgpu_dpm_event_src {
1260 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1261 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1262 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1263 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1264 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1265 };
1266
1267 #define AMDGPU_MAX_VCE_LEVELS 6
1268
1269 enum amdgpu_vce_level {
1270 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1271 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1272 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1273 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1274 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1275 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1276 };
1277
1278 struct amdgpu_ps {
1279 u32 caps; /* vbios flags */
1280 u32 class; /* vbios flags */
1281 u32 class2; /* vbios flags */
1282 /* UVD clocks */
1283 u32 vclk;
1284 u32 dclk;
1285 /* VCE clocks */
1286 u32 evclk;
1287 u32 ecclk;
1288 bool vce_active;
1289 enum amdgpu_vce_level vce_level;
1290 /* asic priv */
1291 void *ps_priv;
1292 };
1293
1294 struct amdgpu_dpm_thermal {
1295 /* thermal interrupt work */
1296 struct work_struct work;
1297 /* low temperature threshold */
1298 int min_temp;
1299 /* high temperature threshold */
1300 int max_temp;
1301 /* was last interrupt low to high or high to low */
1302 bool high_to_low;
1303 /* interrupt source */
1304 struct amdgpu_irq_src irq;
1305 };
1306
1307 enum amdgpu_clk_action
1308 {
1309 AMDGPU_SCLK_UP = 1,
1310 AMDGPU_SCLK_DOWN
1311 };
1312
1313 struct amdgpu_blacklist_clocks
1314 {
1315 u32 sclk;
1316 u32 mclk;
1317 enum amdgpu_clk_action action;
1318 };
1319
1320 struct amdgpu_clock_and_voltage_limits {
1321 u32 sclk;
1322 u32 mclk;
1323 u16 vddc;
1324 u16 vddci;
1325 };
1326
1327 struct amdgpu_clock_array {
1328 u32 count;
1329 u32 *values;
1330 };
1331
1332 struct amdgpu_clock_voltage_dependency_entry {
1333 u32 clk;
1334 u16 v;
1335 };
1336
1337 struct amdgpu_clock_voltage_dependency_table {
1338 u32 count;
1339 struct amdgpu_clock_voltage_dependency_entry *entries;
1340 };
1341
1342 union amdgpu_cac_leakage_entry {
1343 struct {
1344 u16 vddc;
1345 u32 leakage;
1346 };
1347 struct {
1348 u16 vddc1;
1349 u16 vddc2;
1350 u16 vddc3;
1351 };
1352 };
1353
1354 struct amdgpu_cac_leakage_table {
1355 u32 count;
1356 union amdgpu_cac_leakage_entry *entries;
1357 };
1358
1359 struct amdgpu_phase_shedding_limits_entry {
1360 u16 voltage;
1361 u32 sclk;
1362 u32 mclk;
1363 };
1364
1365 struct amdgpu_phase_shedding_limits_table {
1366 u32 count;
1367 struct amdgpu_phase_shedding_limits_entry *entries;
1368 };
1369
1370 struct amdgpu_uvd_clock_voltage_dependency_entry {
1371 u32 vclk;
1372 u32 dclk;
1373 u16 v;
1374 };
1375
1376 struct amdgpu_uvd_clock_voltage_dependency_table {
1377 u8 count;
1378 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1379 };
1380
1381 struct amdgpu_vce_clock_voltage_dependency_entry {
1382 u32 ecclk;
1383 u32 evclk;
1384 u16 v;
1385 };
1386
1387 struct amdgpu_vce_clock_voltage_dependency_table {
1388 u8 count;
1389 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1390 };
1391
1392 struct amdgpu_ppm_table {
1393 u8 ppm_design;
1394 u16 cpu_core_number;
1395 u32 platform_tdp;
1396 u32 small_ac_platform_tdp;
1397 u32 platform_tdc;
1398 u32 small_ac_platform_tdc;
1399 u32 apu_tdp;
1400 u32 dgpu_tdp;
1401 u32 dgpu_ulv_power;
1402 u32 tj_max;
1403 };
1404
1405 struct amdgpu_cac_tdp_table {
1406 u16 tdp;
1407 u16 configurable_tdp;
1408 u16 tdc;
1409 u16 battery_power_limit;
1410 u16 small_power_limit;
1411 u16 low_cac_leakage;
1412 u16 high_cac_leakage;
1413 u16 maximum_power_delivery_limit;
1414 };
1415
1416 struct amdgpu_dpm_dynamic_state {
1417 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1418 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1419 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1420 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1421 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1422 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1423 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1424 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1425 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1426 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1427 struct amdgpu_clock_array valid_sclk_values;
1428 struct amdgpu_clock_array valid_mclk_values;
1429 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1430 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1431 u32 mclk_sclk_ratio;
1432 u32 sclk_mclk_delta;
1433 u16 vddc_vddci_delta;
1434 u16 min_vddc_for_pcie_gen2;
1435 struct amdgpu_cac_leakage_table cac_leakage_table;
1436 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1437 struct amdgpu_ppm_table *ppm_table;
1438 struct amdgpu_cac_tdp_table *cac_tdp_table;
1439 };
1440
1441 struct amdgpu_dpm_fan {
1442 u16 t_min;
1443 u16 t_med;
1444 u16 t_high;
1445 u16 pwm_min;
1446 u16 pwm_med;
1447 u16 pwm_high;
1448 u8 t_hyst;
1449 u32 cycle_delay;
1450 u16 t_max;
1451 u8 control_mode;
1452 u16 default_max_fan_pwm;
1453 u16 default_fan_output_sensitivity;
1454 u16 fan_output_sensitivity;
1455 bool ucode_fan_control;
1456 };
1457
1458 enum amdgpu_pcie_gen {
1459 AMDGPU_PCIE_GEN1 = 0,
1460 AMDGPU_PCIE_GEN2 = 1,
1461 AMDGPU_PCIE_GEN3 = 2,
1462 AMDGPU_PCIE_GEN_INVALID = 0xffff
1463 };
1464
1465 enum amdgpu_dpm_forced_level {
1466 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1467 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1468 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1469 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
1470 };
1471
1472 struct amdgpu_vce_state {
1473 /* vce clocks */
1474 u32 evclk;
1475 u32 ecclk;
1476 /* gpu clocks */
1477 u32 sclk;
1478 u32 mclk;
1479 u8 clk_idx;
1480 u8 pstate;
1481 };
1482
1483 struct amdgpu_dpm_funcs {
1484 int (*get_temperature)(struct amdgpu_device *adev);
1485 int (*pre_set_power_state)(struct amdgpu_device *adev);
1486 int (*set_power_state)(struct amdgpu_device *adev);
1487 void (*post_set_power_state)(struct amdgpu_device *adev);
1488 void (*display_configuration_changed)(struct amdgpu_device *adev);
1489 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1490 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1491 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1492 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1493 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1494 bool (*vblank_too_short)(struct amdgpu_device *adev);
1495 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
1496 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
1497 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1498 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1499 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1500 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1501 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1502 };
1503
1504 struct amdgpu_dpm {
1505 struct amdgpu_ps *ps;
1506 /* number of valid power states */
1507 int num_ps;
1508 /* current power state that is active */
1509 struct amdgpu_ps *current_ps;
1510 /* requested power state */
1511 struct amdgpu_ps *requested_ps;
1512 /* boot up power state */
1513 struct amdgpu_ps *boot_ps;
1514 /* default uvd power state */
1515 struct amdgpu_ps *uvd_ps;
1516 /* vce requirements */
1517 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1518 enum amdgpu_vce_level vce_level;
1519 enum amd_pm_state_type state;
1520 enum amd_pm_state_type user_state;
1521 u32 platform_caps;
1522 u32 voltage_response_time;
1523 u32 backbias_response_time;
1524 void *priv;
1525 u32 new_active_crtcs;
1526 int new_active_crtc_count;
1527 u32 current_active_crtcs;
1528 int current_active_crtc_count;
1529 struct amdgpu_dpm_dynamic_state dyn_state;
1530 struct amdgpu_dpm_fan fan;
1531 u32 tdp_limit;
1532 u32 near_tdp_limit;
1533 u32 near_tdp_limit_adjusted;
1534 u32 sq_ramping_threshold;
1535 u32 cac_leakage;
1536 u16 tdp_od_limit;
1537 u32 tdp_adjustment;
1538 u16 load_line_slope;
1539 bool power_control;
1540 bool ac_power;
1541 /* special states active */
1542 bool thermal_active;
1543 bool uvd_active;
1544 bool vce_active;
1545 /* thermal handling */
1546 struct amdgpu_dpm_thermal thermal;
1547 /* forced levels */
1548 enum amdgpu_dpm_forced_level forced_level;
1549 };
1550
1551 struct amdgpu_pm {
1552 struct mutex mutex;
1553 u32 current_sclk;
1554 u32 current_mclk;
1555 u32 default_sclk;
1556 u32 default_mclk;
1557 struct amdgpu_i2c_chan *i2c_bus;
1558 /* internal thermal controller on rv6xx+ */
1559 enum amdgpu_int_thermal_type int_thermal_type;
1560 struct device *int_hwmon_dev;
1561 /* fan control parameters */
1562 bool no_fan;
1563 u8 fan_pulses_per_revolution;
1564 u8 fan_min_rpm;
1565 u8 fan_max_rpm;
1566 /* dpm */
1567 bool dpm_enabled;
1568 bool sysfs_initialized;
1569 struct amdgpu_dpm dpm;
1570 const struct firmware *fw; /* SMC firmware */
1571 uint32_t fw_version;
1572 const struct amdgpu_dpm_funcs *funcs;
1573 uint32_t pcie_gen_mask;
1574 uint32_t pcie_mlw_mask;
1575 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
1576 };
1577
1578 void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1579
1580 /*
1581 * UVD
1582 */
1583 #define AMDGPU_MAX_UVD_HANDLES 10
1584 #define AMDGPU_UVD_STACK_SIZE (1024*1024)
1585 #define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1586 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1587
1588 struct amdgpu_uvd {
1589 struct amdgpu_bo *vcpu_bo;
1590 void *cpu_addr;
1591 uint64_t gpu_addr;
1592 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1593 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1594 struct delayed_work idle_work;
1595 const struct firmware *fw; /* UVD firmware */
1596 struct amdgpu_ring ring;
1597 struct amdgpu_irq_src irq;
1598 bool address_64_bit;
1599 struct amd_sched_entity entity;
1600 };
1601
1602 /*
1603 * VCE
1604 */
1605 #define AMDGPU_MAX_VCE_HANDLES 16
1606 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1607
1608 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1609 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1610
1611 struct amdgpu_vce {
1612 struct amdgpu_bo *vcpu_bo;
1613 uint64_t gpu_addr;
1614 unsigned fw_version;
1615 unsigned fb_version;
1616 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1617 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
1618 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
1619 struct delayed_work idle_work;
1620 const struct firmware *fw; /* VCE firmware */
1621 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1622 struct amdgpu_irq_src irq;
1623 unsigned harvest_config;
1624 struct amd_sched_entity entity;
1625 };
1626
1627 /*
1628 * SDMA
1629 */
1630 struct amdgpu_sdma_instance {
1631 /* SDMA firmware */
1632 const struct firmware *fw;
1633 uint32_t fw_version;
1634 uint32_t feature_version;
1635
1636 struct amdgpu_ring ring;
1637 bool burst_nop;
1638 };
1639
1640 struct amdgpu_sdma {
1641 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1642 struct amdgpu_irq_src trap_irq;
1643 struct amdgpu_irq_src illegal_inst_irq;
1644 int num_instances;
1645 };
1646
1647 /*
1648 * Firmware
1649 */
1650 struct amdgpu_firmware {
1651 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1652 bool smu_load;
1653 struct amdgpu_bo *fw_buf;
1654 unsigned int fw_size;
1655 };
1656
1657 /*
1658 * Benchmarking
1659 */
1660 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1661
1662
1663 /*
1664 * Testing
1665 */
1666 void amdgpu_test_moves(struct amdgpu_device *adev);
1667 void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1668 struct amdgpu_ring *cpA,
1669 struct amdgpu_ring *cpB);
1670 void amdgpu_test_syncing(struct amdgpu_device *adev);
1671
1672 /*
1673 * MMU Notifier
1674 */
1675 #if defined(CONFIG_MMU_NOTIFIER)
1676 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1677 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1678 #else
1679 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1680 {
1681 return -ENODEV;
1682 }
1683 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1684 #endif
1685
1686 /*
1687 * Debugfs
1688 */
1689 struct amdgpu_debugfs {
1690 struct drm_info_list *files;
1691 unsigned num_files;
1692 };
1693
1694 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1695 struct drm_info_list *files,
1696 unsigned nfiles);
1697 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1698
1699 #if defined(CONFIG_DEBUG_FS)
1700 int amdgpu_debugfs_init(struct drm_minor *minor);
1701 void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1702 #endif
1703
1704 /*
1705 * amdgpu smumgr functions
1706 */
1707 struct amdgpu_smumgr_funcs {
1708 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1709 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1710 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1711 };
1712
1713 /*
1714 * amdgpu smumgr
1715 */
1716 struct amdgpu_smumgr {
1717 struct amdgpu_bo *toc_buf;
1718 struct amdgpu_bo *smu_buf;
1719 /* asic priv smu data */
1720 void *priv;
1721 spinlock_t smu_lock;
1722 /* smumgr functions */
1723 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1724 /* ucode loading complete flag */
1725 uint32_t fw_flags;
1726 };
1727
1728 /*
1729 * ASIC specific register table accessible by UMD
1730 */
1731 struct amdgpu_allowed_register_entry {
1732 uint32_t reg_offset;
1733 bool untouched;
1734 bool grbm_indexed;
1735 };
1736
1737 struct amdgpu_cu_info {
1738 uint32_t number; /* total active CU number */
1739 uint32_t ao_cu_mask;
1740 uint32_t bitmap[4][4];
1741 };
1742
1743
1744 /*
1745 * ASIC specific functions.
1746 */
1747 struct amdgpu_asic_funcs {
1748 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1749 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1750 u8 *bios, u32 length_bytes);
1751 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1752 u32 sh_num, u32 reg_offset, u32 *value);
1753 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1754 int (*reset)(struct amdgpu_device *adev);
1755 /* wait for mc_idle */
1756 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1757 /* get the reference clock */
1758 u32 (*get_xclk)(struct amdgpu_device *adev);
1759 /* get the gpu clock counter */
1760 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1761 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1762 /* MM block clocks */
1763 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1764 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1765 };
1766
1767 /*
1768 * IOCTL.
1769 */
1770 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1771 struct drm_file *filp);
1772 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1773 struct drm_file *filp);
1774
1775 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1776 struct drm_file *filp);
1777 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1778 struct drm_file *filp);
1779 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1780 struct drm_file *filp);
1781 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1782 struct drm_file *filp);
1783 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1784 struct drm_file *filp);
1785 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1786 struct drm_file *filp);
1787 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1788 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1789
1790 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1791 struct drm_file *filp);
1792
1793 /* VRAM scratch page for HDP bug, default vram page */
1794 struct amdgpu_vram_scratch {
1795 struct amdgpu_bo *robj;
1796 volatile uint32_t *ptr;
1797 u64 gpu_addr;
1798 };
1799
1800 /*
1801 * ACPI
1802 */
1803 struct amdgpu_atif_notification_cfg {
1804 bool enabled;
1805 int command_code;
1806 };
1807
1808 struct amdgpu_atif_notifications {
1809 bool display_switch;
1810 bool expansion_mode_change;
1811 bool thermal_state;
1812 bool forced_power_state;
1813 bool system_power_state;
1814 bool display_conf_change;
1815 bool px_gfx_switch;
1816 bool brightness_change;
1817 bool dgpu_display_event;
1818 };
1819
1820 struct amdgpu_atif_functions {
1821 bool system_params;
1822 bool sbios_requests;
1823 bool select_active_disp;
1824 bool lid_state;
1825 bool get_tv_standard;
1826 bool set_tv_standard;
1827 bool get_panel_expansion_mode;
1828 bool set_panel_expansion_mode;
1829 bool temperature_change;
1830 bool graphics_device_types;
1831 };
1832
1833 struct amdgpu_atif {
1834 struct amdgpu_atif_notifications notifications;
1835 struct amdgpu_atif_functions functions;
1836 struct amdgpu_atif_notification_cfg notification_cfg;
1837 struct amdgpu_encoder *encoder_for_bl;
1838 };
1839
1840 struct amdgpu_atcs_functions {
1841 bool get_ext_state;
1842 bool pcie_perf_req;
1843 bool pcie_dev_rdy;
1844 bool pcie_bus_width;
1845 };
1846
1847 struct amdgpu_atcs {
1848 struct amdgpu_atcs_functions functions;
1849 };
1850
1851 /*
1852 * CGS
1853 */
1854 void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1855 void amdgpu_cgs_destroy_device(void *cgs_device);
1856
1857
1858 /*
1859 * CGS
1860 */
1861 void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1862 void amdgpu_cgs_destroy_device(void *cgs_device);
1863
1864
1865 /* GPU virtualization */
1866 struct amdgpu_virtualization {
1867 bool supports_sr_iov;
1868 };
1869
1870 /*
1871 * Core structure, functions and helpers.
1872 */
1873 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1874 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1875
1876 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1877 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1878
1879 struct amdgpu_ip_block_status {
1880 bool valid;
1881 bool sw;
1882 bool hw;
1883 };
1884
1885 struct amdgpu_device {
1886 struct device *dev;
1887 struct drm_device *ddev;
1888 struct pci_dev *pdev;
1889
1890 #ifdef CONFIG_DRM_AMD_ACP
1891 struct amdgpu_acp acp;
1892 #endif
1893
1894 /* ASIC */
1895 enum amd_asic_type asic_type;
1896 uint32_t family;
1897 uint32_t rev_id;
1898 uint32_t external_rev_id;
1899 unsigned long flags;
1900 int usec_timeout;
1901 const struct amdgpu_asic_funcs *asic_funcs;
1902 bool shutdown;
1903 bool suspend;
1904 bool need_dma32;
1905 bool accel_working;
1906 struct work_struct reset_work;
1907 struct notifier_block acpi_nb;
1908 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1909 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1910 unsigned debugfs_count;
1911 #if defined(CONFIG_DEBUG_FS)
1912 struct dentry *debugfs_regs;
1913 #endif
1914 struct amdgpu_atif atif;
1915 struct amdgpu_atcs atcs;
1916 struct mutex srbm_mutex;
1917 /* GRBM index mutex. Protects concurrent access to GRBM index */
1918 struct mutex grbm_idx_mutex;
1919 struct dev_pm_domain vga_pm_domain;
1920 bool have_disp_power_ref;
1921
1922 /* BIOS */
1923 uint8_t *bios;
1924 bool is_atom_bios;
1925 uint16_t bios_header_start;
1926 struct amdgpu_bo *stollen_vga_memory;
1927 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1928
1929 /* Register/doorbell mmio */
1930 resource_size_t rmmio_base;
1931 resource_size_t rmmio_size;
1932 void __iomem *rmmio;
1933 /* protects concurrent MM_INDEX/DATA based register access */
1934 spinlock_t mmio_idx_lock;
1935 /* protects concurrent SMC based register access */
1936 spinlock_t smc_idx_lock;
1937 amdgpu_rreg_t smc_rreg;
1938 amdgpu_wreg_t smc_wreg;
1939 /* protects concurrent PCIE register access */
1940 spinlock_t pcie_idx_lock;
1941 amdgpu_rreg_t pcie_rreg;
1942 amdgpu_wreg_t pcie_wreg;
1943 /* protects concurrent UVD register access */
1944 spinlock_t uvd_ctx_idx_lock;
1945 amdgpu_rreg_t uvd_ctx_rreg;
1946 amdgpu_wreg_t uvd_ctx_wreg;
1947 /* protects concurrent DIDT register access */
1948 spinlock_t didt_idx_lock;
1949 amdgpu_rreg_t didt_rreg;
1950 amdgpu_wreg_t didt_wreg;
1951 /* protects concurrent ENDPOINT (audio) register access */
1952 spinlock_t audio_endpt_idx_lock;
1953 amdgpu_block_rreg_t audio_endpt_rreg;
1954 amdgpu_block_wreg_t audio_endpt_wreg;
1955 void __iomem *rio_mem;
1956 resource_size_t rio_mem_size;
1957 struct amdgpu_doorbell doorbell;
1958
1959 /* clock/pll info */
1960 struct amdgpu_clock clock;
1961
1962 /* MC */
1963 struct amdgpu_mc mc;
1964 struct amdgpu_gart gart;
1965 struct amdgpu_dummy_page dummy_page;
1966 struct amdgpu_vm_manager vm_manager;
1967
1968 /* memory management */
1969 struct amdgpu_mman mman;
1970 struct amdgpu_vram_scratch vram_scratch;
1971 struct amdgpu_wb wb;
1972 atomic64_t vram_usage;
1973 atomic64_t vram_vis_usage;
1974 atomic64_t gtt_usage;
1975 atomic64_t num_bytes_moved;
1976 atomic_t gpu_reset_counter;
1977
1978 /* display */
1979 struct amdgpu_mode_info mode_info;
1980 struct work_struct hotplug_work;
1981 struct amdgpu_irq_src crtc_irq;
1982 struct amdgpu_irq_src pageflip_irq;
1983 struct amdgpu_irq_src hpd_irq;
1984
1985 /* rings */
1986 unsigned fence_context;
1987 unsigned num_rings;
1988 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1989 bool ib_pool_ready;
1990 struct amdgpu_sa_manager ring_tmp_bo;
1991
1992 /* interrupts */
1993 struct amdgpu_irq irq;
1994
1995 /* powerplay */
1996 struct amd_powerplay powerplay;
1997 bool pp_enabled;
1998 bool pp_force_state_enabled;
1999
2000 /* dpm */
2001 struct amdgpu_pm pm;
2002 u32 cg_flags;
2003 u32 pg_flags;
2004
2005 /* amdgpu smumgr */
2006 struct amdgpu_smumgr smu;
2007
2008 /* gfx */
2009 struct amdgpu_gfx gfx;
2010
2011 /* sdma */
2012 struct amdgpu_sdma sdma;
2013
2014 /* uvd */
2015 bool has_uvd;
2016 struct amdgpu_uvd uvd;
2017
2018 /* vce */
2019 struct amdgpu_vce vce;
2020
2021 /* firmwares */
2022 struct amdgpu_firmware firmware;
2023
2024 /* GDS */
2025 struct amdgpu_gds gds;
2026
2027 const struct amdgpu_ip_block_version *ip_blocks;
2028 int num_ip_blocks;
2029 struct amdgpu_ip_block_status *ip_block_status;
2030 struct mutex mn_lock;
2031 DECLARE_HASHTABLE(mn_hash, 7);
2032
2033 /* tracking pinned memory */
2034 u64 vram_pin_size;
2035 u64 gart_pin_size;
2036
2037 /* amdkfd interface */
2038 struct kfd_dev *kfd;
2039
2040 struct amdgpu_virtualization virtualization;
2041 };
2042
2043 bool amdgpu_device_is_px(struct drm_device *dev);
2044 int amdgpu_device_init(struct amdgpu_device *adev,
2045 struct drm_device *ddev,
2046 struct pci_dev *pdev,
2047 uint32_t flags);
2048 void amdgpu_device_fini(struct amdgpu_device *adev);
2049 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2050
2051 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2052 bool always_indirect);
2053 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2054 bool always_indirect);
2055 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2056 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2057
2058 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2059 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2060
2061 /*
2062 * Cast helper
2063 */
2064 extern const struct fence_ops amdgpu_fence_ops;
2065 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2066 {
2067 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2068
2069 if (__f->base.ops == &amdgpu_fence_ops)
2070 return __f;
2071
2072 return NULL;
2073 }
2074
2075 /*
2076 * Registers read & write functions.
2077 */
2078 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2079 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2080 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2081 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2082 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2083 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2084 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2085 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2086 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2087 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2088 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2089 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2090 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2091 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2092 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2093 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2094 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2095 #define WREG32_P(reg, val, mask) \
2096 do { \
2097 uint32_t tmp_ = RREG32(reg); \
2098 tmp_ &= (mask); \
2099 tmp_ |= ((val) & ~(mask)); \
2100 WREG32(reg, tmp_); \
2101 } while (0)
2102 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2103 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2104 #define WREG32_PLL_P(reg, val, mask) \
2105 do { \
2106 uint32_t tmp_ = RREG32_PLL(reg); \
2107 tmp_ &= (mask); \
2108 tmp_ |= ((val) & ~(mask)); \
2109 WREG32_PLL(reg, tmp_); \
2110 } while (0)
2111 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2112 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2113 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2114
2115 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2116 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2117
2118 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2119 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2120
2121 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2122 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2123 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2124
2125 #define REG_GET_FIELD(value, reg, field) \
2126 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2127
2128 /*
2129 * BIOS helpers.
2130 */
2131 #define RBIOS8(i) (adev->bios[i])
2132 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2133 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2134
2135 /*
2136 * RING helpers.
2137 */
2138 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2139 {
2140 if (ring->count_dw <= 0)
2141 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2142 ring->ring[ring->wptr++] = v;
2143 ring->wptr &= ring->ptr_mask;
2144 ring->count_dw--;
2145 }
2146
2147 static inline struct amdgpu_sdma_instance *
2148 amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
2149 {
2150 struct amdgpu_device *adev = ring->adev;
2151 int i;
2152
2153 for (i = 0; i < adev->sdma.num_instances; i++)
2154 if (&adev->sdma.instance[i].ring == ring)
2155 break;
2156
2157 if (i < AMDGPU_MAX_SDMA_INSTANCES)
2158 return &adev->sdma.instance[i];
2159 else
2160 return NULL;
2161 }
2162
2163 /*
2164 * ASICs macro.
2165 */
2166 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2167 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2168 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2169 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2170 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2171 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2172 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2173 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2174 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
2175 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2176 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2177 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2178 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2179 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2180 #define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags)))
2181 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2182 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2183 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2184 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2185 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2186 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2187 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2188 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2189 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2190 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2191 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2192 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2193 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
2194 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2195 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2196 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2197 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2198 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2199 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2200 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2201 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2202 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2203 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2204 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2205 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2206 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2207 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2208 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2209 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2210 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2211 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2212 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2213 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
2214 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
2215 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2216 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2217 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2218 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2219 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2220 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2221 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2222
2223 #define amdgpu_dpm_get_temperature(adev) \
2224 ((adev)->pp_enabled ? \
2225 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
2226 (adev)->pm.funcs->get_temperature((adev)))
2227
2228 #define amdgpu_dpm_set_fan_control_mode(adev, m) \
2229 ((adev)->pp_enabled ? \
2230 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
2231 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
2232
2233 #define amdgpu_dpm_get_fan_control_mode(adev) \
2234 ((adev)->pp_enabled ? \
2235 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
2236 (adev)->pm.funcs->get_fan_control_mode((adev)))
2237
2238 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \
2239 ((adev)->pp_enabled ? \
2240 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2241 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
2242
2243 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \
2244 ((adev)->pp_enabled ? \
2245 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2246 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
2247
2248 #define amdgpu_dpm_get_sclk(adev, l) \
2249 ((adev)->pp_enabled ? \
2250 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
2251 (adev)->pm.funcs->get_sclk((adev), (l)))
2252
2253 #define amdgpu_dpm_get_mclk(adev, l) \
2254 ((adev)->pp_enabled ? \
2255 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
2256 (adev)->pm.funcs->get_mclk((adev), (l)))
2257
2258
2259 #define amdgpu_dpm_force_performance_level(adev, l) \
2260 ((adev)->pp_enabled ? \
2261 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
2262 (adev)->pm.funcs->force_performance_level((adev), (l)))
2263
2264 #define amdgpu_dpm_powergate_uvd(adev, g) \
2265 ((adev)->pp_enabled ? \
2266 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
2267 (adev)->pm.funcs->powergate_uvd((adev), (g)))
2268
2269 #define amdgpu_dpm_powergate_vce(adev, g) \
2270 ((adev)->pp_enabled ? \
2271 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
2272 (adev)->pm.funcs->powergate_vce((adev), (g)))
2273
2274 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
2275 ((adev)->pp_enabled ? \
2276 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
2277 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
2278
2279 #define amdgpu_dpm_get_current_power_state(adev) \
2280 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
2281
2282 #define amdgpu_dpm_get_performance_level(adev) \
2283 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
2284
2285 #define amdgpu_dpm_get_pp_num_states(adev, data) \
2286 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
2287
2288 #define amdgpu_dpm_get_pp_table(adev, table) \
2289 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
2290
2291 #define amdgpu_dpm_set_pp_table(adev, buf, size) \
2292 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
2293
2294 #define amdgpu_dpm_print_clock_levels(adev, type, buf) \
2295 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
2296
2297 #define amdgpu_dpm_force_clock_level(adev, type, level) \
2298 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
2299
2300 #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
2301 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
2302
2303 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2304
2305 /* Common functions */
2306 int amdgpu_gpu_reset(struct amdgpu_device *adev);
2307 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2308 bool amdgpu_card_posted(struct amdgpu_device *adev);
2309 void amdgpu_update_display_priority(struct amdgpu_device *adev);
2310
2311 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2312 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2313 u32 ip_instance, u32 ring,
2314 struct amdgpu_ring **out_ring);
2315 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2316 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2317 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2318 uint32_t flags);
2319 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2320 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
2321 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2322 unsigned long end);
2323 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2324 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2325 struct ttm_mem_reg *mem);
2326 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2327 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2328 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2329 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2330 const u32 *registers,
2331 const u32 array_size);
2332
2333 bool amdgpu_device_is_px(struct drm_device *dev);
2334 /* atpx handler */
2335 #if defined(CONFIG_VGA_SWITCHEROO)
2336 void amdgpu_register_atpx_handler(void);
2337 void amdgpu_unregister_atpx_handler(void);
2338 #else
2339 static inline void amdgpu_register_atpx_handler(void) {}
2340 static inline void amdgpu_unregister_atpx_handler(void) {}
2341 #endif
2342
2343 /*
2344 * KMS
2345 */
2346 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2347 extern int amdgpu_max_kms_ioctl;
2348
2349 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2350 int amdgpu_driver_unload_kms(struct drm_device *dev);
2351 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2352 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2353 void amdgpu_driver_postclose_kms(struct drm_device *dev,
2354 struct drm_file *file_priv);
2355 void amdgpu_driver_preclose_kms(struct drm_device *dev,
2356 struct drm_file *file_priv);
2357 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2358 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2359 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2360 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2361 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2362 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
2363 int *max_error,
2364 struct timeval *vblank_time,
2365 unsigned flags);
2366 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2367 unsigned long arg);
2368
2369 /*
2370 * functions used by amdgpu_encoder.c
2371 */
2372 struct amdgpu_afmt_acr {
2373 u32 clock;
2374
2375 int n_32khz;
2376 int cts_32khz;
2377
2378 int n_44_1khz;
2379 int cts_44_1khz;
2380
2381 int n_48khz;
2382 int cts_48khz;
2383
2384 };
2385
2386 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2387
2388 /* amdgpu_acpi.c */
2389 #if defined(CONFIG_ACPI)
2390 int amdgpu_acpi_init(struct amdgpu_device *adev);
2391 void amdgpu_acpi_fini(struct amdgpu_device *adev);
2392 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2393 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2394 u8 perf_req, bool advertise);
2395 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2396 #else
2397 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2398 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2399 #endif
2400
2401 struct amdgpu_bo_va_mapping *
2402 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2403 uint64_t addr, struct amdgpu_bo **bo);
2404
2405 #include "amdgpu_object.h"
2406
2407 #endif
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