2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/rbtree.h>
36 #include <linux/hashtable.h>
37 #include <linux/dma-fence.h>
39 #include <drm/ttm/ttm_bo_api.h>
40 #include <drm/ttm/ttm_bo_driver.h>
41 #include <drm/ttm/ttm_placement.h>
42 #include <drm/ttm/ttm_module.h>
43 #include <drm/ttm/ttm_execbuf_util.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
49 #include <kgd_kfd_interface.h>
51 #include "amd_shared.h"
52 #include "amdgpu_mode.h"
53 #include "amdgpu_ih.h"
54 #include "amdgpu_irq.h"
55 #include "amdgpu_ucode.h"
56 #include "amdgpu_ttm.h"
57 #include "amdgpu_psp.h"
58 #include "amdgpu_gds.h"
59 #include "amdgpu_sync.h"
60 #include "amdgpu_ring.h"
61 #include "amdgpu_vm.h"
62 #include "amd_powerplay.h"
63 #include "amdgpu_dpm.h"
64 #include "amdgpu_acp.h"
65 #include "amdgpu_uvd.h"
66 #include "amdgpu_vce.h"
67 #include "amdgpu_vcn.h"
69 #include "gpu_scheduler.h"
70 #include "amdgpu_virt.h"
75 extern int amdgpu_modeset
;
76 extern int amdgpu_vram_limit
;
77 extern int amdgpu_gart_size
;
78 extern int amdgpu_moverate
;
79 extern int amdgpu_benchmarking
;
80 extern int amdgpu_testing
;
81 extern int amdgpu_audio
;
82 extern int amdgpu_disp_priority
;
83 extern int amdgpu_hw_i2c
;
84 extern int amdgpu_pcie_gen2
;
85 extern int amdgpu_msi
;
86 extern int amdgpu_lockup_timeout
;
87 extern int amdgpu_dpm
;
88 extern int amdgpu_fw_load_type
;
89 extern int amdgpu_aspm
;
90 extern int amdgpu_runtime_pm
;
91 extern unsigned amdgpu_ip_block_mask
;
92 extern int amdgpu_bapm
;
93 extern int amdgpu_deep_color
;
94 extern int amdgpu_vm_size
;
95 extern int amdgpu_vm_block_size
;
96 extern int amdgpu_vm_fault_stop
;
97 extern int amdgpu_vm_debug
;
98 extern int amdgpu_vm_update_mode
;
99 extern int amdgpu_sched_jobs
;
100 extern int amdgpu_sched_hw_submission
;
101 extern int amdgpu_no_evict
;
102 extern int amdgpu_direct_gma_size
;
103 extern unsigned amdgpu_pcie_gen_cap
;
104 extern unsigned amdgpu_pcie_lane_cap
;
105 extern unsigned amdgpu_cg_mask
;
106 extern unsigned amdgpu_pg_mask
;
107 extern char *amdgpu_disable_cu
;
108 extern char *amdgpu_virtual_display
;
109 extern unsigned amdgpu_pp_feature_mask
;
110 extern int amdgpu_vram_page_split
;
111 extern int amdgpu_ngg
;
112 extern int amdgpu_prim_buf_per_se
;
113 extern int amdgpu_pos_buf_per_se
;
114 extern int amdgpu_cntl_sb_buf_per_se
;
115 extern int amdgpu_param_buf_per_se
;
116 extern int amdgpu_job_hang_limit
;
117 extern int amdgpu_lbpw
;
119 #ifdef CONFIG_DRM_AMDGPU_SI
120 extern int amdgpu_si_support
;
122 #ifdef CONFIG_DRM_AMDGPU_CIK
123 extern int amdgpu_cik_support
;
126 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
127 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
128 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
129 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
130 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
131 #define AMDGPU_IB_POOL_SIZE 16
132 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
133 #define AMDGPUFB_CONN_LIMIT 4
134 #define AMDGPU_BIOS_NUM_SCRATCH 16
136 /* max number of IP instances */
137 #define AMDGPU_MAX_SDMA_INSTANCES 2
139 /* hard reset data */
140 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
143 #define AMDGPU_RESET_GFX (1 << 0)
144 #define AMDGPU_RESET_COMPUTE (1 << 1)
145 #define AMDGPU_RESET_DMA (1 << 2)
146 #define AMDGPU_RESET_CP (1 << 3)
147 #define AMDGPU_RESET_GRBM (1 << 4)
148 #define AMDGPU_RESET_DMA1 (1 << 5)
149 #define AMDGPU_RESET_RLC (1 << 6)
150 #define AMDGPU_RESET_SEM (1 << 7)
151 #define AMDGPU_RESET_IH (1 << 8)
152 #define AMDGPU_RESET_VMC (1 << 9)
153 #define AMDGPU_RESET_MC (1 << 10)
154 #define AMDGPU_RESET_DISPLAY (1 << 11)
155 #define AMDGPU_RESET_UVD (1 << 12)
156 #define AMDGPU_RESET_VCE (1 << 13)
157 #define AMDGPU_RESET_VCE1 (1 << 14)
159 /* GFX current status */
160 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
161 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
162 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
163 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
164 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
166 /* max cursor sizes (in pixels) */
167 #define CIK_CURSOR_WIDTH 128
168 #define CIK_CURSOR_HEIGHT 128
170 struct amdgpu_device
;
172 struct amdgpu_cs_parser
;
174 struct amdgpu_irq_src
;
178 AMDGPU_CP_IRQ_GFX_EOP
= 0,
179 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
,
180 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP
,
181 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP
,
182 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP
,
183 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP
,
184 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP
,
185 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP
,
186 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP
,
191 enum amdgpu_sdma_irq
{
192 AMDGPU_SDMA_IRQ_TRAP0
= 0,
193 AMDGPU_SDMA_IRQ_TRAP1
,
198 enum amdgpu_thermal_irq
{
199 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH
= 0,
200 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW
,
202 AMDGPU_THERMAL_IRQ_LAST
205 enum amdgpu_kiq_irq
{
206 AMDGPU_CP_KIQ_IRQ_DRIVER0
= 0,
207 AMDGPU_CP_KIQ_IRQ_LAST
210 int amdgpu_set_clockgating_state(struct amdgpu_device
*adev
,
211 enum amd_ip_block_type block_type
,
212 enum amd_clockgating_state state
);
213 int amdgpu_set_powergating_state(struct amdgpu_device
*adev
,
214 enum amd_ip_block_type block_type
,
215 enum amd_powergating_state state
);
216 void amdgpu_get_clockgating_state(struct amdgpu_device
*adev
, u32
*flags
);
217 int amdgpu_wait_for_idle(struct amdgpu_device
*adev
,
218 enum amd_ip_block_type block_type
);
219 bool amdgpu_is_idle(struct amdgpu_device
*adev
,
220 enum amd_ip_block_type block_type
);
222 #define AMDGPU_MAX_IP_NUM 16
224 struct amdgpu_ip_block_status
{
228 bool late_initialized
;
232 struct amdgpu_ip_block_version
{
233 const enum amd_ip_block_type type
;
237 const struct amd_ip_funcs
*funcs
;
240 struct amdgpu_ip_block
{
241 struct amdgpu_ip_block_status status
;
242 const struct amdgpu_ip_block_version
*version
;
245 int amdgpu_ip_block_version_cmp(struct amdgpu_device
*adev
,
246 enum amd_ip_block_type type
,
247 u32 major
, u32 minor
);
249 struct amdgpu_ip_block
* amdgpu_get_ip_block(struct amdgpu_device
*adev
,
250 enum amd_ip_block_type type
);
252 int amdgpu_ip_block_add(struct amdgpu_device
*adev
,
253 const struct amdgpu_ip_block_version
*ip_block_version
);
255 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
256 struct amdgpu_buffer_funcs
{
257 /* maximum bytes in a single operation */
258 uint32_t copy_max_bytes
;
260 /* number of dw to reserve per operation */
261 unsigned copy_num_dw
;
263 /* used for buffer migration */
264 void (*emit_copy_buffer
)(struct amdgpu_ib
*ib
,
265 /* src addr in bytes */
267 /* dst addr in bytes */
269 /* number of byte to transfer */
270 uint32_t byte_count
);
272 /* maximum bytes in a single operation */
273 uint32_t fill_max_bytes
;
275 /* number of dw to reserve per operation */
276 unsigned fill_num_dw
;
278 /* used for buffer clearing */
279 void (*emit_fill_buffer
)(struct amdgpu_ib
*ib
,
280 /* value to write to memory */
282 /* dst addr in bytes */
284 /* number of byte to fill */
285 uint32_t byte_count
);
288 /* provided by hw blocks that can write ptes, e.g., sdma */
289 struct amdgpu_vm_pte_funcs
{
290 /* copy pte entries from GART */
291 void (*copy_pte
)(struct amdgpu_ib
*ib
,
292 uint64_t pe
, uint64_t src
,
294 /* write pte one entry at a time with addr mapping */
295 void (*write_pte
)(struct amdgpu_ib
*ib
, uint64_t pe
,
296 uint64_t value
, unsigned count
,
298 /* for linear pte/pde updates without addr mapping */
299 void (*set_pte_pde
)(struct amdgpu_ib
*ib
,
301 uint64_t addr
, unsigned count
,
302 uint32_t incr
, uint64_t flags
);
305 /* provided by the gmc block */
306 struct amdgpu_gart_funcs
{
307 /* flush the vm tlb via mmio */
308 void (*flush_gpu_tlb
)(struct amdgpu_device
*adev
,
310 /* write pte/pde updates using the cpu */
311 int (*set_pte_pde
)(struct amdgpu_device
*adev
,
312 void *cpu_pt_addr
, /* cpu addr of page table */
313 uint32_t gpu_page_idx
, /* pte/pde to update */
314 uint64_t addr
, /* addr to write into pte/pde */
315 uint64_t flags
); /* access flags */
316 /* enable/disable PRT support */
317 void (*set_prt
)(struct amdgpu_device
*adev
, bool enable
);
318 /* set pte flags based per asic */
319 uint64_t (*get_vm_pte_flags
)(struct amdgpu_device
*adev
,
321 /* get the pde for a given mc addr */
322 u64 (*get_vm_pde
)(struct amdgpu_device
*adev
, u64 addr
);
323 uint32_t (*get_invalidate_req
)(unsigned int vm_id
);
326 /* provided by the ih block */
327 struct amdgpu_ih_funcs
{
328 /* ring read/write ptr handling, called from interrupt context */
329 u32 (*get_wptr
)(struct amdgpu_device
*adev
);
330 void (*decode_iv
)(struct amdgpu_device
*adev
,
331 struct amdgpu_iv_entry
*entry
);
332 void (*set_rptr
)(struct amdgpu_device
*adev
);
338 bool amdgpu_get_bios(struct amdgpu_device
*adev
);
339 bool amdgpu_read_bios(struct amdgpu_device
*adev
);
344 struct amdgpu_dummy_page
{
348 int amdgpu_dummy_page_init(struct amdgpu_device
*adev
);
349 void amdgpu_dummy_page_fini(struct amdgpu_device
*adev
);
356 #define AMDGPU_MAX_PPLL 3
358 struct amdgpu_clock
{
359 struct amdgpu_pll ppll
[AMDGPU_MAX_PPLL
];
360 struct amdgpu_pll spll
;
361 struct amdgpu_pll mpll
;
363 uint32_t default_mclk
;
364 uint32_t default_sclk
;
365 uint32_t default_dispclk
;
366 uint32_t current_dispclk
;
368 uint32_t max_pixel_clock
;
374 struct amdgpu_bo_list_entry
{
375 struct amdgpu_bo
*robj
;
376 struct ttm_validate_buffer tv
;
377 struct amdgpu_bo_va
*bo_va
;
379 struct page
**user_pages
;
380 int user_invalidated
;
383 struct amdgpu_bo_va_mapping
{
384 struct list_head list
;
388 uint64_t __subtree_last
;
393 /* bo virtual addresses in a specific vm */
394 struct amdgpu_bo_va
{
395 /* protected by bo being reserved */
396 struct list_head bo_list
;
397 struct dma_fence
*last_pt_update
;
400 /* protected by vm mutex and spinlock */
401 struct list_head vm_status
;
403 /* mappings for this bo_va */
404 struct list_head invalids
;
405 struct list_head valids
;
407 /* constant after initialization */
408 struct amdgpu_vm
*vm
;
409 struct amdgpu_bo
*bo
;
412 #define AMDGPU_GEM_DOMAIN_MAX 0x3
415 /* Protected by tbo.reserved */
416 u32 prefered_domains
;
418 struct ttm_place placements
[AMDGPU_GEM_DOMAIN_MAX
+ 1];
419 struct ttm_placement placement
;
420 struct ttm_buffer_object tbo
;
421 struct ttm_bo_kmap_obj kmap
;
429 unsigned prime_shared_count
;
430 /* list of all virtual address to which this bo
434 /* Constant after initialization */
435 struct drm_gem_object gem_base
;
436 struct amdgpu_bo
*parent
;
437 struct amdgpu_bo
*shadow
;
439 struct ttm_bo_kmap_obj dma_buf_vmap
;
440 struct amdgpu_mn
*mn
;
441 struct list_head mn_list
;
442 struct list_head shadow_list
;
444 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
446 void amdgpu_gem_object_free(struct drm_gem_object
*obj
);
447 int amdgpu_gem_object_open(struct drm_gem_object
*obj
,
448 struct drm_file
*file_priv
);
449 void amdgpu_gem_object_close(struct drm_gem_object
*obj
,
450 struct drm_file
*file_priv
);
451 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns
);
452 struct sg_table
*amdgpu_gem_prime_get_sg_table(struct drm_gem_object
*obj
);
453 struct drm_gem_object
*
454 amdgpu_gem_prime_import_sg_table(struct drm_device
*dev
,
455 struct dma_buf_attachment
*attach
,
456 struct sg_table
*sg
);
457 struct dma_buf
*amdgpu_gem_prime_export(struct drm_device
*dev
,
458 struct drm_gem_object
*gobj
,
460 int amdgpu_gem_prime_pin(struct drm_gem_object
*obj
);
461 void amdgpu_gem_prime_unpin(struct drm_gem_object
*obj
);
462 struct reservation_object
*amdgpu_gem_prime_res_obj(struct drm_gem_object
*);
463 void *amdgpu_gem_prime_vmap(struct drm_gem_object
*obj
);
464 void amdgpu_gem_prime_vunmap(struct drm_gem_object
*obj
, void *vaddr
);
465 int amdgpu_gem_debugfs_init(struct amdgpu_device
*adev
);
467 /* sub-allocation manager, it has to be protected by another lock.
468 * By conception this is an helper for other part of the driver
469 * like the indirect buffer or semaphore, which both have their
472 * Principe is simple, we keep a list of sub allocation in offset
473 * order (first entry has offset == 0, last entry has the highest
476 * When allocating new object we first check if there is room at
477 * the end total_size - (last_object_offset + last_object_size) >=
478 * alloc_size. If so we allocate new object there.
480 * When there is not enough room at the end, we start waiting for
481 * each sub object until we reach object_offset+object_size >=
482 * alloc_size, this object then become the sub object we return.
484 * Alignment can't be bigger than page size.
486 * Hole are not considered for allocation to keep things simple.
487 * Assumption is that there won't be hole (all object on same
491 #define AMDGPU_SA_NUM_FENCE_LISTS 32
493 struct amdgpu_sa_manager
{
494 wait_queue_head_t wq
;
495 struct amdgpu_bo
*bo
;
496 struct list_head
*hole
;
497 struct list_head flist
[AMDGPU_SA_NUM_FENCE_LISTS
];
498 struct list_head olist
;
506 /* sub-allocation buffer */
507 struct amdgpu_sa_bo
{
508 struct list_head olist
;
509 struct list_head flist
;
510 struct amdgpu_sa_manager
*manager
;
513 struct dma_fence
*fence
;
519 void amdgpu_gem_force_release(struct amdgpu_device
*adev
);
520 int amdgpu_gem_object_create(struct amdgpu_device
*adev
, unsigned long size
,
521 int alignment
, u32 initial_domain
,
522 u64 flags
, bool kernel
,
523 struct drm_gem_object
**obj
);
525 int amdgpu_mode_dumb_create(struct drm_file
*file_priv
,
526 struct drm_device
*dev
,
527 struct drm_mode_create_dumb
*args
);
528 int amdgpu_mode_dumb_mmap(struct drm_file
*filp
,
529 struct drm_device
*dev
,
530 uint32_t handle
, uint64_t *offset_p
);
531 int amdgpu_fence_slab_init(void);
532 void amdgpu_fence_slab_fini(void);
535 * GART structures, functions & helpers
539 #define AMDGPU_GPU_PAGE_SIZE 4096
540 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
541 #define AMDGPU_GPU_PAGE_SHIFT 12
542 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
545 dma_addr_t table_addr
;
546 struct amdgpu_bo
*robj
;
548 unsigned num_gpu_pages
;
549 unsigned num_cpu_pages
;
551 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
556 /* Asic default pte flags */
557 uint64_t gart_pte_flags
;
559 const struct amdgpu_gart_funcs
*gart_funcs
;
562 int amdgpu_gart_table_ram_alloc(struct amdgpu_device
*adev
);
563 void amdgpu_gart_table_ram_free(struct amdgpu_device
*adev
);
564 int amdgpu_gart_table_vram_alloc(struct amdgpu_device
*adev
);
565 void amdgpu_gart_table_vram_free(struct amdgpu_device
*adev
);
566 int amdgpu_gart_table_vram_pin(struct amdgpu_device
*adev
);
567 void amdgpu_gart_table_vram_unpin(struct amdgpu_device
*adev
);
568 int amdgpu_gart_init(struct amdgpu_device
*adev
);
569 void amdgpu_gart_fini(struct amdgpu_device
*adev
);
570 int amdgpu_gart_unbind(struct amdgpu_device
*adev
, uint64_t offset
,
572 int amdgpu_gart_bind(struct amdgpu_device
*adev
, uint64_t offset
,
573 int pages
, struct page
**pagelist
,
574 dma_addr_t
*dma_addr
, uint64_t flags
);
575 int amdgpu_ttm_recover_gart(struct amdgpu_device
*adev
);
578 * VMHUB structures, functions & helpers
580 struct amdgpu_vmhub
{
581 uint32_t ctx0_ptb_addr_lo32
;
582 uint32_t ctx0_ptb_addr_hi32
;
583 uint32_t vm_inv_eng0_req
;
584 uint32_t vm_inv_eng0_ack
;
585 uint32_t vm_context0_cntl
;
586 uint32_t vm_l2_pro_fault_status
;
587 uint32_t vm_l2_pro_fault_cntl
;
591 * GPU MC structures, functions & helpers
594 resource_size_t aper_size
;
595 resource_size_t aper_base
;
596 resource_size_t agp_base
;
597 /* for some chips with <= 32MB we need to lie
598 * about vram size near mc fb location */
600 u64 visible_vram_size
;
611 const struct firmware
*fw
; /* MC firmware */
613 struct amdgpu_irq_src vm_fault
;
615 uint32_t srbm_soft_reset
;
616 struct amdgpu_mode_mc_save save
;
618 uint64_t stolen_size
;
620 u64 shared_aperture_start
;
621 u64 shared_aperture_end
;
622 u64 private_aperture_start
;
623 u64 private_aperture_end
;
624 /* protects concurrent invalidation */
625 spinlock_t invalidate_lock
;
629 * GPU doorbell structures, functions & helpers
631 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
633 AMDGPU_DOORBELL_KIQ
= 0x000,
634 AMDGPU_DOORBELL_HIQ
= 0x001,
635 AMDGPU_DOORBELL_DIQ
= 0x002,
636 AMDGPU_DOORBELL_MEC_RING0
= 0x010,
637 AMDGPU_DOORBELL_MEC_RING1
= 0x011,
638 AMDGPU_DOORBELL_MEC_RING2
= 0x012,
639 AMDGPU_DOORBELL_MEC_RING3
= 0x013,
640 AMDGPU_DOORBELL_MEC_RING4
= 0x014,
641 AMDGPU_DOORBELL_MEC_RING5
= 0x015,
642 AMDGPU_DOORBELL_MEC_RING6
= 0x016,
643 AMDGPU_DOORBELL_MEC_RING7
= 0x017,
644 AMDGPU_DOORBELL_GFX_RING0
= 0x020,
645 AMDGPU_DOORBELL_sDMA_ENGINE0
= 0x1E0,
646 AMDGPU_DOORBELL_sDMA_ENGINE1
= 0x1E1,
647 AMDGPU_DOORBELL_IH
= 0x1E8,
648 AMDGPU_DOORBELL_MAX_ASSIGNMENT
= 0x3FF,
649 AMDGPU_DOORBELL_INVALID
= 0xFFFF
650 } AMDGPU_DOORBELL_ASSIGNMENT
;
652 struct amdgpu_doorbell
{
654 resource_size_t base
;
655 resource_size_t size
;
657 u32 num_doorbells
; /* Number of doorbells actually reserved for amdgpu. */
661 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
663 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
666 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
667 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
668 * Compute related doorbells are allocated from 0x00 to 0x8a
672 /* kernel scheduling */
673 AMDGPU_DOORBELL64_KIQ
= 0x00,
675 /* HSA interface queue and debug queue */
676 AMDGPU_DOORBELL64_HIQ
= 0x01,
677 AMDGPU_DOORBELL64_DIQ
= 0x02,
679 /* Compute engines */
680 AMDGPU_DOORBELL64_MEC_RING0
= 0x03,
681 AMDGPU_DOORBELL64_MEC_RING1
= 0x04,
682 AMDGPU_DOORBELL64_MEC_RING2
= 0x05,
683 AMDGPU_DOORBELL64_MEC_RING3
= 0x06,
684 AMDGPU_DOORBELL64_MEC_RING4
= 0x07,
685 AMDGPU_DOORBELL64_MEC_RING5
= 0x08,
686 AMDGPU_DOORBELL64_MEC_RING6
= 0x09,
687 AMDGPU_DOORBELL64_MEC_RING7
= 0x0a,
689 /* User queue doorbell range (128 doorbells) */
690 AMDGPU_DOORBELL64_USERQUEUE_START
= 0x0b,
691 AMDGPU_DOORBELL64_USERQUEUE_END
= 0x8a,
693 /* Graphics engine */
694 AMDGPU_DOORBELL64_GFX_RING0
= 0x8b,
697 * Other graphics doorbells can be allocated here: from 0x8c to 0xef
698 * Graphics voltage island aperture 1
699 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive
703 AMDGPU_DOORBELL64_sDMA_ENGINE0
= 0xF0,
704 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0
= 0xF1,
705 AMDGPU_DOORBELL64_sDMA_ENGINE1
= 0xF2,
706 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1
= 0xF3,
708 /* Interrupt handler */
709 AMDGPU_DOORBELL64_IH
= 0xF4, /* For legacy interrupt ring buffer */
710 AMDGPU_DOORBELL64_IH_RING1
= 0xF5, /* For page migration request log */
711 AMDGPU_DOORBELL64_IH_RING2
= 0xF6, /* For page migration translation/invalidation log */
713 /* VCN engine use 32 bits doorbell */
714 AMDGPU_DOORBELL64_VCN0_1
= 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
715 AMDGPU_DOORBELL64_VCN2_3
= 0xF9,
716 AMDGPU_DOORBELL64_VCN4_5
= 0xFA,
717 AMDGPU_DOORBELL64_VCN6_7
= 0xFB,
719 /* overlap the doorbell assignment with VCN as they are mutually exclusive
720 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
722 AMDGPU_DOORBELL64_RING0_1
= 0xF8,
723 AMDGPU_DOORBELL64_RING2_3
= 0xF9,
724 AMDGPU_DOORBELL64_RING4_5
= 0xFA,
725 AMDGPU_DOORBELL64_RING6_7
= 0xFB,
727 AMDGPU_DOORBELL64_UVD_RING0_1
= 0xFC,
728 AMDGPU_DOORBELL64_UVD_RING2_3
= 0xFD,
729 AMDGPU_DOORBELL64_UVD_RING4_5
= 0xFE,
730 AMDGPU_DOORBELL64_UVD_RING6_7
= 0xFF,
732 AMDGPU_DOORBELL64_MAX_ASSIGNMENT
= 0xFF,
733 AMDGPU_DOORBELL64_INVALID
= 0xFFFF
734 } AMDGPU_DOORBELL64_ASSIGNMENT
;
737 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device
*adev
,
738 phys_addr_t
*aperture_base
,
739 size_t *aperture_size
,
740 size_t *start_offset
);
746 struct amdgpu_flip_work
{
747 struct delayed_work flip_work
;
748 struct work_struct unpin_work
;
749 struct amdgpu_device
*adev
;
753 struct drm_pending_vblank_event
*event
;
754 struct amdgpu_bo
*old_abo
;
755 struct dma_fence
*excl
;
756 unsigned shared_count
;
757 struct dma_fence
**shared
;
758 struct dma_fence_cb cb
;
768 struct amdgpu_sa_bo
*sa_bo
;
775 extern const struct amd_sched_backend_ops amdgpu_sched_ops
;
777 int amdgpu_job_alloc(struct amdgpu_device
*adev
, unsigned num_ibs
,
778 struct amdgpu_job
**job
, struct amdgpu_vm
*vm
);
779 int amdgpu_job_alloc_with_ib(struct amdgpu_device
*adev
, unsigned size
,
780 struct amdgpu_job
**job
);
782 void amdgpu_job_free_resources(struct amdgpu_job
*job
);
783 void amdgpu_job_free(struct amdgpu_job
*job
);
784 int amdgpu_job_submit(struct amdgpu_job
*job
, struct amdgpu_ring
*ring
,
785 struct amd_sched_entity
*entity
, void *owner
,
786 struct dma_fence
**f
);
791 struct amdgpu_queue_mapper
{
794 /* protected by lock */
795 struct amdgpu_ring
*queue_map
[AMDGPU_MAX_RINGS
];
798 struct amdgpu_queue_mgr
{
799 struct amdgpu_queue_mapper mapper
[AMDGPU_MAX_IP_NUM
];
802 int amdgpu_queue_mgr_init(struct amdgpu_device
*adev
,
803 struct amdgpu_queue_mgr
*mgr
);
804 int amdgpu_queue_mgr_fini(struct amdgpu_device
*adev
,
805 struct amdgpu_queue_mgr
*mgr
);
806 int amdgpu_queue_mgr_map(struct amdgpu_device
*adev
,
807 struct amdgpu_queue_mgr
*mgr
,
808 int hw_ip
, int instance
, int ring
,
809 struct amdgpu_ring
**out_ring
);
812 * context related structures
815 struct amdgpu_ctx_ring
{
817 struct dma_fence
**fences
;
818 struct amd_sched_entity entity
;
822 struct kref refcount
;
823 struct amdgpu_device
*adev
;
824 struct amdgpu_queue_mgr queue_mgr
;
825 unsigned reset_counter
;
826 spinlock_t ring_lock
;
827 struct dma_fence
**fences
;
828 struct amdgpu_ctx_ring rings
[AMDGPU_MAX_RINGS
];
829 bool preamble_presented
;
832 struct amdgpu_ctx_mgr
{
833 struct amdgpu_device
*adev
;
835 /* protected by lock */
836 struct idr ctx_handles
;
839 struct amdgpu_ctx
*amdgpu_ctx_get(struct amdgpu_fpriv
*fpriv
, uint32_t id
);
840 int amdgpu_ctx_put(struct amdgpu_ctx
*ctx
);
842 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx
*ctx
, struct amdgpu_ring
*ring
,
843 struct dma_fence
*fence
);
844 struct dma_fence
*amdgpu_ctx_get_fence(struct amdgpu_ctx
*ctx
,
845 struct amdgpu_ring
*ring
, uint64_t seq
);
847 int amdgpu_ctx_ioctl(struct drm_device
*dev
, void *data
,
848 struct drm_file
*filp
);
850 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr
*mgr
);
851 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr
*mgr
);
854 * file private structure
857 struct amdgpu_fpriv
{
859 struct amdgpu_bo_va
*prt_va
;
860 struct mutex bo_list_lock
;
861 struct idr bo_list_handles
;
862 struct amdgpu_ctx_mgr ctx_mgr
;
863 u32 vram_lost_counter
;
870 struct amdgpu_bo_list
{
872 struct rcu_head rhead
;
873 struct kref refcount
;
874 struct amdgpu_bo
*gds_obj
;
875 struct amdgpu_bo
*gws_obj
;
876 struct amdgpu_bo
*oa_obj
;
877 unsigned first_userptr
;
878 unsigned num_entries
;
879 struct amdgpu_bo_list_entry
*array
;
882 struct amdgpu_bo_list
*
883 amdgpu_bo_list_get(struct amdgpu_fpriv
*fpriv
, int id
);
884 void amdgpu_bo_list_get_list(struct amdgpu_bo_list
*list
,
885 struct list_head
*validated
);
886 void amdgpu_bo_list_put(struct amdgpu_bo_list
*list
);
887 void amdgpu_bo_list_free(struct amdgpu_bo_list
*list
);
892 #include "clearstate_defs.h"
894 struct amdgpu_rlc_funcs
{
895 void (*enter_safe_mode
)(struct amdgpu_device
*adev
);
896 void (*exit_safe_mode
)(struct amdgpu_device
*adev
);
900 /* for power gating */
901 struct amdgpu_bo
*save_restore_obj
;
902 uint64_t save_restore_gpu_addr
;
903 volatile uint32_t *sr_ptr
;
906 /* for clear state */
907 struct amdgpu_bo
*clear_state_obj
;
908 uint64_t clear_state_gpu_addr
;
909 volatile uint32_t *cs_ptr
;
910 const struct cs_section_def
*cs_data
;
911 u32 clear_state_size
;
913 struct amdgpu_bo
*cp_table_obj
;
914 uint64_t cp_table_gpu_addr
;
915 volatile uint32_t *cp_table_ptr
;
918 /* safe mode for updating CG/PG state */
920 const struct amdgpu_rlc_funcs
*funcs
;
922 /* for firmware data */
923 u32 save_and_restore_offset
;
924 u32 clear_state_descriptor_offset
;
925 u32 avail_scratch_ram_locations
;
926 u32 reg_restore_list_size
;
927 u32 reg_list_format_start
;
928 u32 reg_list_format_separate_start
;
929 u32 starting_offsets_start
;
930 u32 reg_list_format_size_bytes
;
931 u32 reg_list_size_bytes
;
933 u32
*register_list_format
;
934 u32
*register_restore
;
937 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
940 struct amdgpu_bo
*hpd_eop_obj
;
941 u64 hpd_eop_gpu_addr
;
942 struct amdgpu_bo
*mec_fw_obj
;
945 u32 num_pipe_per_mec
;
946 u32 num_queue_per_pipe
;
947 void *mqd_backup
[AMDGPU_MAX_COMPUTE_RINGS
+ 1];
949 /* These are the resources for which amdgpu takes ownership */
950 DECLARE_BITMAP(queue_bitmap
, AMDGPU_MAX_COMPUTE_QUEUES
);
955 struct amdgpu_bo
*eop_obj
;
956 struct mutex ring_mutex
;
957 struct amdgpu_ring ring
;
958 struct amdgpu_irq_src irq
;
962 * GPU scratch registers structures, functions & helpers
964 struct amdgpu_scratch
{
973 #define AMDGPU_GFX_MAX_SE 4
974 #define AMDGPU_GFX_MAX_SH_PER_SE 2
976 struct amdgpu_rb_config
{
977 uint32_t rb_backend_disable
;
978 uint32_t user_rb_backend_disable
;
979 uint32_t raster_config
;
980 uint32_t raster_config_1
;
983 struct gb_addr_config
{
984 uint16_t pipe_interleave_size
;
986 uint8_t max_compress_frags
;
989 uint8_t num_rb_per_se
;
992 struct amdgpu_gfx_config
{
993 unsigned max_shader_engines
;
994 unsigned max_tile_pipes
;
995 unsigned max_cu_per_sh
;
996 unsigned max_sh_per_se
;
997 unsigned max_backends_per_se
;
998 unsigned max_texture_channel_caches
;
1000 unsigned max_gs_threads
;
1001 unsigned max_hw_contexts
;
1002 unsigned sc_prim_fifo_size_frontend
;
1003 unsigned sc_prim_fifo_size_backend
;
1004 unsigned sc_hiz_tile_fifo_size
;
1005 unsigned sc_earlyz_tile_fifo_size
;
1007 unsigned num_tile_pipes
;
1008 unsigned backend_enable_mask
;
1009 unsigned mem_max_burst_length_bytes
;
1010 unsigned mem_row_size_in_kb
;
1011 unsigned shader_engine_tile_size
;
1013 unsigned multi_gpu_tile_size
;
1014 unsigned mc_arb_ramcfg
;
1015 unsigned gb_addr_config
;
1017 unsigned gs_vgt_table_depth
;
1018 unsigned gs_prim_buffer_depth
;
1020 uint32_t tile_mode_array
[32];
1021 uint32_t macrotile_mode_array
[16];
1023 struct gb_addr_config gb_addr_config_fields
;
1024 struct amdgpu_rb_config rb_config
[AMDGPU_GFX_MAX_SE
][AMDGPU_GFX_MAX_SH_PER_SE
];
1026 /* gfx configure feature */
1027 uint32_t double_offchip_lds_buf
;
1030 struct amdgpu_cu_info
{
1031 uint32_t max_waves_per_simd
;
1032 uint32_t wave_front_size
;
1033 uint32_t max_scratch_slots_per_cu
;
1036 /* total active CU number */
1038 uint32_t ao_cu_mask
;
1039 uint32_t ao_cu_bitmap
[4][4];
1040 uint32_t bitmap
[4][4];
1043 struct amdgpu_gfx_funcs
{
1044 /* get the gpu clock counter */
1045 uint64_t (*get_gpu_clock_counter
)(struct amdgpu_device
*adev
);
1046 void (*select_se_sh
)(struct amdgpu_device
*adev
, u32 se_num
, u32 sh_num
, u32 instance
);
1047 void (*read_wave_data
)(struct amdgpu_device
*adev
, uint32_t simd
, uint32_t wave
, uint32_t *dst
, int *no_fields
);
1048 void (*read_wave_vgprs
)(struct amdgpu_device
*adev
, uint32_t simd
, uint32_t wave
, uint32_t thread
, uint32_t start
, uint32_t size
, uint32_t *dst
);
1049 void (*read_wave_sgprs
)(struct amdgpu_device
*adev
, uint32_t simd
, uint32_t wave
, uint32_t start
, uint32_t size
, uint32_t *dst
);
1052 struct amdgpu_ngg_buf
{
1053 struct amdgpu_bo
*bo
;
1068 struct amdgpu_ngg_buf buf
[NGG_BUF_MAX
];
1069 uint32_t gds_reserve_addr
;
1070 uint32_t gds_reserve_size
;
1075 struct mutex gpu_clock_mutex
;
1076 struct amdgpu_gfx_config config
;
1077 struct amdgpu_rlc rlc
;
1078 struct amdgpu_mec mec
;
1079 struct amdgpu_kiq kiq
;
1080 struct amdgpu_scratch scratch
;
1081 const struct firmware
*me_fw
; /* ME firmware */
1082 uint32_t me_fw_version
;
1083 const struct firmware
*pfp_fw
; /* PFP firmware */
1084 uint32_t pfp_fw_version
;
1085 const struct firmware
*ce_fw
; /* CE firmware */
1086 uint32_t ce_fw_version
;
1087 const struct firmware
*rlc_fw
; /* RLC firmware */
1088 uint32_t rlc_fw_version
;
1089 const struct firmware
*mec_fw
; /* MEC firmware */
1090 uint32_t mec_fw_version
;
1091 const struct firmware
*mec2_fw
; /* MEC2 firmware */
1092 uint32_t mec2_fw_version
;
1093 uint32_t me_feature_version
;
1094 uint32_t ce_feature_version
;
1095 uint32_t pfp_feature_version
;
1096 uint32_t rlc_feature_version
;
1097 uint32_t mec_feature_version
;
1098 uint32_t mec2_feature_version
;
1099 struct amdgpu_ring gfx_ring
[AMDGPU_MAX_GFX_RINGS
];
1100 unsigned num_gfx_rings
;
1101 struct amdgpu_ring compute_ring
[AMDGPU_MAX_COMPUTE_RINGS
];
1102 unsigned num_compute_rings
;
1103 struct amdgpu_irq_src eop_irq
;
1104 struct amdgpu_irq_src priv_reg_irq
;
1105 struct amdgpu_irq_src priv_inst_irq
;
1107 uint32_t gfx_current_status
;
1109 unsigned ce_ram_size
;
1110 struct amdgpu_cu_info cu_info
;
1111 const struct amdgpu_gfx_funcs
*funcs
;
1114 uint32_t grbm_soft_reset
;
1115 uint32_t srbm_soft_reset
;
1120 struct amdgpu_ngg ngg
;
1123 int amdgpu_ib_get(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
1124 unsigned size
, struct amdgpu_ib
*ib
);
1125 void amdgpu_ib_free(struct amdgpu_device
*adev
, struct amdgpu_ib
*ib
,
1126 struct dma_fence
*f
);
1127 int amdgpu_ib_schedule(struct amdgpu_ring
*ring
, unsigned num_ibs
,
1128 struct amdgpu_ib
*ibs
, struct amdgpu_job
*job
,
1129 struct dma_fence
**f
);
1130 int amdgpu_ib_pool_init(struct amdgpu_device
*adev
);
1131 void amdgpu_ib_pool_fini(struct amdgpu_device
*adev
);
1132 int amdgpu_ib_ring_tests(struct amdgpu_device
*adev
);
1137 struct amdgpu_cs_chunk
{
1143 struct amdgpu_cs_parser
{
1144 struct amdgpu_device
*adev
;
1145 struct drm_file
*filp
;
1146 struct amdgpu_ctx
*ctx
;
1150 struct amdgpu_cs_chunk
*chunks
;
1152 /* scheduler job object */
1153 struct amdgpu_job
*job
;
1155 /* buffer objects */
1156 struct ww_acquire_ctx ticket
;
1157 struct amdgpu_bo_list
*bo_list
;
1158 struct amdgpu_bo_list_entry vm_pd
;
1159 struct list_head validated
;
1160 struct dma_fence
*fence
;
1161 uint64_t bytes_moved_threshold
;
1162 uint64_t bytes_moved
;
1163 struct amdgpu_bo_list_entry
*evictable
;
1166 struct amdgpu_bo_list_entry uf_entry
;
1168 unsigned num_post_dep_syncobjs
;
1169 struct drm_syncobj
**post_dep_syncobjs
;
1172 #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
1173 #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
1174 #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
1177 struct amd_sched_job base
;
1178 struct amdgpu_device
*adev
;
1179 struct amdgpu_vm
*vm
;
1180 struct amdgpu_ring
*ring
;
1181 struct amdgpu_sync sync
;
1182 struct amdgpu_sync dep_sync
;
1183 struct amdgpu_sync sched_sync
;
1184 struct amdgpu_ib
*ibs
;
1185 struct dma_fence
*fence
; /* the hw fence */
1186 uint32_t preamble_status
;
1189 uint64_t fence_ctx
; /* the fence_context this job uses */
1190 bool vm_needs_flush
;
1192 uint64_t vm_pd_addr
;
1193 uint32_t gds_base
, gds_size
;
1194 uint32_t gws_base
, gws_size
;
1195 uint32_t oa_base
, oa_size
;
1197 /* user fence handling */
1199 uint64_t uf_sequence
;
1202 #define to_amdgpu_job(sched_job) \
1203 container_of((sched_job), struct amdgpu_job, base)
1205 static inline u32
amdgpu_get_ib_value(struct amdgpu_cs_parser
*p
,
1206 uint32_t ib_idx
, int idx
)
1208 return p
->job
->ibs
[ib_idx
].ptr
[idx
];
1211 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser
*p
,
1212 uint32_t ib_idx
, int idx
,
1215 p
->job
->ibs
[ib_idx
].ptr
[idx
] = value
;
1221 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1224 struct amdgpu_bo
*wb_obj
;
1225 volatile uint32_t *wb
;
1227 u32 num_wb
; /* Number of wb slots actually reserved for amdgpu. */
1228 unsigned long used
[DIV_ROUND_UP(AMDGPU_MAX_WB
, BITS_PER_LONG
)];
1231 int amdgpu_wb_get(struct amdgpu_device
*adev
, u32
*wb
);
1232 void amdgpu_wb_free(struct amdgpu_device
*adev
, u32 wb
);
1233 int amdgpu_wb_get_64bit(struct amdgpu_device
*adev
, u32
*wb
);
1234 void amdgpu_wb_free_64bit(struct amdgpu_device
*adev
, u32 wb
);
1236 void amdgpu_get_pcie_info(struct amdgpu_device
*adev
);
1241 struct amdgpu_sdma_instance
{
1243 const struct firmware
*fw
;
1244 uint32_t fw_version
;
1245 uint32_t feature_version
;
1247 struct amdgpu_ring ring
;
1251 struct amdgpu_sdma
{
1252 struct amdgpu_sdma_instance instance
[AMDGPU_MAX_SDMA_INSTANCES
];
1253 #ifdef CONFIG_DRM_AMDGPU_SI
1254 //SI DMA has a difference trap irq number for the second engine
1255 struct amdgpu_irq_src trap_irq_1
;
1257 struct amdgpu_irq_src trap_irq
;
1258 struct amdgpu_irq_src illegal_inst_irq
;
1260 uint32_t srbm_soft_reset
;
1266 enum amdgpu_firmware_load_type
{
1267 AMDGPU_FW_LOAD_DIRECT
= 0,
1272 struct amdgpu_firmware
{
1273 struct amdgpu_firmware_info ucode
[AMDGPU_UCODE_ID_MAXIMUM
];
1274 enum amdgpu_firmware_load_type load_type
;
1275 struct amdgpu_bo
*fw_buf
;
1276 unsigned int fw_size
;
1277 unsigned int max_ucodes
;
1278 /* firmwares are loaded by psp instead of smu from vega10 */
1279 const struct amdgpu_psp_funcs
*funcs
;
1280 struct amdgpu_bo
*rbuf
;
1283 /* gpu info firmware data pointer */
1284 const struct firmware
*gpu_info_fw
;
1290 void amdgpu_benchmark(struct amdgpu_device
*adev
, int test_number
);
1296 void amdgpu_test_moves(struct amdgpu_device
*adev
);
1301 #if defined(CONFIG_MMU_NOTIFIER)
1302 int amdgpu_mn_register(struct amdgpu_bo
*bo
, unsigned long addr
);
1303 void amdgpu_mn_unregister(struct amdgpu_bo
*bo
);
1305 static inline int amdgpu_mn_register(struct amdgpu_bo
*bo
, unsigned long addr
)
1309 static inline void amdgpu_mn_unregister(struct amdgpu_bo
*bo
) {}
1315 struct amdgpu_debugfs
{
1316 const struct drm_info_list
*files
;
1320 int amdgpu_debugfs_add_files(struct amdgpu_device
*adev
,
1321 const struct drm_info_list
*files
,
1323 int amdgpu_debugfs_fence_init(struct amdgpu_device
*adev
);
1325 #if defined(CONFIG_DEBUG_FS)
1326 int amdgpu_debugfs_init(struct drm_minor
*minor
);
1329 int amdgpu_debugfs_firmware_init(struct amdgpu_device
*adev
);
1332 * amdgpu smumgr functions
1334 struct amdgpu_smumgr_funcs
{
1335 int (*check_fw_load_finish
)(struct amdgpu_device
*adev
, uint32_t fwtype
);
1336 int (*request_smu_load_fw
)(struct amdgpu_device
*adev
);
1337 int (*request_smu_specific_fw
)(struct amdgpu_device
*adev
, uint32_t fwtype
);
1343 struct amdgpu_smumgr
{
1344 struct amdgpu_bo
*toc_buf
;
1345 struct amdgpu_bo
*smu_buf
;
1346 /* asic priv smu data */
1348 spinlock_t smu_lock
;
1349 /* smumgr functions */
1350 const struct amdgpu_smumgr_funcs
*smumgr_funcs
;
1351 /* ucode loading complete flag */
1356 * ASIC specific register table accessible by UMD
1358 struct amdgpu_allowed_register_entry
{
1359 uint32_t reg_offset
;
1364 * ASIC specific functions.
1366 struct amdgpu_asic_funcs
{
1367 bool (*read_disabled_bios
)(struct amdgpu_device
*adev
);
1368 bool (*read_bios_from_rom
)(struct amdgpu_device
*adev
,
1369 u8
*bios
, u32 length_bytes
);
1370 int (*read_register
)(struct amdgpu_device
*adev
, u32 se_num
,
1371 u32 sh_num
, u32 reg_offset
, u32
*value
);
1372 void (*set_vga_state
)(struct amdgpu_device
*adev
, bool state
);
1373 int (*reset
)(struct amdgpu_device
*adev
);
1374 /* get the reference clock */
1375 u32 (*get_xclk
)(struct amdgpu_device
*adev
);
1376 /* MM block clocks */
1377 int (*set_uvd_clocks
)(struct amdgpu_device
*adev
, u32 vclk
, u32 dclk
);
1378 int (*set_vce_clocks
)(struct amdgpu_device
*adev
, u32 evclk
, u32 ecclk
);
1379 /* static power management */
1380 int (*get_pcie_lanes
)(struct amdgpu_device
*adev
);
1381 void (*set_pcie_lanes
)(struct amdgpu_device
*adev
, int lanes
);
1382 /* get config memsize register */
1383 u32 (*get_config_memsize
)(struct amdgpu_device
*adev
);
1389 int amdgpu_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1390 struct drm_file
*filp
);
1391 int amdgpu_bo_list_ioctl(struct drm_device
*dev
, void *data
,
1392 struct drm_file
*filp
);
1394 int amdgpu_gem_info_ioctl(struct drm_device
*dev
, void *data
,
1395 struct drm_file
*filp
);
1396 int amdgpu_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
1397 struct drm_file
*filp
);
1398 int amdgpu_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1399 struct drm_file
*filp
);
1400 int amdgpu_gem_wait_idle_ioctl(struct drm_device
*dev
, void *data
,
1401 struct drm_file
*filp
);
1402 int amdgpu_gem_va_ioctl(struct drm_device
*dev
, void *data
,
1403 struct drm_file
*filp
);
1404 int amdgpu_gem_op_ioctl(struct drm_device
*dev
, void *data
,
1405 struct drm_file
*filp
);
1406 int amdgpu_cs_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
1407 int amdgpu_cs_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
1408 int amdgpu_cs_wait_fences_ioctl(struct drm_device
*dev
, void *data
,
1409 struct drm_file
*filp
);
1411 int amdgpu_gem_metadata_ioctl(struct drm_device
*dev
, void *data
,
1412 struct drm_file
*filp
);
1414 /* VRAM scratch page for HDP bug, default vram page */
1415 struct amdgpu_vram_scratch
{
1416 struct amdgpu_bo
*robj
;
1417 volatile uint32_t *ptr
;
1424 struct amdgpu_atif_notification_cfg
{
1429 struct amdgpu_atif_notifications
{
1430 bool display_switch
;
1431 bool expansion_mode_change
;
1433 bool forced_power_state
;
1434 bool system_power_state
;
1435 bool display_conf_change
;
1437 bool brightness_change
;
1438 bool dgpu_display_event
;
1441 struct amdgpu_atif_functions
{
1443 bool sbios_requests
;
1444 bool select_active_disp
;
1446 bool get_tv_standard
;
1447 bool set_tv_standard
;
1448 bool get_panel_expansion_mode
;
1449 bool set_panel_expansion_mode
;
1450 bool temperature_change
;
1451 bool graphics_device_types
;
1454 struct amdgpu_atif
{
1455 struct amdgpu_atif_notifications notifications
;
1456 struct amdgpu_atif_functions functions
;
1457 struct amdgpu_atif_notification_cfg notification_cfg
;
1458 struct amdgpu_encoder
*encoder_for_bl
;
1461 struct amdgpu_atcs_functions
{
1465 bool pcie_bus_width
;
1468 struct amdgpu_atcs
{
1469 struct amdgpu_atcs_functions functions
;
1475 struct cgs_device
*amdgpu_cgs_create_device(struct amdgpu_device
*adev
);
1476 void amdgpu_cgs_destroy_device(struct cgs_device
*cgs_device
);
1479 * Core structure, functions and helpers.
1481 typedef uint32_t (*amdgpu_rreg_t
)(struct amdgpu_device
*, uint32_t);
1482 typedef void (*amdgpu_wreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t);
1484 typedef uint32_t (*amdgpu_block_rreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t);
1485 typedef void (*amdgpu_block_wreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t, uint32_t);
1487 #define AMDGPU_RESET_MAGIC_NUM 64
1488 struct amdgpu_device
{
1490 struct drm_device
*ddev
;
1491 struct pci_dev
*pdev
;
1493 #ifdef CONFIG_DRM_AMD_ACP
1494 struct amdgpu_acp acp
;
1498 enum amd_asic_type asic_type
;
1501 uint32_t external_rev_id
;
1502 unsigned long flags
;
1504 const struct amdgpu_asic_funcs
*asic_funcs
;
1508 struct work_struct reset_work
;
1509 struct notifier_block acpi_nb
;
1510 struct amdgpu_i2c_chan
*i2c_bus
[AMDGPU_MAX_I2C_BUS
];
1511 struct amdgpu_debugfs debugfs
[AMDGPU_DEBUGFS_MAX_COMPONENTS
];
1512 unsigned debugfs_count
;
1513 #if defined(CONFIG_DEBUG_FS)
1514 struct dentry
*debugfs_regs
[AMDGPU_DEBUGFS_MAX_COMPONENTS
];
1516 struct amdgpu_atif atif
;
1517 struct amdgpu_atcs atcs
;
1518 struct mutex srbm_mutex
;
1519 /* GRBM index mutex. Protects concurrent access to GRBM index */
1520 struct mutex grbm_idx_mutex
;
1521 struct dev_pm_domain vga_pm_domain
;
1522 bool have_disp_power_ref
;
1528 struct amdgpu_bo
*stollen_vga_memory
;
1529 uint32_t bios_scratch_reg_offset
;
1530 uint32_t bios_scratch
[AMDGPU_BIOS_NUM_SCRATCH
];
1532 /* Register/doorbell mmio */
1533 resource_size_t rmmio_base
;
1534 resource_size_t rmmio_size
;
1535 void __iomem
*rmmio
;
1536 /* protects concurrent MM_INDEX/DATA based register access */
1537 spinlock_t mmio_idx_lock
;
1538 /* protects concurrent SMC based register access */
1539 spinlock_t smc_idx_lock
;
1540 amdgpu_rreg_t smc_rreg
;
1541 amdgpu_wreg_t smc_wreg
;
1542 /* protects concurrent PCIE register access */
1543 spinlock_t pcie_idx_lock
;
1544 amdgpu_rreg_t pcie_rreg
;
1545 amdgpu_wreg_t pcie_wreg
;
1546 amdgpu_rreg_t pciep_rreg
;
1547 amdgpu_wreg_t pciep_wreg
;
1548 /* protects concurrent UVD register access */
1549 spinlock_t uvd_ctx_idx_lock
;
1550 amdgpu_rreg_t uvd_ctx_rreg
;
1551 amdgpu_wreg_t uvd_ctx_wreg
;
1552 /* protects concurrent DIDT register access */
1553 spinlock_t didt_idx_lock
;
1554 amdgpu_rreg_t didt_rreg
;
1555 amdgpu_wreg_t didt_wreg
;
1556 /* protects concurrent gc_cac register access */
1557 spinlock_t gc_cac_idx_lock
;
1558 amdgpu_rreg_t gc_cac_rreg
;
1559 amdgpu_wreg_t gc_cac_wreg
;
1560 /* protects concurrent ENDPOINT (audio) register access */
1561 spinlock_t audio_endpt_idx_lock
;
1562 amdgpu_block_rreg_t audio_endpt_rreg
;
1563 amdgpu_block_wreg_t audio_endpt_wreg
;
1564 void __iomem
*rio_mem
;
1565 resource_size_t rio_mem_size
;
1566 struct amdgpu_doorbell doorbell
;
1568 /* clock/pll info */
1569 struct amdgpu_clock clock
;
1572 struct amdgpu_mc mc
;
1573 struct amdgpu_gart gart
;
1574 struct amdgpu_dummy_page dummy_page
;
1575 struct amdgpu_vm_manager vm_manager
;
1576 struct amdgpu_vmhub vmhub
[AMDGPU_MAX_VMHUBS
];
1578 /* memory management */
1579 struct amdgpu_mman mman
;
1580 struct amdgpu_vram_scratch vram_scratch
;
1581 struct amdgpu_wb wb
;
1582 atomic64_t vram_usage
;
1583 atomic64_t vram_vis_usage
;
1584 atomic64_t gtt_usage
;
1585 atomic64_t num_bytes_moved
;
1586 atomic64_t num_evictions
;
1587 atomic64_t num_vram_cpu_page_faults
;
1588 atomic_t gpu_reset_counter
;
1589 atomic_t vram_lost_counter
;
1591 /* data for buffer migration throttling */
1595 s64 accum_us
; /* accumulated microseconds */
1600 bool enable_virtual_display
;
1601 struct amdgpu_mode_info mode_info
;
1602 struct work_struct hotplug_work
;
1603 struct amdgpu_irq_src crtc_irq
;
1604 struct amdgpu_irq_src pageflip_irq
;
1605 struct amdgpu_irq_src hpd_irq
;
1610 struct amdgpu_ring
*rings
[AMDGPU_MAX_RINGS
];
1612 struct amdgpu_sa_manager ring_tmp_bo
;
1615 struct amdgpu_irq irq
;
1618 struct amd_powerplay powerplay
;
1620 bool pp_force_state_enabled
;
1623 struct amdgpu_pm pm
;
1628 struct amdgpu_smumgr smu
;
1631 struct amdgpu_gfx gfx
;
1634 struct amdgpu_sdma sdma
;
1639 struct amdgpu_uvd uvd
;
1642 struct amdgpu_vce vce
;
1646 struct amdgpu_vcn vcn
;
1650 struct amdgpu_firmware firmware
;
1653 struct psp_context psp
;
1656 struct amdgpu_gds gds
;
1658 struct amdgpu_ip_block ip_blocks
[AMDGPU_MAX_IP_NUM
];
1660 struct mutex mn_lock
;
1661 DECLARE_HASHTABLE(mn_hash
, 7);
1663 /* tracking pinned memory */
1665 u64 invisible_pin_size
;
1668 /* amdkfd interface */
1669 struct kfd_dev
*kfd
;
1671 /* delayed work_func for deferring clockgating during resume */
1672 struct delayed_work late_init_work
;
1674 struct amdgpu_virt virt
;
1676 /* link all shadow bo */
1677 struct list_head shadow_list
;
1678 struct mutex shadow_list_lock
;
1680 spinlock_t gtt_list_lock
;
1681 struct list_head gtt_list
;
1682 /* keep an lru list of rings by HW IP */
1683 struct list_head ring_lru_list
;
1684 spinlock_t ring_lru_list_lock
;
1686 /* record hw reset is performed */
1688 u8 reset_magic
[AMDGPU_RESET_MAGIC_NUM
];
1692 static inline struct amdgpu_device
*amdgpu_ttm_adev(struct ttm_bo_device
*bdev
)
1694 return container_of(bdev
, struct amdgpu_device
, mman
.bdev
);
1697 int amdgpu_device_init(struct amdgpu_device
*adev
,
1698 struct drm_device
*ddev
,
1699 struct pci_dev
*pdev
,
1701 void amdgpu_device_fini(struct amdgpu_device
*adev
);
1702 int amdgpu_gpu_wait_for_idle(struct amdgpu_device
*adev
);
1704 uint32_t amdgpu_mm_rreg(struct amdgpu_device
*adev
, uint32_t reg
,
1705 uint32_t acc_flags
);
1706 void amdgpu_mm_wreg(struct amdgpu_device
*adev
, uint32_t reg
, uint32_t v
,
1707 uint32_t acc_flags
);
1708 u32
amdgpu_io_rreg(struct amdgpu_device
*adev
, u32 reg
);
1709 void amdgpu_io_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
);
1711 u32
amdgpu_mm_rdoorbell(struct amdgpu_device
*adev
, u32 index
);
1712 void amdgpu_mm_wdoorbell(struct amdgpu_device
*adev
, u32 index
, u32 v
);
1713 u64
amdgpu_mm_rdoorbell64(struct amdgpu_device
*adev
, u32 index
);
1714 void amdgpu_mm_wdoorbell64(struct amdgpu_device
*adev
, u32 index
, u64 v
);
1717 * Registers read & write functions.
1720 #define AMDGPU_REGS_IDX (1<<0)
1721 #define AMDGPU_REGS_NO_KIQ (1<<1)
1723 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1724 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1726 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1727 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1728 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1729 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1730 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
1731 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1732 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1733 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1734 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1735 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1736 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1737 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1738 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1739 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1740 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1741 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1742 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1743 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1744 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1745 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1746 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1747 #define WREG32_P(reg, val, mask) \
1749 uint32_t tmp_ = RREG32(reg); \
1751 tmp_ |= ((val) & ~(mask)); \
1752 WREG32(reg, tmp_); \
1754 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1755 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1756 #define WREG32_PLL_P(reg, val, mask) \
1758 uint32_t tmp_ = RREG32_PLL(reg); \
1760 tmp_ |= ((val) & ~(mask)); \
1761 WREG32_PLL(reg, tmp_); \
1763 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1764 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1765 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1767 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1768 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
1769 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1770 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
1772 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1773 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1775 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
1776 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1777 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1779 #define REG_GET_FIELD(value, reg, field) \
1780 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1782 #define WREG32_FIELD(reg, field, val) \
1783 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1785 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1786 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1791 #define RBIOS8(i) (adev->bios[i])
1792 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1793 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1798 static inline void amdgpu_ring_write(struct amdgpu_ring
*ring
, uint32_t v
)
1800 if (ring
->count_dw
<= 0)
1801 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
1802 ring
->ring
[ring
->wptr
++ & ring
->buf_mask
] = v
;
1803 ring
->wptr
&= ring
->ptr_mask
;
1807 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring
*ring
, void *src
, int count_dw
)
1809 unsigned occupied
, chunk1
, chunk2
;
1812 if (unlikely(ring
->count_dw
< count_dw
)) {
1813 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
1817 occupied
= ring
->wptr
& ring
->buf_mask
;
1818 dst
= (void *)&ring
->ring
[occupied
];
1819 chunk1
= ring
->buf_mask
+ 1 - occupied
;
1820 chunk1
= (chunk1
>= count_dw
) ? count_dw
: chunk1
;
1821 chunk2
= count_dw
- chunk1
;
1826 memcpy(dst
, src
, chunk1
);
1830 dst
= (void *)ring
->ring
;
1831 memcpy(dst
, src
, chunk2
);
1834 ring
->wptr
+= count_dw
;
1835 ring
->wptr
&= ring
->ptr_mask
;
1836 ring
->count_dw
-= count_dw
;
1839 static inline struct amdgpu_sdma_instance
*
1840 amdgpu_get_sdma_instance(struct amdgpu_ring
*ring
)
1842 struct amdgpu_device
*adev
= ring
->adev
;
1845 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1846 if (&adev
->sdma
.instance
[i
].ring
== ring
)
1849 if (i
< AMDGPU_MAX_SDMA_INSTANCES
)
1850 return &adev
->sdma
.instance
[i
];
1858 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1859 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1860 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1861 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1862 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1863 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1864 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1865 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1866 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1867 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1868 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1869 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1870 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
1871 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
1872 #define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr))
1873 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
1874 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
1875 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
1876 #define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
1877 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1878 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
1879 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
1880 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1881 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1882 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
1883 #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
1884 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
1885 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
1886 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
1887 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
1888 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
1889 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
1890 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
1891 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
1892 #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1893 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
1894 #define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
1895 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
1896 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
1897 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
1898 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
1899 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
1900 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
1901 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
1902 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1903 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
1904 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1905 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1906 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
1907 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
1908 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
1909 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
1910 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
1911 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
1912 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
1913 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
1914 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
1915 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
1916 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
1917 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
1918 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
1919 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
1920 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
1921 #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
1923 /* Common functions */
1924 int amdgpu_gpu_reset(struct amdgpu_device
*adev
);
1925 bool amdgpu_need_backup(struct amdgpu_device
*adev
);
1926 void amdgpu_pci_config_reset(struct amdgpu_device
*adev
);
1927 bool amdgpu_need_post(struct amdgpu_device
*adev
);
1928 void amdgpu_update_display_priority(struct amdgpu_device
*adev
);
1930 void amdgpu_cs_report_moved_bytes(struct amdgpu_device
*adev
, u64 num_bytes
);
1931 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo
*abo
, u32 domain
);
1932 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object
*bo
);
1933 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt
*ttm
, struct page
**pages
);
1934 int amdgpu_ttm_tt_set_userptr(struct ttm_tt
*ttm
, uint64_t addr
,
1936 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt
*ttm
);
1937 struct mm_struct
*amdgpu_ttm_tt_get_usermm(struct ttm_tt
*ttm
);
1938 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt
*ttm
, unsigned long start
,
1940 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt
*ttm
,
1941 int *last_invalidated
);
1942 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt
*ttm
);
1943 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device
*adev
, struct ttm_tt
*ttm
,
1944 struct ttm_mem_reg
*mem
);
1945 void amdgpu_vram_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
, u64 base
);
1946 void amdgpu_gtt_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
);
1947 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device
*adev
, u64 size
);
1948 int amdgpu_ttm_init(struct amdgpu_device
*adev
);
1949 void amdgpu_ttm_fini(struct amdgpu_device
*adev
);
1950 void amdgpu_program_register_sequence(struct amdgpu_device
*adev
,
1951 const u32
*registers
,
1952 const u32 array_size
);
1954 bool amdgpu_device_is_px(struct drm_device
*dev
);
1956 #if defined(CONFIG_VGA_SWITCHEROO)
1957 void amdgpu_register_atpx_handler(void);
1958 void amdgpu_unregister_atpx_handler(void);
1959 bool amdgpu_has_atpx_dgpu_power_cntl(void);
1960 bool amdgpu_is_atpx_hybrid(void);
1961 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1962 bool amdgpu_has_atpx(void);
1964 static inline void amdgpu_register_atpx_handler(void) {}
1965 static inline void amdgpu_unregister_atpx_handler(void) {}
1966 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1967 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1968 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1969 static inline bool amdgpu_has_atpx(void) { return false; }
1975 extern const struct drm_ioctl_desc amdgpu_ioctls_kms
[];
1976 extern const int amdgpu_max_kms_ioctl
;
1978 bool amdgpu_kms_vram_lost(struct amdgpu_device
*adev
,
1979 struct amdgpu_fpriv
*fpriv
);
1980 int amdgpu_driver_load_kms(struct drm_device
*dev
, unsigned long flags
);
1981 void amdgpu_driver_unload_kms(struct drm_device
*dev
);
1982 void amdgpu_driver_lastclose_kms(struct drm_device
*dev
);
1983 int amdgpu_driver_open_kms(struct drm_device
*dev
, struct drm_file
*file_priv
);
1984 void amdgpu_driver_postclose_kms(struct drm_device
*dev
,
1985 struct drm_file
*file_priv
);
1986 int amdgpu_suspend(struct amdgpu_device
*adev
);
1987 int amdgpu_device_suspend(struct drm_device
*dev
, bool suspend
, bool fbcon
);
1988 int amdgpu_device_resume(struct drm_device
*dev
, bool resume
, bool fbcon
);
1989 u32
amdgpu_get_vblank_counter_kms(struct drm_device
*dev
, unsigned int pipe
);
1990 int amdgpu_enable_vblank_kms(struct drm_device
*dev
, unsigned int pipe
);
1991 void amdgpu_disable_vblank_kms(struct drm_device
*dev
, unsigned int pipe
);
1992 long amdgpu_kms_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1996 * functions used by amdgpu_encoder.c
1998 struct amdgpu_afmt_acr
{
2012 struct amdgpu_afmt_acr
amdgpu_afmt_acr(uint32_t clock
);
2015 #if defined(CONFIG_ACPI)
2016 int amdgpu_acpi_init(struct amdgpu_device
*adev
);
2017 void amdgpu_acpi_fini(struct amdgpu_device
*adev
);
2018 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device
*adev
);
2019 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device
*adev
,
2020 u8 perf_req
, bool advertise
);
2021 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device
*adev
);
2023 static inline int amdgpu_acpi_init(struct amdgpu_device
*adev
) { return 0; }
2024 static inline void amdgpu_acpi_fini(struct amdgpu_device
*adev
) { }
2027 struct amdgpu_bo_va_mapping
*
2028 amdgpu_cs_find_mapping(struct amdgpu_cs_parser
*parser
,
2029 uint64_t addr
, struct amdgpu_bo
**bo
);
2030 int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser
*parser
);
2032 #include "amdgpu_object.h"