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Merge tag 'kvm-arm-for-v4.12-round2' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/rbtree.h>
36 #include <linux/hashtable.h>
37 #include <linux/dma-fence.h>
38
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
44
45 #include <drm/drmP.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
48
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_ttm.h"
55 #include "amdgpu_psp.h"
56 #include "amdgpu_gds.h"
57 #include "amdgpu_sync.h"
58 #include "amdgpu_ring.h"
59 #include "amdgpu_vm.h"
60 #include "amd_powerplay.h"
61 #include "amdgpu_dpm.h"
62 #include "amdgpu_acp.h"
63 #include "amdgpu_uvd.h"
64 #include "amdgpu_vce.h"
65
66 #include "gpu_scheduler.h"
67 #include "amdgpu_virt.h"
68
69 /*
70 * Modules parameters.
71 */
72 extern int amdgpu_modeset;
73 extern int amdgpu_vram_limit;
74 extern int amdgpu_gart_size;
75 extern int amdgpu_moverate;
76 extern int amdgpu_benchmarking;
77 extern int amdgpu_testing;
78 extern int amdgpu_audio;
79 extern int amdgpu_disp_priority;
80 extern int amdgpu_hw_i2c;
81 extern int amdgpu_pcie_gen2;
82 extern int amdgpu_msi;
83 extern int amdgpu_lockup_timeout;
84 extern int amdgpu_dpm;
85 extern int amdgpu_fw_load_type;
86 extern int amdgpu_aspm;
87 extern int amdgpu_runtime_pm;
88 extern unsigned amdgpu_ip_block_mask;
89 extern int amdgpu_bapm;
90 extern int amdgpu_deep_color;
91 extern int amdgpu_vm_size;
92 extern int amdgpu_vm_block_size;
93 extern int amdgpu_vm_fault_stop;
94 extern int amdgpu_vm_debug;
95 extern int amdgpu_sched_jobs;
96 extern int amdgpu_sched_hw_submission;
97 extern int amdgpu_no_evict;
98 extern int amdgpu_direct_gma_size;
99 extern unsigned amdgpu_pcie_gen_cap;
100 extern unsigned amdgpu_pcie_lane_cap;
101 extern unsigned amdgpu_cg_mask;
102 extern unsigned amdgpu_pg_mask;
103 extern char *amdgpu_disable_cu;
104 extern char *amdgpu_virtual_display;
105 extern unsigned amdgpu_pp_feature_mask;
106 extern int amdgpu_vram_page_split;
107 extern int amdgpu_ngg;
108 extern int amdgpu_prim_buf_per_se;
109 extern int amdgpu_pos_buf_per_se;
110 extern int amdgpu_cntl_sb_buf_per_se;
111 extern int amdgpu_param_buf_per_se;
112
113 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
114 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
115 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
116 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
117 #define AMDGPU_IB_POOL_SIZE 16
118 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
119 #define AMDGPUFB_CONN_LIMIT 4
120 #define AMDGPU_BIOS_NUM_SCRATCH 16
121
122 /* max number of IP instances */
123 #define AMDGPU_MAX_SDMA_INSTANCES 2
124
125 /* hard reset data */
126 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
127
128 /* reset flags */
129 #define AMDGPU_RESET_GFX (1 << 0)
130 #define AMDGPU_RESET_COMPUTE (1 << 1)
131 #define AMDGPU_RESET_DMA (1 << 2)
132 #define AMDGPU_RESET_CP (1 << 3)
133 #define AMDGPU_RESET_GRBM (1 << 4)
134 #define AMDGPU_RESET_DMA1 (1 << 5)
135 #define AMDGPU_RESET_RLC (1 << 6)
136 #define AMDGPU_RESET_SEM (1 << 7)
137 #define AMDGPU_RESET_IH (1 << 8)
138 #define AMDGPU_RESET_VMC (1 << 9)
139 #define AMDGPU_RESET_MC (1 << 10)
140 #define AMDGPU_RESET_DISPLAY (1 << 11)
141 #define AMDGPU_RESET_UVD (1 << 12)
142 #define AMDGPU_RESET_VCE (1 << 13)
143 #define AMDGPU_RESET_VCE1 (1 << 14)
144
145 /* GFX current status */
146 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
147 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
148 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
149 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
150 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
151
152 /* max cursor sizes (in pixels) */
153 #define CIK_CURSOR_WIDTH 128
154 #define CIK_CURSOR_HEIGHT 128
155
156 struct amdgpu_device;
157 struct amdgpu_ib;
158 struct amdgpu_cs_parser;
159 struct amdgpu_job;
160 struct amdgpu_irq_src;
161 struct amdgpu_fpriv;
162
163 enum amdgpu_cp_irq {
164 AMDGPU_CP_IRQ_GFX_EOP = 0,
165 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
166 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
167 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
168 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
169 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
170 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
171 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
172 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
173
174 AMDGPU_CP_IRQ_LAST
175 };
176
177 enum amdgpu_sdma_irq {
178 AMDGPU_SDMA_IRQ_TRAP0 = 0,
179 AMDGPU_SDMA_IRQ_TRAP1,
180
181 AMDGPU_SDMA_IRQ_LAST
182 };
183
184 enum amdgpu_thermal_irq {
185 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
186 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
187
188 AMDGPU_THERMAL_IRQ_LAST
189 };
190
191 enum amdgpu_kiq_irq {
192 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
193 AMDGPU_CP_KIQ_IRQ_LAST
194 };
195
196 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
197 enum amd_ip_block_type block_type,
198 enum amd_clockgating_state state);
199 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
200 enum amd_ip_block_type block_type,
201 enum amd_powergating_state state);
202 void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
203 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
204 enum amd_ip_block_type block_type);
205 bool amdgpu_is_idle(struct amdgpu_device *adev,
206 enum amd_ip_block_type block_type);
207
208 #define AMDGPU_MAX_IP_NUM 16
209
210 struct amdgpu_ip_block_status {
211 bool valid;
212 bool sw;
213 bool hw;
214 bool late_initialized;
215 bool hang;
216 };
217
218 struct amdgpu_ip_block_version {
219 const enum amd_ip_block_type type;
220 const u32 major;
221 const u32 minor;
222 const u32 rev;
223 const struct amd_ip_funcs *funcs;
224 };
225
226 struct amdgpu_ip_block {
227 struct amdgpu_ip_block_status status;
228 const struct amdgpu_ip_block_version *version;
229 };
230
231 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
232 enum amd_ip_block_type type,
233 u32 major, u32 minor);
234
235 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
236 enum amd_ip_block_type type);
237
238 int amdgpu_ip_block_add(struct amdgpu_device *adev,
239 const struct amdgpu_ip_block_version *ip_block_version);
240
241 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
242 struct amdgpu_buffer_funcs {
243 /* maximum bytes in a single operation */
244 uint32_t copy_max_bytes;
245
246 /* number of dw to reserve per operation */
247 unsigned copy_num_dw;
248
249 /* used for buffer migration */
250 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
251 /* src addr in bytes */
252 uint64_t src_offset,
253 /* dst addr in bytes */
254 uint64_t dst_offset,
255 /* number of byte to transfer */
256 uint32_t byte_count);
257
258 /* maximum bytes in a single operation */
259 uint32_t fill_max_bytes;
260
261 /* number of dw to reserve per operation */
262 unsigned fill_num_dw;
263
264 /* used for buffer clearing */
265 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
266 /* value to write to memory */
267 uint32_t src_data,
268 /* dst addr in bytes */
269 uint64_t dst_offset,
270 /* number of byte to fill */
271 uint32_t byte_count);
272 };
273
274 /* provided by hw blocks that can write ptes, e.g., sdma */
275 struct amdgpu_vm_pte_funcs {
276 /* copy pte entries from GART */
277 void (*copy_pte)(struct amdgpu_ib *ib,
278 uint64_t pe, uint64_t src,
279 unsigned count);
280 /* write pte one entry at a time with addr mapping */
281 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
282 uint64_t value, unsigned count,
283 uint32_t incr);
284 /* for linear pte/pde updates without addr mapping */
285 void (*set_pte_pde)(struct amdgpu_ib *ib,
286 uint64_t pe,
287 uint64_t addr, unsigned count,
288 uint32_t incr, uint64_t flags);
289 };
290
291 /* provided by the gmc block */
292 struct amdgpu_gart_funcs {
293 /* flush the vm tlb via mmio */
294 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
295 uint32_t vmid);
296 /* write pte/pde updates using the cpu */
297 int (*set_pte_pde)(struct amdgpu_device *adev,
298 void *cpu_pt_addr, /* cpu addr of page table */
299 uint32_t gpu_page_idx, /* pte/pde to update */
300 uint64_t addr, /* addr to write into pte/pde */
301 uint64_t flags); /* access flags */
302 /* enable/disable PRT support */
303 void (*set_prt)(struct amdgpu_device *adev, bool enable);
304 /* set pte flags based per asic */
305 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
306 uint32_t flags);
307 /* adjust mc addr in fb for APU case */
308 u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr);
309 uint32_t (*get_invalidate_req)(unsigned int vm_id);
310 };
311
312 /* provided by the ih block */
313 struct amdgpu_ih_funcs {
314 /* ring read/write ptr handling, called from interrupt context */
315 u32 (*get_wptr)(struct amdgpu_device *adev);
316 void (*decode_iv)(struct amdgpu_device *adev,
317 struct amdgpu_iv_entry *entry);
318 void (*set_rptr)(struct amdgpu_device *adev);
319 };
320
321 /*
322 * BIOS.
323 */
324 bool amdgpu_get_bios(struct amdgpu_device *adev);
325 bool amdgpu_read_bios(struct amdgpu_device *adev);
326
327 /*
328 * Dummy page
329 */
330 struct amdgpu_dummy_page {
331 struct page *page;
332 dma_addr_t addr;
333 };
334 int amdgpu_dummy_page_init(struct amdgpu_device *adev);
335 void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
336
337
338 /*
339 * Clocks
340 */
341
342 #define AMDGPU_MAX_PPLL 3
343
344 struct amdgpu_clock {
345 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
346 struct amdgpu_pll spll;
347 struct amdgpu_pll mpll;
348 /* 10 Khz units */
349 uint32_t default_mclk;
350 uint32_t default_sclk;
351 uint32_t default_dispclk;
352 uint32_t current_dispclk;
353 uint32_t dp_extclk;
354 uint32_t max_pixel_clock;
355 };
356
357 /*
358 * BO.
359 */
360 struct amdgpu_bo_list_entry {
361 struct amdgpu_bo *robj;
362 struct ttm_validate_buffer tv;
363 struct amdgpu_bo_va *bo_va;
364 uint32_t priority;
365 struct page **user_pages;
366 int user_invalidated;
367 };
368
369 struct amdgpu_bo_va_mapping {
370 struct list_head list;
371 struct rb_node rb;
372 uint64_t start;
373 uint64_t last;
374 uint64_t __subtree_last;
375 uint64_t offset;
376 uint64_t flags;
377 };
378
379 /* bo virtual addresses in a specific vm */
380 struct amdgpu_bo_va {
381 /* protected by bo being reserved */
382 struct list_head bo_list;
383 struct dma_fence *last_pt_update;
384 unsigned ref_count;
385
386 /* protected by vm mutex and spinlock */
387 struct list_head vm_status;
388
389 /* mappings for this bo_va */
390 struct list_head invalids;
391 struct list_head valids;
392
393 /* constant after initialization */
394 struct amdgpu_vm *vm;
395 struct amdgpu_bo *bo;
396 };
397
398 #define AMDGPU_GEM_DOMAIN_MAX 0x3
399
400 struct amdgpu_bo {
401 /* Protected by tbo.reserved */
402 u32 prefered_domains;
403 u32 allowed_domains;
404 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
405 struct ttm_placement placement;
406 struct ttm_buffer_object tbo;
407 struct ttm_bo_kmap_obj kmap;
408 u64 flags;
409 unsigned pin_count;
410 void *kptr;
411 u64 tiling_flags;
412 u64 metadata_flags;
413 void *metadata;
414 u32 metadata_size;
415 unsigned prime_shared_count;
416 /* list of all virtual address to which this bo
417 * is associated to
418 */
419 struct list_head va;
420 /* Constant after initialization */
421 struct drm_gem_object gem_base;
422 struct amdgpu_bo *parent;
423 struct amdgpu_bo *shadow;
424
425 struct ttm_bo_kmap_obj dma_buf_vmap;
426 struct amdgpu_mn *mn;
427 struct list_head mn_list;
428 struct list_head shadow_list;
429 };
430 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
431
432 void amdgpu_gem_object_free(struct drm_gem_object *obj);
433 int amdgpu_gem_object_open(struct drm_gem_object *obj,
434 struct drm_file *file_priv);
435 void amdgpu_gem_object_close(struct drm_gem_object *obj,
436 struct drm_file *file_priv);
437 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
438 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
439 struct drm_gem_object *
440 amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
441 struct dma_buf_attachment *attach,
442 struct sg_table *sg);
443 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
444 struct drm_gem_object *gobj,
445 int flags);
446 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
447 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
448 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
449 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
450 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
451 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
452
453 /* sub-allocation manager, it has to be protected by another lock.
454 * By conception this is an helper for other part of the driver
455 * like the indirect buffer or semaphore, which both have their
456 * locking.
457 *
458 * Principe is simple, we keep a list of sub allocation in offset
459 * order (first entry has offset == 0, last entry has the highest
460 * offset).
461 *
462 * When allocating new object we first check if there is room at
463 * the end total_size - (last_object_offset + last_object_size) >=
464 * alloc_size. If so we allocate new object there.
465 *
466 * When there is not enough room at the end, we start waiting for
467 * each sub object until we reach object_offset+object_size >=
468 * alloc_size, this object then become the sub object we return.
469 *
470 * Alignment can't be bigger than page size.
471 *
472 * Hole are not considered for allocation to keep things simple.
473 * Assumption is that there won't be hole (all object on same
474 * alignment).
475 */
476
477 #define AMDGPU_SA_NUM_FENCE_LISTS 32
478
479 struct amdgpu_sa_manager {
480 wait_queue_head_t wq;
481 struct amdgpu_bo *bo;
482 struct list_head *hole;
483 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
484 struct list_head olist;
485 unsigned size;
486 uint64_t gpu_addr;
487 void *cpu_ptr;
488 uint32_t domain;
489 uint32_t align;
490 };
491
492 /* sub-allocation buffer */
493 struct amdgpu_sa_bo {
494 struct list_head olist;
495 struct list_head flist;
496 struct amdgpu_sa_manager *manager;
497 unsigned soffset;
498 unsigned eoffset;
499 struct dma_fence *fence;
500 };
501
502 /*
503 * GEM objects.
504 */
505 void amdgpu_gem_force_release(struct amdgpu_device *adev);
506 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
507 int alignment, u32 initial_domain,
508 u64 flags, bool kernel,
509 struct drm_gem_object **obj);
510
511 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
512 struct drm_device *dev,
513 struct drm_mode_create_dumb *args);
514 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
515 struct drm_device *dev,
516 uint32_t handle, uint64_t *offset_p);
517 int amdgpu_fence_slab_init(void);
518 void amdgpu_fence_slab_fini(void);
519
520 /*
521 * GART structures, functions & helpers
522 */
523 struct amdgpu_mc;
524
525 #define AMDGPU_GPU_PAGE_SIZE 4096
526 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
527 #define AMDGPU_GPU_PAGE_SHIFT 12
528 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
529
530 struct amdgpu_gart {
531 dma_addr_t table_addr;
532 struct amdgpu_bo *robj;
533 void *ptr;
534 unsigned num_gpu_pages;
535 unsigned num_cpu_pages;
536 unsigned table_size;
537 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
538 struct page **pages;
539 #endif
540 bool ready;
541
542 /* Asic default pte flags */
543 uint64_t gart_pte_flags;
544
545 const struct amdgpu_gart_funcs *gart_funcs;
546 };
547
548 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
549 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
550 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
551 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
552 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
553 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
554 int amdgpu_gart_init(struct amdgpu_device *adev);
555 void amdgpu_gart_fini(struct amdgpu_device *adev);
556 void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
557 int pages);
558 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
559 int pages, struct page **pagelist,
560 dma_addr_t *dma_addr, uint64_t flags);
561 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
562
563 /*
564 * VMHUB structures, functions & helpers
565 */
566 struct amdgpu_vmhub {
567 uint32_t ctx0_ptb_addr_lo32;
568 uint32_t ctx0_ptb_addr_hi32;
569 uint32_t vm_inv_eng0_req;
570 uint32_t vm_inv_eng0_ack;
571 uint32_t vm_context0_cntl;
572 uint32_t vm_l2_pro_fault_status;
573 uint32_t vm_l2_pro_fault_cntl;
574 };
575
576 /*
577 * GPU MC structures, functions & helpers
578 */
579 struct amdgpu_mc {
580 resource_size_t aper_size;
581 resource_size_t aper_base;
582 resource_size_t agp_base;
583 /* for some chips with <= 32MB we need to lie
584 * about vram size near mc fb location */
585 u64 mc_vram_size;
586 u64 visible_vram_size;
587 u64 gtt_size;
588 u64 gtt_start;
589 u64 gtt_end;
590 u64 vram_start;
591 u64 vram_end;
592 unsigned vram_width;
593 u64 real_vram_size;
594 int vram_mtrr;
595 u64 gtt_base_align;
596 u64 mc_mask;
597 const struct firmware *fw; /* MC firmware */
598 uint32_t fw_version;
599 struct amdgpu_irq_src vm_fault;
600 uint32_t vram_type;
601 uint32_t srbm_soft_reset;
602 struct amdgpu_mode_mc_save save;
603 bool prt_warning;
604 /* apertures */
605 u64 shared_aperture_start;
606 u64 shared_aperture_end;
607 u64 private_aperture_start;
608 u64 private_aperture_end;
609 /* protects concurrent invalidation */
610 spinlock_t invalidate_lock;
611 };
612
613 /*
614 * GPU doorbell structures, functions & helpers
615 */
616 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
617 {
618 AMDGPU_DOORBELL_KIQ = 0x000,
619 AMDGPU_DOORBELL_HIQ = 0x001,
620 AMDGPU_DOORBELL_DIQ = 0x002,
621 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
622 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
623 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
624 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
625 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
626 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
627 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
628 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
629 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
630 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
631 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
632 AMDGPU_DOORBELL_IH = 0x1E8,
633 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
634 AMDGPU_DOORBELL_INVALID = 0xFFFF
635 } AMDGPU_DOORBELL_ASSIGNMENT;
636
637 struct amdgpu_doorbell {
638 /* doorbell mmio */
639 resource_size_t base;
640 resource_size_t size;
641 u32 __iomem *ptr;
642 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
643 };
644
645 /*
646 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
647 */
648 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
649 {
650 /*
651 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
652 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
653 * Compute related doorbells are allocated from 0x00 to 0x8a
654 */
655
656
657 /* kernel scheduling */
658 AMDGPU_DOORBELL64_KIQ = 0x00,
659
660 /* HSA interface queue and debug queue */
661 AMDGPU_DOORBELL64_HIQ = 0x01,
662 AMDGPU_DOORBELL64_DIQ = 0x02,
663
664 /* Compute engines */
665 AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
666 AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
667 AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
668 AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
669 AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
670 AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
671 AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
672 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
673
674 /* User queue doorbell range (128 doorbells) */
675 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
676 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
677
678 /* Graphics engine */
679 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
680
681 /*
682 * Other graphics doorbells can be allocated here: from 0x8c to 0xef
683 * Graphics voltage island aperture 1
684 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive
685 */
686
687 /* sDMA engines */
688 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
689 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
690 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
691 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
692
693 /* Interrupt handler */
694 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
695 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
696 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
697
698 /* VCN engine use 32 bits doorbell */
699 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
700 AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
701 AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
702 AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
703
704 /* overlap the doorbell assignment with VCN as they are mutually exclusive
705 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
706 */
707 AMDGPU_DOORBELL64_RING0_1 = 0xF8,
708 AMDGPU_DOORBELL64_RING2_3 = 0xF9,
709 AMDGPU_DOORBELL64_RING4_5 = 0xFA,
710 AMDGPU_DOORBELL64_RING6_7 = 0xFB,
711
712 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xFC,
713 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xFD,
714 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFE,
715 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFF,
716
717 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
718 AMDGPU_DOORBELL64_INVALID = 0xFFFF
719 } AMDGPU_DOORBELL64_ASSIGNMENT;
720
721
722 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
723 phys_addr_t *aperture_base,
724 size_t *aperture_size,
725 size_t *start_offset);
726
727 /*
728 * IRQS.
729 */
730
731 struct amdgpu_flip_work {
732 struct delayed_work flip_work;
733 struct work_struct unpin_work;
734 struct amdgpu_device *adev;
735 int crtc_id;
736 u32 target_vblank;
737 uint64_t base;
738 struct drm_pending_vblank_event *event;
739 struct amdgpu_bo *old_abo;
740 struct dma_fence *excl;
741 unsigned shared_count;
742 struct dma_fence **shared;
743 struct dma_fence_cb cb;
744 bool async;
745 };
746
747
748 /*
749 * CP & rings.
750 */
751
752 struct amdgpu_ib {
753 struct amdgpu_sa_bo *sa_bo;
754 uint32_t length_dw;
755 uint64_t gpu_addr;
756 uint32_t *ptr;
757 uint32_t flags;
758 };
759
760 extern const struct amd_sched_backend_ops amdgpu_sched_ops;
761
762 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
763 struct amdgpu_job **job, struct amdgpu_vm *vm);
764 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
765 struct amdgpu_job **job);
766
767 void amdgpu_job_free_resources(struct amdgpu_job *job);
768 void amdgpu_job_free(struct amdgpu_job *job);
769 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
770 struct amd_sched_entity *entity, void *owner,
771 struct dma_fence **f);
772
773 /*
774 * context related structures
775 */
776
777 struct amdgpu_ctx_ring {
778 uint64_t sequence;
779 struct dma_fence **fences;
780 struct amd_sched_entity entity;
781 };
782
783 struct amdgpu_ctx {
784 struct kref refcount;
785 struct amdgpu_device *adev;
786 unsigned reset_counter;
787 spinlock_t ring_lock;
788 struct dma_fence **fences;
789 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
790 bool preamble_presented;
791 };
792
793 struct amdgpu_ctx_mgr {
794 struct amdgpu_device *adev;
795 struct mutex lock;
796 /* protected by lock */
797 struct idr ctx_handles;
798 };
799
800 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
801 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
802
803 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
804 struct dma_fence *fence);
805 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
806 struct amdgpu_ring *ring, uint64_t seq);
807
808 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
809 struct drm_file *filp);
810
811 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
812 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
813
814 /*
815 * file private structure
816 */
817
818 struct amdgpu_fpriv {
819 struct amdgpu_vm vm;
820 struct amdgpu_bo_va *prt_va;
821 struct mutex bo_list_lock;
822 struct idr bo_list_handles;
823 struct amdgpu_ctx_mgr ctx_mgr;
824 };
825
826 /*
827 * residency list
828 */
829
830 struct amdgpu_bo_list {
831 struct mutex lock;
832 struct amdgpu_bo *gds_obj;
833 struct amdgpu_bo *gws_obj;
834 struct amdgpu_bo *oa_obj;
835 unsigned first_userptr;
836 unsigned num_entries;
837 struct amdgpu_bo_list_entry *array;
838 };
839
840 struct amdgpu_bo_list *
841 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
842 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
843 struct list_head *validated);
844 void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
845 void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
846
847 /*
848 * GFX stuff
849 */
850 #include "clearstate_defs.h"
851
852 struct amdgpu_rlc_funcs {
853 void (*enter_safe_mode)(struct amdgpu_device *adev);
854 void (*exit_safe_mode)(struct amdgpu_device *adev);
855 };
856
857 struct amdgpu_rlc {
858 /* for power gating */
859 struct amdgpu_bo *save_restore_obj;
860 uint64_t save_restore_gpu_addr;
861 volatile uint32_t *sr_ptr;
862 const u32 *reg_list;
863 u32 reg_list_size;
864 /* for clear state */
865 struct amdgpu_bo *clear_state_obj;
866 uint64_t clear_state_gpu_addr;
867 volatile uint32_t *cs_ptr;
868 const struct cs_section_def *cs_data;
869 u32 clear_state_size;
870 /* for cp tables */
871 struct amdgpu_bo *cp_table_obj;
872 uint64_t cp_table_gpu_addr;
873 volatile uint32_t *cp_table_ptr;
874 u32 cp_table_size;
875
876 /* safe mode for updating CG/PG state */
877 bool in_safe_mode;
878 const struct amdgpu_rlc_funcs *funcs;
879
880 /* for firmware data */
881 u32 save_and_restore_offset;
882 u32 clear_state_descriptor_offset;
883 u32 avail_scratch_ram_locations;
884 u32 reg_restore_list_size;
885 u32 reg_list_format_start;
886 u32 reg_list_format_separate_start;
887 u32 starting_offsets_start;
888 u32 reg_list_format_size_bytes;
889 u32 reg_list_size_bytes;
890
891 u32 *register_list_format;
892 u32 *register_restore;
893 };
894
895 struct amdgpu_mec {
896 struct amdgpu_bo *hpd_eop_obj;
897 u64 hpd_eop_gpu_addr;
898 struct amdgpu_bo *mec_fw_obj;
899 u64 mec_fw_gpu_addr;
900 u32 num_pipe;
901 u32 num_mec;
902 u32 num_queue;
903 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
904 };
905
906 struct amdgpu_kiq {
907 u64 eop_gpu_addr;
908 struct amdgpu_bo *eop_obj;
909 struct amdgpu_ring ring;
910 struct amdgpu_irq_src irq;
911 };
912
913 /*
914 * GPU scratch registers structures, functions & helpers
915 */
916 struct amdgpu_scratch {
917 unsigned num_reg;
918 uint32_t reg_base;
919 uint32_t free_mask;
920 };
921
922 /*
923 * GFX configurations
924 */
925 #define AMDGPU_GFX_MAX_SE 4
926 #define AMDGPU_GFX_MAX_SH_PER_SE 2
927
928 struct amdgpu_rb_config {
929 uint32_t rb_backend_disable;
930 uint32_t user_rb_backend_disable;
931 uint32_t raster_config;
932 uint32_t raster_config_1;
933 };
934
935 struct gb_addr_config {
936 uint16_t pipe_interleave_size;
937 uint8_t num_pipes;
938 uint8_t max_compress_frags;
939 uint8_t num_banks;
940 uint8_t num_se;
941 uint8_t num_rb_per_se;
942 };
943
944 struct amdgpu_gfx_config {
945 unsigned max_shader_engines;
946 unsigned max_tile_pipes;
947 unsigned max_cu_per_sh;
948 unsigned max_sh_per_se;
949 unsigned max_backends_per_se;
950 unsigned max_texture_channel_caches;
951 unsigned max_gprs;
952 unsigned max_gs_threads;
953 unsigned max_hw_contexts;
954 unsigned sc_prim_fifo_size_frontend;
955 unsigned sc_prim_fifo_size_backend;
956 unsigned sc_hiz_tile_fifo_size;
957 unsigned sc_earlyz_tile_fifo_size;
958
959 unsigned num_tile_pipes;
960 unsigned backend_enable_mask;
961 unsigned mem_max_burst_length_bytes;
962 unsigned mem_row_size_in_kb;
963 unsigned shader_engine_tile_size;
964 unsigned num_gpus;
965 unsigned multi_gpu_tile_size;
966 unsigned mc_arb_ramcfg;
967 unsigned gb_addr_config;
968 unsigned num_rbs;
969
970 uint32_t tile_mode_array[32];
971 uint32_t macrotile_mode_array[16];
972
973 struct gb_addr_config gb_addr_config_fields;
974 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
975
976 /* gfx configure feature */
977 uint32_t double_offchip_lds_buf;
978 };
979
980 struct amdgpu_cu_info {
981 uint32_t number; /* total active CU number */
982 uint32_t ao_cu_mask;
983 uint32_t bitmap[4][4];
984 };
985
986 struct amdgpu_gfx_funcs {
987 /* get the gpu clock counter */
988 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
989 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
990 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
991 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
992 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
993 };
994
995 struct amdgpu_ngg_buf {
996 struct amdgpu_bo *bo;
997 uint64_t gpu_addr;
998 uint32_t size;
999 uint32_t bo_size;
1000 };
1001
1002 enum {
1003 PRIM = 0,
1004 POS,
1005 CNTL,
1006 PARAM,
1007 NGG_BUF_MAX
1008 };
1009
1010 struct amdgpu_ngg {
1011 struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
1012 uint32_t gds_reserve_addr;
1013 uint32_t gds_reserve_size;
1014 bool init;
1015 };
1016
1017 struct amdgpu_gfx {
1018 struct mutex gpu_clock_mutex;
1019 struct amdgpu_gfx_config config;
1020 struct amdgpu_rlc rlc;
1021 struct amdgpu_mec mec;
1022 struct amdgpu_kiq kiq;
1023 struct amdgpu_scratch scratch;
1024 const struct firmware *me_fw; /* ME firmware */
1025 uint32_t me_fw_version;
1026 const struct firmware *pfp_fw; /* PFP firmware */
1027 uint32_t pfp_fw_version;
1028 const struct firmware *ce_fw; /* CE firmware */
1029 uint32_t ce_fw_version;
1030 const struct firmware *rlc_fw; /* RLC firmware */
1031 uint32_t rlc_fw_version;
1032 const struct firmware *mec_fw; /* MEC firmware */
1033 uint32_t mec_fw_version;
1034 const struct firmware *mec2_fw; /* MEC2 firmware */
1035 uint32_t mec2_fw_version;
1036 uint32_t me_feature_version;
1037 uint32_t ce_feature_version;
1038 uint32_t pfp_feature_version;
1039 uint32_t rlc_feature_version;
1040 uint32_t mec_feature_version;
1041 uint32_t mec2_feature_version;
1042 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1043 unsigned num_gfx_rings;
1044 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1045 unsigned num_compute_rings;
1046 struct amdgpu_irq_src eop_irq;
1047 struct amdgpu_irq_src priv_reg_irq;
1048 struct amdgpu_irq_src priv_inst_irq;
1049 /* gfx status */
1050 uint32_t gfx_current_status;
1051 /* ce ram size*/
1052 unsigned ce_ram_size;
1053 struct amdgpu_cu_info cu_info;
1054 const struct amdgpu_gfx_funcs *funcs;
1055
1056 /* reset mask */
1057 uint32_t grbm_soft_reset;
1058 uint32_t srbm_soft_reset;
1059 bool in_reset;
1060 /* NGG */
1061 struct amdgpu_ngg ngg;
1062 };
1063
1064 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
1065 unsigned size, struct amdgpu_ib *ib);
1066 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
1067 struct dma_fence *f);
1068 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
1069 struct amdgpu_ib *ibs, struct amdgpu_job *job,
1070 struct dma_fence **f);
1071 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1072 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1073 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1074
1075 /*
1076 * CS.
1077 */
1078 struct amdgpu_cs_chunk {
1079 uint32_t chunk_id;
1080 uint32_t length_dw;
1081 void *kdata;
1082 };
1083
1084 struct amdgpu_cs_parser {
1085 struct amdgpu_device *adev;
1086 struct drm_file *filp;
1087 struct amdgpu_ctx *ctx;
1088
1089 /* chunks */
1090 unsigned nchunks;
1091 struct amdgpu_cs_chunk *chunks;
1092
1093 /* scheduler job object */
1094 struct amdgpu_job *job;
1095
1096 /* buffer objects */
1097 struct ww_acquire_ctx ticket;
1098 struct amdgpu_bo_list *bo_list;
1099 struct amdgpu_bo_list_entry vm_pd;
1100 struct list_head validated;
1101 struct dma_fence *fence;
1102 uint64_t bytes_moved_threshold;
1103 uint64_t bytes_moved;
1104 struct amdgpu_bo_list_entry *evictable;
1105
1106 /* user fence */
1107 struct amdgpu_bo_list_entry uf_entry;
1108 };
1109
1110 #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
1111 #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
1112 #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
1113 #define AMDGPU_VM_DOMAIN (1 << 3) /* bit set means in virtual memory context */
1114
1115 struct amdgpu_job {
1116 struct amd_sched_job base;
1117 struct amdgpu_device *adev;
1118 struct amdgpu_vm *vm;
1119 struct amdgpu_ring *ring;
1120 struct amdgpu_sync sync;
1121 struct amdgpu_ib *ibs;
1122 struct dma_fence *fence; /* the hw fence */
1123 uint32_t preamble_status;
1124 uint32_t num_ibs;
1125 void *owner;
1126 uint64_t fence_ctx; /* the fence_context this job uses */
1127 bool vm_needs_flush;
1128 unsigned vm_id;
1129 uint64_t vm_pd_addr;
1130 uint32_t gds_base, gds_size;
1131 uint32_t gws_base, gws_size;
1132 uint32_t oa_base, oa_size;
1133
1134 /* user fence handling */
1135 uint64_t uf_addr;
1136 uint64_t uf_sequence;
1137
1138 };
1139 #define to_amdgpu_job(sched_job) \
1140 container_of((sched_job), struct amdgpu_job, base)
1141
1142 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1143 uint32_t ib_idx, int idx)
1144 {
1145 return p->job->ibs[ib_idx].ptr[idx];
1146 }
1147
1148 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1149 uint32_t ib_idx, int idx,
1150 uint32_t value)
1151 {
1152 p->job->ibs[ib_idx].ptr[idx] = value;
1153 }
1154
1155 /*
1156 * Writeback
1157 */
1158 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1159
1160 struct amdgpu_wb {
1161 struct amdgpu_bo *wb_obj;
1162 volatile uint32_t *wb;
1163 uint64_t gpu_addr;
1164 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1165 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1166 };
1167
1168 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1169 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1170 int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb);
1171 void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
1172
1173 void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1174
1175 /*
1176 * SDMA
1177 */
1178 struct amdgpu_sdma_instance {
1179 /* SDMA firmware */
1180 const struct firmware *fw;
1181 uint32_t fw_version;
1182 uint32_t feature_version;
1183
1184 struct amdgpu_ring ring;
1185 bool burst_nop;
1186 };
1187
1188 struct amdgpu_sdma {
1189 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1190 #ifdef CONFIG_DRM_AMDGPU_SI
1191 //SI DMA has a difference trap irq number for the second engine
1192 struct amdgpu_irq_src trap_irq_1;
1193 #endif
1194 struct amdgpu_irq_src trap_irq;
1195 struct amdgpu_irq_src illegal_inst_irq;
1196 int num_instances;
1197 uint32_t srbm_soft_reset;
1198 };
1199
1200 /*
1201 * Firmware
1202 */
1203 enum amdgpu_firmware_load_type {
1204 AMDGPU_FW_LOAD_DIRECT = 0,
1205 AMDGPU_FW_LOAD_SMU,
1206 AMDGPU_FW_LOAD_PSP,
1207 };
1208
1209 struct amdgpu_firmware {
1210 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1211 enum amdgpu_firmware_load_type load_type;
1212 struct amdgpu_bo *fw_buf;
1213 unsigned int fw_size;
1214 unsigned int max_ucodes;
1215 /* firmwares are loaded by psp instead of smu from vega10 */
1216 const struct amdgpu_psp_funcs *funcs;
1217 struct amdgpu_bo *rbuf;
1218 struct mutex mutex;
1219 };
1220
1221 /*
1222 * Benchmarking
1223 */
1224 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1225
1226
1227 /*
1228 * Testing
1229 */
1230 void amdgpu_test_moves(struct amdgpu_device *adev);
1231
1232 /*
1233 * MMU Notifier
1234 */
1235 #if defined(CONFIG_MMU_NOTIFIER)
1236 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1237 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1238 #else
1239 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1240 {
1241 return -ENODEV;
1242 }
1243 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1244 #endif
1245
1246 /*
1247 * Debugfs
1248 */
1249 struct amdgpu_debugfs {
1250 const struct drm_info_list *files;
1251 unsigned num_files;
1252 };
1253
1254 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1255 const struct drm_info_list *files,
1256 unsigned nfiles);
1257 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1258
1259 #if defined(CONFIG_DEBUG_FS)
1260 int amdgpu_debugfs_init(struct drm_minor *minor);
1261 #endif
1262
1263 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1264
1265 /*
1266 * amdgpu smumgr functions
1267 */
1268 struct amdgpu_smumgr_funcs {
1269 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1270 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1271 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1272 };
1273
1274 /*
1275 * amdgpu smumgr
1276 */
1277 struct amdgpu_smumgr {
1278 struct amdgpu_bo *toc_buf;
1279 struct amdgpu_bo *smu_buf;
1280 /* asic priv smu data */
1281 void *priv;
1282 spinlock_t smu_lock;
1283 /* smumgr functions */
1284 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1285 /* ucode loading complete flag */
1286 uint32_t fw_flags;
1287 };
1288
1289 /*
1290 * ASIC specific register table accessible by UMD
1291 */
1292 struct amdgpu_allowed_register_entry {
1293 uint32_t reg_offset;
1294 bool untouched;
1295 bool grbm_indexed;
1296 };
1297
1298 /*
1299 * ASIC specific functions.
1300 */
1301 struct amdgpu_asic_funcs {
1302 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1303 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1304 u8 *bios, u32 length_bytes);
1305 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1306 u32 sh_num, u32 reg_offset, u32 *value);
1307 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1308 int (*reset)(struct amdgpu_device *adev);
1309 /* get the reference clock */
1310 u32 (*get_xclk)(struct amdgpu_device *adev);
1311 /* MM block clocks */
1312 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1313 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1314 /* static power management */
1315 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1316 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
1317 /* get config memsize register */
1318 u32 (*get_config_memsize)(struct amdgpu_device *adev);
1319 };
1320
1321 /*
1322 * IOCTL.
1323 */
1324 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1325 struct drm_file *filp);
1326 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1327 struct drm_file *filp);
1328
1329 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1330 struct drm_file *filp);
1331 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1332 struct drm_file *filp);
1333 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1334 struct drm_file *filp);
1335 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1336 struct drm_file *filp);
1337 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1338 struct drm_file *filp);
1339 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1340 struct drm_file *filp);
1341 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1342 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1343 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1344 struct drm_file *filp);
1345
1346 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1347 struct drm_file *filp);
1348
1349 /* VRAM scratch page for HDP bug, default vram page */
1350 struct amdgpu_vram_scratch {
1351 struct amdgpu_bo *robj;
1352 volatile uint32_t *ptr;
1353 u64 gpu_addr;
1354 };
1355
1356 /*
1357 * ACPI
1358 */
1359 struct amdgpu_atif_notification_cfg {
1360 bool enabled;
1361 int command_code;
1362 };
1363
1364 struct amdgpu_atif_notifications {
1365 bool display_switch;
1366 bool expansion_mode_change;
1367 bool thermal_state;
1368 bool forced_power_state;
1369 bool system_power_state;
1370 bool display_conf_change;
1371 bool px_gfx_switch;
1372 bool brightness_change;
1373 bool dgpu_display_event;
1374 };
1375
1376 struct amdgpu_atif_functions {
1377 bool system_params;
1378 bool sbios_requests;
1379 bool select_active_disp;
1380 bool lid_state;
1381 bool get_tv_standard;
1382 bool set_tv_standard;
1383 bool get_panel_expansion_mode;
1384 bool set_panel_expansion_mode;
1385 bool temperature_change;
1386 bool graphics_device_types;
1387 };
1388
1389 struct amdgpu_atif {
1390 struct amdgpu_atif_notifications notifications;
1391 struct amdgpu_atif_functions functions;
1392 struct amdgpu_atif_notification_cfg notification_cfg;
1393 struct amdgpu_encoder *encoder_for_bl;
1394 };
1395
1396 struct amdgpu_atcs_functions {
1397 bool get_ext_state;
1398 bool pcie_perf_req;
1399 bool pcie_dev_rdy;
1400 bool pcie_bus_width;
1401 };
1402
1403 struct amdgpu_atcs {
1404 struct amdgpu_atcs_functions functions;
1405 };
1406
1407 /*
1408 * CGS
1409 */
1410 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1411 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
1412
1413 /*
1414 * Core structure, functions and helpers.
1415 */
1416 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1417 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1418
1419 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1420 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1421
1422 struct amdgpu_device {
1423 struct device *dev;
1424 struct drm_device *ddev;
1425 struct pci_dev *pdev;
1426
1427 #ifdef CONFIG_DRM_AMD_ACP
1428 struct amdgpu_acp acp;
1429 #endif
1430
1431 /* ASIC */
1432 enum amd_asic_type asic_type;
1433 uint32_t family;
1434 uint32_t rev_id;
1435 uint32_t external_rev_id;
1436 unsigned long flags;
1437 int usec_timeout;
1438 const struct amdgpu_asic_funcs *asic_funcs;
1439 bool shutdown;
1440 bool need_dma32;
1441 bool accel_working;
1442 struct work_struct reset_work;
1443 struct notifier_block acpi_nb;
1444 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1445 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1446 unsigned debugfs_count;
1447 #if defined(CONFIG_DEBUG_FS)
1448 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1449 #endif
1450 struct amdgpu_atif atif;
1451 struct amdgpu_atcs atcs;
1452 struct mutex srbm_mutex;
1453 /* GRBM index mutex. Protects concurrent access to GRBM index */
1454 struct mutex grbm_idx_mutex;
1455 struct dev_pm_domain vga_pm_domain;
1456 bool have_disp_power_ref;
1457
1458 /* BIOS */
1459 bool is_atom_fw;
1460 uint8_t *bios;
1461 uint32_t bios_size;
1462 struct amdgpu_bo *stollen_vga_memory;
1463 uint32_t bios_scratch_reg_offset;
1464 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1465
1466 /* Register/doorbell mmio */
1467 resource_size_t rmmio_base;
1468 resource_size_t rmmio_size;
1469 void __iomem *rmmio;
1470 /* protects concurrent MM_INDEX/DATA based register access */
1471 spinlock_t mmio_idx_lock;
1472 /* protects concurrent SMC based register access */
1473 spinlock_t smc_idx_lock;
1474 amdgpu_rreg_t smc_rreg;
1475 amdgpu_wreg_t smc_wreg;
1476 /* protects concurrent PCIE register access */
1477 spinlock_t pcie_idx_lock;
1478 amdgpu_rreg_t pcie_rreg;
1479 amdgpu_wreg_t pcie_wreg;
1480 amdgpu_rreg_t pciep_rreg;
1481 amdgpu_wreg_t pciep_wreg;
1482 /* protects concurrent UVD register access */
1483 spinlock_t uvd_ctx_idx_lock;
1484 amdgpu_rreg_t uvd_ctx_rreg;
1485 amdgpu_wreg_t uvd_ctx_wreg;
1486 /* protects concurrent DIDT register access */
1487 spinlock_t didt_idx_lock;
1488 amdgpu_rreg_t didt_rreg;
1489 amdgpu_wreg_t didt_wreg;
1490 /* protects concurrent gc_cac register access */
1491 spinlock_t gc_cac_idx_lock;
1492 amdgpu_rreg_t gc_cac_rreg;
1493 amdgpu_wreg_t gc_cac_wreg;
1494 /* protects concurrent ENDPOINT (audio) register access */
1495 spinlock_t audio_endpt_idx_lock;
1496 amdgpu_block_rreg_t audio_endpt_rreg;
1497 amdgpu_block_wreg_t audio_endpt_wreg;
1498 void __iomem *rio_mem;
1499 resource_size_t rio_mem_size;
1500 struct amdgpu_doorbell doorbell;
1501
1502 /* clock/pll info */
1503 struct amdgpu_clock clock;
1504
1505 /* MC */
1506 struct amdgpu_mc mc;
1507 struct amdgpu_gart gart;
1508 struct amdgpu_dummy_page dummy_page;
1509 struct amdgpu_vm_manager vm_manager;
1510 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
1511
1512 /* memory management */
1513 struct amdgpu_mman mman;
1514 struct amdgpu_vram_scratch vram_scratch;
1515 struct amdgpu_wb wb;
1516 atomic64_t vram_usage;
1517 atomic64_t vram_vis_usage;
1518 atomic64_t gtt_usage;
1519 atomic64_t num_bytes_moved;
1520 atomic64_t num_evictions;
1521 atomic_t gpu_reset_counter;
1522
1523 /* data for buffer migration throttling */
1524 struct {
1525 spinlock_t lock;
1526 s64 last_update_us;
1527 s64 accum_us; /* accumulated microseconds */
1528 u32 log2_max_MBps;
1529 } mm_stats;
1530
1531 /* display */
1532 bool enable_virtual_display;
1533 struct amdgpu_mode_info mode_info;
1534 struct work_struct hotplug_work;
1535 struct amdgpu_irq_src crtc_irq;
1536 struct amdgpu_irq_src pageflip_irq;
1537 struct amdgpu_irq_src hpd_irq;
1538
1539 /* rings */
1540 u64 fence_context;
1541 unsigned num_rings;
1542 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1543 bool ib_pool_ready;
1544 struct amdgpu_sa_manager ring_tmp_bo;
1545
1546 /* interrupts */
1547 struct amdgpu_irq irq;
1548
1549 /* powerplay */
1550 struct amd_powerplay powerplay;
1551 bool pp_enabled;
1552 bool pp_force_state_enabled;
1553
1554 /* dpm */
1555 struct amdgpu_pm pm;
1556 u32 cg_flags;
1557 u32 pg_flags;
1558
1559 /* amdgpu smumgr */
1560 struct amdgpu_smumgr smu;
1561
1562 /* gfx */
1563 struct amdgpu_gfx gfx;
1564
1565 /* sdma */
1566 struct amdgpu_sdma sdma;
1567
1568 /* uvd */
1569 struct amdgpu_uvd uvd;
1570
1571 /* vce */
1572 struct amdgpu_vce vce;
1573
1574 /* firmwares */
1575 struct amdgpu_firmware firmware;
1576
1577 /* PSP */
1578 struct psp_context psp;
1579
1580 /* GDS */
1581 struct amdgpu_gds gds;
1582
1583 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
1584 int num_ip_blocks;
1585 struct mutex mn_lock;
1586 DECLARE_HASHTABLE(mn_hash, 7);
1587
1588 /* tracking pinned memory */
1589 u64 vram_pin_size;
1590 u64 invisible_pin_size;
1591 u64 gart_pin_size;
1592
1593 /* amdkfd interface */
1594 struct kfd_dev *kfd;
1595
1596 struct amdgpu_virt virt;
1597
1598 /* link all shadow bo */
1599 struct list_head shadow_list;
1600 struct mutex shadow_list_lock;
1601 /* link all gtt */
1602 spinlock_t gtt_list_lock;
1603 struct list_head gtt_list;
1604
1605 /* record hw reset is performed */
1606 bool has_hw_reset;
1607
1608 };
1609
1610 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1611 {
1612 return container_of(bdev, struct amdgpu_device, mman.bdev);
1613 }
1614
1615 bool amdgpu_device_is_px(struct drm_device *dev);
1616 int amdgpu_device_init(struct amdgpu_device *adev,
1617 struct drm_device *ddev,
1618 struct pci_dev *pdev,
1619 uint32_t flags);
1620 void amdgpu_device_fini(struct amdgpu_device *adev);
1621 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1622
1623 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
1624 uint32_t acc_flags);
1625 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
1626 uint32_t acc_flags);
1627 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1628 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1629
1630 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
1631 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
1632 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
1633 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
1634
1635 /*
1636 * Registers read & write functions.
1637 */
1638
1639 #define AMDGPU_REGS_IDX (1<<0)
1640 #define AMDGPU_REGS_NO_KIQ (1<<1)
1641
1642 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1643 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1644
1645 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1646 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1647 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1648 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1649 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
1650 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1651 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1652 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1653 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1654 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1655 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1656 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1657 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1658 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1659 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1660 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1661 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1662 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1663 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1664 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1665 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1666 #define WREG32_P(reg, val, mask) \
1667 do { \
1668 uint32_t tmp_ = RREG32(reg); \
1669 tmp_ &= (mask); \
1670 tmp_ |= ((val) & ~(mask)); \
1671 WREG32(reg, tmp_); \
1672 } while (0)
1673 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1674 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1675 #define WREG32_PLL_P(reg, val, mask) \
1676 do { \
1677 uint32_t tmp_ = RREG32_PLL(reg); \
1678 tmp_ &= (mask); \
1679 tmp_ |= ((val) & ~(mask)); \
1680 WREG32_PLL(reg, tmp_); \
1681 } while (0)
1682 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1683 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1684 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1685
1686 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1687 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
1688 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1689 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
1690
1691 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1692 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1693
1694 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
1695 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1696 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1697
1698 #define REG_GET_FIELD(value, reg, field) \
1699 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1700
1701 #define WREG32_FIELD(reg, field, val) \
1702 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1703
1704 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1705 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1706
1707 #define WREG32_FIELD15(ip, idx, reg, field, val) \
1708 WREG32(SOC15_REG_OFFSET(ip, idx, mm##reg), (RREG32(SOC15_REG_OFFSET(ip, idx, mm##reg)) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1709
1710 /*
1711 * BIOS helpers.
1712 */
1713 #define RBIOS8(i) (adev->bios[i])
1714 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1715 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1716
1717 /*
1718 * RING helpers.
1719 */
1720 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
1721 {
1722 if (ring->count_dw <= 0)
1723 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
1724 ring->ring[ring->wptr++ & ring->buf_mask] = v;
1725 ring->wptr &= ring->ptr_mask;
1726 ring->count_dw--;
1727 }
1728
1729 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, void *src, int count_dw)
1730 {
1731 unsigned occupied, chunk1, chunk2;
1732 void *dst;
1733
1734 if (ring->count_dw < count_dw) {
1735 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
1736 } else {
1737 occupied = ring->wptr & ring->buf_mask;
1738 dst = (void *)&ring->ring[occupied];
1739 chunk1 = ring->buf_mask + 1 - occupied;
1740 chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
1741 chunk2 = count_dw - chunk1;
1742 chunk1 <<= 2;
1743 chunk2 <<= 2;
1744
1745 if (chunk1)
1746 memcpy(dst, src, chunk1);
1747
1748 if (chunk2) {
1749 src += chunk1;
1750 dst = (void *)ring->ring;
1751 memcpy(dst, src, chunk2);
1752 }
1753
1754 ring->wptr += count_dw;
1755 ring->wptr &= ring->ptr_mask;
1756 ring->count_dw -= count_dw;
1757 }
1758 }
1759
1760 static inline struct amdgpu_sdma_instance *
1761 amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
1762 {
1763 struct amdgpu_device *adev = ring->adev;
1764 int i;
1765
1766 for (i = 0; i < adev->sdma.num_instances; i++)
1767 if (&adev->sdma.instance[i].ring == ring)
1768 break;
1769
1770 if (i < AMDGPU_MAX_SDMA_INSTANCES)
1771 return &adev->sdma.instance[i];
1772 else
1773 return NULL;
1774 }
1775
1776 /*
1777 * ASICs macro.
1778 */
1779 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1780 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1781 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1782 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1783 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1784 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1785 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1786 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1787 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1788 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1789 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1790 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1791 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
1792 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
1793 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
1794 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
1795 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
1796 #define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
1797 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1798 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
1799 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
1800 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1801 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1802 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
1803 #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
1804 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
1805 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
1806 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
1807 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
1808 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
1809 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
1810 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
1811 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
1812 #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1813 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
1814 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
1815 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
1816 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
1817 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
1818 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
1819 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
1820 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
1821 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1822 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
1823 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1824 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1825 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
1826 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
1827 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
1828 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
1829 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
1830 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
1831 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
1832 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
1833 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
1834 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
1835 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
1836 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
1837 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
1838 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
1839 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
1840 #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
1841
1842 /* Common functions */
1843 int amdgpu_gpu_reset(struct amdgpu_device *adev);
1844 bool amdgpu_need_backup(struct amdgpu_device *adev);
1845 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
1846 bool amdgpu_need_post(struct amdgpu_device *adev);
1847 void amdgpu_update_display_priority(struct amdgpu_device *adev);
1848
1849 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
1850 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
1851 u32 ip_instance, u32 ring,
1852 struct amdgpu_ring **out_ring);
1853 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes);
1854 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
1855 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
1856 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
1857 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1858 uint32_t flags);
1859 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
1860 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
1861 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1862 unsigned long end);
1863 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1864 int *last_invalidated);
1865 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
1866 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1867 struct ttm_mem_reg *mem);
1868 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
1869 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
1870 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
1871 int amdgpu_ttm_init(struct amdgpu_device *adev);
1872 void amdgpu_ttm_fini(struct amdgpu_device *adev);
1873 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
1874 const u32 *registers,
1875 const u32 array_size);
1876
1877 bool amdgpu_device_is_px(struct drm_device *dev);
1878 /* atpx handler */
1879 #if defined(CONFIG_VGA_SWITCHEROO)
1880 void amdgpu_register_atpx_handler(void);
1881 void amdgpu_unregister_atpx_handler(void);
1882 bool amdgpu_has_atpx_dgpu_power_cntl(void);
1883 bool amdgpu_is_atpx_hybrid(void);
1884 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1885 bool amdgpu_has_atpx(void);
1886 #else
1887 static inline void amdgpu_register_atpx_handler(void) {}
1888 static inline void amdgpu_unregister_atpx_handler(void) {}
1889 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1890 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1891 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1892 static inline bool amdgpu_has_atpx(void) { return false; }
1893 #endif
1894
1895 /*
1896 * KMS
1897 */
1898 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1899 extern const int amdgpu_max_kms_ioctl;
1900
1901 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
1902 void amdgpu_driver_unload_kms(struct drm_device *dev);
1903 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1904 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1905 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1906 struct drm_file *file_priv);
1907 int amdgpu_suspend(struct amdgpu_device *adev);
1908 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1909 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
1910 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1911 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1912 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1913 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
1914 int *max_error,
1915 struct timeval *vblank_time,
1916 unsigned flags);
1917 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1918 unsigned long arg);
1919
1920 /*
1921 * functions used by amdgpu_encoder.c
1922 */
1923 struct amdgpu_afmt_acr {
1924 u32 clock;
1925
1926 int n_32khz;
1927 int cts_32khz;
1928
1929 int n_44_1khz;
1930 int cts_44_1khz;
1931
1932 int n_48khz;
1933 int cts_48khz;
1934
1935 };
1936
1937 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1938
1939 /* amdgpu_acpi.c */
1940 #if defined(CONFIG_ACPI)
1941 int amdgpu_acpi_init(struct amdgpu_device *adev);
1942 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1943 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1944 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1945 u8 perf_req, bool advertise);
1946 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1947 #else
1948 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1949 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1950 #endif
1951
1952 struct amdgpu_bo_va_mapping *
1953 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1954 uint64_t addr, struct amdgpu_bo **bo);
1955 int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);
1956
1957 #include "amdgpu_object.h"
1958 #endif
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