2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
45 #include <drm/drm_gem.h>
46 #include <drm/amdgpu_drm.h>
48 #include "amd_shared.h"
49 #include "amdgpu_family.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_gds.h"
59 extern int amdgpu_modeset
;
60 extern int amdgpu_vram_limit
;
61 extern int amdgpu_gart_size
;
62 extern int amdgpu_benchmarking
;
63 extern int amdgpu_testing
;
64 extern int amdgpu_audio
;
65 extern int amdgpu_disp_priority
;
66 extern int amdgpu_hw_i2c
;
67 extern int amdgpu_pcie_gen2
;
68 extern int amdgpu_msi
;
69 extern int amdgpu_lockup_timeout
;
70 extern int amdgpu_dpm
;
71 extern int amdgpu_smc_load_fw
;
72 extern int amdgpu_aspm
;
73 extern int amdgpu_runtime_pm
;
74 extern int amdgpu_hard_reset
;
75 extern unsigned amdgpu_ip_block_mask
;
76 extern int amdgpu_bapm
;
77 extern int amdgpu_deep_color
;
78 extern int amdgpu_vm_size
;
79 extern int amdgpu_vm_block_size
;
81 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
82 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
83 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
84 #define AMDGPU_IB_POOL_SIZE 16
85 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
86 #define AMDGPUFB_CONN_LIMIT 4
87 #define AMDGPU_BIOS_NUM_SCRATCH 8
89 /* max number of rings */
90 #define AMDGPU_MAX_RINGS 16
91 #define AMDGPU_MAX_GFX_RINGS 1
92 #define AMDGPU_MAX_COMPUTE_RINGS 8
93 #define AMDGPU_MAX_VCE_RINGS 2
95 /* number of hw syncs before falling back on blocking */
96 #define AMDGPU_NUM_SYNCS 4
98 /* hardcode that limit for now */
99 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
101 /* hard reset data */
102 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
105 #define AMDGPU_RESET_GFX (1 << 0)
106 #define AMDGPU_RESET_COMPUTE (1 << 1)
107 #define AMDGPU_RESET_DMA (1 << 2)
108 #define AMDGPU_RESET_CP (1 << 3)
109 #define AMDGPU_RESET_GRBM (1 << 4)
110 #define AMDGPU_RESET_DMA1 (1 << 5)
111 #define AMDGPU_RESET_RLC (1 << 6)
112 #define AMDGPU_RESET_SEM (1 << 7)
113 #define AMDGPU_RESET_IH (1 << 8)
114 #define AMDGPU_RESET_VMC (1 << 9)
115 #define AMDGPU_RESET_MC (1 << 10)
116 #define AMDGPU_RESET_DISPLAY (1 << 11)
117 #define AMDGPU_RESET_UVD (1 << 12)
118 #define AMDGPU_RESET_VCE (1 << 13)
119 #define AMDGPU_RESET_VCE1 (1 << 14)
122 #define AMDGPU_CG_BLOCK_GFX (1 << 0)
123 #define AMDGPU_CG_BLOCK_MC (1 << 1)
124 #define AMDGPU_CG_BLOCK_SDMA (1 << 2)
125 #define AMDGPU_CG_BLOCK_UVD (1 << 3)
126 #define AMDGPU_CG_BLOCK_VCE (1 << 4)
127 #define AMDGPU_CG_BLOCK_HDP (1 << 5)
128 #define AMDGPU_CG_BLOCK_BIF (1 << 6)
131 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
132 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
133 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
134 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
135 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
136 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
137 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
138 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
139 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
140 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
141 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
142 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
143 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
144 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
145 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
146 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
147 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
150 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
151 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
152 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
153 #define AMDGPU_PG_SUPPORT_UVD (1 << 3)
154 #define AMDGPU_PG_SUPPORT_VCE (1 << 4)
155 #define AMDGPU_PG_SUPPORT_CP (1 << 5)
156 #define AMDGPU_PG_SUPPORT_GDS (1 << 6)
157 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
158 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
159 #define AMDGPU_PG_SUPPORT_ACP (1 << 9)
160 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
162 /* GFX current status */
163 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
164 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
165 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
166 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
167 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
169 /* max cursor sizes (in pixels) */
170 #define CIK_CURSOR_WIDTH 128
171 #define CIK_CURSOR_HEIGHT 128
173 struct amdgpu_device
;
178 struct amdgpu_semaphore
;
179 struct amdgpu_cs_parser
;
180 struct amdgpu_irq_src
;
183 AMDGPU_CP_IRQ_GFX_EOP
= 0,
184 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
,
185 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP
,
186 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP
,
187 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP
,
188 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP
,
189 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP
,
190 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP
,
191 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP
,
196 enum amdgpu_sdma_irq
{
197 AMDGPU_SDMA_IRQ_TRAP0
= 0,
198 AMDGPU_SDMA_IRQ_TRAP1
,
203 enum amdgpu_thermal_irq
{
204 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH
= 0,
205 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW
,
207 AMDGPU_THERMAL_IRQ_LAST
210 int amdgpu_set_clockgating_state(struct amdgpu_device
*adev
,
211 enum amd_ip_block_type block_type
,
212 enum amd_clockgating_state state
);
213 int amdgpu_set_powergating_state(struct amdgpu_device
*adev
,
214 enum amd_ip_block_type block_type
,
215 enum amd_powergating_state state
);
217 struct amdgpu_ip_block_version
{
218 enum amd_ip_block_type type
;
222 const struct amd_ip_funcs
*funcs
;
225 int amdgpu_ip_block_version_cmp(struct amdgpu_device
*adev
,
226 enum amd_ip_block_type type
,
227 u32 major
, u32 minor
);
229 const struct amdgpu_ip_block_version
* amdgpu_get_ip_block(
230 struct amdgpu_device
*adev
,
231 enum amd_ip_block_type type
);
233 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
234 struct amdgpu_buffer_funcs
{
235 /* maximum bytes in a single operation */
236 uint32_t copy_max_bytes
;
238 /* number of dw to reserve per operation */
239 unsigned copy_num_dw
;
241 /* used for buffer migration */
242 void (*emit_copy_buffer
)(struct amdgpu_ring
*ring
,
243 /* src addr in bytes */
245 /* dst addr in bytes */
247 /* number of byte to transfer */
248 uint32_t byte_count
);
250 /* maximum bytes in a single operation */
251 uint32_t fill_max_bytes
;
253 /* number of dw to reserve per operation */
254 unsigned fill_num_dw
;
256 /* used for buffer clearing */
257 void (*emit_fill_buffer
)(struct amdgpu_ring
*ring
,
258 /* value to write to memory */
260 /* dst addr in bytes */
262 /* number of byte to fill */
263 uint32_t byte_count
);
266 /* provided by hw blocks that can write ptes, e.g., sdma */
267 struct amdgpu_vm_pte_funcs
{
268 /* copy pte entries from GART */
269 void (*copy_pte
)(struct amdgpu_ib
*ib
,
270 uint64_t pe
, uint64_t src
,
272 /* write pte one entry at a time with addr mapping */
273 void (*write_pte
)(struct amdgpu_ib
*ib
,
275 uint64_t addr
, unsigned count
,
276 uint32_t incr
, uint32_t flags
);
277 /* for linear pte/pde updates without addr mapping */
278 void (*set_pte_pde
)(struct amdgpu_ib
*ib
,
280 uint64_t addr
, unsigned count
,
281 uint32_t incr
, uint32_t flags
);
282 /* pad the indirect buffer to the necessary number of dw */
283 void (*pad_ib
)(struct amdgpu_ib
*ib
);
286 /* provided by the gmc block */
287 struct amdgpu_gart_funcs
{
288 /* flush the vm tlb via mmio */
289 void (*flush_gpu_tlb
)(struct amdgpu_device
*adev
,
291 /* write pte/pde updates using the cpu */
292 int (*set_pte_pde
)(struct amdgpu_device
*adev
,
293 void *cpu_pt_addr
, /* cpu addr of page table */
294 uint32_t gpu_page_idx
, /* pte/pde to update */
295 uint64_t addr
, /* addr to write into pte/pde */
296 uint32_t flags
); /* access flags */
299 /* provided by the ih block */
300 struct amdgpu_ih_funcs
{
301 /* ring read/write ptr handling, called from interrupt context */
302 u32 (*get_wptr
)(struct amdgpu_device
*adev
);
303 void (*decode_iv
)(struct amdgpu_device
*adev
,
304 struct amdgpu_iv_entry
*entry
);
305 void (*set_rptr
)(struct amdgpu_device
*adev
);
308 /* provided by hw blocks that expose a ring buffer for commands */
309 struct amdgpu_ring_funcs
{
310 /* ring read/write ptr handling */
311 u32 (*get_rptr
)(struct amdgpu_ring
*ring
);
312 u32 (*get_wptr
)(struct amdgpu_ring
*ring
);
313 void (*set_wptr
)(struct amdgpu_ring
*ring
);
314 /* validating and patching of IBs */
315 int (*parse_cs
)(struct amdgpu_cs_parser
*p
, uint32_t ib_idx
);
316 /* command emit functions */
317 void (*emit_ib
)(struct amdgpu_ring
*ring
,
318 struct amdgpu_ib
*ib
);
319 void (*emit_fence
)(struct amdgpu_ring
*ring
, uint64_t addr
,
320 uint64_t seq
, unsigned flags
);
321 bool (*emit_semaphore
)(struct amdgpu_ring
*ring
,
322 struct amdgpu_semaphore
*semaphore
,
324 void (*emit_vm_flush
)(struct amdgpu_ring
*ring
, unsigned vm_id
,
326 void (*emit_hdp_flush
)(struct amdgpu_ring
*ring
);
327 void (*emit_gds_switch
)(struct amdgpu_ring
*ring
, uint32_t vmid
,
328 uint32_t gds_base
, uint32_t gds_size
,
329 uint32_t gws_base
, uint32_t gws_size
,
330 uint32_t oa_base
, uint32_t oa_size
);
331 /* testing functions */
332 int (*test_ring
)(struct amdgpu_ring
*ring
);
333 int (*test_ib
)(struct amdgpu_ring
*ring
);
334 bool (*is_lockup
)(struct amdgpu_ring
*ring
);
340 bool amdgpu_get_bios(struct amdgpu_device
*adev
);
341 bool amdgpu_read_bios(struct amdgpu_device
*adev
);
346 struct amdgpu_dummy_page
{
350 int amdgpu_dummy_page_init(struct amdgpu_device
*adev
);
351 void amdgpu_dummy_page_fini(struct amdgpu_device
*adev
);
358 #define AMDGPU_MAX_PPLL 3
360 struct amdgpu_clock
{
361 struct amdgpu_pll ppll
[AMDGPU_MAX_PPLL
];
362 struct amdgpu_pll spll
;
363 struct amdgpu_pll mpll
;
365 uint32_t default_mclk
;
366 uint32_t default_sclk
;
367 uint32_t default_dispclk
;
368 uint32_t current_dispclk
;
370 uint32_t max_pixel_clock
;
376 struct amdgpu_fence_driver
{
377 struct amdgpu_ring
*ring
;
379 volatile uint32_t *cpu_addr
;
380 /* sync_seq is protected by ring emission lock */
381 uint64_t sync_seq
[AMDGPU_MAX_RINGS
];
385 struct amdgpu_irq_src
*irq_src
;
387 struct delayed_work lockup_work
;
390 /* some special values for the owner field */
391 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
392 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
393 #define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul)
395 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
396 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
398 struct amdgpu_fence
{
402 struct amdgpu_ring
*ring
;
405 /* filp or special value for fence creator */
408 wait_queue_t fence_wake
;
411 struct amdgpu_user_fence
{
413 struct amdgpu_bo
*bo
;
414 /* write-back address offset to bo start */
418 int amdgpu_fence_driver_init(struct amdgpu_device
*adev
);
419 void amdgpu_fence_driver_fini(struct amdgpu_device
*adev
);
420 void amdgpu_fence_driver_force_completion(struct amdgpu_device
*adev
);
422 void amdgpu_fence_driver_init_ring(struct amdgpu_ring
*ring
);
423 int amdgpu_fence_driver_start_ring(struct amdgpu_ring
*ring
,
424 struct amdgpu_irq_src
*irq_src
,
426 int amdgpu_fence_emit(struct amdgpu_ring
*ring
, void *owner
,
427 struct amdgpu_fence
**fence
);
428 int amdgpu_fence_recreate(struct amdgpu_ring
*ring
, void *owner
,
429 uint64_t seq
, struct amdgpu_fence
**fence
);
430 void amdgpu_fence_process(struct amdgpu_ring
*ring
);
431 int amdgpu_fence_wait_next(struct amdgpu_ring
*ring
);
432 int amdgpu_fence_wait_empty(struct amdgpu_ring
*ring
);
433 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring
*ring
);
435 bool amdgpu_fence_signaled(struct amdgpu_fence
*fence
);
436 int amdgpu_fence_wait(struct amdgpu_fence
*fence
, bool interruptible
);
437 int amdgpu_fence_wait_any(struct amdgpu_device
*adev
,
438 struct amdgpu_fence
**fences
,
440 struct amdgpu_fence
*amdgpu_fence_ref(struct amdgpu_fence
*fence
);
441 void amdgpu_fence_unref(struct amdgpu_fence
**fence
);
443 bool amdgpu_fence_need_sync(struct amdgpu_fence
*fence
,
444 struct amdgpu_ring
*ring
);
445 void amdgpu_fence_note_sync(struct amdgpu_fence
*fence
,
446 struct amdgpu_ring
*ring
);
448 static inline struct amdgpu_fence
*amdgpu_fence_later(struct amdgpu_fence
*a
,
449 struct amdgpu_fence
*b
)
459 BUG_ON(a
->ring
!= b
->ring
);
461 if (a
->seq
> b
->seq
) {
468 static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence
*a
,
469 struct amdgpu_fence
*b
)
479 BUG_ON(a
->ring
!= b
->ring
);
481 return a
->seq
< b
->seq
;
484 int amdgpu_user_fence_emit(struct amdgpu_ring
*ring
, struct amdgpu_user_fence
*user
,
485 void *owner
, struct amdgpu_fence
**fence
);
491 struct ttm_bo_global_ref bo_global_ref
;
492 struct drm_global_reference mem_global_ref
;
493 struct ttm_bo_device bdev
;
494 bool mem_global_referenced
;
497 #if defined(CONFIG_DEBUG_FS)
502 /* buffer handling */
503 const struct amdgpu_buffer_funcs
*buffer_funcs
;
504 struct amdgpu_ring
*buffer_funcs_ring
;
507 int amdgpu_copy_buffer(struct amdgpu_ring
*ring
,
511 struct reservation_object
*resv
,
512 struct amdgpu_fence
**fence
);
513 int amdgpu_mmap(struct file
*filp
, struct vm_area_struct
*vma
);
515 struct amdgpu_bo_list_entry
{
516 struct amdgpu_bo
*robj
;
517 struct ttm_validate_buffer tv
;
518 struct amdgpu_bo_va
*bo_va
;
519 unsigned prefered_domains
;
520 unsigned allowed_domains
;
524 struct amdgpu_bo_va_mapping
{
525 struct list_head list
;
526 struct interval_tree_node it
;
531 /* bo virtual addresses in a specific vm */
532 struct amdgpu_bo_va
{
533 /* protected by bo being reserved */
534 struct list_head bo_list
;
536 struct amdgpu_fence
*last_pt_update
;
539 /* protected by vm mutex */
540 struct list_head mappings
;
541 struct list_head vm_status
;
543 /* constant after initialization */
544 struct amdgpu_vm
*vm
;
545 struct amdgpu_bo
*bo
;
548 #define AMDGPU_GEM_DOMAIN_MAX 0x3
551 /* Protected by gem.mutex */
552 struct list_head list
;
553 /* Protected by tbo.reserved */
555 struct ttm_place placements
[AMDGPU_GEM_DOMAIN_MAX
+ 1];
556 struct ttm_placement placement
;
557 struct ttm_buffer_object tbo
;
558 struct ttm_bo_kmap_obj kmap
;
566 /* list of all virtual address to which this bo
570 /* Constant after initialization */
571 struct amdgpu_device
*adev
;
572 struct drm_gem_object gem_base
;
574 struct ttm_bo_kmap_obj dma_buf_vmap
;
576 struct amdgpu_mn
*mn
;
577 struct list_head mn_list
;
579 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
581 void amdgpu_gem_object_free(struct drm_gem_object
*obj
);
582 int amdgpu_gem_object_open(struct drm_gem_object
*obj
,
583 struct drm_file
*file_priv
);
584 void amdgpu_gem_object_close(struct drm_gem_object
*obj
,
585 struct drm_file
*file_priv
);
586 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns
);
587 struct sg_table
*amdgpu_gem_prime_get_sg_table(struct drm_gem_object
*obj
);
588 struct drm_gem_object
*amdgpu_gem_prime_import_sg_table(struct drm_device
*dev
,
589 struct dma_buf_attachment
*attach
,
590 struct sg_table
*sg
);
591 struct dma_buf
*amdgpu_gem_prime_export(struct drm_device
*dev
,
592 struct drm_gem_object
*gobj
,
594 int amdgpu_gem_prime_pin(struct drm_gem_object
*obj
);
595 void amdgpu_gem_prime_unpin(struct drm_gem_object
*obj
);
596 struct reservation_object
*amdgpu_gem_prime_res_obj(struct drm_gem_object
*);
597 void *amdgpu_gem_prime_vmap(struct drm_gem_object
*obj
);
598 void amdgpu_gem_prime_vunmap(struct drm_gem_object
*obj
, void *vaddr
);
599 int amdgpu_gem_debugfs_init(struct amdgpu_device
*adev
);
601 /* sub-allocation manager, it has to be protected by another lock.
602 * By conception this is an helper for other part of the driver
603 * like the indirect buffer or semaphore, which both have their
606 * Principe is simple, we keep a list of sub allocation in offset
607 * order (first entry has offset == 0, last entry has the highest
610 * When allocating new object we first check if there is room at
611 * the end total_size - (last_object_offset + last_object_size) >=
612 * alloc_size. If so we allocate new object there.
614 * When there is not enough room at the end, we start waiting for
615 * each sub object until we reach object_offset+object_size >=
616 * alloc_size, this object then become the sub object we return.
618 * Alignment can't be bigger than page size.
620 * Hole are not considered for allocation to keep things simple.
621 * Assumption is that there won't be hole (all object on same
624 struct amdgpu_sa_manager
{
625 wait_queue_head_t wq
;
626 struct amdgpu_bo
*bo
;
627 struct list_head
*hole
;
628 struct list_head flist
[AMDGPU_MAX_RINGS
];
629 struct list_head olist
;
639 /* sub-allocation buffer */
640 struct amdgpu_sa_bo
{
641 struct list_head olist
;
642 struct list_head flist
;
643 struct amdgpu_sa_manager
*manager
;
646 struct amdgpu_fence
*fence
;
654 struct list_head objects
;
657 int amdgpu_gem_init(struct amdgpu_device
*adev
);
658 void amdgpu_gem_fini(struct amdgpu_device
*adev
);
659 int amdgpu_gem_object_create(struct amdgpu_device
*adev
, unsigned long size
,
660 int alignment
, u32 initial_domain
,
661 u64 flags
, bool kernel
,
662 struct drm_gem_object
**obj
);
664 int amdgpu_mode_dumb_create(struct drm_file
*file_priv
,
665 struct drm_device
*dev
,
666 struct drm_mode_create_dumb
*args
);
667 int amdgpu_mode_dumb_mmap(struct drm_file
*filp
,
668 struct drm_device
*dev
,
669 uint32_t handle
, uint64_t *offset_p
);
674 struct amdgpu_semaphore
{
675 struct amdgpu_sa_bo
*sa_bo
;
680 int amdgpu_semaphore_create(struct amdgpu_device
*adev
,
681 struct amdgpu_semaphore
**semaphore
);
682 bool amdgpu_semaphore_emit_signal(struct amdgpu_ring
*ring
,
683 struct amdgpu_semaphore
*semaphore
);
684 bool amdgpu_semaphore_emit_wait(struct amdgpu_ring
*ring
,
685 struct amdgpu_semaphore
*semaphore
);
686 void amdgpu_semaphore_free(struct amdgpu_device
*adev
,
687 struct amdgpu_semaphore
**semaphore
,
688 struct amdgpu_fence
*fence
);
694 struct amdgpu_semaphore
*semaphores
[AMDGPU_NUM_SYNCS
];
695 struct amdgpu_fence
*sync_to
[AMDGPU_MAX_RINGS
];
696 struct amdgpu_fence
*last_vm_update
;
699 void amdgpu_sync_create(struct amdgpu_sync
*sync
);
700 void amdgpu_sync_fence(struct amdgpu_sync
*sync
,
701 struct amdgpu_fence
*fence
);
702 int amdgpu_sync_resv(struct amdgpu_device
*adev
,
703 struct amdgpu_sync
*sync
,
704 struct reservation_object
*resv
,
706 int amdgpu_sync_rings(struct amdgpu_sync
*sync
,
707 struct amdgpu_ring
*ring
);
708 void amdgpu_sync_free(struct amdgpu_device
*adev
, struct amdgpu_sync
*sync
,
709 struct amdgpu_fence
*fence
);
712 * GART structures, functions & helpers
716 #define AMDGPU_GPU_PAGE_SIZE 4096
717 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
718 #define AMDGPU_GPU_PAGE_SHIFT 12
719 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
722 dma_addr_t table_addr
;
723 struct amdgpu_bo
*robj
;
725 unsigned num_gpu_pages
;
726 unsigned num_cpu_pages
;
729 dma_addr_t
*pages_addr
;
731 const struct amdgpu_gart_funcs
*gart_funcs
;
734 int amdgpu_gart_table_ram_alloc(struct amdgpu_device
*adev
);
735 void amdgpu_gart_table_ram_free(struct amdgpu_device
*adev
);
736 int amdgpu_gart_table_vram_alloc(struct amdgpu_device
*adev
);
737 void amdgpu_gart_table_vram_free(struct amdgpu_device
*adev
);
738 int amdgpu_gart_table_vram_pin(struct amdgpu_device
*adev
);
739 void amdgpu_gart_table_vram_unpin(struct amdgpu_device
*adev
);
740 int amdgpu_gart_init(struct amdgpu_device
*adev
);
741 void amdgpu_gart_fini(struct amdgpu_device
*adev
);
742 void amdgpu_gart_unbind(struct amdgpu_device
*adev
, unsigned offset
,
744 int amdgpu_gart_bind(struct amdgpu_device
*adev
, unsigned offset
,
745 int pages
, struct page
**pagelist
,
746 dma_addr_t
*dma_addr
, uint32_t flags
);
749 * GPU MC structures, functions & helpers
752 resource_size_t aper_size
;
753 resource_size_t aper_base
;
754 resource_size_t agp_base
;
755 /* for some chips with <= 32MB we need to lie
756 * about vram size near mc fb location */
758 u64 visible_vram_size
;
769 const struct firmware
*fw
; /* MC firmware */
771 struct amdgpu_irq_src vm_fault
;
776 * GPU doorbell structures, functions & helpers
778 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
780 AMDGPU_DOORBELL_KIQ
= 0x000,
781 AMDGPU_DOORBELL_HIQ
= 0x001,
782 AMDGPU_DOORBELL_DIQ
= 0x002,
783 AMDGPU_DOORBELL_MEC_RING0
= 0x010,
784 AMDGPU_DOORBELL_MEC_RING1
= 0x011,
785 AMDGPU_DOORBELL_MEC_RING2
= 0x012,
786 AMDGPU_DOORBELL_MEC_RING3
= 0x013,
787 AMDGPU_DOORBELL_MEC_RING4
= 0x014,
788 AMDGPU_DOORBELL_MEC_RING5
= 0x015,
789 AMDGPU_DOORBELL_MEC_RING6
= 0x016,
790 AMDGPU_DOORBELL_MEC_RING7
= 0x017,
791 AMDGPU_DOORBELL_GFX_RING0
= 0x020,
792 AMDGPU_DOORBELL_sDMA_ENGINE0
= 0x1E0,
793 AMDGPU_DOORBELL_sDMA_ENGINE1
= 0x1E1,
794 AMDGPU_DOORBELL_IH
= 0x1E8,
795 AMDGPU_DOORBELL_MAX_ASSIGNMENT
= 0x3FF,
796 AMDGPU_DOORBELL_INVALID
= 0xFFFF
797 } AMDGPU_DOORBELL_ASSIGNMENT
;
799 struct amdgpu_doorbell
{
801 resource_size_t base
;
802 resource_size_t size
;
804 u32 num_doorbells
; /* Number of doorbells actually reserved for amdgpu. */
807 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device
*adev
,
808 phys_addr_t
*aperture_base
,
809 size_t *aperture_size
,
810 size_t *start_offset
);
816 struct amdgpu_flip_work
{
817 struct work_struct flip_work
;
818 struct work_struct unpin_work
;
819 struct amdgpu_device
*adev
;
822 struct drm_pending_vblank_event
*event
;
823 struct amdgpu_bo
*old_rbo
;
833 struct amdgpu_sa_bo
*sa_bo
;
837 struct amdgpu_ring
*ring
;
838 struct amdgpu_fence
*fence
;
839 struct amdgpu_user_fence
*user
;
840 struct amdgpu_vm
*vm
;
841 struct amdgpu_ctx
*ctx
;
842 struct amdgpu_sync sync
;
843 uint32_t gds_base
, gds_size
;
844 uint32_t gws_base
, gws_size
;
845 uint32_t oa_base
, oa_size
;
849 enum amdgpu_ring_type
{
850 AMDGPU_RING_TYPE_GFX
,
851 AMDGPU_RING_TYPE_COMPUTE
,
852 AMDGPU_RING_TYPE_SDMA
,
853 AMDGPU_RING_TYPE_UVD
,
858 struct amdgpu_device
*adev
;
859 const struct amdgpu_ring_funcs
*funcs
;
860 struct amdgpu_fence_driver fence_drv
;
862 struct mutex
*ring_lock
;
863 struct amdgpu_bo
*ring_obj
;
864 volatile uint32_t *ring
;
866 u64 next_rptr_gpu_addr
;
867 volatile u32
*next_rptr_cpu_addr
;
871 unsigned ring_free_dw
;
874 atomic64_t last_activity
;
881 u64 last_semaphore_signal_addr
;
882 u64 last_semaphore_wait_addr
;
886 struct amdgpu_bo
*mqd_obj
;
890 unsigned next_rptr_offs
;
892 struct amdgpu_ctx
*current_ctx
;
893 enum amdgpu_ring_type type
;
901 /* maximum number of VMIDs */
902 #define AMDGPU_NUM_VM 16
904 /* number of entries in page table */
905 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
907 /* PTBs (Page Table Blocks) need to be aligned to 32K */
908 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
909 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
910 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
912 #define AMDGPU_PTE_VALID (1 << 0)
913 #define AMDGPU_PTE_SYSTEM (1 << 1)
914 #define AMDGPU_PTE_SNOOPED (1 << 2)
917 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
919 #define AMDGPU_PTE_READABLE (1 << 5)
920 #define AMDGPU_PTE_WRITEABLE (1 << 6)
922 /* PTE (Page Table Entry) fragment field for different page sizes */
923 #define AMDGPU_PTE_FRAG_4KB (0 << 7)
924 #define AMDGPU_PTE_FRAG_64KB (4 << 7)
925 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
927 struct amdgpu_vm_pt
{
928 struct amdgpu_bo
*bo
;
932 struct amdgpu_vm_id
{
934 uint64_t pd_gpu_addr
;
935 /* last flushed PD/PT update */
936 struct amdgpu_fence
*flushed_updates
;
937 /* last use of vmid */
938 struct amdgpu_fence
*last_id_use
;
946 /* protecting invalidated and freed */
947 spinlock_t status_lock
;
949 /* BOs moved, but not yet updated in the PT */
950 struct list_head invalidated
;
952 /* BOs freed, but not yet updated in the PT */
953 struct list_head freed
;
955 /* contains the page directory */
956 struct amdgpu_bo
*page_directory
;
957 unsigned max_pde_used
;
959 /* array of page tables, one for each page directory entry */
960 struct amdgpu_vm_pt
*page_tables
;
962 /* for id and flush management per ring */
963 struct amdgpu_vm_id ids
[AMDGPU_MAX_RINGS
];
966 struct amdgpu_vm_manager
{
967 struct amdgpu_fence
*active
[AMDGPU_NUM_VM
];
969 /* number of VMIDs */
971 /* vram base address for page table entry */
972 u64 vram_base_offset
;
975 /* for hw to save the PD addr on suspend/resume */
976 uint32_t saved_table_addr
[AMDGPU_NUM_VM
];
977 /* vm pte handling */
978 const struct amdgpu_vm_pte_funcs
*vm_pte_funcs
;
979 struct amdgpu_ring
*vm_pte_funcs_ring
;
983 * context related structures
986 struct amdgpu_ctx_state
{
992 /* call kref_get()before CS start and kref_put() after CS fence signaled */
993 struct kref refcount
;
994 struct amdgpu_fpriv
*fpriv
;
995 struct amdgpu_ctx_state state
;
997 unsigned reset_counter
;
1000 struct amdgpu_ctx_mgr
{
1001 struct amdgpu_device
*adev
;
1002 struct idr ctx_handles
;
1003 /* lock for IDR system */
1008 * file private structure
1011 struct amdgpu_fpriv
{
1012 struct amdgpu_vm vm
;
1013 struct mutex bo_list_lock
;
1014 struct idr bo_list_handles
;
1015 struct amdgpu_ctx_mgr ctx_mgr
;
1022 struct amdgpu_bo_list
{
1024 struct amdgpu_bo
*gds_obj
;
1025 struct amdgpu_bo
*gws_obj
;
1026 struct amdgpu_bo
*oa_obj
;
1028 unsigned num_entries
;
1029 struct amdgpu_bo_list_entry
*array
;
1032 struct amdgpu_bo_list
*
1033 amdgpu_bo_list_get(struct amdgpu_fpriv
*fpriv
, int id
);
1034 void amdgpu_bo_list_put(struct amdgpu_bo_list
*list
);
1035 void amdgpu_bo_list_free(struct amdgpu_bo_list
*list
);
1040 #include "clearstate_defs.h"
1043 /* for power gating */
1044 struct amdgpu_bo
*save_restore_obj
;
1045 uint64_t save_restore_gpu_addr
;
1046 volatile uint32_t *sr_ptr
;
1047 const u32
*reg_list
;
1049 /* for clear state */
1050 struct amdgpu_bo
*clear_state_obj
;
1051 uint64_t clear_state_gpu_addr
;
1052 volatile uint32_t *cs_ptr
;
1053 const struct cs_section_def
*cs_data
;
1054 u32 clear_state_size
;
1056 struct amdgpu_bo
*cp_table_obj
;
1057 uint64_t cp_table_gpu_addr
;
1058 volatile uint32_t *cp_table_ptr
;
1063 struct amdgpu_bo
*hpd_eop_obj
;
1064 u64 hpd_eop_gpu_addr
;
1071 * GPU scratch registers structures, functions & helpers
1073 struct amdgpu_scratch
{
1081 * GFX configurations
1083 struct amdgpu_gca_config
{
1084 unsigned max_shader_engines
;
1085 unsigned max_tile_pipes
;
1086 unsigned max_cu_per_sh
;
1087 unsigned max_sh_per_se
;
1088 unsigned max_backends_per_se
;
1089 unsigned max_texture_channel_caches
;
1091 unsigned max_gs_threads
;
1092 unsigned max_hw_contexts
;
1093 unsigned sc_prim_fifo_size_frontend
;
1094 unsigned sc_prim_fifo_size_backend
;
1095 unsigned sc_hiz_tile_fifo_size
;
1096 unsigned sc_earlyz_tile_fifo_size
;
1098 unsigned num_tile_pipes
;
1099 unsigned backend_enable_mask
;
1100 unsigned mem_max_burst_length_bytes
;
1101 unsigned mem_row_size_in_kb
;
1102 unsigned shader_engine_tile_size
;
1104 unsigned multi_gpu_tile_size
;
1105 unsigned mc_arb_ramcfg
;
1106 unsigned gb_addr_config
;
1108 uint32_t tile_mode_array
[32];
1109 uint32_t macrotile_mode_array
[16];
1113 struct mutex gpu_clock_mutex
;
1114 struct amdgpu_gca_config config
;
1115 struct amdgpu_rlc rlc
;
1116 struct amdgpu_mec mec
;
1117 struct amdgpu_scratch scratch
;
1118 const struct firmware
*me_fw
; /* ME firmware */
1119 uint32_t me_fw_version
;
1120 const struct firmware
*pfp_fw
; /* PFP firmware */
1121 uint32_t pfp_fw_version
;
1122 const struct firmware
*ce_fw
; /* CE firmware */
1123 uint32_t ce_fw_version
;
1124 const struct firmware
*rlc_fw
; /* RLC firmware */
1125 uint32_t rlc_fw_version
;
1126 const struct firmware
*mec_fw
; /* MEC firmware */
1127 uint32_t mec_fw_version
;
1128 const struct firmware
*mec2_fw
; /* MEC2 firmware */
1129 uint32_t mec2_fw_version
;
1130 uint32_t me_feature_version
;
1131 uint32_t ce_feature_version
;
1132 uint32_t pfp_feature_version
;
1133 struct amdgpu_ring gfx_ring
[AMDGPU_MAX_GFX_RINGS
];
1134 unsigned num_gfx_rings
;
1135 struct amdgpu_ring compute_ring
[AMDGPU_MAX_COMPUTE_RINGS
];
1136 unsigned num_compute_rings
;
1137 struct amdgpu_irq_src eop_irq
;
1138 struct amdgpu_irq_src priv_reg_irq
;
1139 struct amdgpu_irq_src priv_inst_irq
;
1141 uint32_t gfx_current_status
;
1142 /* sync signal for const engine */
1143 unsigned ce_sync_offs
;
1145 unsigned ce_ram_size
;
1148 int amdgpu_ib_get(struct amdgpu_ring
*ring
, struct amdgpu_vm
*vm
,
1149 unsigned size
, struct amdgpu_ib
*ib
);
1150 void amdgpu_ib_free(struct amdgpu_device
*adev
, struct amdgpu_ib
*ib
);
1151 int amdgpu_ib_schedule(struct amdgpu_device
*adev
, unsigned num_ibs
,
1152 struct amdgpu_ib
*ib
, void *owner
);
1153 int amdgpu_ib_pool_init(struct amdgpu_device
*adev
);
1154 void amdgpu_ib_pool_fini(struct amdgpu_device
*adev
);
1155 int amdgpu_ib_ring_tests(struct amdgpu_device
*adev
);
1156 /* Ring access between begin & end cannot sleep */
1157 void amdgpu_ring_free_size(struct amdgpu_ring
*ring
);
1158 int amdgpu_ring_alloc(struct amdgpu_ring
*ring
, unsigned ndw
);
1159 int amdgpu_ring_lock(struct amdgpu_ring
*ring
, unsigned ndw
);
1160 void amdgpu_ring_commit(struct amdgpu_ring
*ring
);
1161 void amdgpu_ring_unlock_commit(struct amdgpu_ring
*ring
);
1162 void amdgpu_ring_undo(struct amdgpu_ring
*ring
);
1163 void amdgpu_ring_unlock_undo(struct amdgpu_ring
*ring
);
1164 void amdgpu_ring_lockup_update(struct amdgpu_ring
*ring
);
1165 bool amdgpu_ring_test_lockup(struct amdgpu_ring
*ring
);
1166 unsigned amdgpu_ring_backup(struct amdgpu_ring
*ring
,
1168 int amdgpu_ring_restore(struct amdgpu_ring
*ring
,
1169 unsigned size
, uint32_t *data
);
1170 int amdgpu_ring_init(struct amdgpu_device
*adev
, struct amdgpu_ring
*ring
,
1171 unsigned ring_size
, u32 nop
, u32 align_mask
,
1172 struct amdgpu_irq_src
*irq_src
, unsigned irq_type
,
1173 enum amdgpu_ring_type ring_type
);
1174 void amdgpu_ring_fini(struct amdgpu_ring
*ring
);
1179 struct amdgpu_cs_chunk
{
1183 void __user
*user_ptr
;
1186 struct amdgpu_cs_parser
{
1187 struct amdgpu_device
*adev
;
1188 struct drm_file
*filp
;
1189 struct amdgpu_ctx
*ctx
;
1190 struct amdgpu_bo_list
*bo_list
;
1193 struct amdgpu_cs_chunk
*chunks
;
1195 struct amdgpu_bo_list_entry
*vm_bos
;
1196 struct list_head validated
;
1198 struct amdgpu_ib
*ibs
;
1201 struct ww_acquire_ctx ticket
;
1204 struct amdgpu_user_fence uf
;
1207 static inline u32
amdgpu_get_ib_value(struct amdgpu_cs_parser
*p
, uint32_t ib_idx
, int idx
)
1209 return p
->ibs
[ib_idx
].ptr
[idx
];
1215 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1218 struct amdgpu_bo
*wb_obj
;
1219 volatile uint32_t *wb
;
1221 u32 num_wb
; /* Number of wb slots actually reserved for amdgpu. */
1222 unsigned long used
[DIV_ROUND_UP(AMDGPU_MAX_WB
, BITS_PER_LONG
)];
1225 int amdgpu_wb_get(struct amdgpu_device
*adev
, u32
*wb
);
1226 void amdgpu_wb_free(struct amdgpu_device
*adev
, u32 wb
);
1229 * struct amdgpu_pm - power management datas
1230 * It keeps track of various data needed to take powermanagement decision.
1233 enum amdgpu_pm_state_type
{
1234 /* not used for dpm */
1235 POWER_STATE_TYPE_DEFAULT
,
1236 POWER_STATE_TYPE_POWERSAVE
,
1237 /* user selectable states */
1238 POWER_STATE_TYPE_BATTERY
,
1239 POWER_STATE_TYPE_BALANCED
,
1240 POWER_STATE_TYPE_PERFORMANCE
,
1241 /* internal states */
1242 POWER_STATE_TYPE_INTERNAL_UVD
,
1243 POWER_STATE_TYPE_INTERNAL_UVD_SD
,
1244 POWER_STATE_TYPE_INTERNAL_UVD_HD
,
1245 POWER_STATE_TYPE_INTERNAL_UVD_HD2
,
1246 POWER_STATE_TYPE_INTERNAL_UVD_MVC
,
1247 POWER_STATE_TYPE_INTERNAL_BOOT
,
1248 POWER_STATE_TYPE_INTERNAL_THERMAL
,
1249 POWER_STATE_TYPE_INTERNAL_ACPI
,
1250 POWER_STATE_TYPE_INTERNAL_ULV
,
1251 POWER_STATE_TYPE_INTERNAL_3DPERF
,
1254 enum amdgpu_int_thermal_type
{
1256 THERMAL_TYPE_EXTERNAL
,
1257 THERMAL_TYPE_EXTERNAL_GPIO
,
1260 THERMAL_TYPE_ADT7473_WITH_INTERNAL
,
1261 THERMAL_TYPE_EVERGREEN
,
1265 THERMAL_TYPE_EMC2103_WITH_INTERNAL
,
1270 enum amdgpu_dpm_auto_throttle_src
{
1271 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL
,
1272 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1275 enum amdgpu_dpm_event_src
{
1276 AMDGPU_DPM_EVENT_SRC_ANALOG
= 0,
1277 AMDGPU_DPM_EVENT_SRC_EXTERNAL
= 1,
1278 AMDGPU_DPM_EVENT_SRC_DIGITAL
= 2,
1279 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL
= 3,
1280 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL
= 4
1283 #define AMDGPU_MAX_VCE_LEVELS 6
1285 enum amdgpu_vce_level
{
1286 AMDGPU_VCE_LEVEL_AC_ALL
= 0, /* AC, All cases */
1287 AMDGPU_VCE_LEVEL_DC_EE
= 1, /* DC, entropy encoding */
1288 AMDGPU_VCE_LEVEL_DC_LL_LOW
= 2, /* DC, low latency queue, res <= 720 */
1289 AMDGPU_VCE_LEVEL_DC_LL_HIGH
= 3, /* DC, low latency queue, 1080 >= res > 720 */
1290 AMDGPU_VCE_LEVEL_DC_GP_LOW
= 4, /* DC, general purpose queue, res <= 720 */
1291 AMDGPU_VCE_LEVEL_DC_GP_HIGH
= 5, /* DC, general purpose queue, 1080 >= res > 720 */
1295 u32 caps
; /* vbios flags */
1296 u32
class; /* vbios flags */
1297 u32 class2
; /* vbios flags */
1305 enum amdgpu_vce_level vce_level
;
1310 struct amdgpu_dpm_thermal
{
1311 /* thermal interrupt work */
1312 struct work_struct work
;
1313 /* low temperature threshold */
1315 /* high temperature threshold */
1317 /* was last interrupt low to high or high to low */
1319 /* interrupt source */
1320 struct amdgpu_irq_src irq
;
1323 enum amdgpu_clk_action
1329 struct amdgpu_blacklist_clocks
1333 enum amdgpu_clk_action action
;
1336 struct amdgpu_clock_and_voltage_limits
{
1343 struct amdgpu_clock_array
{
1348 struct amdgpu_clock_voltage_dependency_entry
{
1353 struct amdgpu_clock_voltage_dependency_table
{
1355 struct amdgpu_clock_voltage_dependency_entry
*entries
;
1358 union amdgpu_cac_leakage_entry
{
1370 struct amdgpu_cac_leakage_table
{
1372 union amdgpu_cac_leakage_entry
*entries
;
1375 struct amdgpu_phase_shedding_limits_entry
{
1381 struct amdgpu_phase_shedding_limits_table
{
1383 struct amdgpu_phase_shedding_limits_entry
*entries
;
1386 struct amdgpu_uvd_clock_voltage_dependency_entry
{
1392 struct amdgpu_uvd_clock_voltage_dependency_table
{
1394 struct amdgpu_uvd_clock_voltage_dependency_entry
*entries
;
1397 struct amdgpu_vce_clock_voltage_dependency_entry
{
1403 struct amdgpu_vce_clock_voltage_dependency_table
{
1405 struct amdgpu_vce_clock_voltage_dependency_entry
*entries
;
1408 struct amdgpu_ppm_table
{
1410 u16 cpu_core_number
;
1412 u32 small_ac_platform_tdp
;
1414 u32 small_ac_platform_tdc
;
1421 struct amdgpu_cac_tdp_table
{
1423 u16 configurable_tdp
;
1425 u16 battery_power_limit
;
1426 u16 small_power_limit
;
1427 u16 low_cac_leakage
;
1428 u16 high_cac_leakage
;
1429 u16 maximum_power_delivery_limit
;
1432 struct amdgpu_dpm_dynamic_state
{
1433 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk
;
1434 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk
;
1435 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk
;
1436 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk
;
1437 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk
;
1438 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table
;
1439 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table
;
1440 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table
;
1441 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table
;
1442 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk
;
1443 struct amdgpu_clock_array valid_sclk_values
;
1444 struct amdgpu_clock_array valid_mclk_values
;
1445 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc
;
1446 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac
;
1447 u32 mclk_sclk_ratio
;
1448 u32 sclk_mclk_delta
;
1449 u16 vddc_vddci_delta
;
1450 u16 min_vddc_for_pcie_gen2
;
1451 struct amdgpu_cac_leakage_table cac_leakage_table
;
1452 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table
;
1453 struct amdgpu_ppm_table
*ppm_table
;
1454 struct amdgpu_cac_tdp_table
*cac_tdp_table
;
1457 struct amdgpu_dpm_fan
{
1468 u16 default_max_fan_pwm
;
1469 u16 default_fan_output_sensitivity
;
1470 u16 fan_output_sensitivity
;
1471 bool ucode_fan_control
;
1474 enum amdgpu_pcie_gen
{
1475 AMDGPU_PCIE_GEN1
= 0,
1476 AMDGPU_PCIE_GEN2
= 1,
1477 AMDGPU_PCIE_GEN3
= 2,
1478 AMDGPU_PCIE_GEN_INVALID
= 0xffff
1481 enum amdgpu_dpm_forced_level
{
1482 AMDGPU_DPM_FORCED_LEVEL_AUTO
= 0,
1483 AMDGPU_DPM_FORCED_LEVEL_LOW
= 1,
1484 AMDGPU_DPM_FORCED_LEVEL_HIGH
= 2,
1487 struct amdgpu_vce_state
{
1498 struct amdgpu_dpm_funcs
{
1499 int (*get_temperature
)(struct amdgpu_device
*adev
);
1500 int (*pre_set_power_state
)(struct amdgpu_device
*adev
);
1501 int (*set_power_state
)(struct amdgpu_device
*adev
);
1502 void (*post_set_power_state
)(struct amdgpu_device
*adev
);
1503 void (*display_configuration_changed
)(struct amdgpu_device
*adev
);
1504 u32 (*get_sclk
)(struct amdgpu_device
*adev
, bool low
);
1505 u32 (*get_mclk
)(struct amdgpu_device
*adev
, bool low
);
1506 void (*print_power_state
)(struct amdgpu_device
*adev
, struct amdgpu_ps
*ps
);
1507 void (*debugfs_print_current_performance_level
)(struct amdgpu_device
*adev
, struct seq_file
*m
);
1508 int (*force_performance_level
)(struct amdgpu_device
*adev
, enum amdgpu_dpm_forced_level level
);
1509 bool (*vblank_too_short
)(struct amdgpu_device
*adev
);
1510 void (*powergate_uvd
)(struct amdgpu_device
*adev
, bool gate
);
1511 void (*powergate_vce
)(struct amdgpu_device
*adev
, bool gate
);
1512 void (*enable_bapm
)(struct amdgpu_device
*adev
, bool enable
);
1513 void (*set_fan_control_mode
)(struct amdgpu_device
*adev
, u32 mode
);
1514 u32 (*get_fan_control_mode
)(struct amdgpu_device
*adev
);
1515 int (*set_fan_speed_percent
)(struct amdgpu_device
*adev
, u32 speed
);
1516 int (*get_fan_speed_percent
)(struct amdgpu_device
*adev
, u32
*speed
);
1520 struct amdgpu_ps
*ps
;
1521 /* number of valid power states */
1523 /* current power state that is active */
1524 struct amdgpu_ps
*current_ps
;
1525 /* requested power state */
1526 struct amdgpu_ps
*requested_ps
;
1527 /* boot up power state */
1528 struct amdgpu_ps
*boot_ps
;
1529 /* default uvd power state */
1530 struct amdgpu_ps
*uvd_ps
;
1531 /* vce requirements */
1532 struct amdgpu_vce_state vce_states
[AMDGPU_MAX_VCE_LEVELS
];
1533 enum amdgpu_vce_level vce_level
;
1534 enum amdgpu_pm_state_type state
;
1535 enum amdgpu_pm_state_type user_state
;
1537 u32 voltage_response_time
;
1538 u32 backbias_response_time
;
1540 u32 new_active_crtcs
;
1541 int new_active_crtc_count
;
1542 u32 current_active_crtcs
;
1543 int current_active_crtc_count
;
1544 struct amdgpu_dpm_dynamic_state dyn_state
;
1545 struct amdgpu_dpm_fan fan
;
1548 u32 near_tdp_limit_adjusted
;
1549 u32 sq_ramping_threshold
;
1553 u16 load_line_slope
;
1556 /* special states active */
1557 bool thermal_active
;
1560 /* thermal handling */
1561 struct amdgpu_dpm_thermal thermal
;
1563 enum amdgpu_dpm_forced_level forced_level
;
1572 struct amdgpu_i2c_chan
*i2c_bus
;
1573 /* internal thermal controller on rv6xx+ */
1574 enum amdgpu_int_thermal_type int_thermal_type
;
1575 struct device
*int_hwmon_dev
;
1576 /* fan control parameters */
1578 u8 fan_pulses_per_revolution
;
1583 struct amdgpu_dpm dpm
;
1584 const struct firmware
*fw
; /* SMC firmware */
1585 uint32_t fw_version
;
1586 const struct amdgpu_dpm_funcs
*funcs
;
1592 #define AMDGPU_MAX_UVD_HANDLES 10
1593 #define AMDGPU_UVD_STACK_SIZE (1024*1024)
1594 #define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1595 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1598 struct amdgpu_bo
*vcpu_bo
;
1602 atomic_t handles
[AMDGPU_MAX_UVD_HANDLES
];
1603 struct drm_file
*filp
[AMDGPU_MAX_UVD_HANDLES
];
1604 struct delayed_work idle_work
;
1605 const struct firmware
*fw
; /* UVD firmware */
1606 struct amdgpu_ring ring
;
1607 struct amdgpu_irq_src irq
;
1608 bool address_64_bit
;
1614 #define AMDGPU_MAX_VCE_HANDLES 16
1615 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1617 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1618 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1621 struct amdgpu_bo
*vcpu_bo
;
1623 unsigned fw_version
;
1624 unsigned fb_version
;
1625 atomic_t handles
[AMDGPU_MAX_VCE_HANDLES
];
1626 struct drm_file
*filp
[AMDGPU_MAX_VCE_HANDLES
];
1627 uint32_t img_size
[AMDGPU_MAX_VCE_HANDLES
];
1628 struct delayed_work idle_work
;
1629 const struct firmware
*fw
; /* VCE firmware */
1630 struct amdgpu_ring ring
[AMDGPU_MAX_VCE_RINGS
];
1631 struct amdgpu_irq_src irq
;
1632 unsigned harvest_config
;
1638 struct amdgpu_sdma
{
1640 const struct firmware
*fw
;
1641 uint32_t fw_version
;
1643 struct amdgpu_ring ring
;
1649 struct amdgpu_firmware
{
1650 struct amdgpu_firmware_info ucode
[AMDGPU_UCODE_ID_MAXIMUM
];
1652 struct amdgpu_bo
*fw_buf
;
1653 unsigned int fw_size
;
1659 void amdgpu_benchmark(struct amdgpu_device
*adev
, int test_number
);
1665 void amdgpu_test_moves(struct amdgpu_device
*adev
);
1666 void amdgpu_test_ring_sync(struct amdgpu_device
*adev
,
1667 struct amdgpu_ring
*cpA
,
1668 struct amdgpu_ring
*cpB
);
1669 void amdgpu_test_syncing(struct amdgpu_device
*adev
);
1674 #if defined(CONFIG_MMU_NOTIFIER)
1675 int amdgpu_mn_register(struct amdgpu_bo
*bo
, unsigned long addr
);
1676 void amdgpu_mn_unregister(struct amdgpu_bo
*bo
);
1678 static int amdgpu_mn_register(struct amdgpu_bo
*bo
, unsigned long addr
)
1682 static void amdgpu_mn_unregister(struct amdgpu_bo
*bo
) {}
1688 struct amdgpu_debugfs
{
1689 struct drm_info_list
*files
;
1693 int amdgpu_debugfs_add_files(struct amdgpu_device
*adev
,
1694 struct drm_info_list
*files
,
1696 int amdgpu_debugfs_fence_init(struct amdgpu_device
*adev
);
1698 #if defined(CONFIG_DEBUG_FS)
1699 int amdgpu_debugfs_init(struct drm_minor
*minor
);
1700 void amdgpu_debugfs_cleanup(struct drm_minor
*minor
);
1704 * amdgpu smumgr functions
1706 struct amdgpu_smumgr_funcs
{
1707 int (*check_fw_load_finish
)(struct amdgpu_device
*adev
, uint32_t fwtype
);
1708 int (*request_smu_load_fw
)(struct amdgpu_device
*adev
);
1709 int (*request_smu_specific_fw
)(struct amdgpu_device
*adev
, uint32_t fwtype
);
1715 struct amdgpu_smumgr
{
1716 struct amdgpu_bo
*toc_buf
;
1717 struct amdgpu_bo
*smu_buf
;
1718 /* asic priv smu data */
1720 spinlock_t smu_lock
;
1721 /* smumgr functions */
1722 const struct amdgpu_smumgr_funcs
*smumgr_funcs
;
1723 /* ucode loading complete flag */
1728 * ASIC specific register table accessible by UMD
1730 struct amdgpu_allowed_register_entry
{
1731 uint32_t reg_offset
;
1736 struct amdgpu_cu_info
{
1737 uint32_t number
; /* total active CU number */
1738 uint32_t ao_cu_mask
;
1739 uint32_t bitmap
[4][4];
1744 * ASIC specific functions.
1746 struct amdgpu_asic_funcs
{
1747 bool (*read_disabled_bios
)(struct amdgpu_device
*adev
);
1748 int (*read_register
)(struct amdgpu_device
*adev
, u32 se_num
,
1749 u32 sh_num
, u32 reg_offset
, u32
*value
);
1750 void (*set_vga_state
)(struct amdgpu_device
*adev
, bool state
);
1751 int (*reset
)(struct amdgpu_device
*adev
);
1752 /* wait for mc_idle */
1753 int (*wait_for_mc_idle
)(struct amdgpu_device
*adev
);
1754 /* get the reference clock */
1755 u32 (*get_xclk
)(struct amdgpu_device
*adev
);
1756 /* get the gpu clock counter */
1757 uint64_t (*get_gpu_clock_counter
)(struct amdgpu_device
*adev
);
1758 int (*get_cu_info
)(struct amdgpu_device
*adev
, struct amdgpu_cu_info
*info
);
1759 /* MM block clocks */
1760 int (*set_uvd_clocks
)(struct amdgpu_device
*adev
, u32 vclk
, u32 dclk
);
1761 int (*set_vce_clocks
)(struct amdgpu_device
*adev
, u32 evclk
, u32 ecclk
);
1767 int amdgpu_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1768 struct drm_file
*filp
);
1769 int amdgpu_bo_list_ioctl(struct drm_device
*dev
, void *data
,
1770 struct drm_file
*filp
);
1772 int amdgpu_gem_info_ioctl(struct drm_device
*dev
, void *data
,
1773 struct drm_file
*filp
);
1774 int amdgpu_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
1775 struct drm_file
*filp
);
1776 int amdgpu_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1777 struct drm_file
*filp
);
1778 int amdgpu_gem_wait_idle_ioctl(struct drm_device
*dev
, void *data
,
1779 struct drm_file
*filp
);
1780 int amdgpu_gem_va_ioctl(struct drm_device
*dev
, void *data
,
1781 struct drm_file
*filp
);
1782 int amdgpu_gem_op_ioctl(struct drm_device
*dev
, void *data
,
1783 struct drm_file
*filp
);
1784 int amdgpu_cs_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
1785 int amdgpu_cs_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
1787 int amdgpu_gem_metadata_ioctl(struct drm_device
*dev
, void *data
,
1788 struct drm_file
*filp
);
1790 /* VRAM scratch page for HDP bug, default vram page */
1791 struct amdgpu_vram_scratch
{
1792 struct amdgpu_bo
*robj
;
1793 volatile uint32_t *ptr
;
1800 struct amdgpu_atif_notification_cfg
{
1805 struct amdgpu_atif_notifications
{
1806 bool display_switch
;
1807 bool expansion_mode_change
;
1809 bool forced_power_state
;
1810 bool system_power_state
;
1811 bool display_conf_change
;
1813 bool brightness_change
;
1814 bool dgpu_display_event
;
1817 struct amdgpu_atif_functions
{
1819 bool sbios_requests
;
1820 bool select_active_disp
;
1822 bool get_tv_standard
;
1823 bool set_tv_standard
;
1824 bool get_panel_expansion_mode
;
1825 bool set_panel_expansion_mode
;
1826 bool temperature_change
;
1827 bool graphics_device_types
;
1830 struct amdgpu_atif
{
1831 struct amdgpu_atif_notifications notifications
;
1832 struct amdgpu_atif_functions functions
;
1833 struct amdgpu_atif_notification_cfg notification_cfg
;
1834 struct amdgpu_encoder
*encoder_for_bl
;
1837 struct amdgpu_atcs_functions
{
1841 bool pcie_bus_width
;
1844 struct amdgpu_atcs
{
1845 struct amdgpu_atcs_functions functions
;
1848 int amdgpu_ctx_alloc(struct amdgpu_device
*adev
,struct amdgpu_fpriv
*fpriv
,
1849 uint32_t *id
,uint32_t flags
);
1850 int amdgpu_ctx_free(struct amdgpu_device
*adev
, struct amdgpu_fpriv
*fpriv
,
1853 void amdgpu_ctx_fini(struct amdgpu_fpriv
*fpriv
);
1854 struct amdgpu_ctx
*amdgpu_ctx_get(struct amdgpu_fpriv
*fpriv
, uint32_t id
);
1855 int amdgpu_ctx_put(struct amdgpu_ctx
*ctx
);
1857 extern int amdgpu_ctx_ioctl(struct drm_device
*dev
, void *data
,
1858 struct drm_file
*filp
);
1861 * Core structure, functions and helpers.
1863 typedef uint32_t (*amdgpu_rreg_t
)(struct amdgpu_device
*, uint32_t);
1864 typedef void (*amdgpu_wreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t);
1866 typedef uint32_t (*amdgpu_block_rreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t);
1867 typedef void (*amdgpu_block_wreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t, uint32_t);
1869 struct amdgpu_ip_block_status
{
1875 struct amdgpu_device
{
1877 struct drm_device
*ddev
;
1878 struct pci_dev
*pdev
;
1879 struct rw_semaphore exclusive_lock
;
1882 enum amdgpu_asic_type asic_type
;
1885 uint32_t external_rev_id
;
1886 unsigned long flags
;
1888 const struct amdgpu_asic_funcs
*asic_funcs
;
1894 struct work_struct reset_work
;
1895 struct notifier_block acpi_nb
;
1896 struct amdgpu_i2c_chan
*i2c_bus
[AMDGPU_MAX_I2C_BUS
];
1897 struct amdgpu_debugfs debugfs
[AMDGPU_DEBUGFS_MAX_COMPONENTS
];
1898 unsigned debugfs_count
;
1899 #if defined(CONFIG_DEBUG_FS)
1900 struct dentry
*debugfs_regs
;
1902 struct amdgpu_atif atif
;
1903 struct amdgpu_atcs atcs
;
1904 struct mutex srbm_mutex
;
1905 /* GRBM index mutex. Protects concurrent access to GRBM index */
1906 struct mutex grbm_idx_mutex
;
1907 struct dev_pm_domain vga_pm_domain
;
1908 bool have_disp_power_ref
;
1913 uint16_t bios_header_start
;
1914 struct amdgpu_bo
*stollen_vga_memory
;
1915 uint32_t bios_scratch
[AMDGPU_BIOS_NUM_SCRATCH
];
1917 /* Register/doorbell mmio */
1918 resource_size_t rmmio_base
;
1919 resource_size_t rmmio_size
;
1920 void __iomem
*rmmio
;
1921 /* protects concurrent MM_INDEX/DATA based register access */
1922 spinlock_t mmio_idx_lock
;
1923 /* protects concurrent SMC based register access */
1924 spinlock_t smc_idx_lock
;
1925 amdgpu_rreg_t smc_rreg
;
1926 amdgpu_wreg_t smc_wreg
;
1927 /* protects concurrent PCIE register access */
1928 spinlock_t pcie_idx_lock
;
1929 amdgpu_rreg_t pcie_rreg
;
1930 amdgpu_wreg_t pcie_wreg
;
1931 /* protects concurrent UVD register access */
1932 spinlock_t uvd_ctx_idx_lock
;
1933 amdgpu_rreg_t uvd_ctx_rreg
;
1934 amdgpu_wreg_t uvd_ctx_wreg
;
1935 /* protects concurrent DIDT register access */
1936 spinlock_t didt_idx_lock
;
1937 amdgpu_rreg_t didt_rreg
;
1938 amdgpu_wreg_t didt_wreg
;
1939 /* protects concurrent ENDPOINT (audio) register access */
1940 spinlock_t audio_endpt_idx_lock
;
1941 amdgpu_block_rreg_t audio_endpt_rreg
;
1942 amdgpu_block_wreg_t audio_endpt_wreg
;
1943 void __iomem
*rio_mem
;
1944 resource_size_t rio_mem_size
;
1945 struct amdgpu_doorbell doorbell
;
1947 /* clock/pll info */
1948 struct amdgpu_clock clock
;
1951 struct amdgpu_mc mc
;
1952 struct amdgpu_gart gart
;
1953 struct amdgpu_dummy_page dummy_page
;
1954 struct amdgpu_vm_manager vm_manager
;
1956 /* memory management */
1957 struct amdgpu_mman mman
;
1958 struct amdgpu_gem gem
;
1959 struct amdgpu_vram_scratch vram_scratch
;
1960 struct amdgpu_wb wb
;
1961 atomic64_t vram_usage
;
1962 atomic64_t vram_vis_usage
;
1963 atomic64_t gtt_usage
;
1964 atomic64_t num_bytes_moved
;
1965 atomic_t gpu_reset_counter
;
1968 struct amdgpu_mode_info mode_info
;
1969 struct work_struct hotplug_work
;
1970 struct amdgpu_irq_src crtc_irq
;
1971 struct amdgpu_irq_src pageflip_irq
;
1972 struct amdgpu_irq_src hpd_irq
;
1975 wait_queue_head_t fence_queue
;
1976 unsigned fence_context
;
1977 struct mutex ring_lock
;
1979 struct amdgpu_ring
*rings
[AMDGPU_MAX_RINGS
];
1981 struct amdgpu_sa_manager ring_tmp_bo
;
1984 struct amdgpu_irq irq
;
1987 struct amdgpu_pm pm
;
1992 struct amdgpu_smumgr smu
;
1995 struct amdgpu_gfx gfx
;
1998 struct amdgpu_sdma sdma
[2];
1999 struct amdgpu_irq_src sdma_trap_irq
;
2000 struct amdgpu_irq_src sdma_illegal_inst_irq
;
2004 struct amdgpu_uvd uvd
;
2007 struct amdgpu_vce vce
;
2010 struct amdgpu_firmware firmware
;
2013 struct amdgpu_gds gds
;
2015 const struct amdgpu_ip_block_version
*ip_blocks
;
2017 struct amdgpu_ip_block_status
*ip_block_status
;
2018 struct mutex mn_lock
;
2019 DECLARE_HASHTABLE(mn_hash
, 7);
2021 /* tracking pinned memory */
2026 bool amdgpu_device_is_px(struct drm_device
*dev
);
2027 int amdgpu_device_init(struct amdgpu_device
*adev
,
2028 struct drm_device
*ddev
,
2029 struct pci_dev
*pdev
,
2031 void amdgpu_device_fini(struct amdgpu_device
*adev
);
2032 int amdgpu_gpu_wait_for_idle(struct amdgpu_device
*adev
);
2034 uint32_t amdgpu_mm_rreg(struct amdgpu_device
*adev
, uint32_t reg
,
2035 bool always_indirect
);
2036 void amdgpu_mm_wreg(struct amdgpu_device
*adev
, uint32_t reg
, uint32_t v
,
2037 bool always_indirect
);
2038 u32
amdgpu_io_rreg(struct amdgpu_device
*adev
, u32 reg
);
2039 void amdgpu_io_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
);
2041 u32
amdgpu_mm_rdoorbell(struct amdgpu_device
*adev
, u32 index
);
2042 void amdgpu_mm_wdoorbell(struct amdgpu_device
*adev
, u32 index
, u32 v
);
2047 extern const struct fence_ops amdgpu_fence_ops
;
2048 static inline struct amdgpu_fence
*to_amdgpu_fence(struct fence
*f
)
2050 struct amdgpu_fence
*__f
= container_of(f
, struct amdgpu_fence
, base
);
2052 if (__f
->base
.ops
== &amdgpu_fence_ops
)
2059 * Registers read & write functions.
2061 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2062 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2063 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2064 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2065 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2066 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2067 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2068 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2069 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2070 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2071 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2072 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2073 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2074 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2075 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2076 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2077 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2078 #define WREG32_P(reg, val, mask) \
2080 uint32_t tmp_ = RREG32(reg); \
2082 tmp_ |= ((val) & ~(mask)); \
2083 WREG32(reg, tmp_); \
2085 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2086 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2087 #define WREG32_PLL_P(reg, val, mask) \
2089 uint32_t tmp_ = RREG32_PLL(reg); \
2091 tmp_ |= ((val) & ~(mask)); \
2092 WREG32_PLL(reg, tmp_); \
2094 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2095 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2096 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2098 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2099 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2101 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2102 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2104 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2105 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2106 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2108 #define REG_GET_FIELD(value, reg, field) \
2109 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2114 #define RBIOS8(i) (adev->bios[i])
2115 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2116 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2121 static inline void amdgpu_ring_write(struct amdgpu_ring
*ring
, uint32_t v
)
2123 if (ring
->count_dw
<= 0)
2124 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2125 ring
->ring
[ring
->wptr
++] = v
;
2126 ring
->wptr
&= ring
->ptr_mask
;
2128 ring
->ring_free_dw
--;
2134 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2135 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2136 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2137 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2138 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2139 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2140 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2141 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2142 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2143 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2144 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2145 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2146 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2147 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2148 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2149 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2150 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2151 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2152 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2153 #define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r))
2154 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2155 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2156 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2157 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2158 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2159 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2160 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2161 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2162 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2163 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2164 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2165 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2166 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2167 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2168 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2169 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2170 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2171 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2172 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2173 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2174 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2175 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2176 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2177 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2178 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2179 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2180 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2181 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2182 #define amdgpu_emit_copy_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((r), (s), (d), (b))
2183 #define amdgpu_emit_fill_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((r), (s), (d), (b))
2184 #define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev))
2185 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2186 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2187 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2188 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2189 #define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l))
2190 #define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l))
2191 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2192 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
2193 #define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
2194 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2195 #define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
2196 #define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g))
2197 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2198 #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
2199 #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
2200 #define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
2201 #define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
2203 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2205 /* Common functions */
2206 int amdgpu_gpu_reset(struct amdgpu_device
*adev
);
2207 void amdgpu_pci_config_reset(struct amdgpu_device
*adev
);
2208 bool amdgpu_card_posted(struct amdgpu_device
*adev
);
2209 void amdgpu_update_display_priority(struct amdgpu_device
*adev
);
2210 bool amdgpu_boot_test_post_card(struct amdgpu_device
*adev
);
2211 int amdgpu_cs_parser_init(struct amdgpu_cs_parser
*p
, void *data
);
2212 int amdgpu_cs_get_ring(struct amdgpu_device
*adev
, u32 ip_type
,
2213 u32 ip_instance
, u32 ring
,
2214 struct amdgpu_ring
**out_ring
);
2215 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo
*rbo
, u32 domain
);
2216 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object
*bo
);
2217 int amdgpu_ttm_tt_set_userptr(struct ttm_tt
*ttm
, uint64_t addr
,
2219 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt
*ttm
);
2220 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt
*ttm
);
2221 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device
*adev
, struct ttm_tt
*ttm
,
2222 struct ttm_mem_reg
*mem
);
2223 void amdgpu_vram_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
, u64 base
);
2224 void amdgpu_gtt_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
);
2225 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device
*adev
, u64 size
);
2226 void amdgpu_program_register_sequence(struct amdgpu_device
*adev
,
2227 const u32
*registers
,
2228 const u32 array_size
);
2230 bool amdgpu_device_is_px(struct drm_device
*dev
);
2232 #if defined(CONFIG_VGA_SWITCHEROO)
2233 void amdgpu_register_atpx_handler(void);
2234 void amdgpu_unregister_atpx_handler(void);
2236 static inline void amdgpu_register_atpx_handler(void) {}
2237 static inline void amdgpu_unregister_atpx_handler(void) {}
2243 extern const struct drm_ioctl_desc amdgpu_ioctls_kms
[];
2244 extern int amdgpu_max_kms_ioctl
;
2246 int amdgpu_driver_load_kms(struct drm_device
*dev
, unsigned long flags
);
2247 int amdgpu_driver_unload_kms(struct drm_device
*dev
);
2248 void amdgpu_driver_lastclose_kms(struct drm_device
*dev
);
2249 int amdgpu_driver_open_kms(struct drm_device
*dev
, struct drm_file
*file_priv
);
2250 void amdgpu_driver_postclose_kms(struct drm_device
*dev
,
2251 struct drm_file
*file_priv
);
2252 void amdgpu_driver_preclose_kms(struct drm_device
*dev
,
2253 struct drm_file
*file_priv
);
2254 int amdgpu_suspend_kms(struct drm_device
*dev
, bool suspend
, bool fbcon
);
2255 int amdgpu_resume_kms(struct drm_device
*dev
, bool resume
, bool fbcon
);
2256 u32
amdgpu_get_vblank_counter_kms(struct drm_device
*dev
, int crtc
);
2257 int amdgpu_enable_vblank_kms(struct drm_device
*dev
, int crtc
);
2258 void amdgpu_disable_vblank_kms(struct drm_device
*dev
, int crtc
);
2259 int amdgpu_get_vblank_timestamp_kms(struct drm_device
*dev
, int crtc
,
2261 struct timeval
*vblank_time
,
2263 long amdgpu_kms_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2269 int amdgpu_vm_init(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
);
2270 void amdgpu_vm_fini(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
);
2271 struct amdgpu_bo_list_entry
*amdgpu_vm_get_bos(struct amdgpu_device
*adev
,
2272 struct amdgpu_vm
*vm
,
2273 struct list_head
*head
);
2274 struct amdgpu_fence
*amdgpu_vm_grab_id(struct amdgpu_ring
*ring
,
2275 struct amdgpu_vm
*vm
);
2276 void amdgpu_vm_flush(struct amdgpu_ring
*ring
,
2277 struct amdgpu_vm
*vm
,
2278 struct amdgpu_fence
*updates
);
2279 void amdgpu_vm_fence(struct amdgpu_device
*adev
,
2280 struct amdgpu_vm
*vm
,
2281 struct amdgpu_fence
*fence
);
2282 uint64_t amdgpu_vm_map_gart(struct amdgpu_device
*adev
, uint64_t addr
);
2283 int amdgpu_vm_update_page_directory(struct amdgpu_device
*adev
,
2284 struct amdgpu_vm
*vm
);
2285 int amdgpu_vm_clear_freed(struct amdgpu_device
*adev
,
2286 struct amdgpu_vm
*vm
);
2287 int amdgpu_vm_clear_invalids(struct amdgpu_device
*adev
,
2288 struct amdgpu_vm
*vm
, struct amdgpu_sync
*sync
);
2289 int amdgpu_vm_bo_update(struct amdgpu_device
*adev
,
2290 struct amdgpu_bo_va
*bo_va
,
2291 struct ttm_mem_reg
*mem
);
2292 void amdgpu_vm_bo_invalidate(struct amdgpu_device
*adev
,
2293 struct amdgpu_bo
*bo
);
2294 struct amdgpu_bo_va
*amdgpu_vm_bo_find(struct amdgpu_vm
*vm
,
2295 struct amdgpu_bo
*bo
);
2296 struct amdgpu_bo_va
*amdgpu_vm_bo_add(struct amdgpu_device
*adev
,
2297 struct amdgpu_vm
*vm
,
2298 struct amdgpu_bo
*bo
);
2299 int amdgpu_vm_bo_map(struct amdgpu_device
*adev
,
2300 struct amdgpu_bo_va
*bo_va
,
2301 uint64_t addr
, uint64_t offset
,
2302 uint64_t size
, uint32_t flags
);
2303 int amdgpu_vm_bo_unmap(struct amdgpu_device
*adev
,
2304 struct amdgpu_bo_va
*bo_va
,
2306 void amdgpu_vm_bo_rmv(struct amdgpu_device
*adev
,
2307 struct amdgpu_bo_va
*bo_va
);
2310 * functions used by amdgpu_encoder.c
2312 struct amdgpu_afmt_acr
{
2326 struct amdgpu_afmt_acr
amdgpu_afmt_acr(uint32_t clock
);
2329 #if defined(CONFIG_ACPI)
2330 int amdgpu_acpi_init(struct amdgpu_device
*adev
);
2331 void amdgpu_acpi_fini(struct amdgpu_device
*adev
);
2332 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device
*adev
);
2333 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device
*adev
,
2334 u8 perf_req
, bool advertise
);
2335 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device
*adev
);
2337 static inline int amdgpu_acpi_init(struct amdgpu_device
*adev
) { return 0; }
2338 static inline void amdgpu_acpi_fini(struct amdgpu_device
*adev
) { }
2341 struct amdgpu_bo_va_mapping
*
2342 amdgpu_cs_find_mapping(struct amdgpu_cs_parser
*parser
,
2343 uint64_t addr
, struct amdgpu_bo
**bo
);
2345 #include "amdgpu_object.h"