2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_gds.h"
56 #include "gpu_scheduler.h"
61 extern int amdgpu_modeset
;
62 extern int amdgpu_vram_limit
;
63 extern int amdgpu_gart_size
;
64 extern int amdgpu_benchmarking
;
65 extern int amdgpu_testing
;
66 extern int amdgpu_audio
;
67 extern int amdgpu_disp_priority
;
68 extern int amdgpu_hw_i2c
;
69 extern int amdgpu_pcie_gen2
;
70 extern int amdgpu_msi
;
71 extern int amdgpu_lockup_timeout
;
72 extern int amdgpu_dpm
;
73 extern int amdgpu_smc_load_fw
;
74 extern int amdgpu_aspm
;
75 extern int amdgpu_runtime_pm
;
76 extern int amdgpu_hard_reset
;
77 extern unsigned amdgpu_ip_block_mask
;
78 extern int amdgpu_bapm
;
79 extern int amdgpu_deep_color
;
80 extern int amdgpu_vm_size
;
81 extern int amdgpu_vm_block_size
;
82 extern int amdgpu_vm_fault_stop
;
83 extern int amdgpu_vm_debug
;
84 extern int amdgpu_enable_scheduler
;
85 extern int amdgpu_sched_jobs
;
86 extern int amdgpu_sched_hw_submission
;
87 extern int amdgpu_enable_semaphores
;
89 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
90 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
91 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
92 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
93 #define AMDGPU_IB_POOL_SIZE 16
94 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
95 #define AMDGPUFB_CONN_LIMIT 4
96 #define AMDGPU_BIOS_NUM_SCRATCH 8
98 /* max number of rings */
99 #define AMDGPU_MAX_RINGS 16
100 #define AMDGPU_MAX_GFX_RINGS 1
101 #define AMDGPU_MAX_COMPUTE_RINGS 8
102 #define AMDGPU_MAX_VCE_RINGS 2
104 /* max number of IP instances */
105 #define AMDGPU_MAX_SDMA_INSTANCES 2
107 /* number of hw syncs before falling back on blocking */
108 #define AMDGPU_NUM_SYNCS 4
110 /* hardcode that limit for now */
111 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
113 /* hard reset data */
114 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
117 #define AMDGPU_RESET_GFX (1 << 0)
118 #define AMDGPU_RESET_COMPUTE (1 << 1)
119 #define AMDGPU_RESET_DMA (1 << 2)
120 #define AMDGPU_RESET_CP (1 << 3)
121 #define AMDGPU_RESET_GRBM (1 << 4)
122 #define AMDGPU_RESET_DMA1 (1 << 5)
123 #define AMDGPU_RESET_RLC (1 << 6)
124 #define AMDGPU_RESET_SEM (1 << 7)
125 #define AMDGPU_RESET_IH (1 << 8)
126 #define AMDGPU_RESET_VMC (1 << 9)
127 #define AMDGPU_RESET_MC (1 << 10)
128 #define AMDGPU_RESET_DISPLAY (1 << 11)
129 #define AMDGPU_RESET_UVD (1 << 12)
130 #define AMDGPU_RESET_VCE (1 << 13)
131 #define AMDGPU_RESET_VCE1 (1 << 14)
134 #define AMDGPU_CG_BLOCK_GFX (1 << 0)
135 #define AMDGPU_CG_BLOCK_MC (1 << 1)
136 #define AMDGPU_CG_BLOCK_SDMA (1 << 2)
137 #define AMDGPU_CG_BLOCK_UVD (1 << 3)
138 #define AMDGPU_CG_BLOCK_VCE (1 << 4)
139 #define AMDGPU_CG_BLOCK_HDP (1 << 5)
140 #define AMDGPU_CG_BLOCK_BIF (1 << 6)
143 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
144 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
145 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
146 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
147 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
148 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
149 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
150 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
151 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
152 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
153 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
154 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
155 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
156 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
157 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
158 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
159 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
162 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
163 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
164 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
165 #define AMDGPU_PG_SUPPORT_UVD (1 << 3)
166 #define AMDGPU_PG_SUPPORT_VCE (1 << 4)
167 #define AMDGPU_PG_SUPPORT_CP (1 << 5)
168 #define AMDGPU_PG_SUPPORT_GDS (1 << 6)
169 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
170 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
171 #define AMDGPU_PG_SUPPORT_ACP (1 << 9)
172 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
174 /* GFX current status */
175 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
176 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
177 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
178 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
179 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
181 /* max cursor sizes (in pixels) */
182 #define CIK_CURSOR_WIDTH 128
183 #define CIK_CURSOR_HEIGHT 128
185 struct amdgpu_device
;
190 struct amdgpu_semaphore
;
191 struct amdgpu_cs_parser
;
193 struct amdgpu_irq_src
;
197 AMDGPU_CP_IRQ_GFX_EOP
= 0,
198 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
,
199 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP
,
200 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP
,
201 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP
,
202 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP
,
203 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP
,
204 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP
,
205 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP
,
210 enum amdgpu_sdma_irq
{
211 AMDGPU_SDMA_IRQ_TRAP0
= 0,
212 AMDGPU_SDMA_IRQ_TRAP1
,
217 enum amdgpu_thermal_irq
{
218 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH
= 0,
219 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW
,
221 AMDGPU_THERMAL_IRQ_LAST
224 int amdgpu_set_clockgating_state(struct amdgpu_device
*adev
,
225 enum amd_ip_block_type block_type
,
226 enum amd_clockgating_state state
);
227 int amdgpu_set_powergating_state(struct amdgpu_device
*adev
,
228 enum amd_ip_block_type block_type
,
229 enum amd_powergating_state state
);
231 struct amdgpu_ip_block_version
{
232 enum amd_ip_block_type type
;
236 const struct amd_ip_funcs
*funcs
;
239 int amdgpu_ip_block_version_cmp(struct amdgpu_device
*adev
,
240 enum amd_ip_block_type type
,
241 u32 major
, u32 minor
);
243 const struct amdgpu_ip_block_version
* amdgpu_get_ip_block(
244 struct amdgpu_device
*adev
,
245 enum amd_ip_block_type type
);
247 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
248 struct amdgpu_buffer_funcs
{
249 /* maximum bytes in a single operation */
250 uint32_t copy_max_bytes
;
252 /* number of dw to reserve per operation */
253 unsigned copy_num_dw
;
255 /* used for buffer migration */
256 void (*emit_copy_buffer
)(struct amdgpu_ib
*ib
,
257 /* src addr in bytes */
259 /* dst addr in bytes */
261 /* number of byte to transfer */
262 uint32_t byte_count
);
264 /* maximum bytes in a single operation */
265 uint32_t fill_max_bytes
;
267 /* number of dw to reserve per operation */
268 unsigned fill_num_dw
;
270 /* used for buffer clearing */
271 void (*emit_fill_buffer
)(struct amdgpu_ib
*ib
,
272 /* value to write to memory */
274 /* dst addr in bytes */
276 /* number of byte to fill */
277 uint32_t byte_count
);
280 /* provided by hw blocks that can write ptes, e.g., sdma */
281 struct amdgpu_vm_pte_funcs
{
282 /* copy pte entries from GART */
283 void (*copy_pte
)(struct amdgpu_ib
*ib
,
284 uint64_t pe
, uint64_t src
,
286 /* write pte one entry at a time with addr mapping */
287 void (*write_pte
)(struct amdgpu_ib
*ib
,
289 uint64_t addr
, unsigned count
,
290 uint32_t incr
, uint32_t flags
);
291 /* for linear pte/pde updates without addr mapping */
292 void (*set_pte_pde
)(struct amdgpu_ib
*ib
,
294 uint64_t addr
, unsigned count
,
295 uint32_t incr
, uint32_t flags
);
296 /* pad the indirect buffer to the necessary number of dw */
297 void (*pad_ib
)(struct amdgpu_ib
*ib
);
300 /* provided by the gmc block */
301 struct amdgpu_gart_funcs
{
302 /* flush the vm tlb via mmio */
303 void (*flush_gpu_tlb
)(struct amdgpu_device
*adev
,
305 /* write pte/pde updates using the cpu */
306 int (*set_pte_pde
)(struct amdgpu_device
*adev
,
307 void *cpu_pt_addr
, /* cpu addr of page table */
308 uint32_t gpu_page_idx
, /* pte/pde to update */
309 uint64_t addr
, /* addr to write into pte/pde */
310 uint32_t flags
); /* access flags */
313 /* provided by the ih block */
314 struct amdgpu_ih_funcs
{
315 /* ring read/write ptr handling, called from interrupt context */
316 u32 (*get_wptr
)(struct amdgpu_device
*adev
);
317 void (*decode_iv
)(struct amdgpu_device
*adev
,
318 struct amdgpu_iv_entry
*entry
);
319 void (*set_rptr
)(struct amdgpu_device
*adev
);
322 /* provided by hw blocks that expose a ring buffer for commands */
323 struct amdgpu_ring_funcs
{
324 /* ring read/write ptr handling */
325 u32 (*get_rptr
)(struct amdgpu_ring
*ring
);
326 u32 (*get_wptr
)(struct amdgpu_ring
*ring
);
327 void (*set_wptr
)(struct amdgpu_ring
*ring
);
328 /* validating and patching of IBs */
329 int (*parse_cs
)(struct amdgpu_cs_parser
*p
, uint32_t ib_idx
);
330 /* command emit functions */
331 void (*emit_ib
)(struct amdgpu_ring
*ring
,
332 struct amdgpu_ib
*ib
);
333 void (*emit_fence
)(struct amdgpu_ring
*ring
, uint64_t addr
,
334 uint64_t seq
, unsigned flags
);
335 bool (*emit_semaphore
)(struct amdgpu_ring
*ring
,
336 struct amdgpu_semaphore
*semaphore
,
338 void (*emit_vm_flush
)(struct amdgpu_ring
*ring
, unsigned vm_id
,
340 void (*emit_hdp_flush
)(struct amdgpu_ring
*ring
);
341 void (*emit_gds_switch
)(struct amdgpu_ring
*ring
, uint32_t vmid
,
342 uint32_t gds_base
, uint32_t gds_size
,
343 uint32_t gws_base
, uint32_t gws_size
,
344 uint32_t oa_base
, uint32_t oa_size
);
345 /* testing functions */
346 int (*test_ring
)(struct amdgpu_ring
*ring
);
347 int (*test_ib
)(struct amdgpu_ring
*ring
);
348 /* insert NOP packets */
349 void (*insert_nop
)(struct amdgpu_ring
*ring
, uint32_t count
);
355 bool amdgpu_get_bios(struct amdgpu_device
*adev
);
356 bool amdgpu_read_bios(struct amdgpu_device
*adev
);
361 struct amdgpu_dummy_page
{
365 int amdgpu_dummy_page_init(struct amdgpu_device
*adev
);
366 void amdgpu_dummy_page_fini(struct amdgpu_device
*adev
);
373 #define AMDGPU_MAX_PPLL 3
375 struct amdgpu_clock
{
376 struct amdgpu_pll ppll
[AMDGPU_MAX_PPLL
];
377 struct amdgpu_pll spll
;
378 struct amdgpu_pll mpll
;
380 uint32_t default_mclk
;
381 uint32_t default_sclk
;
382 uint32_t default_dispclk
;
383 uint32_t current_dispclk
;
385 uint32_t max_pixel_clock
;
391 struct amdgpu_fence_driver
{
393 volatile uint32_t *cpu_addr
;
394 /* sync_seq is protected by ring emission lock */
395 uint64_t sync_seq
[AMDGPU_MAX_RINGS
];
398 struct amdgpu_irq_src
*irq_src
;
400 struct timer_list fallback_timer
;
401 wait_queue_head_t fence_queue
;
404 /* some special values for the owner field */
405 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
406 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
408 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
409 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
411 struct amdgpu_fence
{
415 struct amdgpu_ring
*ring
;
418 /* filp or special value for fence creator */
421 wait_queue_t fence_wake
;
424 struct amdgpu_user_fence
{
426 struct amdgpu_bo
*bo
;
427 /* write-back address offset to bo start */
431 int amdgpu_fence_driver_init(struct amdgpu_device
*adev
);
432 void amdgpu_fence_driver_fini(struct amdgpu_device
*adev
);
433 void amdgpu_fence_driver_force_completion(struct amdgpu_device
*adev
);
435 int amdgpu_fence_driver_init_ring(struct amdgpu_ring
*ring
);
436 int amdgpu_fence_driver_start_ring(struct amdgpu_ring
*ring
,
437 struct amdgpu_irq_src
*irq_src
,
439 void amdgpu_fence_driver_suspend(struct amdgpu_device
*adev
);
440 void amdgpu_fence_driver_resume(struct amdgpu_device
*adev
);
441 int amdgpu_fence_emit(struct amdgpu_ring
*ring
, void *owner
,
442 struct amdgpu_fence
**fence
);
443 void amdgpu_fence_process(struct amdgpu_ring
*ring
);
444 int amdgpu_fence_wait_next(struct amdgpu_ring
*ring
);
445 int amdgpu_fence_wait_empty(struct amdgpu_ring
*ring
);
446 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring
*ring
);
448 bool amdgpu_fence_need_sync(struct amdgpu_fence
*fence
,
449 struct amdgpu_ring
*ring
);
450 void amdgpu_fence_note_sync(struct amdgpu_fence
*fence
,
451 struct amdgpu_ring
*ring
);
457 struct ttm_bo_global_ref bo_global_ref
;
458 struct drm_global_reference mem_global_ref
;
459 struct ttm_bo_device bdev
;
460 bool mem_global_referenced
;
463 #if defined(CONFIG_DEBUG_FS)
468 /* buffer handling */
469 const struct amdgpu_buffer_funcs
*buffer_funcs
;
470 struct amdgpu_ring
*buffer_funcs_ring
;
473 int amdgpu_copy_buffer(struct amdgpu_ring
*ring
,
477 struct reservation_object
*resv
,
478 struct fence
**fence
);
479 int amdgpu_mmap(struct file
*filp
, struct vm_area_struct
*vma
);
481 struct amdgpu_bo_list_entry
{
482 struct amdgpu_bo
*robj
;
483 struct ttm_validate_buffer tv
;
484 struct amdgpu_bo_va
*bo_va
;
485 unsigned prefered_domains
;
486 unsigned allowed_domains
;
490 struct amdgpu_bo_va_mapping
{
491 struct list_head list
;
492 struct interval_tree_node it
;
497 /* bo virtual addresses in a specific vm */
498 struct amdgpu_bo_va
{
500 /* protected by bo being reserved */
501 struct list_head bo_list
;
502 struct fence
*last_pt_update
;
505 /* protected by vm mutex and spinlock */
506 struct list_head vm_status
;
508 /* mappings for this bo_va */
509 struct list_head invalids
;
510 struct list_head valids
;
512 /* constant after initialization */
513 struct amdgpu_vm
*vm
;
514 struct amdgpu_bo
*bo
;
517 #define AMDGPU_GEM_DOMAIN_MAX 0x3
520 /* Protected by gem.mutex */
521 struct list_head list
;
522 /* Protected by tbo.reserved */
524 struct ttm_place placements
[AMDGPU_GEM_DOMAIN_MAX
+ 1];
525 struct ttm_placement placement
;
526 struct ttm_buffer_object tbo
;
527 struct ttm_bo_kmap_obj kmap
;
535 /* list of all virtual address to which this bo
539 /* Constant after initialization */
540 struct amdgpu_device
*adev
;
541 struct drm_gem_object gem_base
;
542 struct amdgpu_bo
*parent
;
544 struct ttm_bo_kmap_obj dma_buf_vmap
;
546 struct amdgpu_mn
*mn
;
547 struct list_head mn_list
;
549 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
551 void amdgpu_gem_object_free(struct drm_gem_object
*obj
);
552 int amdgpu_gem_object_open(struct drm_gem_object
*obj
,
553 struct drm_file
*file_priv
);
554 void amdgpu_gem_object_close(struct drm_gem_object
*obj
,
555 struct drm_file
*file_priv
);
556 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns
);
557 struct sg_table
*amdgpu_gem_prime_get_sg_table(struct drm_gem_object
*obj
);
558 struct drm_gem_object
*amdgpu_gem_prime_import_sg_table(struct drm_device
*dev
,
559 struct dma_buf_attachment
*attach
,
560 struct sg_table
*sg
);
561 struct dma_buf
*amdgpu_gem_prime_export(struct drm_device
*dev
,
562 struct drm_gem_object
*gobj
,
564 int amdgpu_gem_prime_pin(struct drm_gem_object
*obj
);
565 void amdgpu_gem_prime_unpin(struct drm_gem_object
*obj
);
566 struct reservation_object
*amdgpu_gem_prime_res_obj(struct drm_gem_object
*);
567 void *amdgpu_gem_prime_vmap(struct drm_gem_object
*obj
);
568 void amdgpu_gem_prime_vunmap(struct drm_gem_object
*obj
, void *vaddr
);
569 int amdgpu_gem_debugfs_init(struct amdgpu_device
*adev
);
571 /* sub-allocation manager, it has to be protected by another lock.
572 * By conception this is an helper for other part of the driver
573 * like the indirect buffer or semaphore, which both have their
576 * Principe is simple, we keep a list of sub allocation in offset
577 * order (first entry has offset == 0, last entry has the highest
580 * When allocating new object we first check if there is room at
581 * the end total_size - (last_object_offset + last_object_size) >=
582 * alloc_size. If so we allocate new object there.
584 * When there is not enough room at the end, we start waiting for
585 * each sub object until we reach object_offset+object_size >=
586 * alloc_size, this object then become the sub object we return.
588 * Alignment can't be bigger than page size.
590 * Hole are not considered for allocation to keep things simple.
591 * Assumption is that there won't be hole (all object on same
594 struct amdgpu_sa_manager
{
595 wait_queue_head_t wq
;
596 struct amdgpu_bo
*bo
;
597 struct list_head
*hole
;
598 struct list_head flist
[AMDGPU_MAX_RINGS
];
599 struct list_head olist
;
609 /* sub-allocation buffer */
610 struct amdgpu_sa_bo
{
611 struct list_head olist
;
612 struct list_head flist
;
613 struct amdgpu_sa_manager
*manager
;
624 struct list_head objects
;
627 int amdgpu_gem_init(struct amdgpu_device
*adev
);
628 void amdgpu_gem_fini(struct amdgpu_device
*adev
);
629 int amdgpu_gem_object_create(struct amdgpu_device
*adev
, unsigned long size
,
630 int alignment
, u32 initial_domain
,
631 u64 flags
, bool kernel
,
632 struct drm_gem_object
**obj
);
634 int amdgpu_mode_dumb_create(struct drm_file
*file_priv
,
635 struct drm_device
*dev
,
636 struct drm_mode_create_dumb
*args
);
637 int amdgpu_mode_dumb_mmap(struct drm_file
*filp
,
638 struct drm_device
*dev
,
639 uint32_t handle
, uint64_t *offset_p
);
644 struct amdgpu_semaphore
{
645 struct amdgpu_sa_bo
*sa_bo
;
650 int amdgpu_semaphore_create(struct amdgpu_device
*adev
,
651 struct amdgpu_semaphore
**semaphore
);
652 bool amdgpu_semaphore_emit_signal(struct amdgpu_ring
*ring
,
653 struct amdgpu_semaphore
*semaphore
);
654 bool amdgpu_semaphore_emit_wait(struct amdgpu_ring
*ring
,
655 struct amdgpu_semaphore
*semaphore
);
656 void amdgpu_semaphore_free(struct amdgpu_device
*adev
,
657 struct amdgpu_semaphore
**semaphore
,
658 struct fence
*fence
);
664 struct amdgpu_semaphore
*semaphores
[AMDGPU_NUM_SYNCS
];
665 struct fence
*sync_to
[AMDGPU_MAX_RINGS
];
666 DECLARE_HASHTABLE(fences
, 4);
667 struct fence
*last_vm_update
;
670 void amdgpu_sync_create(struct amdgpu_sync
*sync
);
671 int amdgpu_sync_fence(struct amdgpu_device
*adev
, struct amdgpu_sync
*sync
,
673 int amdgpu_sync_resv(struct amdgpu_device
*adev
,
674 struct amdgpu_sync
*sync
,
675 struct reservation_object
*resv
,
677 int amdgpu_sync_rings(struct amdgpu_sync
*sync
,
678 struct amdgpu_ring
*ring
);
679 struct fence
*amdgpu_sync_get_fence(struct amdgpu_sync
*sync
);
680 int amdgpu_sync_wait(struct amdgpu_sync
*sync
);
681 void amdgpu_sync_free(struct amdgpu_device
*adev
, struct amdgpu_sync
*sync
,
682 struct fence
*fence
);
685 * GART structures, functions & helpers
689 #define AMDGPU_GPU_PAGE_SIZE 4096
690 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
691 #define AMDGPU_GPU_PAGE_SHIFT 12
692 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
695 dma_addr_t table_addr
;
696 struct amdgpu_bo
*robj
;
698 unsigned num_gpu_pages
;
699 unsigned num_cpu_pages
;
702 dma_addr_t
*pages_addr
;
704 const struct amdgpu_gart_funcs
*gart_funcs
;
707 int amdgpu_gart_table_ram_alloc(struct amdgpu_device
*adev
);
708 void amdgpu_gart_table_ram_free(struct amdgpu_device
*adev
);
709 int amdgpu_gart_table_vram_alloc(struct amdgpu_device
*adev
);
710 void amdgpu_gart_table_vram_free(struct amdgpu_device
*adev
);
711 int amdgpu_gart_table_vram_pin(struct amdgpu_device
*adev
);
712 void amdgpu_gart_table_vram_unpin(struct amdgpu_device
*adev
);
713 int amdgpu_gart_init(struct amdgpu_device
*adev
);
714 void amdgpu_gart_fini(struct amdgpu_device
*adev
);
715 void amdgpu_gart_unbind(struct amdgpu_device
*adev
, unsigned offset
,
717 int amdgpu_gart_bind(struct amdgpu_device
*adev
, unsigned offset
,
718 int pages
, struct page
**pagelist
,
719 dma_addr_t
*dma_addr
, uint32_t flags
);
722 * GPU MC structures, functions & helpers
725 resource_size_t aper_size
;
726 resource_size_t aper_base
;
727 resource_size_t agp_base
;
728 /* for some chips with <= 32MB we need to lie
729 * about vram size near mc fb location */
731 u64 visible_vram_size
;
742 const struct firmware
*fw
; /* MC firmware */
744 struct amdgpu_irq_src vm_fault
;
749 * GPU doorbell structures, functions & helpers
751 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
753 AMDGPU_DOORBELL_KIQ
= 0x000,
754 AMDGPU_DOORBELL_HIQ
= 0x001,
755 AMDGPU_DOORBELL_DIQ
= 0x002,
756 AMDGPU_DOORBELL_MEC_RING0
= 0x010,
757 AMDGPU_DOORBELL_MEC_RING1
= 0x011,
758 AMDGPU_DOORBELL_MEC_RING2
= 0x012,
759 AMDGPU_DOORBELL_MEC_RING3
= 0x013,
760 AMDGPU_DOORBELL_MEC_RING4
= 0x014,
761 AMDGPU_DOORBELL_MEC_RING5
= 0x015,
762 AMDGPU_DOORBELL_MEC_RING6
= 0x016,
763 AMDGPU_DOORBELL_MEC_RING7
= 0x017,
764 AMDGPU_DOORBELL_GFX_RING0
= 0x020,
765 AMDGPU_DOORBELL_sDMA_ENGINE0
= 0x1E0,
766 AMDGPU_DOORBELL_sDMA_ENGINE1
= 0x1E1,
767 AMDGPU_DOORBELL_IH
= 0x1E8,
768 AMDGPU_DOORBELL_MAX_ASSIGNMENT
= 0x3FF,
769 AMDGPU_DOORBELL_INVALID
= 0xFFFF
770 } AMDGPU_DOORBELL_ASSIGNMENT
;
772 struct amdgpu_doorbell
{
774 resource_size_t base
;
775 resource_size_t size
;
777 u32 num_doorbells
; /* Number of doorbells actually reserved for amdgpu. */
780 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device
*adev
,
781 phys_addr_t
*aperture_base
,
782 size_t *aperture_size
,
783 size_t *start_offset
);
789 struct amdgpu_flip_work
{
790 struct work_struct flip_work
;
791 struct work_struct unpin_work
;
792 struct amdgpu_device
*adev
;
795 struct drm_pending_vblank_event
*event
;
796 struct amdgpu_bo
*old_rbo
;
798 unsigned shared_count
;
799 struct fence
**shared
;
808 struct amdgpu_sa_bo
*sa_bo
;
812 struct amdgpu_ring
*ring
;
813 struct amdgpu_fence
*fence
;
814 struct amdgpu_user_fence
*user
;
815 struct amdgpu_vm
*vm
;
816 struct amdgpu_ctx
*ctx
;
817 struct amdgpu_sync sync
;
818 uint32_t gds_base
, gds_size
;
819 uint32_t gws_base
, gws_size
;
820 uint32_t oa_base
, oa_size
;
822 /* resulting sequence number */
826 enum amdgpu_ring_type
{
827 AMDGPU_RING_TYPE_GFX
,
828 AMDGPU_RING_TYPE_COMPUTE
,
829 AMDGPU_RING_TYPE_SDMA
,
830 AMDGPU_RING_TYPE_UVD
,
834 extern struct amd_sched_backend_ops amdgpu_sched_ops
;
836 int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device
*adev
,
837 struct amdgpu_ring
*ring
,
838 struct amdgpu_ib
*ibs
,
840 int (*free_job
)(struct amdgpu_job
*),
842 struct fence
**fence
);
845 struct amdgpu_device
*adev
;
846 const struct amdgpu_ring_funcs
*funcs
;
847 struct amdgpu_fence_driver fence_drv
;
848 struct amd_gpu_scheduler sched
;
850 spinlock_t fence_lock
;
851 struct mutex
*ring_lock
;
852 struct amdgpu_bo
*ring_obj
;
853 volatile uint32_t *ring
;
855 u64 next_rptr_gpu_addr
;
856 volatile u32
*next_rptr_cpu_addr
;
860 unsigned ring_free_dw
;
868 u64 last_semaphore_signal_addr
;
869 u64 last_semaphore_wait_addr
;
873 struct amdgpu_bo
*mqd_obj
;
877 unsigned next_rptr_offs
;
879 struct amdgpu_ctx
*current_ctx
;
880 enum amdgpu_ring_type type
;
889 /* maximum number of VMIDs */
890 #define AMDGPU_NUM_VM 16
892 /* number of entries in page table */
893 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
895 /* PTBs (Page Table Blocks) need to be aligned to 32K */
896 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
897 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
898 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
900 #define AMDGPU_PTE_VALID (1 << 0)
901 #define AMDGPU_PTE_SYSTEM (1 << 1)
902 #define AMDGPU_PTE_SNOOPED (1 << 2)
905 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
907 #define AMDGPU_PTE_READABLE (1 << 5)
908 #define AMDGPU_PTE_WRITEABLE (1 << 6)
910 /* PTE (Page Table Entry) fragment field for different page sizes */
911 #define AMDGPU_PTE_FRAG_4KB (0 << 7)
912 #define AMDGPU_PTE_FRAG_64KB (4 << 7)
913 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
915 /* How to programm VM fault handling */
916 #define AMDGPU_VM_FAULT_STOP_NEVER 0
917 #define AMDGPU_VM_FAULT_STOP_FIRST 1
918 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
920 struct amdgpu_vm_pt
{
921 struct amdgpu_bo
*bo
;
925 struct amdgpu_vm_id
{
927 uint64_t pd_gpu_addr
;
928 /* last flushed PD/PT update */
929 struct fence
*flushed_updates
;
935 /* protecting invalidated */
936 spinlock_t status_lock
;
938 /* BOs moved, but not yet updated in the PT */
939 struct list_head invalidated
;
941 /* BOs cleared in the PT because of a move */
942 struct list_head cleared
;
944 /* BO mappings freed, but not yet updated in the PT */
945 struct list_head freed
;
947 /* contains the page directory */
948 struct amdgpu_bo
*page_directory
;
949 unsigned max_pde_used
;
950 struct fence
*page_directory_fence
;
952 /* array of page tables, one for each page directory entry */
953 struct amdgpu_vm_pt
*page_tables
;
955 /* for id and flush management per ring */
956 struct amdgpu_vm_id ids
[AMDGPU_MAX_RINGS
];
957 /* for interval tree */
959 /* protecting freed */
960 spinlock_t freed_lock
;
963 struct amdgpu_vm_manager
{
965 struct fence
*active
;
967 } ids
[AMDGPU_NUM_VM
];
970 /* number of VMIDs */
972 /* vram base address for page table entry */
973 u64 vram_base_offset
;
976 /* vm pte handling */
977 const struct amdgpu_vm_pte_funcs
*vm_pte_funcs
;
978 struct amdgpu_ring
*vm_pte_funcs_ring
;
981 void amdgpu_vm_manager_fini(struct amdgpu_device
*adev
);
982 int amdgpu_vm_init(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
);
983 void amdgpu_vm_fini(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
);
984 struct amdgpu_bo_list_entry
*amdgpu_vm_get_bos(struct amdgpu_device
*adev
,
985 struct amdgpu_vm
*vm
,
986 struct list_head
*head
);
987 int amdgpu_vm_grab_id(struct amdgpu_vm
*vm
, struct amdgpu_ring
*ring
,
988 struct amdgpu_sync
*sync
);
989 void amdgpu_vm_flush(struct amdgpu_ring
*ring
,
990 struct amdgpu_vm
*vm
,
991 struct fence
*updates
);
992 void amdgpu_vm_fence(struct amdgpu_device
*adev
,
993 struct amdgpu_vm
*vm
,
994 struct fence
*fence
);
995 uint64_t amdgpu_vm_map_gart(struct amdgpu_device
*adev
, uint64_t addr
);
996 int amdgpu_vm_update_page_directory(struct amdgpu_device
*adev
,
997 struct amdgpu_vm
*vm
);
998 int amdgpu_vm_clear_freed(struct amdgpu_device
*adev
,
999 struct amdgpu_vm
*vm
);
1000 int amdgpu_vm_clear_invalids(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
1001 struct amdgpu_sync
*sync
);
1002 int amdgpu_vm_bo_update(struct amdgpu_device
*adev
,
1003 struct amdgpu_bo_va
*bo_va
,
1004 struct ttm_mem_reg
*mem
);
1005 void amdgpu_vm_bo_invalidate(struct amdgpu_device
*adev
,
1006 struct amdgpu_bo
*bo
);
1007 struct amdgpu_bo_va
*amdgpu_vm_bo_find(struct amdgpu_vm
*vm
,
1008 struct amdgpu_bo
*bo
);
1009 struct amdgpu_bo_va
*amdgpu_vm_bo_add(struct amdgpu_device
*adev
,
1010 struct amdgpu_vm
*vm
,
1011 struct amdgpu_bo
*bo
);
1012 int amdgpu_vm_bo_map(struct amdgpu_device
*adev
,
1013 struct amdgpu_bo_va
*bo_va
,
1014 uint64_t addr
, uint64_t offset
,
1015 uint64_t size
, uint32_t flags
);
1016 int amdgpu_vm_bo_unmap(struct amdgpu_device
*adev
,
1017 struct amdgpu_bo_va
*bo_va
,
1019 void amdgpu_vm_bo_rmv(struct amdgpu_device
*adev
,
1020 struct amdgpu_bo_va
*bo_va
);
1021 int amdgpu_vm_free_job(struct amdgpu_job
*job
);
1024 * context related structures
1027 #define AMDGPU_CTX_MAX_CS_PENDING 16
1029 struct amdgpu_ctx_ring
{
1031 struct fence
*fences
[AMDGPU_CTX_MAX_CS_PENDING
];
1032 struct amd_sched_entity entity
;
1036 struct kref refcount
;
1037 struct amdgpu_device
*adev
;
1038 unsigned reset_counter
;
1039 spinlock_t ring_lock
;
1040 struct amdgpu_ctx_ring rings
[AMDGPU_MAX_RINGS
];
1043 struct amdgpu_ctx_mgr
{
1044 struct amdgpu_device
*adev
;
1046 /* protected by lock */
1047 struct idr ctx_handles
;
1050 int amdgpu_ctx_init(struct amdgpu_device
*adev
, bool kernel
,
1051 struct amdgpu_ctx
*ctx
);
1052 void amdgpu_ctx_fini(struct amdgpu_ctx
*ctx
);
1054 struct amdgpu_ctx
*amdgpu_ctx_get(struct amdgpu_fpriv
*fpriv
, uint32_t id
);
1055 int amdgpu_ctx_put(struct amdgpu_ctx
*ctx
);
1057 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx
*ctx
, struct amdgpu_ring
*ring
,
1058 struct fence
*fence
);
1059 struct fence
*amdgpu_ctx_get_fence(struct amdgpu_ctx
*ctx
,
1060 struct amdgpu_ring
*ring
, uint64_t seq
);
1062 int amdgpu_ctx_ioctl(struct drm_device
*dev
, void *data
,
1063 struct drm_file
*filp
);
1065 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr
*mgr
);
1066 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr
*mgr
);
1069 * file private structure
1072 struct amdgpu_fpriv
{
1073 struct amdgpu_vm vm
;
1074 struct mutex bo_list_lock
;
1075 struct idr bo_list_handles
;
1076 struct amdgpu_ctx_mgr ctx_mgr
;
1083 struct amdgpu_bo_list
{
1085 struct amdgpu_bo
*gds_obj
;
1086 struct amdgpu_bo
*gws_obj
;
1087 struct amdgpu_bo
*oa_obj
;
1089 unsigned num_entries
;
1090 struct amdgpu_bo_list_entry
*array
;
1093 struct amdgpu_bo_list
*
1094 amdgpu_bo_list_get(struct amdgpu_fpriv
*fpriv
, int id
);
1095 void amdgpu_bo_list_put(struct amdgpu_bo_list
*list
);
1096 void amdgpu_bo_list_free(struct amdgpu_bo_list
*list
);
1101 #include "clearstate_defs.h"
1104 /* for power gating */
1105 struct amdgpu_bo
*save_restore_obj
;
1106 uint64_t save_restore_gpu_addr
;
1107 volatile uint32_t *sr_ptr
;
1108 const u32
*reg_list
;
1110 /* for clear state */
1111 struct amdgpu_bo
*clear_state_obj
;
1112 uint64_t clear_state_gpu_addr
;
1113 volatile uint32_t *cs_ptr
;
1114 const struct cs_section_def
*cs_data
;
1115 u32 clear_state_size
;
1117 struct amdgpu_bo
*cp_table_obj
;
1118 uint64_t cp_table_gpu_addr
;
1119 volatile uint32_t *cp_table_ptr
;
1124 struct amdgpu_bo
*hpd_eop_obj
;
1125 u64 hpd_eop_gpu_addr
;
1132 * GPU scratch registers structures, functions & helpers
1134 struct amdgpu_scratch
{
1142 * GFX configurations
1144 struct amdgpu_gca_config
{
1145 unsigned max_shader_engines
;
1146 unsigned max_tile_pipes
;
1147 unsigned max_cu_per_sh
;
1148 unsigned max_sh_per_se
;
1149 unsigned max_backends_per_se
;
1150 unsigned max_texture_channel_caches
;
1152 unsigned max_gs_threads
;
1153 unsigned max_hw_contexts
;
1154 unsigned sc_prim_fifo_size_frontend
;
1155 unsigned sc_prim_fifo_size_backend
;
1156 unsigned sc_hiz_tile_fifo_size
;
1157 unsigned sc_earlyz_tile_fifo_size
;
1159 unsigned num_tile_pipes
;
1160 unsigned backend_enable_mask
;
1161 unsigned mem_max_burst_length_bytes
;
1162 unsigned mem_row_size_in_kb
;
1163 unsigned shader_engine_tile_size
;
1165 unsigned multi_gpu_tile_size
;
1166 unsigned mc_arb_ramcfg
;
1167 unsigned gb_addr_config
;
1169 uint32_t tile_mode_array
[32];
1170 uint32_t macrotile_mode_array
[16];
1174 struct mutex gpu_clock_mutex
;
1175 struct amdgpu_gca_config config
;
1176 struct amdgpu_rlc rlc
;
1177 struct amdgpu_mec mec
;
1178 struct amdgpu_scratch scratch
;
1179 const struct firmware
*me_fw
; /* ME firmware */
1180 uint32_t me_fw_version
;
1181 const struct firmware
*pfp_fw
; /* PFP firmware */
1182 uint32_t pfp_fw_version
;
1183 const struct firmware
*ce_fw
; /* CE firmware */
1184 uint32_t ce_fw_version
;
1185 const struct firmware
*rlc_fw
; /* RLC firmware */
1186 uint32_t rlc_fw_version
;
1187 const struct firmware
*mec_fw
; /* MEC firmware */
1188 uint32_t mec_fw_version
;
1189 const struct firmware
*mec2_fw
; /* MEC2 firmware */
1190 uint32_t mec2_fw_version
;
1191 uint32_t me_feature_version
;
1192 uint32_t ce_feature_version
;
1193 uint32_t pfp_feature_version
;
1194 uint32_t rlc_feature_version
;
1195 uint32_t mec_feature_version
;
1196 uint32_t mec2_feature_version
;
1197 struct amdgpu_ring gfx_ring
[AMDGPU_MAX_GFX_RINGS
];
1198 unsigned num_gfx_rings
;
1199 struct amdgpu_ring compute_ring
[AMDGPU_MAX_COMPUTE_RINGS
];
1200 unsigned num_compute_rings
;
1201 struct amdgpu_irq_src eop_irq
;
1202 struct amdgpu_irq_src priv_reg_irq
;
1203 struct amdgpu_irq_src priv_inst_irq
;
1205 uint32_t gfx_current_status
;
1207 unsigned ce_ram_size
;
1210 int amdgpu_ib_get(struct amdgpu_ring
*ring
, struct amdgpu_vm
*vm
,
1211 unsigned size
, struct amdgpu_ib
*ib
);
1212 void amdgpu_ib_free(struct amdgpu_device
*adev
, struct amdgpu_ib
*ib
);
1213 int amdgpu_ib_schedule(struct amdgpu_device
*adev
, unsigned num_ibs
,
1214 struct amdgpu_ib
*ib
, void *owner
);
1215 int amdgpu_ib_pool_init(struct amdgpu_device
*adev
);
1216 void amdgpu_ib_pool_fini(struct amdgpu_device
*adev
);
1217 int amdgpu_ib_ring_tests(struct amdgpu_device
*adev
);
1218 /* Ring access between begin & end cannot sleep */
1219 void amdgpu_ring_free_size(struct amdgpu_ring
*ring
);
1220 int amdgpu_ring_alloc(struct amdgpu_ring
*ring
, unsigned ndw
);
1221 int amdgpu_ring_lock(struct amdgpu_ring
*ring
, unsigned ndw
);
1222 void amdgpu_ring_insert_nop(struct amdgpu_ring
*ring
, uint32_t count
);
1223 void amdgpu_ring_commit(struct amdgpu_ring
*ring
);
1224 void amdgpu_ring_unlock_commit(struct amdgpu_ring
*ring
);
1225 void amdgpu_ring_undo(struct amdgpu_ring
*ring
);
1226 void amdgpu_ring_unlock_undo(struct amdgpu_ring
*ring
);
1227 unsigned amdgpu_ring_backup(struct amdgpu_ring
*ring
,
1229 int amdgpu_ring_restore(struct amdgpu_ring
*ring
,
1230 unsigned size
, uint32_t *data
);
1231 int amdgpu_ring_init(struct amdgpu_device
*adev
, struct amdgpu_ring
*ring
,
1232 unsigned ring_size
, u32 nop
, u32 align_mask
,
1233 struct amdgpu_irq_src
*irq_src
, unsigned irq_type
,
1234 enum amdgpu_ring_type ring_type
);
1235 void amdgpu_ring_fini(struct amdgpu_ring
*ring
);
1236 struct amdgpu_ring
*amdgpu_ring_from_fence(struct fence
*f
);
1241 struct amdgpu_cs_chunk
{
1245 void __user
*user_ptr
;
1248 struct amdgpu_cs_parser
{
1249 struct amdgpu_device
*adev
;
1250 struct drm_file
*filp
;
1251 struct amdgpu_ctx
*ctx
;
1252 struct amdgpu_bo_list
*bo_list
;
1255 struct amdgpu_cs_chunk
*chunks
;
1257 struct amdgpu_bo_list_entry
*vm_bos
;
1258 struct list_head validated
;
1259 struct fence
*fence
;
1261 struct amdgpu_ib
*ibs
;
1264 struct ww_acquire_ctx ticket
;
1267 struct amdgpu_user_fence uf
;
1268 struct amdgpu_bo_list_entry uf_entry
;
1272 struct amd_sched_job base
;
1273 struct amdgpu_device
*adev
;
1274 struct amdgpu_ib
*ibs
;
1277 struct amdgpu_user_fence uf
;
1278 int (*free_job
)(struct amdgpu_job
*job
);
1280 #define to_amdgpu_job(sched_job) \
1281 container_of((sched_job), struct amdgpu_job, base)
1283 static inline u32
amdgpu_get_ib_value(struct amdgpu_cs_parser
*p
, uint32_t ib_idx
, int idx
)
1285 return p
->ibs
[ib_idx
].ptr
[idx
];
1291 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1294 struct amdgpu_bo
*wb_obj
;
1295 volatile uint32_t *wb
;
1297 u32 num_wb
; /* Number of wb slots actually reserved for amdgpu. */
1298 unsigned long used
[DIV_ROUND_UP(AMDGPU_MAX_WB
, BITS_PER_LONG
)];
1301 int amdgpu_wb_get(struct amdgpu_device
*adev
, u32
*wb
);
1302 void amdgpu_wb_free(struct amdgpu_device
*adev
, u32 wb
);
1305 * struct amdgpu_pm - power management datas
1306 * It keeps track of various data needed to take powermanagement decision.
1309 enum amdgpu_pm_state_type
{
1310 /* not used for dpm */
1311 POWER_STATE_TYPE_DEFAULT
,
1312 POWER_STATE_TYPE_POWERSAVE
,
1313 /* user selectable states */
1314 POWER_STATE_TYPE_BATTERY
,
1315 POWER_STATE_TYPE_BALANCED
,
1316 POWER_STATE_TYPE_PERFORMANCE
,
1317 /* internal states */
1318 POWER_STATE_TYPE_INTERNAL_UVD
,
1319 POWER_STATE_TYPE_INTERNAL_UVD_SD
,
1320 POWER_STATE_TYPE_INTERNAL_UVD_HD
,
1321 POWER_STATE_TYPE_INTERNAL_UVD_HD2
,
1322 POWER_STATE_TYPE_INTERNAL_UVD_MVC
,
1323 POWER_STATE_TYPE_INTERNAL_BOOT
,
1324 POWER_STATE_TYPE_INTERNAL_THERMAL
,
1325 POWER_STATE_TYPE_INTERNAL_ACPI
,
1326 POWER_STATE_TYPE_INTERNAL_ULV
,
1327 POWER_STATE_TYPE_INTERNAL_3DPERF
,
1330 enum amdgpu_int_thermal_type
{
1332 THERMAL_TYPE_EXTERNAL
,
1333 THERMAL_TYPE_EXTERNAL_GPIO
,
1336 THERMAL_TYPE_ADT7473_WITH_INTERNAL
,
1337 THERMAL_TYPE_EVERGREEN
,
1341 THERMAL_TYPE_EMC2103_WITH_INTERNAL
,
1346 enum amdgpu_dpm_auto_throttle_src
{
1347 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL
,
1348 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1351 enum amdgpu_dpm_event_src
{
1352 AMDGPU_DPM_EVENT_SRC_ANALOG
= 0,
1353 AMDGPU_DPM_EVENT_SRC_EXTERNAL
= 1,
1354 AMDGPU_DPM_EVENT_SRC_DIGITAL
= 2,
1355 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL
= 3,
1356 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL
= 4
1359 #define AMDGPU_MAX_VCE_LEVELS 6
1361 enum amdgpu_vce_level
{
1362 AMDGPU_VCE_LEVEL_AC_ALL
= 0, /* AC, All cases */
1363 AMDGPU_VCE_LEVEL_DC_EE
= 1, /* DC, entropy encoding */
1364 AMDGPU_VCE_LEVEL_DC_LL_LOW
= 2, /* DC, low latency queue, res <= 720 */
1365 AMDGPU_VCE_LEVEL_DC_LL_HIGH
= 3, /* DC, low latency queue, 1080 >= res > 720 */
1366 AMDGPU_VCE_LEVEL_DC_GP_LOW
= 4, /* DC, general purpose queue, res <= 720 */
1367 AMDGPU_VCE_LEVEL_DC_GP_HIGH
= 5, /* DC, general purpose queue, 1080 >= res > 720 */
1371 u32 caps
; /* vbios flags */
1372 u32
class; /* vbios flags */
1373 u32 class2
; /* vbios flags */
1381 enum amdgpu_vce_level vce_level
;
1386 struct amdgpu_dpm_thermal
{
1387 /* thermal interrupt work */
1388 struct work_struct work
;
1389 /* low temperature threshold */
1391 /* high temperature threshold */
1393 /* was last interrupt low to high or high to low */
1395 /* interrupt source */
1396 struct amdgpu_irq_src irq
;
1399 enum amdgpu_clk_action
1405 struct amdgpu_blacklist_clocks
1409 enum amdgpu_clk_action action
;
1412 struct amdgpu_clock_and_voltage_limits
{
1419 struct amdgpu_clock_array
{
1424 struct amdgpu_clock_voltage_dependency_entry
{
1429 struct amdgpu_clock_voltage_dependency_table
{
1431 struct amdgpu_clock_voltage_dependency_entry
*entries
;
1434 union amdgpu_cac_leakage_entry
{
1446 struct amdgpu_cac_leakage_table
{
1448 union amdgpu_cac_leakage_entry
*entries
;
1451 struct amdgpu_phase_shedding_limits_entry
{
1457 struct amdgpu_phase_shedding_limits_table
{
1459 struct amdgpu_phase_shedding_limits_entry
*entries
;
1462 struct amdgpu_uvd_clock_voltage_dependency_entry
{
1468 struct amdgpu_uvd_clock_voltage_dependency_table
{
1470 struct amdgpu_uvd_clock_voltage_dependency_entry
*entries
;
1473 struct amdgpu_vce_clock_voltage_dependency_entry
{
1479 struct amdgpu_vce_clock_voltage_dependency_table
{
1481 struct amdgpu_vce_clock_voltage_dependency_entry
*entries
;
1484 struct amdgpu_ppm_table
{
1486 u16 cpu_core_number
;
1488 u32 small_ac_platform_tdp
;
1490 u32 small_ac_platform_tdc
;
1497 struct amdgpu_cac_tdp_table
{
1499 u16 configurable_tdp
;
1501 u16 battery_power_limit
;
1502 u16 small_power_limit
;
1503 u16 low_cac_leakage
;
1504 u16 high_cac_leakage
;
1505 u16 maximum_power_delivery_limit
;
1508 struct amdgpu_dpm_dynamic_state
{
1509 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk
;
1510 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk
;
1511 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk
;
1512 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk
;
1513 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk
;
1514 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table
;
1515 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table
;
1516 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table
;
1517 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table
;
1518 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk
;
1519 struct amdgpu_clock_array valid_sclk_values
;
1520 struct amdgpu_clock_array valid_mclk_values
;
1521 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc
;
1522 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac
;
1523 u32 mclk_sclk_ratio
;
1524 u32 sclk_mclk_delta
;
1525 u16 vddc_vddci_delta
;
1526 u16 min_vddc_for_pcie_gen2
;
1527 struct amdgpu_cac_leakage_table cac_leakage_table
;
1528 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table
;
1529 struct amdgpu_ppm_table
*ppm_table
;
1530 struct amdgpu_cac_tdp_table
*cac_tdp_table
;
1533 struct amdgpu_dpm_fan
{
1544 u16 default_max_fan_pwm
;
1545 u16 default_fan_output_sensitivity
;
1546 u16 fan_output_sensitivity
;
1547 bool ucode_fan_control
;
1550 enum amdgpu_pcie_gen
{
1551 AMDGPU_PCIE_GEN1
= 0,
1552 AMDGPU_PCIE_GEN2
= 1,
1553 AMDGPU_PCIE_GEN3
= 2,
1554 AMDGPU_PCIE_GEN_INVALID
= 0xffff
1557 enum amdgpu_dpm_forced_level
{
1558 AMDGPU_DPM_FORCED_LEVEL_AUTO
= 0,
1559 AMDGPU_DPM_FORCED_LEVEL_LOW
= 1,
1560 AMDGPU_DPM_FORCED_LEVEL_HIGH
= 2,
1563 struct amdgpu_vce_state
{
1574 struct amdgpu_dpm_funcs
{
1575 int (*get_temperature
)(struct amdgpu_device
*adev
);
1576 int (*pre_set_power_state
)(struct amdgpu_device
*adev
);
1577 int (*set_power_state
)(struct amdgpu_device
*adev
);
1578 void (*post_set_power_state
)(struct amdgpu_device
*adev
);
1579 void (*display_configuration_changed
)(struct amdgpu_device
*adev
);
1580 u32 (*get_sclk
)(struct amdgpu_device
*adev
, bool low
);
1581 u32 (*get_mclk
)(struct amdgpu_device
*adev
, bool low
);
1582 void (*print_power_state
)(struct amdgpu_device
*adev
, struct amdgpu_ps
*ps
);
1583 void (*debugfs_print_current_performance_level
)(struct amdgpu_device
*adev
, struct seq_file
*m
);
1584 int (*force_performance_level
)(struct amdgpu_device
*adev
, enum amdgpu_dpm_forced_level level
);
1585 bool (*vblank_too_short
)(struct amdgpu_device
*adev
);
1586 void (*powergate_uvd
)(struct amdgpu_device
*adev
, bool gate
);
1587 void (*powergate_vce
)(struct amdgpu_device
*adev
, bool gate
);
1588 void (*enable_bapm
)(struct amdgpu_device
*adev
, bool enable
);
1589 void (*set_fan_control_mode
)(struct amdgpu_device
*adev
, u32 mode
);
1590 u32 (*get_fan_control_mode
)(struct amdgpu_device
*adev
);
1591 int (*set_fan_speed_percent
)(struct amdgpu_device
*adev
, u32 speed
);
1592 int (*get_fan_speed_percent
)(struct amdgpu_device
*adev
, u32
*speed
);
1596 struct amdgpu_ps
*ps
;
1597 /* number of valid power states */
1599 /* current power state that is active */
1600 struct amdgpu_ps
*current_ps
;
1601 /* requested power state */
1602 struct amdgpu_ps
*requested_ps
;
1603 /* boot up power state */
1604 struct amdgpu_ps
*boot_ps
;
1605 /* default uvd power state */
1606 struct amdgpu_ps
*uvd_ps
;
1607 /* vce requirements */
1608 struct amdgpu_vce_state vce_states
[AMDGPU_MAX_VCE_LEVELS
];
1609 enum amdgpu_vce_level vce_level
;
1610 enum amdgpu_pm_state_type state
;
1611 enum amdgpu_pm_state_type user_state
;
1613 u32 voltage_response_time
;
1614 u32 backbias_response_time
;
1616 u32 new_active_crtcs
;
1617 int new_active_crtc_count
;
1618 u32 current_active_crtcs
;
1619 int current_active_crtc_count
;
1620 struct amdgpu_dpm_dynamic_state dyn_state
;
1621 struct amdgpu_dpm_fan fan
;
1624 u32 near_tdp_limit_adjusted
;
1625 u32 sq_ramping_threshold
;
1629 u16 load_line_slope
;
1632 /* special states active */
1633 bool thermal_active
;
1636 /* thermal handling */
1637 struct amdgpu_dpm_thermal thermal
;
1639 enum amdgpu_dpm_forced_level forced_level
;
1648 struct amdgpu_i2c_chan
*i2c_bus
;
1649 /* internal thermal controller on rv6xx+ */
1650 enum amdgpu_int_thermal_type int_thermal_type
;
1651 struct device
*int_hwmon_dev
;
1652 /* fan control parameters */
1654 u8 fan_pulses_per_revolution
;
1659 bool sysfs_initialized
;
1660 struct amdgpu_dpm dpm
;
1661 const struct firmware
*fw
; /* SMC firmware */
1662 uint32_t fw_version
;
1663 const struct amdgpu_dpm_funcs
*funcs
;
1669 #define AMDGPU_MAX_UVD_HANDLES 10
1670 #define AMDGPU_UVD_STACK_SIZE (1024*1024)
1671 #define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1672 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1675 struct amdgpu_bo
*vcpu_bo
;
1678 atomic_t handles
[AMDGPU_MAX_UVD_HANDLES
];
1679 struct drm_file
*filp
[AMDGPU_MAX_UVD_HANDLES
];
1680 struct delayed_work idle_work
;
1681 const struct firmware
*fw
; /* UVD firmware */
1682 struct amdgpu_ring ring
;
1683 struct amdgpu_irq_src irq
;
1684 bool address_64_bit
;
1690 #define AMDGPU_MAX_VCE_HANDLES 16
1691 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1693 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1694 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1697 struct amdgpu_bo
*vcpu_bo
;
1699 unsigned fw_version
;
1700 unsigned fb_version
;
1701 atomic_t handles
[AMDGPU_MAX_VCE_HANDLES
];
1702 struct drm_file
*filp
[AMDGPU_MAX_VCE_HANDLES
];
1703 uint32_t img_size
[AMDGPU_MAX_VCE_HANDLES
];
1704 struct delayed_work idle_work
;
1705 const struct firmware
*fw
; /* VCE firmware */
1706 struct amdgpu_ring ring
[AMDGPU_MAX_VCE_RINGS
];
1707 struct amdgpu_irq_src irq
;
1708 unsigned harvest_config
;
1714 struct amdgpu_sdma_instance
{
1716 const struct firmware
*fw
;
1717 uint32_t fw_version
;
1718 uint32_t feature_version
;
1720 struct amdgpu_ring ring
;
1724 struct amdgpu_sdma
{
1725 struct amdgpu_sdma_instance instance
[AMDGPU_MAX_SDMA_INSTANCES
];
1726 struct amdgpu_irq_src trap_irq
;
1727 struct amdgpu_irq_src illegal_inst_irq
;
1734 struct amdgpu_firmware
{
1735 struct amdgpu_firmware_info ucode
[AMDGPU_UCODE_ID_MAXIMUM
];
1737 struct amdgpu_bo
*fw_buf
;
1738 unsigned int fw_size
;
1744 void amdgpu_benchmark(struct amdgpu_device
*adev
, int test_number
);
1750 void amdgpu_test_moves(struct amdgpu_device
*adev
);
1751 void amdgpu_test_ring_sync(struct amdgpu_device
*adev
,
1752 struct amdgpu_ring
*cpA
,
1753 struct amdgpu_ring
*cpB
);
1754 void amdgpu_test_syncing(struct amdgpu_device
*adev
);
1759 #if defined(CONFIG_MMU_NOTIFIER)
1760 int amdgpu_mn_register(struct amdgpu_bo
*bo
, unsigned long addr
);
1761 void amdgpu_mn_unregister(struct amdgpu_bo
*bo
);
1763 static inline int amdgpu_mn_register(struct amdgpu_bo
*bo
, unsigned long addr
)
1767 static inline void amdgpu_mn_unregister(struct amdgpu_bo
*bo
) {}
1773 struct amdgpu_debugfs
{
1774 struct drm_info_list
*files
;
1778 int amdgpu_debugfs_add_files(struct amdgpu_device
*adev
,
1779 struct drm_info_list
*files
,
1781 int amdgpu_debugfs_fence_init(struct amdgpu_device
*adev
);
1783 #if defined(CONFIG_DEBUG_FS)
1784 int amdgpu_debugfs_init(struct drm_minor
*minor
);
1785 void amdgpu_debugfs_cleanup(struct drm_minor
*minor
);
1789 * amdgpu smumgr functions
1791 struct amdgpu_smumgr_funcs
{
1792 int (*check_fw_load_finish
)(struct amdgpu_device
*adev
, uint32_t fwtype
);
1793 int (*request_smu_load_fw
)(struct amdgpu_device
*adev
);
1794 int (*request_smu_specific_fw
)(struct amdgpu_device
*adev
, uint32_t fwtype
);
1800 struct amdgpu_smumgr
{
1801 struct amdgpu_bo
*toc_buf
;
1802 struct amdgpu_bo
*smu_buf
;
1803 /* asic priv smu data */
1805 spinlock_t smu_lock
;
1806 /* smumgr functions */
1807 const struct amdgpu_smumgr_funcs
*smumgr_funcs
;
1808 /* ucode loading complete flag */
1813 * ASIC specific register table accessible by UMD
1815 struct amdgpu_allowed_register_entry
{
1816 uint32_t reg_offset
;
1821 struct amdgpu_cu_info
{
1822 uint32_t number
; /* total active CU number */
1823 uint32_t ao_cu_mask
;
1824 uint32_t bitmap
[4][4];
1829 * ASIC specific functions.
1831 struct amdgpu_asic_funcs
{
1832 bool (*read_disabled_bios
)(struct amdgpu_device
*adev
);
1833 int (*read_register
)(struct amdgpu_device
*adev
, u32 se_num
,
1834 u32 sh_num
, u32 reg_offset
, u32
*value
);
1835 void (*set_vga_state
)(struct amdgpu_device
*adev
, bool state
);
1836 int (*reset
)(struct amdgpu_device
*adev
);
1837 /* wait for mc_idle */
1838 int (*wait_for_mc_idle
)(struct amdgpu_device
*adev
);
1839 /* get the reference clock */
1840 u32 (*get_xclk
)(struct amdgpu_device
*adev
);
1841 /* get the gpu clock counter */
1842 uint64_t (*get_gpu_clock_counter
)(struct amdgpu_device
*adev
);
1843 int (*get_cu_info
)(struct amdgpu_device
*adev
, struct amdgpu_cu_info
*info
);
1844 /* MM block clocks */
1845 int (*set_uvd_clocks
)(struct amdgpu_device
*adev
, u32 vclk
, u32 dclk
);
1846 int (*set_vce_clocks
)(struct amdgpu_device
*adev
, u32 evclk
, u32 ecclk
);
1852 int amdgpu_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1853 struct drm_file
*filp
);
1854 int amdgpu_bo_list_ioctl(struct drm_device
*dev
, void *data
,
1855 struct drm_file
*filp
);
1857 int amdgpu_gem_info_ioctl(struct drm_device
*dev
, void *data
,
1858 struct drm_file
*filp
);
1859 int amdgpu_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
1860 struct drm_file
*filp
);
1861 int amdgpu_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1862 struct drm_file
*filp
);
1863 int amdgpu_gem_wait_idle_ioctl(struct drm_device
*dev
, void *data
,
1864 struct drm_file
*filp
);
1865 int amdgpu_gem_va_ioctl(struct drm_device
*dev
, void *data
,
1866 struct drm_file
*filp
);
1867 int amdgpu_gem_op_ioctl(struct drm_device
*dev
, void *data
,
1868 struct drm_file
*filp
);
1869 int amdgpu_cs_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
1870 int amdgpu_cs_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
1872 int amdgpu_gem_metadata_ioctl(struct drm_device
*dev
, void *data
,
1873 struct drm_file
*filp
);
1875 /* VRAM scratch page for HDP bug, default vram page */
1876 struct amdgpu_vram_scratch
{
1877 struct amdgpu_bo
*robj
;
1878 volatile uint32_t *ptr
;
1885 struct amdgpu_atif_notification_cfg
{
1890 struct amdgpu_atif_notifications
{
1891 bool display_switch
;
1892 bool expansion_mode_change
;
1894 bool forced_power_state
;
1895 bool system_power_state
;
1896 bool display_conf_change
;
1898 bool brightness_change
;
1899 bool dgpu_display_event
;
1902 struct amdgpu_atif_functions
{
1904 bool sbios_requests
;
1905 bool select_active_disp
;
1907 bool get_tv_standard
;
1908 bool set_tv_standard
;
1909 bool get_panel_expansion_mode
;
1910 bool set_panel_expansion_mode
;
1911 bool temperature_change
;
1912 bool graphics_device_types
;
1915 struct amdgpu_atif
{
1916 struct amdgpu_atif_notifications notifications
;
1917 struct amdgpu_atif_functions functions
;
1918 struct amdgpu_atif_notification_cfg notification_cfg
;
1919 struct amdgpu_encoder
*encoder_for_bl
;
1922 struct amdgpu_atcs_functions
{
1926 bool pcie_bus_width
;
1929 struct amdgpu_atcs
{
1930 struct amdgpu_atcs_functions functions
;
1936 void *amdgpu_cgs_create_device(struct amdgpu_device
*adev
);
1937 void amdgpu_cgs_destroy_device(void *cgs_device
);
1941 * Core structure, functions and helpers.
1943 typedef uint32_t (*amdgpu_rreg_t
)(struct amdgpu_device
*, uint32_t);
1944 typedef void (*amdgpu_wreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t);
1946 typedef uint32_t (*amdgpu_block_rreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t);
1947 typedef void (*amdgpu_block_wreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t, uint32_t);
1949 struct amdgpu_ip_block_status
{
1955 struct amdgpu_device
{
1957 struct drm_device
*ddev
;
1958 struct pci_dev
*pdev
;
1961 enum amd_asic_type asic_type
;
1964 uint32_t external_rev_id
;
1965 unsigned long flags
;
1967 const struct amdgpu_asic_funcs
*asic_funcs
;
1972 struct work_struct reset_work
;
1973 struct notifier_block acpi_nb
;
1974 struct amdgpu_i2c_chan
*i2c_bus
[AMDGPU_MAX_I2C_BUS
];
1975 struct amdgpu_debugfs debugfs
[AMDGPU_DEBUGFS_MAX_COMPONENTS
];
1976 unsigned debugfs_count
;
1977 #if defined(CONFIG_DEBUG_FS)
1978 struct dentry
*debugfs_regs
;
1980 struct amdgpu_atif atif
;
1981 struct amdgpu_atcs atcs
;
1982 struct mutex srbm_mutex
;
1983 /* GRBM index mutex. Protects concurrent access to GRBM index */
1984 struct mutex grbm_idx_mutex
;
1985 struct dev_pm_domain vga_pm_domain
;
1986 bool have_disp_power_ref
;
1991 uint16_t bios_header_start
;
1992 struct amdgpu_bo
*stollen_vga_memory
;
1993 uint32_t bios_scratch
[AMDGPU_BIOS_NUM_SCRATCH
];
1995 /* Register/doorbell mmio */
1996 resource_size_t rmmio_base
;
1997 resource_size_t rmmio_size
;
1998 void __iomem
*rmmio
;
1999 /* protects concurrent MM_INDEX/DATA based register access */
2000 spinlock_t mmio_idx_lock
;
2001 /* protects concurrent SMC based register access */
2002 spinlock_t smc_idx_lock
;
2003 amdgpu_rreg_t smc_rreg
;
2004 amdgpu_wreg_t smc_wreg
;
2005 /* protects concurrent PCIE register access */
2006 spinlock_t pcie_idx_lock
;
2007 amdgpu_rreg_t pcie_rreg
;
2008 amdgpu_wreg_t pcie_wreg
;
2009 /* protects concurrent UVD register access */
2010 spinlock_t uvd_ctx_idx_lock
;
2011 amdgpu_rreg_t uvd_ctx_rreg
;
2012 amdgpu_wreg_t uvd_ctx_wreg
;
2013 /* protects concurrent DIDT register access */
2014 spinlock_t didt_idx_lock
;
2015 amdgpu_rreg_t didt_rreg
;
2016 amdgpu_wreg_t didt_wreg
;
2017 /* protects concurrent ENDPOINT (audio) register access */
2018 spinlock_t audio_endpt_idx_lock
;
2019 amdgpu_block_rreg_t audio_endpt_rreg
;
2020 amdgpu_block_wreg_t audio_endpt_wreg
;
2021 void __iomem
*rio_mem
;
2022 resource_size_t rio_mem_size
;
2023 struct amdgpu_doorbell doorbell
;
2025 /* clock/pll info */
2026 struct amdgpu_clock clock
;
2029 struct amdgpu_mc mc
;
2030 struct amdgpu_gart gart
;
2031 struct amdgpu_dummy_page dummy_page
;
2032 struct amdgpu_vm_manager vm_manager
;
2034 /* memory management */
2035 struct amdgpu_mman mman
;
2036 struct amdgpu_gem gem
;
2037 struct amdgpu_vram_scratch vram_scratch
;
2038 struct amdgpu_wb wb
;
2039 atomic64_t vram_usage
;
2040 atomic64_t vram_vis_usage
;
2041 atomic64_t gtt_usage
;
2042 atomic64_t num_bytes_moved
;
2043 atomic_t gpu_reset_counter
;
2046 struct amdgpu_mode_info mode_info
;
2047 struct work_struct hotplug_work
;
2048 struct amdgpu_irq_src crtc_irq
;
2049 struct amdgpu_irq_src pageflip_irq
;
2050 struct amdgpu_irq_src hpd_irq
;
2053 unsigned fence_context
;
2054 struct mutex ring_lock
;
2056 struct amdgpu_ring
*rings
[AMDGPU_MAX_RINGS
];
2058 struct amdgpu_sa_manager ring_tmp_bo
;
2061 struct amdgpu_irq irq
;
2064 struct amdgpu_pm pm
;
2069 struct amdgpu_smumgr smu
;
2072 struct amdgpu_gfx gfx
;
2075 struct amdgpu_sdma sdma
;
2079 struct amdgpu_uvd uvd
;
2082 struct amdgpu_vce vce
;
2085 struct amdgpu_firmware firmware
;
2088 struct amdgpu_gds gds
;
2090 const struct amdgpu_ip_block_version
*ip_blocks
;
2092 struct amdgpu_ip_block_status
*ip_block_status
;
2093 struct mutex mn_lock
;
2094 DECLARE_HASHTABLE(mn_hash
, 7);
2096 /* tracking pinned memory */
2100 /* amdkfd interface */
2101 struct kfd_dev
*kfd
;
2103 /* kernel conext for IB submission */
2104 struct amdgpu_ctx kernel_ctx
;
2107 bool amdgpu_device_is_px(struct drm_device
*dev
);
2108 int amdgpu_device_init(struct amdgpu_device
*adev
,
2109 struct drm_device
*ddev
,
2110 struct pci_dev
*pdev
,
2112 void amdgpu_device_fini(struct amdgpu_device
*adev
);
2113 int amdgpu_gpu_wait_for_idle(struct amdgpu_device
*adev
);
2115 uint32_t amdgpu_mm_rreg(struct amdgpu_device
*adev
, uint32_t reg
,
2116 bool always_indirect
);
2117 void amdgpu_mm_wreg(struct amdgpu_device
*adev
, uint32_t reg
, uint32_t v
,
2118 bool always_indirect
);
2119 u32
amdgpu_io_rreg(struct amdgpu_device
*adev
, u32 reg
);
2120 void amdgpu_io_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
);
2122 u32
amdgpu_mm_rdoorbell(struct amdgpu_device
*adev
, u32 index
);
2123 void amdgpu_mm_wdoorbell(struct amdgpu_device
*adev
, u32 index
, u32 v
);
2128 extern const struct fence_ops amdgpu_fence_ops
;
2129 static inline struct amdgpu_fence
*to_amdgpu_fence(struct fence
*f
)
2131 struct amdgpu_fence
*__f
= container_of(f
, struct amdgpu_fence
, base
);
2133 if (__f
->base
.ops
== &amdgpu_fence_ops
)
2140 * Registers read & write functions.
2142 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2143 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2144 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2145 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2146 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2147 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2148 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2149 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2150 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2151 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2152 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2153 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2154 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2155 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2156 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2157 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2158 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2159 #define WREG32_P(reg, val, mask) \
2161 uint32_t tmp_ = RREG32(reg); \
2163 tmp_ |= ((val) & ~(mask)); \
2164 WREG32(reg, tmp_); \
2166 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2167 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2168 #define WREG32_PLL_P(reg, val, mask) \
2170 uint32_t tmp_ = RREG32_PLL(reg); \
2172 tmp_ |= ((val) & ~(mask)); \
2173 WREG32_PLL(reg, tmp_); \
2175 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2176 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2177 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2179 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2180 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2182 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2183 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2185 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2186 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2187 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2189 #define REG_GET_FIELD(value, reg, field) \
2190 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2195 #define RBIOS8(i) (adev->bios[i])
2196 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2197 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2202 static inline void amdgpu_ring_write(struct amdgpu_ring
*ring
, uint32_t v
)
2204 if (ring
->count_dw
<= 0)
2205 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2206 ring
->ring
[ring
->wptr
++] = v
;
2207 ring
->wptr
&= ring
->ptr_mask
;
2209 ring
->ring_free_dw
--;
2212 static inline struct amdgpu_sdma_instance
*
2213 amdgpu_get_sdma_instance(struct amdgpu_ring
*ring
)
2215 struct amdgpu_device
*adev
= ring
->adev
;
2218 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
2219 if (&adev
->sdma
.instance
[i
].ring
== ring
)
2222 if (i
< AMDGPU_MAX_SDMA_INSTANCES
)
2223 return &adev
->sdma
.instance
[i
];
2231 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2232 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2233 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2234 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2235 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2236 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2237 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2238 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2239 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2240 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2241 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2242 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2243 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2244 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2245 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2246 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2247 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2248 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2249 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2250 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2251 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2252 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2253 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2254 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2255 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2256 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2257 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2258 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2259 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2260 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2261 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2262 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2263 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2264 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2265 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2266 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2267 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2268 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2269 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2270 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2271 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2272 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2273 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2274 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2275 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2276 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2277 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2278 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
2279 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
2280 #define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev))
2281 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2282 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2283 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2284 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2285 #define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l))
2286 #define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l))
2287 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2288 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
2289 #define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
2290 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2291 #define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
2292 #define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g))
2293 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2294 #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
2295 #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
2296 #define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
2297 #define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
2299 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2301 /* Common functions */
2302 int amdgpu_gpu_reset(struct amdgpu_device
*adev
);
2303 void amdgpu_pci_config_reset(struct amdgpu_device
*adev
);
2304 bool amdgpu_card_posted(struct amdgpu_device
*adev
);
2305 void amdgpu_update_display_priority(struct amdgpu_device
*adev
);
2306 bool amdgpu_boot_test_post_card(struct amdgpu_device
*adev
);
2308 int amdgpu_cs_parser_init(struct amdgpu_cs_parser
*p
, void *data
);
2309 int amdgpu_cs_get_ring(struct amdgpu_device
*adev
, u32 ip_type
,
2310 u32 ip_instance
, u32 ring
,
2311 struct amdgpu_ring
**out_ring
);
2312 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo
*rbo
, u32 domain
);
2313 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object
*bo
);
2314 int amdgpu_ttm_tt_set_userptr(struct ttm_tt
*ttm
, uint64_t addr
,
2316 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt
*ttm
);
2317 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt
*ttm
);
2318 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device
*adev
, struct ttm_tt
*ttm
,
2319 struct ttm_mem_reg
*mem
);
2320 void amdgpu_vram_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
, u64 base
);
2321 void amdgpu_gtt_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
);
2322 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device
*adev
, u64 size
);
2323 void amdgpu_program_register_sequence(struct amdgpu_device
*adev
,
2324 const u32
*registers
,
2325 const u32 array_size
);
2327 bool amdgpu_device_is_px(struct drm_device
*dev
);
2329 #if defined(CONFIG_VGA_SWITCHEROO)
2330 void amdgpu_register_atpx_handler(void);
2331 void amdgpu_unregister_atpx_handler(void);
2333 static inline void amdgpu_register_atpx_handler(void) {}
2334 static inline void amdgpu_unregister_atpx_handler(void) {}
2340 extern const struct drm_ioctl_desc amdgpu_ioctls_kms
[];
2341 extern int amdgpu_max_kms_ioctl
;
2343 int amdgpu_driver_load_kms(struct drm_device
*dev
, unsigned long flags
);
2344 int amdgpu_driver_unload_kms(struct drm_device
*dev
);
2345 void amdgpu_driver_lastclose_kms(struct drm_device
*dev
);
2346 int amdgpu_driver_open_kms(struct drm_device
*dev
, struct drm_file
*file_priv
);
2347 void amdgpu_driver_postclose_kms(struct drm_device
*dev
,
2348 struct drm_file
*file_priv
);
2349 void amdgpu_driver_preclose_kms(struct drm_device
*dev
,
2350 struct drm_file
*file_priv
);
2351 int amdgpu_suspend_kms(struct drm_device
*dev
, bool suspend
, bool fbcon
);
2352 int amdgpu_resume_kms(struct drm_device
*dev
, bool resume
, bool fbcon
);
2353 u32
amdgpu_get_vblank_counter_kms(struct drm_device
*dev
, unsigned int pipe
);
2354 int amdgpu_enable_vblank_kms(struct drm_device
*dev
, unsigned int pipe
);
2355 void amdgpu_disable_vblank_kms(struct drm_device
*dev
, unsigned int pipe
);
2356 int amdgpu_get_vblank_timestamp_kms(struct drm_device
*dev
, unsigned int pipe
,
2358 struct timeval
*vblank_time
,
2360 long amdgpu_kms_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2364 * functions used by amdgpu_encoder.c
2366 struct amdgpu_afmt_acr
{
2380 struct amdgpu_afmt_acr
amdgpu_afmt_acr(uint32_t clock
);
2383 #if defined(CONFIG_ACPI)
2384 int amdgpu_acpi_init(struct amdgpu_device
*adev
);
2385 void amdgpu_acpi_fini(struct amdgpu_device
*adev
);
2386 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device
*adev
);
2387 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device
*adev
,
2388 u8 perf_req
, bool advertise
);
2389 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device
*adev
);
2391 static inline int amdgpu_acpi_init(struct amdgpu_device
*adev
) { return 0; }
2392 static inline void amdgpu_acpi_fini(struct amdgpu_device
*adev
) { }
2395 struct amdgpu_bo_va_mapping
*
2396 amdgpu_cs_find_mapping(struct amdgpu_cs_parser
*parser
,
2397 uint64_t addr
, struct amdgpu_bo
**bo
);
2399 #include "amdgpu_object.h"