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[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #ifdef pr_fmt
32 #undef pr_fmt
33 #endif
34
35 #define pr_fmt(fmt) "amdgpu: " fmt
36
37 #ifdef dev_fmt
38 #undef dev_fmt
39 #endif
40
41 #define dev_fmt(fmt) "amdgpu: " fmt
42
43 #include "amdgpu_ctx.h"
44
45 #include <linux/atomic.h>
46 #include <linux/wait.h>
47 #include <linux/list.h>
48 #include <linux/kref.h>
49 #include <linux/rbtree.h>
50 #include <linux/hashtable.h>
51 #include <linux/dma-fence.h>
52 #include <linux/pci.h>
53 #include <linux/aer.h>
54
55 #include <drm/ttm/ttm_bo_api.h>
56 #include <drm/ttm/ttm_bo_driver.h>
57 #include <drm/ttm/ttm_placement.h>
58 #include <drm/ttm/ttm_module.h>
59 #include <drm/ttm/ttm_execbuf_util.h>
60
61 #include <drm/amdgpu_drm.h>
62 #include <drm/drm_gem.h>
63 #include <drm/drm_ioctl.h>
64 #include <drm/gpu_scheduler.h>
65
66 #include <kgd_kfd_interface.h>
67 #include "dm_pp_interface.h"
68 #include "kgd_pp_interface.h"
69
70 #include "amd_shared.h"
71 #include "amdgpu_mode.h"
72 #include "amdgpu_ih.h"
73 #include "amdgpu_irq.h"
74 #include "amdgpu_ucode.h"
75 #include "amdgpu_ttm.h"
76 #include "amdgpu_psp.h"
77 #include "amdgpu_gds.h"
78 #include "amdgpu_sync.h"
79 #include "amdgpu_ring.h"
80 #include "amdgpu_vm.h"
81 #include "amdgpu_dpm.h"
82 #include "amdgpu_acp.h"
83 #include "amdgpu_uvd.h"
84 #include "amdgpu_vce.h"
85 #include "amdgpu_vcn.h"
86 #include "amdgpu_jpeg.h"
87 #include "amdgpu_mn.h"
88 #include "amdgpu_gmc.h"
89 #include "amdgpu_gfx.h"
90 #include "amdgpu_sdma.h"
91 #include "amdgpu_nbio.h"
92 #include "amdgpu_dm.h"
93 #include "amdgpu_virt.h"
94 #include "amdgpu_csa.h"
95 #include "amdgpu_gart.h"
96 #include "amdgpu_debugfs.h"
97 #include "amdgpu_job.h"
98 #include "amdgpu_bo_list.h"
99 #include "amdgpu_gem.h"
100 #include "amdgpu_doorbell.h"
101 #include "amdgpu_amdkfd.h"
102 #include "amdgpu_smu.h"
103 #include "amdgpu_discovery.h"
104 #include "amdgpu_mes.h"
105 #include "amdgpu_umc.h"
106 #include "amdgpu_mmhub.h"
107 #include "amdgpu_gfxhub.h"
108 #include "amdgpu_df.h"
109 #include "amdgpu_smuio.h"
110
111 #define MAX_GPU_INSTANCE 16
112
113 struct amdgpu_gpu_instance
114 {
115 struct amdgpu_device *adev;
116 int mgpu_fan_enabled;
117 };
118
119 struct amdgpu_mgpu_info
120 {
121 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
122 struct mutex mutex;
123 uint32_t num_gpu;
124 uint32_t num_dgpu;
125 uint32_t num_apu;
126 };
127
128 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
129
130 /*
131 * Modules parameters.
132 */
133 extern int amdgpu_modeset;
134 extern int amdgpu_vram_limit;
135 extern int amdgpu_vis_vram_limit;
136 extern int amdgpu_gart_size;
137 extern int amdgpu_gtt_size;
138 extern int amdgpu_moverate;
139 extern int amdgpu_benchmarking;
140 extern int amdgpu_testing;
141 extern int amdgpu_audio;
142 extern int amdgpu_disp_priority;
143 extern int amdgpu_hw_i2c;
144 extern int amdgpu_pcie_gen2;
145 extern int amdgpu_msi;
146 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
147 extern int amdgpu_dpm;
148 extern int amdgpu_fw_load_type;
149 extern int amdgpu_aspm;
150 extern int amdgpu_runtime_pm;
151 extern uint amdgpu_ip_block_mask;
152 extern int amdgpu_bapm;
153 extern int amdgpu_deep_color;
154 extern int amdgpu_vm_size;
155 extern int amdgpu_vm_block_size;
156 extern int amdgpu_vm_fragment_size;
157 extern int amdgpu_vm_fault_stop;
158 extern int amdgpu_vm_debug;
159 extern int amdgpu_vm_update_mode;
160 extern int amdgpu_exp_hw_support;
161 extern int amdgpu_dc;
162 extern int amdgpu_sched_jobs;
163 extern int amdgpu_sched_hw_submission;
164 extern uint amdgpu_pcie_gen_cap;
165 extern uint amdgpu_pcie_lane_cap;
166 extern uint amdgpu_cg_mask;
167 extern uint amdgpu_pg_mask;
168 extern uint amdgpu_sdma_phase_quantum;
169 extern char *amdgpu_disable_cu;
170 extern char *amdgpu_virtual_display;
171 extern uint amdgpu_pp_feature_mask;
172 extern uint amdgpu_force_long_training;
173 extern int amdgpu_job_hang_limit;
174 extern int amdgpu_lbpw;
175 extern int amdgpu_compute_multipipe;
176 extern int amdgpu_gpu_recovery;
177 extern int amdgpu_emu_mode;
178 extern uint amdgpu_smu_memory_pool_size;
179 extern uint amdgpu_dc_feature_mask;
180 extern uint amdgpu_dc_debug_mask;
181 extern uint amdgpu_dm_abm_level;
182 extern int amdgpu_backlight;
183 extern struct amdgpu_mgpu_info mgpu_info;
184 extern int amdgpu_ras_enable;
185 extern uint amdgpu_ras_mask;
186 extern int amdgpu_bad_page_threshold;
187 extern int amdgpu_async_gfx_ring;
188 extern int amdgpu_mcbp;
189 extern int amdgpu_discovery;
190 extern int amdgpu_mes;
191 extern int amdgpu_noretry;
192 extern int amdgpu_force_asic_type;
193 #ifdef CONFIG_HSA_AMD
194 extern int sched_policy;
195 extern bool debug_evictions;
196 extern bool no_system_mem_limit;
197 #else
198 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
199 static const bool __maybe_unused debug_evictions; /* = false */
200 static const bool __maybe_unused no_system_mem_limit;
201 #endif
202
203 extern int amdgpu_tmz;
204 extern int amdgpu_reset_method;
205
206 #ifdef CONFIG_DRM_AMDGPU_SI
207 extern int amdgpu_si_support;
208 #endif
209 #ifdef CONFIG_DRM_AMDGPU_CIK
210 extern int amdgpu_cik_support;
211 #endif
212 extern int amdgpu_num_kcq;
213
214 #define AMDGPU_VM_MAX_NUM_CTX 4096
215 #define AMDGPU_SG_THRESHOLD (256*1024*1024)
216 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
217 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
218 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
219 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
220 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
221 #define AMDGPUFB_CONN_LIMIT 4
222 #define AMDGPU_BIOS_NUM_SCRATCH 16
223
224 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
225
226 /* hard reset data */
227 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
228
229 /* reset flags */
230 #define AMDGPU_RESET_GFX (1 << 0)
231 #define AMDGPU_RESET_COMPUTE (1 << 1)
232 #define AMDGPU_RESET_DMA (1 << 2)
233 #define AMDGPU_RESET_CP (1 << 3)
234 #define AMDGPU_RESET_GRBM (1 << 4)
235 #define AMDGPU_RESET_DMA1 (1 << 5)
236 #define AMDGPU_RESET_RLC (1 << 6)
237 #define AMDGPU_RESET_SEM (1 << 7)
238 #define AMDGPU_RESET_IH (1 << 8)
239 #define AMDGPU_RESET_VMC (1 << 9)
240 #define AMDGPU_RESET_MC (1 << 10)
241 #define AMDGPU_RESET_DISPLAY (1 << 11)
242 #define AMDGPU_RESET_UVD (1 << 12)
243 #define AMDGPU_RESET_VCE (1 << 13)
244 #define AMDGPU_RESET_VCE1 (1 << 14)
245
246 /* max cursor sizes (in pixels) */
247 #define CIK_CURSOR_WIDTH 128
248 #define CIK_CURSOR_HEIGHT 128
249
250 struct amdgpu_device;
251 struct amdgpu_ib;
252 struct amdgpu_cs_parser;
253 struct amdgpu_job;
254 struct amdgpu_irq_src;
255 struct amdgpu_fpriv;
256 struct amdgpu_bo_va_mapping;
257 struct amdgpu_atif;
258 struct kfd_vm_fault_info;
259 struct amdgpu_hive_info;
260
261 enum amdgpu_cp_irq {
262 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
263 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
264 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
265 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
266 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
267 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
268 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
269 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
270 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
271 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
272
273 AMDGPU_CP_IRQ_LAST
274 };
275
276 enum amdgpu_thermal_irq {
277 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
278 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
279
280 AMDGPU_THERMAL_IRQ_LAST
281 };
282
283 enum amdgpu_kiq_irq {
284 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
285 AMDGPU_CP_KIQ_IRQ_LAST
286 };
287
288 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
289 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
290 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */
291
292 int amdgpu_device_ip_set_clockgating_state(void *dev,
293 enum amd_ip_block_type block_type,
294 enum amd_clockgating_state state);
295 int amdgpu_device_ip_set_powergating_state(void *dev,
296 enum amd_ip_block_type block_type,
297 enum amd_powergating_state state);
298 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
299 u32 *flags);
300 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
301 enum amd_ip_block_type block_type);
302 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
303 enum amd_ip_block_type block_type);
304
305 #define AMDGPU_MAX_IP_NUM 16
306
307 struct amdgpu_ip_block_status {
308 bool valid;
309 bool sw;
310 bool hw;
311 bool late_initialized;
312 bool hang;
313 };
314
315 struct amdgpu_ip_block_version {
316 const enum amd_ip_block_type type;
317 const u32 major;
318 const u32 minor;
319 const u32 rev;
320 const struct amd_ip_funcs *funcs;
321 };
322
323 #define HW_REV(_Major, _Minor, _Rev) \
324 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
325
326 struct amdgpu_ip_block {
327 struct amdgpu_ip_block_status status;
328 const struct amdgpu_ip_block_version *version;
329 };
330
331 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
332 enum amd_ip_block_type type,
333 u32 major, u32 minor);
334
335 struct amdgpu_ip_block *
336 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
337 enum amd_ip_block_type type);
338
339 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
340 const struct amdgpu_ip_block_version *ip_block_version);
341
342 /*
343 * BIOS.
344 */
345 bool amdgpu_get_bios(struct amdgpu_device *adev);
346 bool amdgpu_read_bios(struct amdgpu_device *adev);
347
348 /*
349 * Clocks
350 */
351
352 #define AMDGPU_MAX_PPLL 3
353
354 struct amdgpu_clock {
355 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
356 struct amdgpu_pll spll;
357 struct amdgpu_pll mpll;
358 /* 10 Khz units */
359 uint32_t default_mclk;
360 uint32_t default_sclk;
361 uint32_t default_dispclk;
362 uint32_t current_dispclk;
363 uint32_t dp_extclk;
364 uint32_t max_pixel_clock;
365 };
366
367 /* sub-allocation manager, it has to be protected by another lock.
368 * By conception this is an helper for other part of the driver
369 * like the indirect buffer or semaphore, which both have their
370 * locking.
371 *
372 * Principe is simple, we keep a list of sub allocation in offset
373 * order (first entry has offset == 0, last entry has the highest
374 * offset).
375 *
376 * When allocating new object we first check if there is room at
377 * the end total_size - (last_object_offset + last_object_size) >=
378 * alloc_size. If so we allocate new object there.
379 *
380 * When there is not enough room at the end, we start waiting for
381 * each sub object until we reach object_offset+object_size >=
382 * alloc_size, this object then become the sub object we return.
383 *
384 * Alignment can't be bigger than page size.
385 *
386 * Hole are not considered for allocation to keep things simple.
387 * Assumption is that there won't be hole (all object on same
388 * alignment).
389 */
390
391 #define AMDGPU_SA_NUM_FENCE_LISTS 32
392
393 struct amdgpu_sa_manager {
394 wait_queue_head_t wq;
395 struct amdgpu_bo *bo;
396 struct list_head *hole;
397 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
398 struct list_head olist;
399 unsigned size;
400 uint64_t gpu_addr;
401 void *cpu_ptr;
402 uint32_t domain;
403 uint32_t align;
404 };
405
406 /* sub-allocation buffer */
407 struct amdgpu_sa_bo {
408 struct list_head olist;
409 struct list_head flist;
410 struct amdgpu_sa_manager *manager;
411 unsigned soffset;
412 unsigned eoffset;
413 struct dma_fence *fence;
414 };
415
416 int amdgpu_fence_slab_init(void);
417 void amdgpu_fence_slab_fini(void);
418
419 /*
420 * IRQS.
421 */
422
423 struct amdgpu_flip_work {
424 struct delayed_work flip_work;
425 struct work_struct unpin_work;
426 struct amdgpu_device *adev;
427 int crtc_id;
428 u32 target_vblank;
429 uint64_t base;
430 struct drm_pending_vblank_event *event;
431 struct amdgpu_bo *old_abo;
432 struct dma_fence *excl;
433 unsigned shared_count;
434 struct dma_fence **shared;
435 struct dma_fence_cb cb;
436 bool async;
437 };
438
439
440 /*
441 * CP & rings.
442 */
443
444 struct amdgpu_ib {
445 struct amdgpu_sa_bo *sa_bo;
446 uint32_t length_dw;
447 uint64_t gpu_addr;
448 uint32_t *ptr;
449 uint32_t flags;
450 };
451
452 extern const struct drm_sched_backend_ops amdgpu_sched_ops;
453
454 /*
455 * file private structure
456 */
457
458 struct amdgpu_fpriv {
459 struct amdgpu_vm vm;
460 struct amdgpu_bo_va *prt_va;
461 struct amdgpu_bo_va *csa_va;
462 struct mutex bo_list_lock;
463 struct idr bo_list_handles;
464 struct amdgpu_ctx_mgr ctx_mgr;
465 };
466
467 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
468
469 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
470 unsigned size,
471 enum amdgpu_ib_pool_type pool,
472 struct amdgpu_ib *ib);
473 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
474 struct dma_fence *f);
475 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
476 struct amdgpu_ib *ibs, struct amdgpu_job *job,
477 struct dma_fence **f);
478 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
479 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
480 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
481
482 /*
483 * CS.
484 */
485 struct amdgpu_cs_chunk {
486 uint32_t chunk_id;
487 uint32_t length_dw;
488 void *kdata;
489 };
490
491 struct amdgpu_cs_post_dep {
492 struct drm_syncobj *syncobj;
493 struct dma_fence_chain *chain;
494 u64 point;
495 };
496
497 struct amdgpu_cs_parser {
498 struct amdgpu_device *adev;
499 struct drm_file *filp;
500 struct amdgpu_ctx *ctx;
501
502 /* chunks */
503 unsigned nchunks;
504 struct amdgpu_cs_chunk *chunks;
505
506 /* scheduler job object */
507 struct amdgpu_job *job;
508 struct drm_sched_entity *entity;
509
510 /* buffer objects */
511 struct ww_acquire_ctx ticket;
512 struct amdgpu_bo_list *bo_list;
513 struct amdgpu_mn *mn;
514 struct amdgpu_bo_list_entry vm_pd;
515 struct list_head validated;
516 struct dma_fence *fence;
517 uint64_t bytes_moved_threshold;
518 uint64_t bytes_moved_vis_threshold;
519 uint64_t bytes_moved;
520 uint64_t bytes_moved_vis;
521
522 /* user fence */
523 struct amdgpu_bo_list_entry uf_entry;
524
525 unsigned num_post_deps;
526 struct amdgpu_cs_post_dep *post_deps;
527 };
528
529 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
530 uint32_t ib_idx, int idx)
531 {
532 return p->job->ibs[ib_idx].ptr[idx];
533 }
534
535 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
536 uint32_t ib_idx, int idx,
537 uint32_t value)
538 {
539 p->job->ibs[ib_idx].ptr[idx] = value;
540 }
541
542 /*
543 * Writeback
544 */
545 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */
546
547 struct amdgpu_wb {
548 struct amdgpu_bo *wb_obj;
549 volatile uint32_t *wb;
550 uint64_t gpu_addr;
551 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
552 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
553 };
554
555 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
556 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
557
558 /*
559 * Benchmarking
560 */
561 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
562
563
564 /*
565 * Testing
566 */
567 void amdgpu_test_moves(struct amdgpu_device *adev);
568
569 /*
570 * ASIC specific register table accessible by UMD
571 */
572 struct amdgpu_allowed_register_entry {
573 uint32_t reg_offset;
574 bool grbm_indexed;
575 };
576
577 enum amd_reset_method {
578 AMD_RESET_METHOD_LEGACY = 0,
579 AMD_RESET_METHOD_MODE0,
580 AMD_RESET_METHOD_MODE1,
581 AMD_RESET_METHOD_MODE2,
582 AMD_RESET_METHOD_BACO
583 };
584
585 /*
586 * ASIC specific functions.
587 */
588 struct amdgpu_asic_funcs {
589 bool (*read_disabled_bios)(struct amdgpu_device *adev);
590 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
591 u8 *bios, u32 length_bytes);
592 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
593 u32 sh_num, u32 reg_offset, u32 *value);
594 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
595 int (*reset)(struct amdgpu_device *adev);
596 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
597 /* get the reference clock */
598 u32 (*get_xclk)(struct amdgpu_device *adev);
599 /* MM block clocks */
600 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
601 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
602 /* static power management */
603 int (*get_pcie_lanes)(struct amdgpu_device *adev);
604 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
605 /* get config memsize register */
606 u32 (*get_config_memsize)(struct amdgpu_device *adev);
607 /* flush hdp write queue */
608 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
609 /* invalidate hdp read cache */
610 void (*invalidate_hdp)(struct amdgpu_device *adev,
611 struct amdgpu_ring *ring);
612 void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev);
613 /* check if the asic needs a full reset of if soft reset will work */
614 bool (*need_full_reset)(struct amdgpu_device *adev);
615 /* initialize doorbell layout for specific asic*/
616 void (*init_doorbell_index)(struct amdgpu_device *adev);
617 /* PCIe bandwidth usage */
618 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
619 uint64_t *count1);
620 /* do we need to reset the asic at init time (e.g., kexec) */
621 bool (*need_reset_on_init)(struct amdgpu_device *adev);
622 /* PCIe replay counter */
623 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
624 /* device supports BACO */
625 bool (*supports_baco)(struct amdgpu_device *adev);
626 /* pre asic_init quirks */
627 void (*pre_asic_init)(struct amdgpu_device *adev);
628 /* enter/exit umd stable pstate */
629 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
630 };
631
632 /*
633 * IOCTL.
634 */
635 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
636 struct drm_file *filp);
637
638 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
639 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
640 struct drm_file *filp);
641 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
642 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
643 struct drm_file *filp);
644
645 /* VRAM scratch page for HDP bug, default vram page */
646 struct amdgpu_vram_scratch {
647 struct amdgpu_bo *robj;
648 volatile uint32_t *ptr;
649 u64 gpu_addr;
650 };
651
652 /*
653 * ACPI
654 */
655 struct amdgpu_atcs_functions {
656 bool get_ext_state;
657 bool pcie_perf_req;
658 bool pcie_dev_rdy;
659 bool pcie_bus_width;
660 };
661
662 struct amdgpu_atcs {
663 struct amdgpu_atcs_functions functions;
664 };
665
666 /*
667 * CGS
668 */
669 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
670 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
671
672 /*
673 * Core structure, functions and helpers.
674 */
675 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
676 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
677
678 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
679 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
680
681 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
682 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
683
684 struct amdgpu_mmio_remap {
685 u32 reg_offset;
686 resource_size_t bus_addr;
687 };
688
689 /* Define the HW IP blocks will be used in driver , add more if necessary */
690 enum amd_hw_ip_block_type {
691 GC_HWIP = 1,
692 HDP_HWIP,
693 SDMA0_HWIP,
694 SDMA1_HWIP,
695 SDMA2_HWIP,
696 SDMA3_HWIP,
697 SDMA4_HWIP,
698 SDMA5_HWIP,
699 SDMA6_HWIP,
700 SDMA7_HWIP,
701 MMHUB_HWIP,
702 ATHUB_HWIP,
703 NBIO_HWIP,
704 MP0_HWIP,
705 MP1_HWIP,
706 UVD_HWIP,
707 VCN_HWIP = UVD_HWIP,
708 JPEG_HWIP = VCN_HWIP,
709 VCE_HWIP,
710 DF_HWIP,
711 DCE_HWIP,
712 OSSSYS_HWIP,
713 SMUIO_HWIP,
714 PWR_HWIP,
715 NBIF_HWIP,
716 THM_HWIP,
717 CLK_HWIP,
718 UMC_HWIP,
719 RSMU_HWIP,
720 MAX_HWIP
721 };
722
723 #define HWIP_MAX_INSTANCE 8
724
725 struct amd_powerplay {
726 void *pp_handle;
727 const struct amd_pm_funcs *pp_funcs;
728 };
729
730 /* polaris10 kickers */
731 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
732 ((rid == 0xE3) || \
733 (rid == 0xE4) || \
734 (rid == 0xE5) || \
735 (rid == 0xE7) || \
736 (rid == 0xEF))) || \
737 ((did == 0x6FDF) && \
738 ((rid == 0xE7) || \
739 (rid == 0xEF) || \
740 (rid == 0xFF))))
741
742 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \
743 ((rid == 0xE1) || \
744 (rid == 0xF7)))
745
746 /* polaris11 kickers */
747 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \
748 ((rid == 0xE0) || \
749 (rid == 0xE5))) || \
750 ((did == 0x67FF) && \
751 ((rid == 0xCF) || \
752 (rid == 0xEF) || \
753 (rid == 0xFF))))
754
755 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \
756 ((rid == 0xE2)))
757
758 /* polaris12 kickers */
759 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \
760 ((rid == 0xC0) || \
761 (rid == 0xC1) || \
762 (rid == 0xC3) || \
763 (rid == 0xC7))) || \
764 ((did == 0x6981) && \
765 ((rid == 0x00) || \
766 (rid == 0x01) || \
767 (rid == 0x10))))
768
769 #define AMDGPU_RESET_MAGIC_NUM 64
770 #define AMDGPU_MAX_DF_PERFMONS 4
771 struct amdgpu_device {
772 struct device *dev;
773 struct pci_dev *pdev;
774 struct drm_device ddev;
775
776 #ifdef CONFIG_DRM_AMD_ACP
777 struct amdgpu_acp acp;
778 #endif
779 struct amdgpu_hive_info *hive;
780 /* ASIC */
781 enum amd_asic_type asic_type;
782 uint32_t family;
783 uint32_t rev_id;
784 uint32_t external_rev_id;
785 unsigned long flags;
786 unsigned long apu_flags;
787 int usec_timeout;
788 const struct amdgpu_asic_funcs *asic_funcs;
789 bool shutdown;
790 bool need_swiotlb;
791 bool accel_working;
792 struct notifier_block acpi_nb;
793 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
794 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
795 unsigned debugfs_count;
796 #if defined(CONFIG_DEBUG_FS)
797 struct dentry *debugfs_preempt;
798 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
799 #endif
800 struct amdgpu_atif *atif;
801 struct amdgpu_atcs atcs;
802 struct mutex srbm_mutex;
803 /* GRBM index mutex. Protects concurrent access to GRBM index */
804 struct mutex grbm_idx_mutex;
805 struct dev_pm_domain vga_pm_domain;
806 bool have_disp_power_ref;
807 bool have_atomics_support;
808
809 /* BIOS */
810 bool is_atom_fw;
811 uint8_t *bios;
812 uint32_t bios_size;
813 uint32_t bios_scratch_reg_offset;
814 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
815
816 /* Register/doorbell mmio */
817 resource_size_t rmmio_base;
818 resource_size_t rmmio_size;
819 void __iomem *rmmio;
820 /* protects concurrent MM_INDEX/DATA based register access */
821 spinlock_t mmio_idx_lock;
822 struct amdgpu_mmio_remap rmmio_remap;
823 /* protects concurrent SMC based register access */
824 spinlock_t smc_idx_lock;
825 amdgpu_rreg_t smc_rreg;
826 amdgpu_wreg_t smc_wreg;
827 /* protects concurrent PCIE register access */
828 spinlock_t pcie_idx_lock;
829 amdgpu_rreg_t pcie_rreg;
830 amdgpu_wreg_t pcie_wreg;
831 amdgpu_rreg_t pciep_rreg;
832 amdgpu_wreg_t pciep_wreg;
833 amdgpu_rreg64_t pcie_rreg64;
834 amdgpu_wreg64_t pcie_wreg64;
835 /* protects concurrent UVD register access */
836 spinlock_t uvd_ctx_idx_lock;
837 amdgpu_rreg_t uvd_ctx_rreg;
838 amdgpu_wreg_t uvd_ctx_wreg;
839 /* protects concurrent DIDT register access */
840 spinlock_t didt_idx_lock;
841 amdgpu_rreg_t didt_rreg;
842 amdgpu_wreg_t didt_wreg;
843 /* protects concurrent gc_cac register access */
844 spinlock_t gc_cac_idx_lock;
845 amdgpu_rreg_t gc_cac_rreg;
846 amdgpu_wreg_t gc_cac_wreg;
847 /* protects concurrent se_cac register access */
848 spinlock_t se_cac_idx_lock;
849 amdgpu_rreg_t se_cac_rreg;
850 amdgpu_wreg_t se_cac_wreg;
851 /* protects concurrent ENDPOINT (audio) register access */
852 spinlock_t audio_endpt_idx_lock;
853 amdgpu_block_rreg_t audio_endpt_rreg;
854 amdgpu_block_wreg_t audio_endpt_wreg;
855 void __iomem *rio_mem;
856 resource_size_t rio_mem_size;
857 struct amdgpu_doorbell doorbell;
858
859 /* clock/pll info */
860 struct amdgpu_clock clock;
861
862 /* MC */
863 struct amdgpu_gmc gmc;
864 struct amdgpu_gart gart;
865 dma_addr_t dummy_page_addr;
866 struct amdgpu_vm_manager vm_manager;
867 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
868 unsigned num_vmhubs;
869
870 /* memory management */
871 struct amdgpu_mman mman;
872 struct amdgpu_vram_scratch vram_scratch;
873 struct amdgpu_wb wb;
874 atomic64_t num_bytes_moved;
875 atomic64_t num_evictions;
876 atomic64_t num_vram_cpu_page_faults;
877 atomic_t gpu_reset_counter;
878 atomic_t vram_lost_counter;
879
880 /* data for buffer migration throttling */
881 struct {
882 spinlock_t lock;
883 s64 last_update_us;
884 s64 accum_us; /* accumulated microseconds */
885 s64 accum_us_vis; /* for visible VRAM */
886 u32 log2_max_MBps;
887 } mm_stats;
888
889 /* display */
890 bool enable_virtual_display;
891 struct amdgpu_mode_info mode_info;
892 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
893 struct work_struct hotplug_work;
894 struct amdgpu_irq_src crtc_irq;
895 struct amdgpu_irq_src vupdate_irq;
896 struct amdgpu_irq_src pageflip_irq;
897 struct amdgpu_irq_src hpd_irq;
898
899 /* rings */
900 u64 fence_context;
901 unsigned num_rings;
902 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
903 bool ib_pool_ready;
904 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
905 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
906
907 /* interrupts */
908 struct amdgpu_irq irq;
909
910 /* powerplay */
911 struct amd_powerplay powerplay;
912 bool pp_force_state_enabled;
913
914 /* smu */
915 struct smu_context smu;
916
917 /* dpm */
918 struct amdgpu_pm pm;
919 u32 cg_flags;
920 u32 pg_flags;
921
922 /* nbio */
923 struct amdgpu_nbio nbio;
924
925 /* smuio */
926 struct amdgpu_smuio smuio;
927
928 /* mmhub */
929 struct amdgpu_mmhub mmhub;
930
931 /* gfxhub */
932 struct amdgpu_gfxhub gfxhub;
933
934 /* gfx */
935 struct amdgpu_gfx gfx;
936
937 /* sdma */
938 struct amdgpu_sdma sdma;
939
940 /* uvd */
941 struct amdgpu_uvd uvd;
942
943 /* vce */
944 struct amdgpu_vce vce;
945
946 /* vcn */
947 struct amdgpu_vcn vcn;
948
949 /* jpeg */
950 struct amdgpu_jpeg jpeg;
951
952 /* firmwares */
953 struct amdgpu_firmware firmware;
954
955 /* PSP */
956 struct psp_context psp;
957
958 /* GDS */
959 struct amdgpu_gds gds;
960
961 /* KFD */
962 struct amdgpu_kfd_dev kfd;
963
964 /* UMC */
965 struct amdgpu_umc umc;
966
967 /* display related functionality */
968 struct amdgpu_display_manager dm;
969
970 /* mes */
971 bool enable_mes;
972 struct amdgpu_mes mes;
973
974 /* df */
975 struct amdgpu_df df;
976
977 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
978 int num_ip_blocks;
979 struct mutex mn_lock;
980 DECLARE_HASHTABLE(mn_hash, 7);
981
982 /* tracking pinned memory */
983 atomic64_t vram_pin_size;
984 atomic64_t visible_pin_size;
985 atomic64_t gart_pin_size;
986
987 /* soc15 register offset based on ip, instance and segment */
988 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
989
990 /* delayed work_func for deferring clockgating during resume */
991 struct delayed_work delayed_init_work;
992
993 struct amdgpu_virt virt;
994
995 /* link all shadow bo */
996 struct list_head shadow_list;
997 struct mutex shadow_list_lock;
998
999 /* record hw reset is performed */
1000 bool has_hw_reset;
1001 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
1002
1003 /* s3/s4 mask */
1004 bool in_suspend;
1005 bool in_hibernate;
1006
1007 /*
1008 * The combination flag in_poweroff_reboot_com used to identify the poweroff
1009 * and reboot opt in the s0i3 system-wide suspend.
1010 */
1011 bool in_poweroff_reboot_com;
1012
1013 atomic_t in_gpu_reset;
1014 enum pp_mp1_state mp1_state;
1015 struct rw_semaphore reset_sem;
1016 struct amdgpu_doorbell_index doorbell_index;
1017
1018 struct mutex notifier_lock;
1019
1020 int asic_reset_res;
1021 struct work_struct xgmi_reset_work;
1022
1023 long gfx_timeout;
1024 long sdma_timeout;
1025 long video_timeout;
1026 long compute_timeout;
1027
1028 uint64_t unique_id;
1029 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1030
1031 /* enable runtime pm on the device */
1032 bool runpm;
1033 bool in_runpm;
1034 bool has_pr3;
1035
1036 bool pm_sysfs_en;
1037 bool ucode_sysfs_en;
1038
1039 /* Chip product information */
1040 char product_number[16];
1041 char product_name[32];
1042 char serial[20];
1043
1044 struct amdgpu_autodump autodump;
1045
1046 atomic_t throttling_logging_enabled;
1047 struct ratelimit_state throttling_logging_rs;
1048 uint32_t ras_features;
1049
1050 bool in_pci_err_recovery;
1051 struct pci_saved_state *pci_state;
1052 };
1053
1054 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1055 {
1056 return container_of(ddev, struct amdgpu_device, ddev);
1057 }
1058
1059 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1060 {
1061 return &adev->ddev;
1062 }
1063
1064 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1065 {
1066 return container_of(bdev, struct amdgpu_device, mman.bdev);
1067 }
1068
1069 int amdgpu_device_init(struct amdgpu_device *adev,
1070 uint32_t flags);
1071 void amdgpu_device_fini(struct amdgpu_device *adev);
1072 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1073
1074 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1075 uint32_t *buf, size_t size, bool write);
1076 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1077 uint32_t reg, uint32_t acc_flags);
1078 void amdgpu_device_wreg(struct amdgpu_device *adev,
1079 uint32_t reg, uint32_t v,
1080 uint32_t acc_flags);
1081 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1082 uint32_t reg, uint32_t v);
1083 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1084 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1085
1086 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1087 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1088
1089 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1090 u32 pcie_index, u32 pcie_data,
1091 u32 reg_addr);
1092 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1093 u32 pcie_index, u32 pcie_data,
1094 u32 reg_addr);
1095 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1096 u32 pcie_index, u32 pcie_data,
1097 u32 reg_addr, u32 reg_data);
1098 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1099 u32 pcie_index, u32 pcie_data,
1100 u32 reg_addr, u64 reg_data);
1101
1102 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1103 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1104
1105 int emu_soc_asic_init(struct amdgpu_device *adev);
1106
1107 /*
1108 * Registers read & write functions.
1109 */
1110 #define AMDGPU_REGS_NO_KIQ (1<<1)
1111
1112 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1113 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1114
1115 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1116 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1117
1118 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1119 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1120
1121 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1122 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1123 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1124 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1125 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1126 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1127 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1128 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1129 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1130 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1131 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1132 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1133 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1134 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1135 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1136 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1137 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1138 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1139 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1140 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1141 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1142 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1143 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1144 #define WREG32_P(reg, val, mask) \
1145 do { \
1146 uint32_t tmp_ = RREG32(reg); \
1147 tmp_ &= (mask); \
1148 tmp_ |= ((val) & ~(mask)); \
1149 WREG32(reg, tmp_); \
1150 } while (0)
1151 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1152 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1153 #define WREG32_PLL_P(reg, val, mask) \
1154 do { \
1155 uint32_t tmp_ = RREG32_PLL(reg); \
1156 tmp_ &= (mask); \
1157 tmp_ |= ((val) & ~(mask)); \
1158 WREG32_PLL(reg, tmp_); \
1159 } while (0)
1160
1161 #define WREG32_SMC_P(_Reg, _Val, _Mask) \
1162 do { \
1163 u32 tmp = RREG32_SMC(_Reg); \
1164 tmp &= (_Mask); \
1165 tmp |= ((_Val) & ~(_Mask)); \
1166 WREG32_SMC(_Reg, tmp); \
1167 } while (0)
1168
1169 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1170 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1171 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1172
1173 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1174 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1175
1176 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
1177 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1178 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1179
1180 #define REG_GET_FIELD(value, reg, field) \
1181 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1182
1183 #define WREG32_FIELD(reg, field, val) \
1184 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1185
1186 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1187 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1188
1189 /*
1190 * BIOS helpers.
1191 */
1192 #define RBIOS8(i) (adev->bios[i])
1193 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1194 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1195
1196 /*
1197 * ASICs macro.
1198 */
1199 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1200 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1201 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1202 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1203 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1204 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1205 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1206 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1207 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1208 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1209 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1210 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1211 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1212 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
1213 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
1214 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1215 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1216 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1217 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1218 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1219 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1220 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1221 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1222 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1223
1224 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1225
1226 /* Common functions */
1227 bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1228 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1229 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1230 struct amdgpu_job* job);
1231 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1232 bool amdgpu_device_need_post(struct amdgpu_device *adev);
1233
1234 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1235 u64 num_vis_bytes);
1236 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1237 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1238 const u32 *registers,
1239 const u32 array_size);
1240
1241 bool amdgpu_device_supports_atpx(struct drm_device *dev);
1242 bool amdgpu_device_supports_boco(struct drm_device *dev);
1243 bool amdgpu_device_supports_baco(struct drm_device *dev);
1244 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1245 struct amdgpu_device *peer_adev);
1246 int amdgpu_device_baco_enter(struct drm_device *dev);
1247 int amdgpu_device_baco_exit(struct drm_device *dev);
1248
1249 /* atpx handler */
1250 #if defined(CONFIG_VGA_SWITCHEROO)
1251 void amdgpu_register_atpx_handler(void);
1252 void amdgpu_unregister_atpx_handler(void);
1253 bool amdgpu_has_atpx_dgpu_power_cntl(void);
1254 bool amdgpu_is_atpx_hybrid(void);
1255 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1256 bool amdgpu_has_atpx(void);
1257 #else
1258 static inline void amdgpu_register_atpx_handler(void) {}
1259 static inline void amdgpu_unregister_atpx_handler(void) {}
1260 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1261 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1262 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1263 static inline bool amdgpu_has_atpx(void) { return false; }
1264 #endif
1265
1266 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1267 void *amdgpu_atpx_get_dhandle(void);
1268 #else
1269 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1270 #endif
1271
1272 /*
1273 * KMS
1274 */
1275 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1276 extern const int amdgpu_max_kms_ioctl;
1277
1278 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1279 void amdgpu_driver_unload_kms(struct drm_device *dev);
1280 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1281 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1282 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1283 struct drm_file *file_priv);
1284 int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1285 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1286 int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1287 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1288 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1289 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1290 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1291 unsigned long arg);
1292 int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1293 struct drm_file *filp);
1294
1295 /*
1296 * functions used by amdgpu_encoder.c
1297 */
1298 struct amdgpu_afmt_acr {
1299 u32 clock;
1300
1301 int n_32khz;
1302 int cts_32khz;
1303
1304 int n_44_1khz;
1305 int cts_44_1khz;
1306
1307 int n_48khz;
1308 int cts_48khz;
1309
1310 };
1311
1312 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1313
1314 /* amdgpu_acpi.c */
1315 #if defined(CONFIG_ACPI)
1316 int amdgpu_acpi_init(struct amdgpu_device *adev);
1317 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1318 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1319 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1320 u8 perf_req, bool advertise);
1321 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1322
1323 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
1324 struct amdgpu_dm_backlight_caps *caps);
1325 bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev);
1326 #else
1327 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1328 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1329 static inline bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) { return false; }
1330 #endif
1331
1332 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1333 uint64_t addr, struct amdgpu_bo **bo,
1334 struct amdgpu_bo_va_mapping **mapping);
1335
1336 #if defined(CONFIG_DRM_AMD_DC)
1337 int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1338 #else
1339 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1340 #endif
1341
1342
1343 void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1344 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1345
1346 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1347 pci_channel_state_t state);
1348 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1349 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1350 void amdgpu_pci_resume(struct pci_dev *pdev);
1351
1352 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1353 bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1354
1355 #include "amdgpu_object.h"
1356
1357 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1358 {
1359 return adev->gmc.tmz_enabled;
1360 }
1361
1362 static inline int amdgpu_in_reset(struct amdgpu_device *adev)
1363 {
1364 return atomic_read(&adev->in_gpu_reset);
1365 }
1366 #endif
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