2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/rbtree.h>
36 #include <linux/hashtable.h>
37 #include <linux/dma-fence.h>
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_ttm.h"
55 #include "amdgpu_psp.h"
56 #include "amdgpu_gds.h"
57 #include "amdgpu_sync.h"
58 #include "amdgpu_ring.h"
59 #include "amdgpu_vm.h"
60 #include "amd_powerplay.h"
61 #include "amdgpu_dpm.h"
62 #include "amdgpu_acp.h"
63 #include "amdgpu_uvd.h"
64 #include "amdgpu_vce.h"
66 #include "gpu_scheduler.h"
67 #include "amdgpu_virt.h"
72 extern int amdgpu_modeset
;
73 extern int amdgpu_vram_limit
;
74 extern int amdgpu_gart_size
;
75 extern int amdgpu_moverate
;
76 extern int amdgpu_benchmarking
;
77 extern int amdgpu_testing
;
78 extern int amdgpu_audio
;
79 extern int amdgpu_disp_priority
;
80 extern int amdgpu_hw_i2c
;
81 extern int amdgpu_pcie_gen2
;
82 extern int amdgpu_msi
;
83 extern int amdgpu_lockup_timeout
;
84 extern int amdgpu_dpm
;
85 extern int amdgpu_fw_load_type
;
86 extern int amdgpu_aspm
;
87 extern int amdgpu_runtime_pm
;
88 extern unsigned amdgpu_ip_block_mask
;
89 extern int amdgpu_bapm
;
90 extern int amdgpu_deep_color
;
91 extern int amdgpu_vm_size
;
92 extern int amdgpu_vm_block_size
;
93 extern int amdgpu_vm_fault_stop
;
94 extern int amdgpu_vm_debug
;
95 extern int amdgpu_sched_jobs
;
96 extern int amdgpu_sched_hw_submission
;
97 extern int amdgpu_no_evict
;
98 extern int amdgpu_direct_gma_size
;
99 extern unsigned amdgpu_pcie_gen_cap
;
100 extern unsigned amdgpu_pcie_lane_cap
;
101 extern unsigned amdgpu_cg_mask
;
102 extern unsigned amdgpu_pg_mask
;
103 extern char *amdgpu_disable_cu
;
104 extern char *amdgpu_virtual_display
;
105 extern unsigned amdgpu_pp_feature_mask
;
106 extern int amdgpu_vram_page_split
;
107 extern int amdgpu_ngg
;
108 extern int amdgpu_prim_buf_per_se
;
109 extern int amdgpu_pos_buf_per_se
;
110 extern int amdgpu_cntl_sb_buf_per_se
;
111 extern int amdgpu_param_buf_per_se
;
113 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
114 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
115 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
116 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
117 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
118 #define AMDGPU_IB_POOL_SIZE 16
119 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
120 #define AMDGPUFB_CONN_LIMIT 4
121 #define AMDGPU_BIOS_NUM_SCRATCH 16
123 /* max number of IP instances */
124 #define AMDGPU_MAX_SDMA_INSTANCES 2
126 /* hard reset data */
127 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
130 #define AMDGPU_RESET_GFX (1 << 0)
131 #define AMDGPU_RESET_COMPUTE (1 << 1)
132 #define AMDGPU_RESET_DMA (1 << 2)
133 #define AMDGPU_RESET_CP (1 << 3)
134 #define AMDGPU_RESET_GRBM (1 << 4)
135 #define AMDGPU_RESET_DMA1 (1 << 5)
136 #define AMDGPU_RESET_RLC (1 << 6)
137 #define AMDGPU_RESET_SEM (1 << 7)
138 #define AMDGPU_RESET_IH (1 << 8)
139 #define AMDGPU_RESET_VMC (1 << 9)
140 #define AMDGPU_RESET_MC (1 << 10)
141 #define AMDGPU_RESET_DISPLAY (1 << 11)
142 #define AMDGPU_RESET_UVD (1 << 12)
143 #define AMDGPU_RESET_VCE (1 << 13)
144 #define AMDGPU_RESET_VCE1 (1 << 14)
146 /* GFX current status */
147 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
148 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
149 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
150 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
151 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
153 /* max cursor sizes (in pixels) */
154 #define CIK_CURSOR_WIDTH 128
155 #define CIK_CURSOR_HEIGHT 128
157 struct amdgpu_device
;
159 struct amdgpu_cs_parser
;
161 struct amdgpu_irq_src
;
165 AMDGPU_CP_IRQ_GFX_EOP
= 0,
166 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
,
167 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP
,
168 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP
,
169 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP
,
170 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP
,
171 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP
,
172 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP
,
173 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP
,
178 enum amdgpu_sdma_irq
{
179 AMDGPU_SDMA_IRQ_TRAP0
= 0,
180 AMDGPU_SDMA_IRQ_TRAP1
,
185 enum amdgpu_thermal_irq
{
186 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH
= 0,
187 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW
,
189 AMDGPU_THERMAL_IRQ_LAST
192 enum amdgpu_kiq_irq
{
193 AMDGPU_CP_KIQ_IRQ_DRIVER0
= 0,
194 AMDGPU_CP_KIQ_IRQ_LAST
197 int amdgpu_set_clockgating_state(struct amdgpu_device
*adev
,
198 enum amd_ip_block_type block_type
,
199 enum amd_clockgating_state state
);
200 int amdgpu_set_powergating_state(struct amdgpu_device
*adev
,
201 enum amd_ip_block_type block_type
,
202 enum amd_powergating_state state
);
203 void amdgpu_get_clockgating_state(struct amdgpu_device
*adev
, u32
*flags
);
204 int amdgpu_wait_for_idle(struct amdgpu_device
*adev
,
205 enum amd_ip_block_type block_type
);
206 bool amdgpu_is_idle(struct amdgpu_device
*adev
,
207 enum amd_ip_block_type block_type
);
209 #define AMDGPU_MAX_IP_NUM 16
211 struct amdgpu_ip_block_status
{
215 bool late_initialized
;
219 struct amdgpu_ip_block_version
{
220 const enum amd_ip_block_type type
;
224 const struct amd_ip_funcs
*funcs
;
227 struct amdgpu_ip_block
{
228 struct amdgpu_ip_block_status status
;
229 const struct amdgpu_ip_block_version
*version
;
232 int amdgpu_ip_block_version_cmp(struct amdgpu_device
*adev
,
233 enum amd_ip_block_type type
,
234 u32 major
, u32 minor
);
236 struct amdgpu_ip_block
* amdgpu_get_ip_block(struct amdgpu_device
*adev
,
237 enum amd_ip_block_type type
);
239 int amdgpu_ip_block_add(struct amdgpu_device
*adev
,
240 const struct amdgpu_ip_block_version
*ip_block_version
);
242 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
243 struct amdgpu_buffer_funcs
{
244 /* maximum bytes in a single operation */
245 uint32_t copy_max_bytes
;
247 /* number of dw to reserve per operation */
248 unsigned copy_num_dw
;
250 /* used for buffer migration */
251 void (*emit_copy_buffer
)(struct amdgpu_ib
*ib
,
252 /* src addr in bytes */
254 /* dst addr in bytes */
256 /* number of byte to transfer */
257 uint32_t byte_count
);
259 /* maximum bytes in a single operation */
260 uint32_t fill_max_bytes
;
262 /* number of dw to reserve per operation */
263 unsigned fill_num_dw
;
265 /* used for buffer clearing */
266 void (*emit_fill_buffer
)(struct amdgpu_ib
*ib
,
267 /* value to write to memory */
269 /* dst addr in bytes */
271 /* number of byte to fill */
272 uint32_t byte_count
);
275 /* provided by hw blocks that can write ptes, e.g., sdma */
276 struct amdgpu_vm_pte_funcs
{
277 /* copy pte entries from GART */
278 void (*copy_pte
)(struct amdgpu_ib
*ib
,
279 uint64_t pe
, uint64_t src
,
281 /* write pte one entry at a time with addr mapping */
282 void (*write_pte
)(struct amdgpu_ib
*ib
, uint64_t pe
,
283 uint64_t value
, unsigned count
,
285 /* for linear pte/pde updates without addr mapping */
286 void (*set_pte_pde
)(struct amdgpu_ib
*ib
,
288 uint64_t addr
, unsigned count
,
289 uint32_t incr
, uint64_t flags
);
292 /* provided by the gmc block */
293 struct amdgpu_gart_funcs
{
294 /* flush the vm tlb via mmio */
295 void (*flush_gpu_tlb
)(struct amdgpu_device
*adev
,
297 /* write pte/pde updates using the cpu */
298 int (*set_pte_pde
)(struct amdgpu_device
*adev
,
299 void *cpu_pt_addr
, /* cpu addr of page table */
300 uint32_t gpu_page_idx
, /* pte/pde to update */
301 uint64_t addr
, /* addr to write into pte/pde */
302 uint64_t flags
); /* access flags */
303 /* enable/disable PRT support */
304 void (*set_prt
)(struct amdgpu_device
*adev
, bool enable
);
305 /* set pte flags based per asic */
306 uint64_t (*get_vm_pte_flags
)(struct amdgpu_device
*adev
,
308 /* adjust mc addr in fb for APU case */
309 u64 (*adjust_mc_addr
)(struct amdgpu_device
*adev
, u64 addr
);
310 uint32_t (*get_invalidate_req
)(unsigned int vm_id
);
313 /* provided by the ih block */
314 struct amdgpu_ih_funcs
{
315 /* ring read/write ptr handling, called from interrupt context */
316 u32 (*get_wptr
)(struct amdgpu_device
*adev
);
317 void (*decode_iv
)(struct amdgpu_device
*adev
,
318 struct amdgpu_iv_entry
*entry
);
319 void (*set_rptr
)(struct amdgpu_device
*adev
);
325 bool amdgpu_get_bios(struct amdgpu_device
*adev
);
326 bool amdgpu_read_bios(struct amdgpu_device
*adev
);
331 struct amdgpu_dummy_page
{
335 int amdgpu_dummy_page_init(struct amdgpu_device
*adev
);
336 void amdgpu_dummy_page_fini(struct amdgpu_device
*adev
);
343 #define AMDGPU_MAX_PPLL 3
345 struct amdgpu_clock
{
346 struct amdgpu_pll ppll
[AMDGPU_MAX_PPLL
];
347 struct amdgpu_pll spll
;
348 struct amdgpu_pll mpll
;
350 uint32_t default_mclk
;
351 uint32_t default_sclk
;
352 uint32_t default_dispclk
;
353 uint32_t current_dispclk
;
355 uint32_t max_pixel_clock
;
361 struct amdgpu_bo_list_entry
{
362 struct amdgpu_bo
*robj
;
363 struct ttm_validate_buffer tv
;
364 struct amdgpu_bo_va
*bo_va
;
366 struct page
**user_pages
;
367 int user_invalidated
;
370 struct amdgpu_bo_va_mapping
{
371 struct list_head list
;
375 uint64_t __subtree_last
;
380 /* bo virtual addresses in a specific vm */
381 struct amdgpu_bo_va
{
382 /* protected by bo being reserved */
383 struct list_head bo_list
;
384 struct dma_fence
*last_pt_update
;
387 /* protected by vm mutex and spinlock */
388 struct list_head vm_status
;
390 /* mappings for this bo_va */
391 struct list_head invalids
;
392 struct list_head valids
;
394 /* constant after initialization */
395 struct amdgpu_vm
*vm
;
396 struct amdgpu_bo
*bo
;
399 #define AMDGPU_GEM_DOMAIN_MAX 0x3
402 /* Protected by tbo.reserved */
403 u32 prefered_domains
;
405 struct ttm_place placements
[AMDGPU_GEM_DOMAIN_MAX
+ 1];
406 struct ttm_placement placement
;
407 struct ttm_buffer_object tbo
;
408 struct ttm_bo_kmap_obj kmap
;
416 unsigned prime_shared_count
;
417 /* list of all virtual address to which this bo
421 /* Constant after initialization */
422 struct drm_gem_object gem_base
;
423 struct amdgpu_bo
*parent
;
424 struct amdgpu_bo
*shadow
;
426 struct ttm_bo_kmap_obj dma_buf_vmap
;
427 struct amdgpu_mn
*mn
;
428 struct list_head mn_list
;
429 struct list_head shadow_list
;
431 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
433 void amdgpu_gem_object_free(struct drm_gem_object
*obj
);
434 int amdgpu_gem_object_open(struct drm_gem_object
*obj
,
435 struct drm_file
*file_priv
);
436 void amdgpu_gem_object_close(struct drm_gem_object
*obj
,
437 struct drm_file
*file_priv
);
438 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns
);
439 struct sg_table
*amdgpu_gem_prime_get_sg_table(struct drm_gem_object
*obj
);
440 struct drm_gem_object
*
441 amdgpu_gem_prime_import_sg_table(struct drm_device
*dev
,
442 struct dma_buf_attachment
*attach
,
443 struct sg_table
*sg
);
444 struct dma_buf
*amdgpu_gem_prime_export(struct drm_device
*dev
,
445 struct drm_gem_object
*gobj
,
447 int amdgpu_gem_prime_pin(struct drm_gem_object
*obj
);
448 void amdgpu_gem_prime_unpin(struct drm_gem_object
*obj
);
449 struct reservation_object
*amdgpu_gem_prime_res_obj(struct drm_gem_object
*);
450 void *amdgpu_gem_prime_vmap(struct drm_gem_object
*obj
);
451 void amdgpu_gem_prime_vunmap(struct drm_gem_object
*obj
, void *vaddr
);
452 int amdgpu_gem_debugfs_init(struct amdgpu_device
*adev
);
454 /* sub-allocation manager, it has to be protected by another lock.
455 * By conception this is an helper for other part of the driver
456 * like the indirect buffer or semaphore, which both have their
459 * Principe is simple, we keep a list of sub allocation in offset
460 * order (first entry has offset == 0, last entry has the highest
463 * When allocating new object we first check if there is room at
464 * the end total_size - (last_object_offset + last_object_size) >=
465 * alloc_size. If so we allocate new object there.
467 * When there is not enough room at the end, we start waiting for
468 * each sub object until we reach object_offset+object_size >=
469 * alloc_size, this object then become the sub object we return.
471 * Alignment can't be bigger than page size.
473 * Hole are not considered for allocation to keep things simple.
474 * Assumption is that there won't be hole (all object on same
478 #define AMDGPU_SA_NUM_FENCE_LISTS 32
480 struct amdgpu_sa_manager
{
481 wait_queue_head_t wq
;
482 struct amdgpu_bo
*bo
;
483 struct list_head
*hole
;
484 struct list_head flist
[AMDGPU_SA_NUM_FENCE_LISTS
];
485 struct list_head olist
;
493 /* sub-allocation buffer */
494 struct amdgpu_sa_bo
{
495 struct list_head olist
;
496 struct list_head flist
;
497 struct amdgpu_sa_manager
*manager
;
500 struct dma_fence
*fence
;
506 void amdgpu_gem_force_release(struct amdgpu_device
*adev
);
507 int amdgpu_gem_object_create(struct amdgpu_device
*adev
, unsigned long size
,
508 int alignment
, u32 initial_domain
,
509 u64 flags
, bool kernel
,
510 struct drm_gem_object
**obj
);
512 int amdgpu_mode_dumb_create(struct drm_file
*file_priv
,
513 struct drm_device
*dev
,
514 struct drm_mode_create_dumb
*args
);
515 int amdgpu_mode_dumb_mmap(struct drm_file
*filp
,
516 struct drm_device
*dev
,
517 uint32_t handle
, uint64_t *offset_p
);
518 int amdgpu_fence_slab_init(void);
519 void amdgpu_fence_slab_fini(void);
522 * GART structures, functions & helpers
526 #define AMDGPU_GPU_PAGE_SIZE 4096
527 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
528 #define AMDGPU_GPU_PAGE_SHIFT 12
529 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
532 dma_addr_t table_addr
;
533 struct amdgpu_bo
*robj
;
535 unsigned num_gpu_pages
;
536 unsigned num_cpu_pages
;
538 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
543 /* Asic default pte flags */
544 uint64_t gart_pte_flags
;
546 const struct amdgpu_gart_funcs
*gart_funcs
;
549 int amdgpu_gart_table_ram_alloc(struct amdgpu_device
*adev
);
550 void amdgpu_gart_table_ram_free(struct amdgpu_device
*adev
);
551 int amdgpu_gart_table_vram_alloc(struct amdgpu_device
*adev
);
552 void amdgpu_gart_table_vram_free(struct amdgpu_device
*adev
);
553 int amdgpu_gart_table_vram_pin(struct amdgpu_device
*adev
);
554 void amdgpu_gart_table_vram_unpin(struct amdgpu_device
*adev
);
555 int amdgpu_gart_init(struct amdgpu_device
*adev
);
556 void amdgpu_gart_fini(struct amdgpu_device
*adev
);
557 void amdgpu_gart_unbind(struct amdgpu_device
*adev
, uint64_t offset
,
559 int amdgpu_gart_bind(struct amdgpu_device
*adev
, uint64_t offset
,
560 int pages
, struct page
**pagelist
,
561 dma_addr_t
*dma_addr
, uint64_t flags
);
562 int amdgpu_ttm_recover_gart(struct amdgpu_device
*adev
);
565 * VMHUB structures, functions & helpers
567 struct amdgpu_vmhub
{
568 uint32_t ctx0_ptb_addr_lo32
;
569 uint32_t ctx0_ptb_addr_hi32
;
570 uint32_t vm_inv_eng0_req
;
571 uint32_t vm_inv_eng0_ack
;
572 uint32_t vm_context0_cntl
;
573 uint32_t vm_l2_pro_fault_status
;
574 uint32_t vm_l2_pro_fault_cntl
;
578 * GPU MC structures, functions & helpers
581 resource_size_t aper_size
;
582 resource_size_t aper_base
;
583 resource_size_t agp_base
;
584 /* for some chips with <= 32MB we need to lie
585 * about vram size near mc fb location */
587 u64 visible_vram_size
;
598 const struct firmware
*fw
; /* MC firmware */
600 struct amdgpu_irq_src vm_fault
;
602 uint32_t srbm_soft_reset
;
603 struct amdgpu_mode_mc_save save
;
606 u64 shared_aperture_start
;
607 u64 shared_aperture_end
;
608 u64 private_aperture_start
;
609 u64 private_aperture_end
;
610 /* protects concurrent invalidation */
611 spinlock_t invalidate_lock
;
615 * GPU doorbell structures, functions & helpers
617 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
619 AMDGPU_DOORBELL_KIQ
= 0x000,
620 AMDGPU_DOORBELL_HIQ
= 0x001,
621 AMDGPU_DOORBELL_DIQ
= 0x002,
622 AMDGPU_DOORBELL_MEC_RING0
= 0x010,
623 AMDGPU_DOORBELL_MEC_RING1
= 0x011,
624 AMDGPU_DOORBELL_MEC_RING2
= 0x012,
625 AMDGPU_DOORBELL_MEC_RING3
= 0x013,
626 AMDGPU_DOORBELL_MEC_RING4
= 0x014,
627 AMDGPU_DOORBELL_MEC_RING5
= 0x015,
628 AMDGPU_DOORBELL_MEC_RING6
= 0x016,
629 AMDGPU_DOORBELL_MEC_RING7
= 0x017,
630 AMDGPU_DOORBELL_GFX_RING0
= 0x020,
631 AMDGPU_DOORBELL_sDMA_ENGINE0
= 0x1E0,
632 AMDGPU_DOORBELL_sDMA_ENGINE1
= 0x1E1,
633 AMDGPU_DOORBELL_IH
= 0x1E8,
634 AMDGPU_DOORBELL_MAX_ASSIGNMENT
= 0x3FF,
635 AMDGPU_DOORBELL_INVALID
= 0xFFFF
636 } AMDGPU_DOORBELL_ASSIGNMENT
;
638 struct amdgpu_doorbell
{
640 resource_size_t base
;
641 resource_size_t size
;
643 u32 num_doorbells
; /* Number of doorbells actually reserved for amdgpu. */
647 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
649 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
652 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
653 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
654 * Compute related doorbells are allocated from 0x00 to 0x8a
658 /* kernel scheduling */
659 AMDGPU_DOORBELL64_KIQ
= 0x00,
661 /* HSA interface queue and debug queue */
662 AMDGPU_DOORBELL64_HIQ
= 0x01,
663 AMDGPU_DOORBELL64_DIQ
= 0x02,
665 /* Compute engines */
666 AMDGPU_DOORBELL64_MEC_RING0
= 0x03,
667 AMDGPU_DOORBELL64_MEC_RING1
= 0x04,
668 AMDGPU_DOORBELL64_MEC_RING2
= 0x05,
669 AMDGPU_DOORBELL64_MEC_RING3
= 0x06,
670 AMDGPU_DOORBELL64_MEC_RING4
= 0x07,
671 AMDGPU_DOORBELL64_MEC_RING5
= 0x08,
672 AMDGPU_DOORBELL64_MEC_RING6
= 0x09,
673 AMDGPU_DOORBELL64_MEC_RING7
= 0x0a,
675 /* User queue doorbell range (128 doorbells) */
676 AMDGPU_DOORBELL64_USERQUEUE_START
= 0x0b,
677 AMDGPU_DOORBELL64_USERQUEUE_END
= 0x8a,
679 /* Graphics engine */
680 AMDGPU_DOORBELL64_GFX_RING0
= 0x8b,
683 * Other graphics doorbells can be allocated here: from 0x8c to 0xef
684 * Graphics voltage island aperture 1
685 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive
689 AMDGPU_DOORBELL64_sDMA_ENGINE0
= 0xF0,
690 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0
= 0xF1,
691 AMDGPU_DOORBELL64_sDMA_ENGINE1
= 0xF2,
692 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1
= 0xF3,
694 /* Interrupt handler */
695 AMDGPU_DOORBELL64_IH
= 0xF4, /* For legacy interrupt ring buffer */
696 AMDGPU_DOORBELL64_IH_RING1
= 0xF5, /* For page migration request log */
697 AMDGPU_DOORBELL64_IH_RING2
= 0xF6, /* For page migration translation/invalidation log */
699 /* VCN engine use 32 bits doorbell */
700 AMDGPU_DOORBELL64_VCN0_1
= 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
701 AMDGPU_DOORBELL64_VCN2_3
= 0xF9,
702 AMDGPU_DOORBELL64_VCN4_5
= 0xFA,
703 AMDGPU_DOORBELL64_VCN6_7
= 0xFB,
705 /* overlap the doorbell assignment with VCN as they are mutually exclusive
706 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
708 AMDGPU_DOORBELL64_RING0_1
= 0xF8,
709 AMDGPU_DOORBELL64_RING2_3
= 0xF9,
710 AMDGPU_DOORBELL64_RING4_5
= 0xFA,
711 AMDGPU_DOORBELL64_RING6_7
= 0xFB,
713 AMDGPU_DOORBELL64_UVD_RING0_1
= 0xFC,
714 AMDGPU_DOORBELL64_UVD_RING2_3
= 0xFD,
715 AMDGPU_DOORBELL64_UVD_RING4_5
= 0xFE,
716 AMDGPU_DOORBELL64_UVD_RING6_7
= 0xFF,
718 AMDGPU_DOORBELL64_MAX_ASSIGNMENT
= 0xFF,
719 AMDGPU_DOORBELL64_INVALID
= 0xFFFF
720 } AMDGPU_DOORBELL64_ASSIGNMENT
;
723 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device
*adev
,
724 phys_addr_t
*aperture_base
,
725 size_t *aperture_size
,
726 size_t *start_offset
);
732 struct amdgpu_flip_work
{
733 struct delayed_work flip_work
;
734 struct work_struct unpin_work
;
735 struct amdgpu_device
*adev
;
739 struct drm_pending_vblank_event
*event
;
740 struct amdgpu_bo
*old_abo
;
741 struct dma_fence
*excl
;
742 unsigned shared_count
;
743 struct dma_fence
**shared
;
744 struct dma_fence_cb cb
;
754 struct amdgpu_sa_bo
*sa_bo
;
761 extern const struct amd_sched_backend_ops amdgpu_sched_ops
;
763 int amdgpu_job_alloc(struct amdgpu_device
*adev
, unsigned num_ibs
,
764 struct amdgpu_job
**job
, struct amdgpu_vm
*vm
);
765 int amdgpu_job_alloc_with_ib(struct amdgpu_device
*adev
, unsigned size
,
766 struct amdgpu_job
**job
);
768 void amdgpu_job_free_resources(struct amdgpu_job
*job
);
769 void amdgpu_job_free(struct amdgpu_job
*job
);
770 int amdgpu_job_submit(struct amdgpu_job
*job
, struct amdgpu_ring
*ring
,
771 struct amd_sched_entity
*entity
, void *owner
,
772 struct dma_fence
**f
);
775 * context related structures
778 struct amdgpu_ctx_ring
{
780 struct dma_fence
**fences
;
781 struct amd_sched_entity entity
;
785 struct kref refcount
;
786 struct amdgpu_device
*adev
;
787 unsigned reset_counter
;
788 spinlock_t ring_lock
;
789 struct dma_fence
**fences
;
790 struct amdgpu_ctx_ring rings
[AMDGPU_MAX_RINGS
];
791 bool preamble_presented
;
794 struct amdgpu_ctx_mgr
{
795 struct amdgpu_device
*adev
;
797 /* protected by lock */
798 struct idr ctx_handles
;
801 struct amdgpu_ctx
*amdgpu_ctx_get(struct amdgpu_fpriv
*fpriv
, uint32_t id
);
802 int amdgpu_ctx_put(struct amdgpu_ctx
*ctx
);
804 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx
*ctx
, struct amdgpu_ring
*ring
,
805 struct dma_fence
*fence
);
806 struct dma_fence
*amdgpu_ctx_get_fence(struct amdgpu_ctx
*ctx
,
807 struct amdgpu_ring
*ring
, uint64_t seq
);
809 int amdgpu_ctx_ioctl(struct drm_device
*dev
, void *data
,
810 struct drm_file
*filp
);
812 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr
*mgr
);
813 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr
*mgr
);
816 * file private structure
819 struct amdgpu_fpriv
{
821 struct amdgpu_bo_va
*prt_va
;
822 struct mutex bo_list_lock
;
823 struct idr bo_list_handles
;
824 struct amdgpu_ctx_mgr ctx_mgr
;
831 struct amdgpu_bo_list
{
833 struct amdgpu_bo
*gds_obj
;
834 struct amdgpu_bo
*gws_obj
;
835 struct amdgpu_bo
*oa_obj
;
836 unsigned first_userptr
;
837 unsigned num_entries
;
838 struct amdgpu_bo_list_entry
*array
;
841 struct amdgpu_bo_list
*
842 amdgpu_bo_list_get(struct amdgpu_fpriv
*fpriv
, int id
);
843 void amdgpu_bo_list_get_list(struct amdgpu_bo_list
*list
,
844 struct list_head
*validated
);
845 void amdgpu_bo_list_put(struct amdgpu_bo_list
*list
);
846 void amdgpu_bo_list_free(struct amdgpu_bo_list
*list
);
851 #include "clearstate_defs.h"
853 struct amdgpu_rlc_funcs
{
854 void (*enter_safe_mode
)(struct amdgpu_device
*adev
);
855 void (*exit_safe_mode
)(struct amdgpu_device
*adev
);
859 /* for power gating */
860 struct amdgpu_bo
*save_restore_obj
;
861 uint64_t save_restore_gpu_addr
;
862 volatile uint32_t *sr_ptr
;
865 /* for clear state */
866 struct amdgpu_bo
*clear_state_obj
;
867 uint64_t clear_state_gpu_addr
;
868 volatile uint32_t *cs_ptr
;
869 const struct cs_section_def
*cs_data
;
870 u32 clear_state_size
;
872 struct amdgpu_bo
*cp_table_obj
;
873 uint64_t cp_table_gpu_addr
;
874 volatile uint32_t *cp_table_ptr
;
877 /* safe mode for updating CG/PG state */
879 const struct amdgpu_rlc_funcs
*funcs
;
881 /* for firmware data */
882 u32 save_and_restore_offset
;
883 u32 clear_state_descriptor_offset
;
884 u32 avail_scratch_ram_locations
;
885 u32 reg_restore_list_size
;
886 u32 reg_list_format_start
;
887 u32 reg_list_format_separate_start
;
888 u32 starting_offsets_start
;
889 u32 reg_list_format_size_bytes
;
890 u32 reg_list_size_bytes
;
892 u32
*register_list_format
;
893 u32
*register_restore
;
897 struct amdgpu_bo
*hpd_eop_obj
;
898 u64 hpd_eop_gpu_addr
;
899 struct amdgpu_bo
*mec_fw_obj
;
904 void *mqd_backup
[AMDGPU_MAX_COMPUTE_RINGS
+ 1];
909 struct amdgpu_bo
*eop_obj
;
910 struct amdgpu_ring ring
;
911 struct amdgpu_irq_src irq
;
915 * GPU scratch registers structures, functions & helpers
917 struct amdgpu_scratch
{
926 #define AMDGPU_GFX_MAX_SE 4
927 #define AMDGPU_GFX_MAX_SH_PER_SE 2
929 struct amdgpu_rb_config
{
930 uint32_t rb_backend_disable
;
931 uint32_t user_rb_backend_disable
;
932 uint32_t raster_config
;
933 uint32_t raster_config_1
;
936 struct gb_addr_config
{
937 uint16_t pipe_interleave_size
;
939 uint8_t max_compress_frags
;
942 uint8_t num_rb_per_se
;
945 struct amdgpu_gfx_config
{
946 unsigned max_shader_engines
;
947 unsigned max_tile_pipes
;
948 unsigned max_cu_per_sh
;
949 unsigned max_sh_per_se
;
950 unsigned max_backends_per_se
;
951 unsigned max_texture_channel_caches
;
953 unsigned max_gs_threads
;
954 unsigned max_hw_contexts
;
955 unsigned sc_prim_fifo_size_frontend
;
956 unsigned sc_prim_fifo_size_backend
;
957 unsigned sc_hiz_tile_fifo_size
;
958 unsigned sc_earlyz_tile_fifo_size
;
960 unsigned num_tile_pipes
;
961 unsigned backend_enable_mask
;
962 unsigned mem_max_burst_length_bytes
;
963 unsigned mem_row_size_in_kb
;
964 unsigned shader_engine_tile_size
;
966 unsigned multi_gpu_tile_size
;
967 unsigned mc_arb_ramcfg
;
968 unsigned gb_addr_config
;
970 unsigned gs_vgt_table_depth
;
971 unsigned gs_prim_buffer_depth
;
973 uint32_t tile_mode_array
[32];
974 uint32_t macrotile_mode_array
[16];
976 struct gb_addr_config gb_addr_config_fields
;
977 struct amdgpu_rb_config rb_config
[AMDGPU_GFX_MAX_SE
][AMDGPU_GFX_MAX_SH_PER_SE
];
979 /* gfx configure feature */
980 uint32_t double_offchip_lds_buf
;
983 struct amdgpu_cu_info
{
984 uint32_t number
; /* total active CU number */
986 uint32_t wave_front_size
;
987 uint32_t bitmap
[4][4];
990 struct amdgpu_gfx_funcs
{
991 /* get the gpu clock counter */
992 uint64_t (*get_gpu_clock_counter
)(struct amdgpu_device
*adev
);
993 void (*select_se_sh
)(struct amdgpu_device
*adev
, u32 se_num
, u32 sh_num
, u32 instance
);
994 void (*read_wave_data
)(struct amdgpu_device
*adev
, uint32_t simd
, uint32_t wave
, uint32_t *dst
, int *no_fields
);
995 void (*read_wave_vgprs
)(struct amdgpu_device
*adev
, uint32_t simd
, uint32_t wave
, uint32_t thread
, uint32_t start
, uint32_t size
, uint32_t *dst
);
996 void (*read_wave_sgprs
)(struct amdgpu_device
*adev
, uint32_t simd
, uint32_t wave
, uint32_t start
, uint32_t size
, uint32_t *dst
);
999 struct amdgpu_ngg_buf
{
1000 struct amdgpu_bo
*bo
;
1015 struct amdgpu_ngg_buf buf
[NGG_BUF_MAX
];
1016 uint32_t gds_reserve_addr
;
1017 uint32_t gds_reserve_size
;
1022 struct mutex gpu_clock_mutex
;
1023 struct amdgpu_gfx_config config
;
1024 struct amdgpu_rlc rlc
;
1025 struct amdgpu_mec mec
;
1026 struct amdgpu_kiq kiq
;
1027 struct amdgpu_scratch scratch
;
1028 const struct firmware
*me_fw
; /* ME firmware */
1029 uint32_t me_fw_version
;
1030 const struct firmware
*pfp_fw
; /* PFP firmware */
1031 uint32_t pfp_fw_version
;
1032 const struct firmware
*ce_fw
; /* CE firmware */
1033 uint32_t ce_fw_version
;
1034 const struct firmware
*rlc_fw
; /* RLC firmware */
1035 uint32_t rlc_fw_version
;
1036 const struct firmware
*mec_fw
; /* MEC firmware */
1037 uint32_t mec_fw_version
;
1038 const struct firmware
*mec2_fw
; /* MEC2 firmware */
1039 uint32_t mec2_fw_version
;
1040 uint32_t me_feature_version
;
1041 uint32_t ce_feature_version
;
1042 uint32_t pfp_feature_version
;
1043 uint32_t rlc_feature_version
;
1044 uint32_t mec_feature_version
;
1045 uint32_t mec2_feature_version
;
1046 struct amdgpu_ring gfx_ring
[AMDGPU_MAX_GFX_RINGS
];
1047 unsigned num_gfx_rings
;
1048 struct amdgpu_ring compute_ring
[AMDGPU_MAX_COMPUTE_RINGS
];
1049 unsigned num_compute_rings
;
1050 struct amdgpu_irq_src eop_irq
;
1051 struct amdgpu_irq_src priv_reg_irq
;
1052 struct amdgpu_irq_src priv_inst_irq
;
1054 uint32_t gfx_current_status
;
1056 unsigned ce_ram_size
;
1057 struct amdgpu_cu_info cu_info
;
1058 const struct amdgpu_gfx_funcs
*funcs
;
1061 uint32_t grbm_soft_reset
;
1062 uint32_t srbm_soft_reset
;
1065 struct amdgpu_ngg ngg
;
1068 int amdgpu_ib_get(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
1069 unsigned size
, struct amdgpu_ib
*ib
);
1070 void amdgpu_ib_free(struct amdgpu_device
*adev
, struct amdgpu_ib
*ib
,
1071 struct dma_fence
*f
);
1072 int amdgpu_ib_schedule(struct amdgpu_ring
*ring
, unsigned num_ibs
,
1073 struct amdgpu_ib
*ibs
, struct amdgpu_job
*job
,
1074 struct dma_fence
**f
);
1075 int amdgpu_ib_pool_init(struct amdgpu_device
*adev
);
1076 void amdgpu_ib_pool_fini(struct amdgpu_device
*adev
);
1077 int amdgpu_ib_ring_tests(struct amdgpu_device
*adev
);
1082 struct amdgpu_cs_chunk
{
1088 struct amdgpu_cs_parser
{
1089 struct amdgpu_device
*adev
;
1090 struct drm_file
*filp
;
1091 struct amdgpu_ctx
*ctx
;
1095 struct amdgpu_cs_chunk
*chunks
;
1097 /* scheduler job object */
1098 struct amdgpu_job
*job
;
1100 /* buffer objects */
1101 struct ww_acquire_ctx ticket
;
1102 struct amdgpu_bo_list
*bo_list
;
1103 struct amdgpu_bo_list_entry vm_pd
;
1104 struct list_head validated
;
1105 struct dma_fence
*fence
;
1106 uint64_t bytes_moved_threshold
;
1107 uint64_t bytes_moved
;
1108 struct amdgpu_bo_list_entry
*evictable
;
1111 struct amdgpu_bo_list_entry uf_entry
;
1114 #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
1115 #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
1116 #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
1117 #define AMDGPU_VM_DOMAIN (1 << 3) /* bit set means in virtual memory context */
1120 struct amd_sched_job base
;
1121 struct amdgpu_device
*adev
;
1122 struct amdgpu_vm
*vm
;
1123 struct amdgpu_ring
*ring
;
1124 struct amdgpu_sync sync
;
1125 struct amdgpu_ib
*ibs
;
1126 struct dma_fence
*fence
; /* the hw fence */
1127 uint32_t preamble_status
;
1130 uint64_t fence_ctx
; /* the fence_context this job uses */
1131 bool vm_needs_flush
;
1132 bool need_pipeline_sync
;
1134 uint64_t vm_pd_addr
;
1135 uint32_t gds_base
, gds_size
;
1136 uint32_t gws_base
, gws_size
;
1137 uint32_t oa_base
, oa_size
;
1139 /* user fence handling */
1141 uint64_t uf_sequence
;
1144 #define to_amdgpu_job(sched_job) \
1145 container_of((sched_job), struct amdgpu_job, base)
1147 static inline u32
amdgpu_get_ib_value(struct amdgpu_cs_parser
*p
,
1148 uint32_t ib_idx
, int idx
)
1150 return p
->job
->ibs
[ib_idx
].ptr
[idx
];
1153 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser
*p
,
1154 uint32_t ib_idx
, int idx
,
1157 p
->job
->ibs
[ib_idx
].ptr
[idx
] = value
;
1163 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1166 struct amdgpu_bo
*wb_obj
;
1167 volatile uint32_t *wb
;
1169 u32 num_wb
; /* Number of wb slots actually reserved for amdgpu. */
1170 unsigned long used
[DIV_ROUND_UP(AMDGPU_MAX_WB
, BITS_PER_LONG
)];
1173 int amdgpu_wb_get(struct amdgpu_device
*adev
, u32
*wb
);
1174 void amdgpu_wb_free(struct amdgpu_device
*adev
, u32 wb
);
1175 int amdgpu_wb_get_64bit(struct amdgpu_device
*adev
, u32
*wb
);
1176 void amdgpu_wb_free_64bit(struct amdgpu_device
*adev
, u32 wb
);
1178 void amdgpu_get_pcie_info(struct amdgpu_device
*adev
);
1183 struct amdgpu_sdma_instance
{
1185 const struct firmware
*fw
;
1186 uint32_t fw_version
;
1187 uint32_t feature_version
;
1189 struct amdgpu_ring ring
;
1193 struct amdgpu_sdma
{
1194 struct amdgpu_sdma_instance instance
[AMDGPU_MAX_SDMA_INSTANCES
];
1195 #ifdef CONFIG_DRM_AMDGPU_SI
1196 //SI DMA has a difference trap irq number for the second engine
1197 struct amdgpu_irq_src trap_irq_1
;
1199 struct amdgpu_irq_src trap_irq
;
1200 struct amdgpu_irq_src illegal_inst_irq
;
1202 uint32_t srbm_soft_reset
;
1208 enum amdgpu_firmware_load_type
{
1209 AMDGPU_FW_LOAD_DIRECT
= 0,
1214 struct amdgpu_firmware
{
1215 struct amdgpu_firmware_info ucode
[AMDGPU_UCODE_ID_MAXIMUM
];
1216 enum amdgpu_firmware_load_type load_type
;
1217 struct amdgpu_bo
*fw_buf
;
1218 unsigned int fw_size
;
1219 unsigned int max_ucodes
;
1220 /* firmwares are loaded by psp instead of smu from vega10 */
1221 const struct amdgpu_psp_funcs
*funcs
;
1222 struct amdgpu_bo
*rbuf
;
1229 void amdgpu_benchmark(struct amdgpu_device
*adev
, int test_number
);
1235 void amdgpu_test_moves(struct amdgpu_device
*adev
);
1240 #if defined(CONFIG_MMU_NOTIFIER)
1241 int amdgpu_mn_register(struct amdgpu_bo
*bo
, unsigned long addr
);
1242 void amdgpu_mn_unregister(struct amdgpu_bo
*bo
);
1244 static inline int amdgpu_mn_register(struct amdgpu_bo
*bo
, unsigned long addr
)
1248 static inline void amdgpu_mn_unregister(struct amdgpu_bo
*bo
) {}
1254 struct amdgpu_debugfs
{
1255 const struct drm_info_list
*files
;
1259 int amdgpu_debugfs_add_files(struct amdgpu_device
*adev
,
1260 const struct drm_info_list
*files
,
1262 int amdgpu_debugfs_fence_init(struct amdgpu_device
*adev
);
1264 #if defined(CONFIG_DEBUG_FS)
1265 int amdgpu_debugfs_init(struct drm_minor
*minor
);
1268 int amdgpu_debugfs_firmware_init(struct amdgpu_device
*adev
);
1271 * amdgpu smumgr functions
1273 struct amdgpu_smumgr_funcs
{
1274 int (*check_fw_load_finish
)(struct amdgpu_device
*adev
, uint32_t fwtype
);
1275 int (*request_smu_load_fw
)(struct amdgpu_device
*adev
);
1276 int (*request_smu_specific_fw
)(struct amdgpu_device
*adev
, uint32_t fwtype
);
1282 struct amdgpu_smumgr
{
1283 struct amdgpu_bo
*toc_buf
;
1284 struct amdgpu_bo
*smu_buf
;
1285 /* asic priv smu data */
1287 spinlock_t smu_lock
;
1288 /* smumgr functions */
1289 const struct amdgpu_smumgr_funcs
*smumgr_funcs
;
1290 /* ucode loading complete flag */
1295 * ASIC specific register table accessible by UMD
1297 struct amdgpu_allowed_register_entry
{
1298 uint32_t reg_offset
;
1304 * ASIC specific functions.
1306 struct amdgpu_asic_funcs
{
1307 bool (*read_disabled_bios
)(struct amdgpu_device
*adev
);
1308 bool (*read_bios_from_rom
)(struct amdgpu_device
*adev
,
1309 u8
*bios
, u32 length_bytes
);
1310 int (*read_register
)(struct amdgpu_device
*adev
, u32 se_num
,
1311 u32 sh_num
, u32 reg_offset
, u32
*value
);
1312 void (*set_vga_state
)(struct amdgpu_device
*adev
, bool state
);
1313 int (*reset
)(struct amdgpu_device
*adev
);
1314 /* get the reference clock */
1315 u32 (*get_xclk
)(struct amdgpu_device
*adev
);
1316 /* MM block clocks */
1317 int (*set_uvd_clocks
)(struct amdgpu_device
*adev
, u32 vclk
, u32 dclk
);
1318 int (*set_vce_clocks
)(struct amdgpu_device
*adev
, u32 evclk
, u32 ecclk
);
1319 /* static power management */
1320 int (*get_pcie_lanes
)(struct amdgpu_device
*adev
);
1321 void (*set_pcie_lanes
)(struct amdgpu_device
*adev
, int lanes
);
1322 /* get config memsize register */
1323 u32 (*get_config_memsize
)(struct amdgpu_device
*adev
);
1329 int amdgpu_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1330 struct drm_file
*filp
);
1331 int amdgpu_bo_list_ioctl(struct drm_device
*dev
, void *data
,
1332 struct drm_file
*filp
);
1334 int amdgpu_gem_info_ioctl(struct drm_device
*dev
, void *data
,
1335 struct drm_file
*filp
);
1336 int amdgpu_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
1337 struct drm_file
*filp
);
1338 int amdgpu_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1339 struct drm_file
*filp
);
1340 int amdgpu_gem_wait_idle_ioctl(struct drm_device
*dev
, void *data
,
1341 struct drm_file
*filp
);
1342 int amdgpu_gem_va_ioctl(struct drm_device
*dev
, void *data
,
1343 struct drm_file
*filp
);
1344 int amdgpu_gem_op_ioctl(struct drm_device
*dev
, void *data
,
1345 struct drm_file
*filp
);
1346 int amdgpu_cs_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
1347 int amdgpu_cs_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
1348 int amdgpu_cs_wait_fences_ioctl(struct drm_device
*dev
, void *data
,
1349 struct drm_file
*filp
);
1351 int amdgpu_gem_metadata_ioctl(struct drm_device
*dev
, void *data
,
1352 struct drm_file
*filp
);
1354 /* VRAM scratch page for HDP bug, default vram page */
1355 struct amdgpu_vram_scratch
{
1356 struct amdgpu_bo
*robj
;
1357 volatile uint32_t *ptr
;
1364 struct amdgpu_atif_notification_cfg
{
1369 struct amdgpu_atif_notifications
{
1370 bool display_switch
;
1371 bool expansion_mode_change
;
1373 bool forced_power_state
;
1374 bool system_power_state
;
1375 bool display_conf_change
;
1377 bool brightness_change
;
1378 bool dgpu_display_event
;
1381 struct amdgpu_atif_functions
{
1383 bool sbios_requests
;
1384 bool select_active_disp
;
1386 bool get_tv_standard
;
1387 bool set_tv_standard
;
1388 bool get_panel_expansion_mode
;
1389 bool set_panel_expansion_mode
;
1390 bool temperature_change
;
1391 bool graphics_device_types
;
1394 struct amdgpu_atif
{
1395 struct amdgpu_atif_notifications notifications
;
1396 struct amdgpu_atif_functions functions
;
1397 struct amdgpu_atif_notification_cfg notification_cfg
;
1398 struct amdgpu_encoder
*encoder_for_bl
;
1401 struct amdgpu_atcs_functions
{
1405 bool pcie_bus_width
;
1408 struct amdgpu_atcs
{
1409 struct amdgpu_atcs_functions functions
;
1415 struct cgs_device
*amdgpu_cgs_create_device(struct amdgpu_device
*adev
);
1416 void amdgpu_cgs_destroy_device(struct cgs_device
*cgs_device
);
1419 * Core structure, functions and helpers.
1421 typedef uint32_t (*amdgpu_rreg_t
)(struct amdgpu_device
*, uint32_t);
1422 typedef void (*amdgpu_wreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t);
1424 typedef uint32_t (*amdgpu_block_rreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t);
1425 typedef void (*amdgpu_block_wreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t, uint32_t);
1427 struct amdgpu_device
{
1429 struct drm_device
*ddev
;
1430 struct pci_dev
*pdev
;
1432 #ifdef CONFIG_DRM_AMD_ACP
1433 struct amdgpu_acp acp
;
1437 enum amd_asic_type asic_type
;
1440 uint32_t external_rev_id
;
1441 unsigned long flags
;
1443 const struct amdgpu_asic_funcs
*asic_funcs
;
1447 struct work_struct reset_work
;
1448 struct notifier_block acpi_nb
;
1449 struct amdgpu_i2c_chan
*i2c_bus
[AMDGPU_MAX_I2C_BUS
];
1450 struct amdgpu_debugfs debugfs
[AMDGPU_DEBUGFS_MAX_COMPONENTS
];
1451 unsigned debugfs_count
;
1452 #if defined(CONFIG_DEBUG_FS)
1453 struct dentry
*debugfs_regs
[AMDGPU_DEBUGFS_MAX_COMPONENTS
];
1455 struct amdgpu_atif atif
;
1456 struct amdgpu_atcs atcs
;
1457 struct mutex srbm_mutex
;
1458 /* GRBM index mutex. Protects concurrent access to GRBM index */
1459 struct mutex grbm_idx_mutex
;
1460 struct dev_pm_domain vga_pm_domain
;
1461 bool have_disp_power_ref
;
1467 struct amdgpu_bo
*stollen_vga_memory
;
1468 uint32_t bios_scratch_reg_offset
;
1469 uint32_t bios_scratch
[AMDGPU_BIOS_NUM_SCRATCH
];
1471 /* Register/doorbell mmio */
1472 resource_size_t rmmio_base
;
1473 resource_size_t rmmio_size
;
1474 void __iomem
*rmmio
;
1475 /* protects concurrent MM_INDEX/DATA based register access */
1476 spinlock_t mmio_idx_lock
;
1477 /* protects concurrent SMC based register access */
1478 spinlock_t smc_idx_lock
;
1479 amdgpu_rreg_t smc_rreg
;
1480 amdgpu_wreg_t smc_wreg
;
1481 /* protects concurrent PCIE register access */
1482 spinlock_t pcie_idx_lock
;
1483 amdgpu_rreg_t pcie_rreg
;
1484 amdgpu_wreg_t pcie_wreg
;
1485 amdgpu_rreg_t pciep_rreg
;
1486 amdgpu_wreg_t pciep_wreg
;
1487 /* protects concurrent UVD register access */
1488 spinlock_t uvd_ctx_idx_lock
;
1489 amdgpu_rreg_t uvd_ctx_rreg
;
1490 amdgpu_wreg_t uvd_ctx_wreg
;
1491 /* protects concurrent DIDT register access */
1492 spinlock_t didt_idx_lock
;
1493 amdgpu_rreg_t didt_rreg
;
1494 amdgpu_wreg_t didt_wreg
;
1495 /* protects concurrent gc_cac register access */
1496 spinlock_t gc_cac_idx_lock
;
1497 amdgpu_rreg_t gc_cac_rreg
;
1498 amdgpu_wreg_t gc_cac_wreg
;
1499 /* protects concurrent ENDPOINT (audio) register access */
1500 spinlock_t audio_endpt_idx_lock
;
1501 amdgpu_block_rreg_t audio_endpt_rreg
;
1502 amdgpu_block_wreg_t audio_endpt_wreg
;
1503 void __iomem
*rio_mem
;
1504 resource_size_t rio_mem_size
;
1505 struct amdgpu_doorbell doorbell
;
1507 /* clock/pll info */
1508 struct amdgpu_clock clock
;
1511 struct amdgpu_mc mc
;
1512 struct amdgpu_gart gart
;
1513 struct amdgpu_dummy_page dummy_page
;
1514 struct amdgpu_vm_manager vm_manager
;
1515 struct amdgpu_vmhub vmhub
[AMDGPU_MAX_VMHUBS
];
1517 /* memory management */
1518 struct amdgpu_mman mman
;
1519 struct amdgpu_vram_scratch vram_scratch
;
1520 struct amdgpu_wb wb
;
1521 atomic64_t vram_usage
;
1522 atomic64_t vram_vis_usage
;
1523 atomic64_t gtt_usage
;
1524 atomic64_t num_bytes_moved
;
1525 atomic64_t num_evictions
;
1526 atomic_t gpu_reset_counter
;
1528 /* data for buffer migration throttling */
1532 s64 accum_us
; /* accumulated microseconds */
1537 bool enable_virtual_display
;
1538 struct amdgpu_mode_info mode_info
;
1539 struct work_struct hotplug_work
;
1540 struct amdgpu_irq_src crtc_irq
;
1541 struct amdgpu_irq_src pageflip_irq
;
1542 struct amdgpu_irq_src hpd_irq
;
1547 struct amdgpu_ring
*rings
[AMDGPU_MAX_RINGS
];
1549 struct amdgpu_sa_manager ring_tmp_bo
;
1552 struct amdgpu_irq irq
;
1555 struct amd_powerplay powerplay
;
1557 bool pp_force_state_enabled
;
1560 struct amdgpu_pm pm
;
1565 struct amdgpu_smumgr smu
;
1568 struct amdgpu_gfx gfx
;
1571 struct amdgpu_sdma sdma
;
1574 struct amdgpu_uvd uvd
;
1577 struct amdgpu_vce vce
;
1580 struct amdgpu_firmware firmware
;
1583 struct psp_context psp
;
1586 struct amdgpu_gds gds
;
1588 struct amdgpu_ip_block ip_blocks
[AMDGPU_MAX_IP_NUM
];
1590 struct mutex mn_lock
;
1591 DECLARE_HASHTABLE(mn_hash
, 7);
1593 /* tracking pinned memory */
1595 u64 invisible_pin_size
;
1598 /* amdkfd interface */
1599 struct kfd_dev
*kfd
;
1601 struct amdgpu_virt virt
;
1603 /* link all shadow bo */
1604 struct list_head shadow_list
;
1605 struct mutex shadow_list_lock
;
1607 spinlock_t gtt_list_lock
;
1608 struct list_head gtt_list
;
1610 /* record hw reset is performed */
1615 static inline struct amdgpu_device
*amdgpu_ttm_adev(struct ttm_bo_device
*bdev
)
1617 return container_of(bdev
, struct amdgpu_device
, mman
.bdev
);
1620 bool amdgpu_device_is_px(struct drm_device
*dev
);
1621 int amdgpu_device_init(struct amdgpu_device
*adev
,
1622 struct drm_device
*ddev
,
1623 struct pci_dev
*pdev
,
1625 void amdgpu_device_fini(struct amdgpu_device
*adev
);
1626 int amdgpu_gpu_wait_for_idle(struct amdgpu_device
*adev
);
1628 uint32_t amdgpu_mm_rreg(struct amdgpu_device
*adev
, uint32_t reg
,
1629 uint32_t acc_flags
);
1630 void amdgpu_mm_wreg(struct amdgpu_device
*adev
, uint32_t reg
, uint32_t v
,
1631 uint32_t acc_flags
);
1632 u32
amdgpu_io_rreg(struct amdgpu_device
*adev
, u32 reg
);
1633 void amdgpu_io_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
);
1635 u32
amdgpu_mm_rdoorbell(struct amdgpu_device
*adev
, u32 index
);
1636 void amdgpu_mm_wdoorbell(struct amdgpu_device
*adev
, u32 index
, u32 v
);
1637 u64
amdgpu_mm_rdoorbell64(struct amdgpu_device
*adev
, u32 index
);
1638 void amdgpu_mm_wdoorbell64(struct amdgpu_device
*adev
, u32 index
, u64 v
);
1641 * Registers read & write functions.
1644 #define AMDGPU_REGS_IDX (1<<0)
1645 #define AMDGPU_REGS_NO_KIQ (1<<1)
1647 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1648 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1650 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1651 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1652 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1653 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1654 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
1655 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1656 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1657 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1658 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1659 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1660 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1661 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1662 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1663 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1664 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1665 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1666 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1667 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1668 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1669 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1670 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1671 #define WREG32_P(reg, val, mask) \
1673 uint32_t tmp_ = RREG32(reg); \
1675 tmp_ |= ((val) & ~(mask)); \
1676 WREG32(reg, tmp_); \
1678 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1679 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1680 #define WREG32_PLL_P(reg, val, mask) \
1682 uint32_t tmp_ = RREG32_PLL(reg); \
1684 tmp_ |= ((val) & ~(mask)); \
1685 WREG32_PLL(reg, tmp_); \
1687 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1688 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1689 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1691 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1692 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
1693 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1694 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
1696 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1697 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1699 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
1700 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1701 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1703 #define REG_GET_FIELD(value, reg, field) \
1704 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1706 #define WREG32_FIELD(reg, field, val) \
1707 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1709 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1710 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1715 #define RBIOS8(i) (adev->bios[i])
1716 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1717 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1722 static inline void amdgpu_ring_write(struct amdgpu_ring
*ring
, uint32_t v
)
1724 if (ring
->count_dw
<= 0)
1725 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
1726 ring
->ring
[ring
->wptr
++ & ring
->buf_mask
] = v
;
1727 ring
->wptr
&= ring
->ptr_mask
;
1731 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring
*ring
, void *src
, int count_dw
)
1733 unsigned occupied
, chunk1
, chunk2
;
1736 if (ring
->count_dw
< count_dw
) {
1737 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
1739 occupied
= ring
->wptr
& ring
->buf_mask
;
1740 dst
= (void *)&ring
->ring
[occupied
];
1741 chunk1
= ring
->buf_mask
+ 1 - occupied
;
1742 chunk1
= (chunk1
>= count_dw
) ? count_dw
: chunk1
;
1743 chunk2
= count_dw
- chunk1
;
1748 memcpy(dst
, src
, chunk1
);
1752 dst
= (void *)ring
->ring
;
1753 memcpy(dst
, src
, chunk2
);
1756 ring
->wptr
+= count_dw
;
1757 ring
->wptr
&= ring
->ptr_mask
;
1758 ring
->count_dw
-= count_dw
;
1762 static inline struct amdgpu_sdma_instance
*
1763 amdgpu_get_sdma_instance(struct amdgpu_ring
*ring
)
1765 struct amdgpu_device
*adev
= ring
->adev
;
1768 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1769 if (&adev
->sdma
.instance
[i
].ring
== ring
)
1772 if (i
< AMDGPU_MAX_SDMA_INSTANCES
)
1773 return &adev
->sdma
.instance
[i
];
1781 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1782 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1783 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1784 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1785 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1786 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1787 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1788 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1789 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1790 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1791 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1792 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1793 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
1794 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
1795 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
1796 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
1797 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
1798 #define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
1799 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1800 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
1801 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
1802 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1803 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1804 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
1805 #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
1806 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
1807 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
1808 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
1809 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
1810 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
1811 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
1812 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
1813 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
1814 #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1815 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
1816 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
1817 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
1818 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
1819 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
1820 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
1821 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
1822 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
1823 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1824 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
1825 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1826 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1827 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
1828 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
1829 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
1830 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
1831 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
1832 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
1833 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
1834 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
1835 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
1836 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
1837 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
1838 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
1839 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
1840 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
1841 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
1842 #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
1844 /* Common functions */
1845 int amdgpu_gpu_reset(struct amdgpu_device
*adev
);
1846 bool amdgpu_need_backup(struct amdgpu_device
*adev
);
1847 void amdgpu_pci_config_reset(struct amdgpu_device
*adev
);
1848 bool amdgpu_need_post(struct amdgpu_device
*adev
);
1849 void amdgpu_update_display_priority(struct amdgpu_device
*adev
);
1851 int amdgpu_cs_parser_init(struct amdgpu_cs_parser
*p
, void *data
);
1852 int amdgpu_cs_get_ring(struct amdgpu_device
*adev
, u32 ip_type
,
1853 u32 ip_instance
, u32 ring
,
1854 struct amdgpu_ring
**out_ring
);
1855 void amdgpu_cs_report_moved_bytes(struct amdgpu_device
*adev
, u64 num_bytes
);
1856 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo
*abo
, u32 domain
);
1857 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object
*bo
);
1858 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt
*ttm
, struct page
**pages
);
1859 int amdgpu_ttm_tt_set_userptr(struct ttm_tt
*ttm
, uint64_t addr
,
1861 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt
*ttm
);
1862 struct mm_struct
*amdgpu_ttm_tt_get_usermm(struct ttm_tt
*ttm
);
1863 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt
*ttm
, unsigned long start
,
1865 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt
*ttm
,
1866 int *last_invalidated
);
1867 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt
*ttm
);
1868 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device
*adev
, struct ttm_tt
*ttm
,
1869 struct ttm_mem_reg
*mem
);
1870 void amdgpu_vram_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
, u64 base
);
1871 void amdgpu_gtt_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
);
1872 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device
*adev
, u64 size
);
1873 int amdgpu_ttm_init(struct amdgpu_device
*adev
);
1874 void amdgpu_ttm_fini(struct amdgpu_device
*adev
);
1875 void amdgpu_program_register_sequence(struct amdgpu_device
*adev
,
1876 const u32
*registers
,
1877 const u32 array_size
);
1879 bool amdgpu_device_is_px(struct drm_device
*dev
);
1881 #if defined(CONFIG_VGA_SWITCHEROO)
1882 void amdgpu_register_atpx_handler(void);
1883 void amdgpu_unregister_atpx_handler(void);
1884 bool amdgpu_has_atpx_dgpu_power_cntl(void);
1885 bool amdgpu_is_atpx_hybrid(void);
1886 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1887 bool amdgpu_has_atpx(void);
1889 static inline void amdgpu_register_atpx_handler(void) {}
1890 static inline void amdgpu_unregister_atpx_handler(void) {}
1891 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1892 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1893 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1894 static inline bool amdgpu_has_atpx(void) { return false; }
1900 extern const struct drm_ioctl_desc amdgpu_ioctls_kms
[];
1901 extern const int amdgpu_max_kms_ioctl
;
1903 int amdgpu_driver_load_kms(struct drm_device
*dev
, unsigned long flags
);
1904 void amdgpu_driver_unload_kms(struct drm_device
*dev
);
1905 void amdgpu_driver_lastclose_kms(struct drm_device
*dev
);
1906 int amdgpu_driver_open_kms(struct drm_device
*dev
, struct drm_file
*file_priv
);
1907 void amdgpu_driver_postclose_kms(struct drm_device
*dev
,
1908 struct drm_file
*file_priv
);
1909 int amdgpu_suspend(struct amdgpu_device
*adev
);
1910 int amdgpu_device_suspend(struct drm_device
*dev
, bool suspend
, bool fbcon
);
1911 int amdgpu_device_resume(struct drm_device
*dev
, bool resume
, bool fbcon
);
1912 u32
amdgpu_get_vblank_counter_kms(struct drm_device
*dev
, unsigned int pipe
);
1913 int amdgpu_enable_vblank_kms(struct drm_device
*dev
, unsigned int pipe
);
1914 void amdgpu_disable_vblank_kms(struct drm_device
*dev
, unsigned int pipe
);
1915 long amdgpu_kms_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1919 * functions used by amdgpu_encoder.c
1921 struct amdgpu_afmt_acr
{
1935 struct amdgpu_afmt_acr
amdgpu_afmt_acr(uint32_t clock
);
1938 #if defined(CONFIG_ACPI)
1939 int amdgpu_acpi_init(struct amdgpu_device
*adev
);
1940 void amdgpu_acpi_fini(struct amdgpu_device
*adev
);
1941 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device
*adev
);
1942 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device
*adev
,
1943 u8 perf_req
, bool advertise
);
1944 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device
*adev
);
1946 static inline int amdgpu_acpi_init(struct amdgpu_device
*adev
) { return 0; }
1947 static inline void amdgpu_acpi_fini(struct amdgpu_device
*adev
) { }
1950 struct amdgpu_bo_va_mapping
*
1951 amdgpu_cs_find_mapping(struct amdgpu_cs_parser
*parser
,
1952 uint64_t addr
, struct amdgpu_bo
**bo
);
1953 int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser
*parser
);
1955 #include "amdgpu_object.h"