2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/irqdomain.h>
27 #include <linux/pm_domain.h>
28 #include <linux/platform_device.h>
29 #include <sound/designware_i2s.h>
30 #include <sound/pcm.h>
34 #include "amdgpu_acp.h"
36 #include "acp_gfx_if.h"
38 #define ACP_TILE_ON_MASK 0x03
39 #define ACP_TILE_OFF_MASK 0x02
40 #define ACP_TILE_ON_RETAIN_REG_MASK 0x1f
41 #define ACP_TILE_OFF_RETAIN_REG_MASK 0x20
43 #define ACP_TILE_P1_MASK 0x3e
44 #define ACP_TILE_P2_MASK 0x3d
45 #define ACP_TILE_DSP0_MASK 0x3b
46 #define ACP_TILE_DSP1_MASK 0x37
48 #define ACP_TILE_DSP2_MASK 0x2f
50 #define ACP_DMA_REGS_END 0x146c0
51 #define ACP_I2S_PLAY_REGS_START 0x14840
52 #define ACP_I2S_PLAY_REGS_END 0x148b4
53 #define ACP_I2S_CAP_REGS_START 0x148b8
54 #define ACP_I2S_CAP_REGS_END 0x1496c
56 #define ACP_I2S_COMP1_CAP_REG_OFFSET 0xac
57 #define ACP_I2S_COMP2_CAP_REG_OFFSET 0xa8
58 #define ACP_I2S_COMP1_PLAY_REG_OFFSET 0x6c
59 #define ACP_I2S_COMP2_PLAY_REG_OFFSET 0x68
61 #define mmACP_PGFSM_RETAIN_REG 0x51c9
62 #define mmACP_PGFSM_CONFIG_REG 0x51ca
63 #define mmACP_PGFSM_READ_REG_0 0x51cc
65 #define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8
66 #define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9
67 #define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa
68 #define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb
70 #define ACP_TIMEOUT_LOOP 0x000000FF
72 #define ACP_SRC_ID 162
82 static int acp_sw_init(void *handle
)
84 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
86 adev
->acp
.parent
= adev
->dev
;
88 adev
->acp
.cgs_device
=
89 amdgpu_cgs_create_device(adev
);
90 if (!adev
->acp
.cgs_device
)
96 static int acp_sw_fini(void *handle
)
98 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
100 if (adev
->acp
.cgs_device
)
101 amdgpu_cgs_destroy_device(adev
->acp
.cgs_device
);
106 /* power off a tile/block within ACP */
107 static int acp_suspend_tile(void *cgs_dev
, int tile
)
112 if ((tile
< ACP_TILE_P1
) || (tile
> ACP_TILE_DSP2
)) {
113 pr_err("Invalid ACP tile : %d to suspend\n", tile
);
117 val
= cgs_read_register(cgs_dev
, mmACP_PGFSM_READ_REG_0
+ tile
);
118 val
&= ACP_TILE_ON_MASK
;
121 val
= cgs_read_register(cgs_dev
, mmACP_PGFSM_RETAIN_REG
);
122 val
= val
| (1 << tile
);
123 cgs_write_register(cgs_dev
, mmACP_PGFSM_RETAIN_REG
, val
);
124 cgs_write_register(cgs_dev
, mmACP_PGFSM_CONFIG_REG
,
127 count
= ACP_TIMEOUT_LOOP
;
129 val
= cgs_read_register(cgs_dev
, mmACP_PGFSM_READ_REG_0
131 val
= val
& ACP_TILE_ON_MASK
;
132 if (val
== ACP_TILE_OFF_MASK
)
135 pr_err("Timeout reading ACP PGFSM status\n");
141 val
= cgs_read_register(cgs_dev
, mmACP_PGFSM_RETAIN_REG
);
143 val
|= ACP_TILE_OFF_RETAIN_REG_MASK
;
144 cgs_write_register(cgs_dev
, mmACP_PGFSM_RETAIN_REG
, val
);
149 /* power on a tile/block within ACP */
150 static int acp_resume_tile(void *cgs_dev
, int tile
)
155 if ((tile
< ACP_TILE_P1
) || (tile
> ACP_TILE_DSP2
)) {
156 pr_err("Invalid ACP tile to resume\n");
160 val
= cgs_read_register(cgs_dev
, mmACP_PGFSM_READ_REG_0
+ tile
);
161 val
= val
& ACP_TILE_ON_MASK
;
164 cgs_write_register(cgs_dev
, mmACP_PGFSM_CONFIG_REG
,
166 count
= ACP_TIMEOUT_LOOP
;
168 val
= cgs_read_register(cgs_dev
, mmACP_PGFSM_READ_REG_0
170 val
= val
& ACP_TILE_ON_MASK
;
174 pr_err("Timeout reading ACP PGFSM status\n");
179 val
= cgs_read_register(cgs_dev
, mmACP_PGFSM_RETAIN_REG
);
180 if (tile
== ACP_TILE_P1
)
181 val
= val
& (ACP_TILE_P1_MASK
);
182 else if (tile
== ACP_TILE_P2
)
183 val
= val
& (ACP_TILE_P2_MASK
);
185 cgs_write_register(cgs_dev
, mmACP_PGFSM_RETAIN_REG
, val
);
190 struct acp_pm_domain
{
192 struct generic_pm_domain gpd
;
195 static int acp_poweroff(struct generic_pm_domain
*genpd
)
198 struct acp_pm_domain
*apd
;
200 apd
= container_of(genpd
, struct acp_pm_domain
, gpd
);
202 /* Donot return abruptly if any of power tile fails to suspend.
203 * Log it and continue powering off other tile
205 for (i
= 4; i
>= 0 ; i
--) {
206 ret
= acp_suspend_tile(apd
->cgs_dev
, ACP_TILE_P1
+ i
);
208 pr_err("ACP tile %d tile suspend failed\n", i
);
214 static int acp_poweron(struct generic_pm_domain
*genpd
)
217 struct acp_pm_domain
*apd
;
219 apd
= container_of(genpd
, struct acp_pm_domain
, gpd
);
221 for (i
= 0; i
< 2; i
++) {
222 ret
= acp_resume_tile(apd
->cgs_dev
, ACP_TILE_P1
+ i
);
224 pr_err("ACP tile %d resume failed\n", i
);
229 /* Disable DSPs which are not going to be used */
230 for (i
= 0; i
< 3; i
++) {
231 ret
= acp_suspend_tile(apd
->cgs_dev
, ACP_TILE_DSP0
+ i
);
232 /* Continue suspending other DSP, even if one fails */
234 pr_err("ACP DSP %d suspend failed\n", i
);
240 static struct device
*get_mfd_cell_dev(const char *device_name
, int r
)
242 char auto_dev_name
[25];
245 snprintf(auto_dev_name
, sizeof(auto_dev_name
),
246 "%s.%d.auto", device_name
, r
);
247 dev
= bus_find_device_by_name(&platform_bus_type
, NULL
, auto_dev_name
);
248 dev_info(dev
, "device %s added to pm domain\n", auto_dev_name
);
254 * acp_hw_init - start and test ACP block
256 * @adev: amdgpu_device pointer
259 static int acp_hw_init(void *handle
)
264 struct i2s_platform_data
*i2s_pdata
;
266 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
268 const struct amdgpu_ip_block
*ip_block
=
269 amdgpu_get_ip_block(adev
, AMD_IP_BLOCK_TYPE_ACP
);
274 r
= amd_acp_hw_init(adev
->acp
.cgs_device
,
275 ip_block
->version
->major
, ip_block
->version
->minor
);
276 /* -ENODEV means board uses AZ rather than ACP */
282 r
= cgs_get_pci_resource(adev
->acp
.cgs_device
, CGS_RESOURCE_TYPE_MMIO
,
283 0x5289, 0, &acp_base
);
289 adev
->acp
.acp_genpd
= kzalloc(sizeof(struct acp_pm_domain
), GFP_KERNEL
);
290 if (adev
->acp
.acp_genpd
== NULL
)
293 adev
->acp
.acp_genpd
->gpd
.name
= "ACP_AUDIO";
294 adev
->acp
.acp_genpd
->gpd
.power_off
= acp_poweroff
;
295 adev
->acp
.acp_genpd
->gpd
.power_on
= acp_poweron
;
298 adev
->acp
.acp_genpd
->cgs_dev
= adev
->acp
.cgs_device
;
300 pm_genpd_init(&adev
->acp
.acp_genpd
->gpd
, NULL
, false);
302 adev
->acp
.acp_cell
= kzalloc(sizeof(struct mfd_cell
) * ACP_DEVS
,
305 if (adev
->acp
.acp_cell
== NULL
)
308 adev
->acp
.acp_res
= kzalloc(sizeof(struct resource
) * 4, GFP_KERNEL
);
310 if (adev
->acp
.acp_res
== NULL
) {
311 kfree(adev
->acp
.acp_cell
);
315 i2s_pdata
= kzalloc(sizeof(struct i2s_platform_data
) * 2, GFP_KERNEL
);
316 if (i2s_pdata
== NULL
) {
317 kfree(adev
->acp
.acp_res
);
318 kfree(adev
->acp
.acp_cell
);
322 i2s_pdata
[0].quirks
= DW_I2S_QUIRK_COMP_REG_OFFSET
;
323 i2s_pdata
[0].cap
= DWC_I2S_PLAY
;
324 i2s_pdata
[0].snd_rates
= SNDRV_PCM_RATE_8000_96000
;
325 i2s_pdata
[0].i2s_reg_comp1
= ACP_I2S_COMP1_PLAY_REG_OFFSET
;
326 i2s_pdata
[0].i2s_reg_comp2
= ACP_I2S_COMP2_PLAY_REG_OFFSET
;
328 i2s_pdata
[1].quirks
= DW_I2S_QUIRK_COMP_REG_OFFSET
|
329 DW_I2S_QUIRK_COMP_PARAM1
;
330 i2s_pdata
[1].cap
= DWC_I2S_RECORD
;
331 i2s_pdata
[1].snd_rates
= SNDRV_PCM_RATE_8000_96000
;
332 i2s_pdata
[1].i2s_reg_comp1
= ACP_I2S_COMP1_CAP_REG_OFFSET
;
333 i2s_pdata
[1].i2s_reg_comp2
= ACP_I2S_COMP2_CAP_REG_OFFSET
;
335 adev
->acp
.acp_res
[0].name
= "acp2x_dma";
336 adev
->acp
.acp_res
[0].flags
= IORESOURCE_MEM
;
337 adev
->acp
.acp_res
[0].start
= acp_base
;
338 adev
->acp
.acp_res
[0].end
= acp_base
+ ACP_DMA_REGS_END
;
340 adev
->acp
.acp_res
[1].name
= "acp2x_dw_i2s_play";
341 adev
->acp
.acp_res
[1].flags
= IORESOURCE_MEM
;
342 adev
->acp
.acp_res
[1].start
= acp_base
+ ACP_I2S_PLAY_REGS_START
;
343 adev
->acp
.acp_res
[1].end
= acp_base
+ ACP_I2S_PLAY_REGS_END
;
345 adev
->acp
.acp_res
[2].name
= "acp2x_dw_i2s_cap";
346 adev
->acp
.acp_res
[2].flags
= IORESOURCE_MEM
;
347 adev
->acp
.acp_res
[2].start
= acp_base
+ ACP_I2S_CAP_REGS_START
;
348 adev
->acp
.acp_res
[2].end
= acp_base
+ ACP_I2S_CAP_REGS_END
;
350 adev
->acp
.acp_res
[3].name
= "acp2x_dma_irq";
351 adev
->acp
.acp_res
[3].flags
= IORESOURCE_IRQ
;
352 adev
->acp
.acp_res
[3].start
= amdgpu_irq_create_mapping(adev
, 162);
353 adev
->acp
.acp_res
[3].end
= adev
->acp
.acp_res
[3].start
;
355 adev
->acp
.acp_cell
[0].name
= "acp_audio_dma";
356 adev
->acp
.acp_cell
[0].num_resources
= 4;
357 adev
->acp
.acp_cell
[0].resources
= &adev
->acp
.acp_res
[0];
359 adev
->acp
.acp_cell
[1].name
= "designware-i2s";
360 adev
->acp
.acp_cell
[1].num_resources
= 1;
361 adev
->acp
.acp_cell
[1].resources
= &adev
->acp
.acp_res
[1];
362 adev
->acp
.acp_cell
[1].platform_data
= &i2s_pdata
[0];
363 adev
->acp
.acp_cell
[1].pdata_size
= sizeof(struct i2s_platform_data
);
365 adev
->acp
.acp_cell
[2].name
= "designware-i2s";
366 adev
->acp
.acp_cell
[2].num_resources
= 1;
367 adev
->acp
.acp_cell
[2].resources
= &adev
->acp
.acp_res
[2];
368 adev
->acp
.acp_cell
[2].platform_data
= &i2s_pdata
[1];
369 adev
->acp
.acp_cell
[2].pdata_size
= sizeof(struct i2s_platform_data
);
371 r
= mfd_add_hotplug_devices(adev
->acp
.parent
, adev
->acp
.acp_cell
,
376 for (i
= 0; i
< ACP_DEVS
; i
++) {
377 dev
= get_mfd_cell_dev(adev
->acp
.acp_cell
[i
].name
, i
);
378 r
= pm_genpd_add_device(&adev
->acp
.acp_genpd
->gpd
, dev
);
380 dev_err(dev
, "Failed to add dev to genpd\n");
389 * acp_hw_fini - stop the hardware block
391 * @adev: amdgpu_device pointer
394 static int acp_hw_fini(void *handle
)
398 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
400 /* return early if no ACP */
401 if (!adev
->acp
.acp_genpd
)
404 for (i
= 0; i
< ACP_DEVS
; i
++) {
405 dev
= get_mfd_cell_dev(adev
->acp
.acp_cell
[i
].name
, i
);
406 ret
= pm_genpd_remove_device(&adev
->acp
.acp_genpd
->gpd
, dev
);
407 /* If removal fails, dont giveup and try rest */
409 dev_err(dev
, "remove dev from genpd failed\n");
412 mfd_remove_devices(adev
->acp
.parent
);
413 kfree(adev
->acp
.acp_res
);
414 kfree(adev
->acp
.acp_genpd
);
415 kfree(adev
->acp
.acp_cell
);
420 static int acp_suspend(void *handle
)
425 static int acp_resume(void *handle
)
430 static int acp_early_init(void *handle
)
435 static bool acp_is_idle(void *handle
)
440 static int acp_wait_for_idle(void *handle
)
445 static int acp_soft_reset(void *handle
)
450 static int acp_set_clockgating_state(void *handle
,
451 enum amd_clockgating_state state
)
456 static int acp_set_powergating_state(void *handle
,
457 enum amd_powergating_state state
)
462 static const struct amd_ip_funcs acp_ip_funcs
= {
464 .early_init
= acp_early_init
,
466 .sw_init
= acp_sw_init
,
467 .sw_fini
= acp_sw_fini
,
468 .hw_init
= acp_hw_init
,
469 .hw_fini
= acp_hw_fini
,
470 .suspend
= acp_suspend
,
471 .resume
= acp_resume
,
472 .is_idle
= acp_is_idle
,
473 .wait_for_idle
= acp_wait_for_idle
,
474 .soft_reset
= acp_soft_reset
,
475 .set_clockgating_state
= acp_set_clockgating_state
,
476 .set_powergating_state
= acp_set_powergating_state
,
479 const struct amdgpu_ip_block_version acp_ip_block
=
481 .type
= AMD_IP_BLOCK_TYPE_ACP
,
485 .funcs
= &acp_ip_funcs
,