drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/fdtable.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/firmware.h>
  27 #include <drm/drmP.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_amdkfd.h"
  30 #include "amdgpu_ucode.h"
  31 #include "gfx_v8_0.h"
  32 #include "gca/gfx_8_0_sh_mask.h"
  33 #include "gca/gfx_8_0_d.h"
  34 #include "gca/gfx_8_0_enum.h"
  35 #include "oss/oss_3_0_sh_mask.h"
  36 #include "oss/oss_3_0_d.h"
  37 #include "gmc/gmc_8_1_sh_mask.h"
  38 #include "gmc/gmc_8_1_d.h"
  39 #include "vi_structs.h"
  40 #include "vid.h"
  41
  42 enum hqd_dequeue_request_type {
  43         NO_ACTION = 0,
  44         DRAIN_PIPE,
  45         RESET_WAVES
  46 };
  47
  48 struct vi_sdma_mqd;
  49
  50 /*
  51  * Register access functions
  52  */
  53
  54 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
  55                 uint32_t sh_mem_config,
  56                 uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
  57                 uint32_t sh_mem_bases);
  58 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
  59                 unsigned int vmid);
  60 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
  61 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
  62                         uint32_t queue_id, uint32_t __user *wptr,
  63                         uint32_t wptr_shift, uint32_t wptr_mask,
  64                         struct mm_struct *mm);
  65 static int kgd_hqd_dump(struct kgd_dev *kgd,
  66                         uint32_t pipe_id, uint32_t queue_id,
  67                         uint32_t (**dump)[2], uint32_t *n_regs);
  68 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
  69                              uint32_t __user *wptr, struct mm_struct *mm);
  70 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
  71                              uint32_t engine_id, uint32_t queue_id,
  72                              uint32_t (**dump)[2], uint32_t *n_regs);
  73 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
  74                 uint32_t pipe_id, uint32_t queue_id);
  75 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
  76 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
  77                                 enum kfd_preempt_type reset_type,
  78                                 unsigned int utimeout, uint32_t pipe_id,
  79                                 uint32_t queue_id);
  80 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
  81                                 unsigned int utimeout);
  82 static int kgd_address_watch_disable(struct kgd_dev *kgd);
  83 static int kgd_address_watch_execute(struct kgd_dev *kgd,
  84                                         unsigned int watch_point_id,
  85                                         uint32_t cntl_val,
  86                                         uint32_t addr_hi,
  87                                         uint32_t addr_lo);
  88 static int kgd_wave_control_execute(struct kgd_dev *kgd,
  89                                         uint32_t gfx_index_val,
  90                                         uint32_t sq_cmd);
  91 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
  92                                         unsigned int watch_point_id,
  93                                         unsigned int reg_offset);
  94
  95 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
  96                 uint8_t vmid);
  97 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
  98                 uint8_t vmid);
  99 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
 100 static void set_scratch_backing_va(struct kgd_dev *kgd,
 101                                         uint64_t va, uint32_t vmid);
 102 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
 103                 uint32_t page_table_base);
 104 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
 105 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
 106
 107 /* Because of REG_GET_FIELD() being used, we put this function in the
 108  * asic specific file.
 109  */
 110 static int get_tile_config(struct kgd_dev *kgd,
 111                 struct tile_config *config)
 112 {
 113         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 114
 115         config->gb_addr_config = adev->gfx.config.gb_addr_config;
 116         config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
 117                                 MC_ARB_RAMCFG, NOOFBANK);
 118         config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
 119                                 MC_ARB_RAMCFG, NOOFRANKS);
 120
 121         config->tile_config_ptr = adev->gfx.config.tile_mode_array;
 122         config->num_tile_configs =
 123                         ARRAY_SIZE(adev->gfx.config.tile_mode_array);
 124         config->macro_tile_config_ptr =
 125                         adev->gfx.config.macrotile_mode_array;
 126         config->num_macro_tile_configs =
 127                         ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
 128
 129         return 0;
 130 }
 131
 132 static const struct kfd2kgd_calls kfd2kgd = {
 133         .init_gtt_mem_allocation = alloc_gtt_mem,
 134         .free_gtt_mem = free_gtt_mem,
 135         .get_local_mem_info = get_local_mem_info,
 136         .get_gpu_clock_counter = get_gpu_clock_counter,
 137         .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
 138         .alloc_pasid = amdgpu_pasid_alloc,
 139         .free_pasid = amdgpu_pasid_free,
 140         .program_sh_mem_settings = kgd_program_sh_mem_settings,
 141         .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
 142         .init_interrupts = kgd_init_interrupts,
 143         .hqd_load = kgd_hqd_load,
 144         .hqd_sdma_load = kgd_hqd_sdma_load,
 145         .hqd_dump = kgd_hqd_dump,
 146         .hqd_sdma_dump = kgd_hqd_sdma_dump,
 147         .hqd_is_occupied = kgd_hqd_is_occupied,
 148         .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
 149         .hqd_destroy = kgd_hqd_destroy,
 150         .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
 151         .address_watch_disable = kgd_address_watch_disable,
 152         .address_watch_execute = kgd_address_watch_execute,
 153         .wave_control_execute = kgd_wave_control_execute,
 154         .address_watch_get_offset = kgd_address_watch_get_offset,
 155         .get_atc_vmid_pasid_mapping_pasid =
 156                         get_atc_vmid_pasid_mapping_pasid,
 157         .get_atc_vmid_pasid_mapping_valid =
 158                         get_atc_vmid_pasid_mapping_valid,
 159         .get_fw_version = get_fw_version,
 160         .set_scratch_backing_va = set_scratch_backing_va,
 161         .get_tile_config = get_tile_config,
 162         .get_cu_info = get_cu_info,
 163         .get_vram_usage = amdgpu_amdkfd_get_vram_usage,
 164         .create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm,
 165         .acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm,
 166         .destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm,
 167         .release_process_vm = amdgpu_amdkfd_gpuvm_release_process_vm,
 168         .get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir,
 169         .set_vm_context_page_table_base = set_vm_context_page_table_base,
 170         .alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu,
 171         .free_memory_of_gpu = amdgpu_amdkfd_gpuvm_free_memory_of_gpu,
 172         .map_memory_to_gpu = amdgpu_amdkfd_gpuvm_map_memory_to_gpu,
 173         .unmap_memory_to_gpu = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu,
 174         .sync_memory = amdgpu_amdkfd_gpuvm_sync_memory,
 175         .map_gtt_bo_to_kernel = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel,
 176         .restore_process_bos = amdgpu_amdkfd_gpuvm_restore_process_bos,
 177         .invalidate_tlbs = invalidate_tlbs,
 178         .invalidate_tlbs_vmid = invalidate_tlbs_vmid,
 179         .submit_ib = amdgpu_amdkfd_submit_ib,
 180         .get_vm_fault_info = amdgpu_amdkfd_gpuvm_get_vm_fault_info,
 181         .gpu_recover = amdgpu_amdkfd_gpu_reset,
 182         .set_compute_idle = amdgpu_amdkfd_set_compute_idle
 183 };
 184
 185 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
 186 {
 187         return (struct kfd2kgd_calls *)&kfd2kgd;
 188 }
 189
 190 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
 191 {
 192         return (struct amdgpu_device *)kgd;
 193 }
 194
 195 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
 196                         uint32_t queue, uint32_t vmid)
 197 {
 198         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 199         uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
 200
 201         mutex_lock(&adev->srbm_mutex);
 202         WREG32(mmSRBM_GFX_CNTL, value);
 203 }
 204
 205 static void unlock_srbm(struct kgd_dev *kgd)
 206 {
 207         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 208
 209         WREG32(mmSRBM_GFX_CNTL, 0);
 210         mutex_unlock(&adev->srbm_mutex);
 211 }
 212
 213 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
 214                                 uint32_t queue_id)
 215 {
 216         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 217
 218         uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 219         uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 220
 221         lock_srbm(kgd, mec, pipe, queue_id, 0);
 222 }
 223
 224 static void release_queue(struct kgd_dev *kgd)
 225 {
 226         unlock_srbm(kgd);
 227 }
 228
 229 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
 230                                         uint32_t sh_mem_config,
 231                                         uint32_t sh_mem_ape1_base,
 232                                         uint32_t sh_mem_ape1_limit,
 233                                         uint32_t sh_mem_bases)
 234 {
 235         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 236
 237         lock_srbm(kgd, 0, 0, 0, vmid);
 238
 239         WREG32(mmSH_MEM_CONFIG, sh_mem_config);
 240         WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
 241         WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
 242         WREG32(mmSH_MEM_BASES, sh_mem_bases);
 243
 244         unlock_srbm(kgd);
 245 }
 246
 247 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
 248                                         unsigned int vmid)
 249 {
 250         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 251
 252         /*
 253          * We have to assume that there is no outstanding mapping.
 254          * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
 255          * a mapping is in progress or because a mapping finished
 256          * and the SW cleared it.
 257          * So the protocol is to always wait & clear.
 258          */
 259         uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
 260                         ATC_VMID0_PASID_MAPPING__VALID_MASK;
 261
 262         WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
 263
 264         while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
 265                 cpu_relax();
 266         WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
 267
 268         /* Mapping vmid to pasid also for IH block */
 269         WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
 270
 271         return 0;
 272 }
 273
 274 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
 275 {
 276         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 277         uint32_t mec;
 278         uint32_t pipe;
 279
 280         mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 281         pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 282
 283         lock_srbm(kgd, mec, pipe, 0, 0);
 284
 285         WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK);
 286
 287         unlock_srbm(kgd);
 288
 289         return 0;
 290 }
 291
 292 static inline uint32_t get_sdma_base_addr(struct vi_sdma_mqd *m)
 293 {
 294         uint32_t retval;
 295
 296         retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
 297                 m->sdma_queue_id * KFD_VI_SDMA_QUEUE_OFFSET;
 298         pr_debug("kfd: sdma base address: 0x%x\n", retval);
 299
 300         return retval;
 301 }
 302
 303 static inline struct vi_mqd *get_mqd(void *mqd)
 304 {
 305         return (struct vi_mqd *)mqd;
 306 }
 307
 308 static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd)
 309 {
 310         return (struct vi_sdma_mqd *)mqd;
 311 }
 312
 313 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 314                         uint32_t queue_id, uint32_t __user *wptr,
 315                         uint32_t wptr_shift, uint32_t wptr_mask,
 316                         struct mm_struct *mm)
 317 {
 318         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 319         struct vi_mqd *m;
 320         uint32_t *mqd_hqd;
 321         uint32_t reg, wptr_val, data;
 322         bool valid_wptr = false;
 323
 324         m = get_mqd(mqd);
 325
 326         acquire_queue(kgd, pipe_id, queue_id);
 327
 328         /* HIQ is set during driver init period with vmid set to 0*/
 329         if (m->cp_hqd_vmid == 0) {
 330                 uint32_t value, mec, pipe;
 331
 332                 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 333                 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 334
 335                 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
 336                         mec, pipe, queue_id);
 337                 value = RREG32(mmRLC_CP_SCHEDULERS);
 338                 value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
 339                         ((mec << 5) | (pipe << 3) | queue_id | 0x80));
 340                 WREG32(mmRLC_CP_SCHEDULERS, value);
 341         }
 342
 343         /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */
 344         mqd_hqd = &m->cp_mqd_base_addr_lo;
 345
 346         for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++)
 347                 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
 348
 349         /* Tonga errata: EOP RPTR/WPTR should be left unmodified.
 350          * This is safe since EOP RPTR==WPTR for any inactive HQD
 351          * on ASICs that do not support context-save.
 352          * EOP writes/reads can start anywhere in the ring.
 353          */
 354         if (get_amdgpu_device(kgd)->asic_type != CHIP_TONGA) {
 355                 WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr);
 356                 WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr);
 357                 WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem);
 358         }
 359
 360         for (reg = mmCP_HQD_EOP_EVENTS; reg <= mmCP_HQD_ERROR; reg++)
 361                 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
 362
 363         /* Copy userspace write pointer value to register.
 364          * Activate doorbell logic to monitor subsequent changes.
 365          */
 366         data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
 367                              CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
 368         WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
 369
 370         /* read_user_ptr may take the mm->mmap_sem.
 371          * release srbm_mutex to avoid circular dependency between
 372          * srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex.
 373          */
 374         release_queue(kgd);
 375         valid_wptr = read_user_wptr(mm, wptr, wptr_val);
 376         acquire_queue(kgd, pipe_id, queue_id);
 377         if (valid_wptr)
 378                 WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);
 379
 380         data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
 381         WREG32(mmCP_HQD_ACTIVE, data);
 382
 383         release_queue(kgd);
 384
 385         return 0;
 386 }
 387
 388 static int kgd_hqd_dump(struct kgd_dev *kgd,
 389                         uint32_t pipe_id, uint32_t queue_id,
 390                         uint32_t (**dump)[2], uint32_t *n_regs)
 391 {
 392         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 393         uint32_t i = 0, reg;
 394 #define HQD_N_REGS (54+4)
 395 #define DUMP_REG(addr) do {                             \
 396                 if (WARN_ON_ONCE(i >= HQD_N_REGS))      \
 397                         break;                          \
 398                 (*dump)[i][0] = (addr) << 2;            \
 399                 (*dump)[i++][1] = RREG32(addr);         \
 400         } while (0)
 401
 402         *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
 403         if (*dump == NULL)
 404                 return -ENOMEM;
 405
 406         acquire_queue(kgd, pipe_id, queue_id);
 407
 408         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0);
 409         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1);
 410         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2);
 411         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3);
 412
 413         for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_DONES; reg++)
 414                 DUMP_REG(reg);
 415
 416         release_queue(kgd);
 417
 418         WARN_ON_ONCE(i != HQD_N_REGS);
 419         *n_regs = i;
 420
 421         return 0;
 422 }
 423
 424 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
 425                              uint32_t __user *wptr, struct mm_struct *mm)
 426 {
 427         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 428         struct vi_sdma_mqd *m;
 429         unsigned long end_jiffies;
 430         uint32_t sdma_base_addr;
 431         uint32_t data;
 432
 433         m = get_sdma_mqd(mqd);
 434         sdma_base_addr = get_sdma_base_addr(m);
 435         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
 436                 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
 437
 438         end_jiffies = msecs_to_jiffies(2000) + jiffies;
 439         while (true) {
 440                 data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
 441                 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
 442                         break;
 443                 if (time_after(jiffies, end_jiffies))
 444                         return -ETIME;
 445                 usleep_range(500, 1000);
 446         }
 447         if (m->sdma_engine_id) {
 448                 data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
 449                 data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
 450                                 RESUME_CTX, 0);
 451                 WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
 452         } else {
 453                 data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
 454                 data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
 455                                 RESUME_CTX, 0);
 456                 WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
 457         }
 458
 459         data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
 460                              ENABLE, 1);
 461         WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
 462         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
 463
 464         if (read_user_wptr(mm, wptr, data))
 465                 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
 466         else
 467                 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
 468                        m->sdmax_rlcx_rb_rptr);
 469
 470         WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
 471                                 m->sdmax_rlcx_virtual_addr);
 472         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
 473         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
 474                         m->sdmax_rlcx_rb_base_hi);
 475         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
 476                         m->sdmax_rlcx_rb_rptr_addr_lo);
 477         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
 478                         m->sdmax_rlcx_rb_rptr_addr_hi);
 479
 480         data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
 481                              RB_ENABLE, 1);
 482         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
 483
 484         return 0;
 485 }
 486
 487 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
 488                              uint32_t engine_id, uint32_t queue_id,
 489                              uint32_t (**dump)[2], uint32_t *n_regs)
 490 {
 491         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 492         uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET +
 493                 queue_id * KFD_VI_SDMA_QUEUE_OFFSET;
 494         uint32_t i = 0, reg;
 495 #undef HQD_N_REGS
 496 #define HQD_N_REGS (19+4+2+3+7)
 497
 498         *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
 499         if (*dump == NULL)
 500                 return -ENOMEM;
 501
 502         for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
 503                 DUMP_REG(sdma_offset + reg);
 504         for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK;
 505              reg++)
 506                 DUMP_REG(sdma_offset + reg);
 507         for (reg = mmSDMA0_RLC0_CSA_ADDR_LO; reg <= mmSDMA0_RLC0_CSA_ADDR_HI;
 508              reg++)
 509                 DUMP_REG(sdma_offset + reg);
 510         for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; reg <= mmSDMA0_RLC0_DUMMY_REG;
 511              reg++)
 512                 DUMP_REG(sdma_offset + reg);
 513         for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; reg <= mmSDMA0_RLC0_MIDCMD_CNTL;
 514              reg++)
 515                 DUMP_REG(sdma_offset + reg);
 516
 517         WARN_ON_ONCE(i != HQD_N_REGS);
 518         *n_regs = i;
 519
 520         return 0;
 521 }
 522
 523 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
 524                                 uint32_t pipe_id, uint32_t queue_id)
 525 {
 526         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 527         uint32_t act;
 528         bool retval = false;
 529         uint32_t low, high;
 530
 531         acquire_queue(kgd, pipe_id, queue_id);
 532         act = RREG32(mmCP_HQD_ACTIVE);
 533         if (act) {
 534                 low = lower_32_bits(queue_address >> 8);
 535                 high = upper_32_bits(queue_address >> 8);
 536
 537                 if (low == RREG32(mmCP_HQD_PQ_BASE) &&
 538                                 high == RREG32(mmCP_HQD_PQ_BASE_HI))
 539                         retval = true;
 540         }
 541         release_queue(kgd);
 542         return retval;
 543 }
 544
 545 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
 546 {
 547         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 548         struct vi_sdma_mqd *m;
 549         uint32_t sdma_base_addr;
 550         uint32_t sdma_rlc_rb_cntl;
 551
 552         m = get_sdma_mqd(mqd);
 553         sdma_base_addr = get_sdma_base_addr(m);
 554
 555         sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
 556
 557         if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
 558                 return true;
 559
 560         return false;
 561 }
 562
 563 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
 564                                 enum kfd_preempt_type reset_type,
 565                                 unsigned int utimeout, uint32_t pipe_id,
 566                                 uint32_t queue_id)
 567 {
 568         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 569         uint32_t temp;
 570         enum hqd_dequeue_request_type type;
 571         unsigned long flags, end_jiffies;
 572         int retry;
 573         struct vi_mqd *m = get_mqd(mqd);
 574
 575         if (adev->in_gpu_reset)
 576                 return -EIO;
 577
 578         acquire_queue(kgd, pipe_id, queue_id);
 579
 580         if (m->cp_hqd_vmid == 0)
 581                 WREG32_FIELD(RLC_CP_SCHEDULERS, scheduler1, 0);
 582
 583         switch (reset_type) {
 584         case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
 585                 type = DRAIN_PIPE;
 586                 break;
 587         case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
 588                 type = RESET_WAVES;
 589                 break;
 590         default:
 591                 type = DRAIN_PIPE;
 592                 break;
 593         }
 594
 595         /* Workaround: If IQ timer is active and the wait time is close to or
 596          * equal to 0, dequeueing is not safe. Wait until either the wait time
 597          * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is
 598          * cleared before continuing. Also, ensure wait times are set to at
 599          * least 0x3.
 600          */
 601         local_irq_save(flags);
 602         preempt_disable();
 603         retry = 5000; /* wait for 500 usecs at maximum */
 604         while (true) {
 605                 temp = RREG32(mmCP_HQD_IQ_TIMER);
 606                 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
 607                         pr_debug("HW is processing IQ\n");
 608                         goto loop;
 609                 }
 610                 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
 611                         if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
 612                                         == 3) /* SEM-rearm is safe */
 613                                 break;
 614                         /* Wait time 3 is safe for CP, but our MMIO read/write
 615                          * time is close to 1 microsecond, so check for 10 to
 616                          * leave more buffer room
 617                          */
 618                         if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
 619                                         >= 10)
 620                                 break;
 621                         pr_debug("IQ timer is active\n");
 622                 } else
 623                         break;
 624 loop:
 625                 if (!retry) {
 626                         pr_err("CP HQD IQ timer status time out\n");
 627                         break;
 628                 }
 629                 ndelay(100);
 630                 --retry;
 631         }
 632         retry = 1000;
 633         while (true) {
 634                 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
 635                 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK))
 636                         break;
 637                 pr_debug("Dequeue request is pending\n");
 638
 639                 if (!retry) {
 640                         pr_err("CP HQD dequeue request time out\n");
 641                         break;
 642                 }
 643                 ndelay(100);
 644                 --retry;
 645         }
 646         local_irq_restore(flags);
 647         preempt_enable();
 648
 649         WREG32(mmCP_HQD_DEQUEUE_REQUEST, type);
 650
 651         end_jiffies = (utimeout * HZ / 1000) + jiffies;
 652         while (true) {
 653                 temp = RREG32(mmCP_HQD_ACTIVE);
 654                 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
 655                         break;
 656                 if (time_after(jiffies, end_jiffies)) {
 657                         pr_err("cp queue preemption time out.\n");
 658                         release_queue(kgd);
 659                         return -ETIME;
 660                 }
 661                 usleep_range(500, 1000);
 662         }
 663
 664         release_queue(kgd);
 665         return 0;
 666 }
 667
 668 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 669                                 unsigned int utimeout)
 670 {
 671         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 672         struct vi_sdma_mqd *m;
 673         uint32_t sdma_base_addr;
 674         uint32_t temp;
 675         unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
 676
 677         m = get_sdma_mqd(mqd);
 678         sdma_base_addr = get_sdma_base_addr(m);
 679
 680         temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
 681         temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
 682         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
 683
 684         while (true) {
 685                 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
 686                 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
 687                         break;
 688                 if (time_after(jiffies, end_jiffies))
 689                         return -ETIME;
 690                 usleep_range(500, 1000);
 691         }
 692
 693         WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
 694         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
 695                 RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
 696                 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
 697
 698         m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
 699
 700         return 0;
 701 }
 702
 703 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
 704                                                         uint8_t vmid)
 705 {
 706         uint32_t reg;
 707         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 708
 709         reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 710         return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
 711 }
 712
 713 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
 714                                                                 uint8_t vmid)
 715 {
 716         uint32_t reg;
 717         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 718
 719         reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 720         return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 721 }
 722
 723 static int kgd_address_watch_disable(struct kgd_dev *kgd)
 724 {
 725         return 0;
 726 }
 727
 728 static int kgd_address_watch_execute(struct kgd_dev *kgd,
 729                                         unsigned int watch_point_id,
 730                                         uint32_t cntl_val,
 731                                         uint32_t addr_hi,
 732                                         uint32_t addr_lo)
 733 {
 734         return 0;
 735 }
 736
 737 static int kgd_wave_control_execute(struct kgd_dev *kgd,
 738                                         uint32_t gfx_index_val,
 739                                         uint32_t sq_cmd)
 740 {
 741         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 742         uint32_t data = 0;
 743
 744         mutex_lock(&adev->grbm_idx_mutex);
 745
 746         WREG32(mmGRBM_GFX_INDEX, gfx_index_val);
 747         WREG32(mmSQ_CMD, sq_cmd);
 748
 749         data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 750                 INSTANCE_BROADCAST_WRITES, 1);
 751         data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 752                 SH_BROADCAST_WRITES, 1);
 753         data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 754                 SE_BROADCAST_WRITES, 1);
 755
 756         WREG32(mmGRBM_GFX_INDEX, data);
 757         mutex_unlock(&adev->grbm_idx_mutex);
 758
 759         return 0;
 760 }
 761
 762 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
 763                                         unsigned int watch_point_id,
 764                                         unsigned int reg_offset)
 765 {
 766         return 0;
 767 }
 768
 769 static void set_scratch_backing_va(struct kgd_dev *kgd,
 770                                         uint64_t va, uint32_t vmid)
 771 {
 772         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 773
 774         lock_srbm(kgd, 0, 0, 0, vmid);
 775         WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va);
 776         unlock_srbm(kgd);
 777 }
 778
 779 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
 780 {
 781         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 782         const union amdgpu_firmware_header *hdr;
 783
 784         switch (type) {
 785         case KGD_ENGINE_PFP:
 786                 hdr = (const union amdgpu_firmware_header *)
 787                                                 adev->gfx.pfp_fw->data;
 788                 break;
 789
 790         case KGD_ENGINE_ME:
 791                 hdr = (const union amdgpu_firmware_header *)
 792                                                 adev->gfx.me_fw->data;
 793                 break;
 794
 795         case KGD_ENGINE_CE:
 796                 hdr = (const union amdgpu_firmware_header *)
 797                                                 adev->gfx.ce_fw->data;
 798                 break;
 799
 800         case KGD_ENGINE_MEC1:
 801                 hdr = (const union amdgpu_firmware_header *)
 802                                                 adev->gfx.mec_fw->data;
 803                 break;
 804
 805         case KGD_ENGINE_MEC2:
 806                 hdr = (const union amdgpu_firmware_header *)
 807                                                 adev->gfx.mec2_fw->data;
 808                 break;
 809
 810         case KGD_ENGINE_RLC:
 811                 hdr = (const union amdgpu_firmware_header *)
 812                                                 adev->gfx.rlc_fw->data;
 813                 break;
 814
 815         case KGD_ENGINE_SDMA1:
 816                 hdr = (const union amdgpu_firmware_header *)
 817                                                 adev->sdma.instance[0].fw->data;
 818                 break;
 819
 820         case KGD_ENGINE_SDMA2:
 821                 hdr = (const union amdgpu_firmware_header *)
 822                                                 adev->sdma.instance[1].fw->data;
 823                 break;
 824
 825         default:
 826                 return 0;
 827         }
 828
 829         if (hdr == NULL)
 830                 return 0;
 831
 832         /* Only 12 bit in use*/
 833         return hdr->common.ucode_version;
 834 }
 835
 836 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
 837                 uint32_t page_table_base)
 838 {
 839         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 840
 841         if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
 842                 pr_err("trying to set page table base for wrong VMID\n");
 843                 return;
 844         }
 845         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, page_table_base);
 846 }
 847
 848 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
 849 {
 850         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 851         int vmid;
 852         unsigned int tmp;
 853
 854         if (adev->in_gpu_reset)
 855                 return -EIO;
 856
 857         for (vmid = 0; vmid < 16; vmid++) {
 858                 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid))
 859                         continue;
 860
 861                 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 862                 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
 863                         (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
 864                         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 865                         RREG32(mmVM_INVALIDATE_RESPONSE);
 866                         break;
 867                 }
 868         }
 869
 870         return 0;
 871 }
 872
 873 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
 874 {
 875         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 876
 877         if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
 878                 pr_err("non kfd vmid %d\n", vmid);
 879                 return -EINVAL;
 880         }
 881
 882         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 883         RREG32(mmVM_INVALIDATE_RESPONSE);
 884         return 0;
 885 }