2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
27 #include <linux/pagemap.h>
29 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_trace.h"
33 int amdgpu_cs_get_ring(struct amdgpu_device
*adev
, u32 ip_type
,
34 u32 ip_instance
, u32 ring
,
35 struct amdgpu_ring
**out_ring
)
37 /* Right now all IPs have only one instance - multiple rings. */
38 if (ip_instance
!= 0) {
39 DRM_ERROR("invalid ip instance: %d\n", ip_instance
);
45 DRM_ERROR("unknown ip type: %d\n", ip_type
);
47 case AMDGPU_HW_IP_GFX
:
48 if (ring
< adev
->gfx
.num_gfx_rings
) {
49 *out_ring
= &adev
->gfx
.gfx_ring
[ring
];
51 DRM_ERROR("only %d gfx rings are supported now\n",
52 adev
->gfx
.num_gfx_rings
);
56 case AMDGPU_HW_IP_COMPUTE
:
57 if (ring
< adev
->gfx
.num_compute_rings
) {
58 *out_ring
= &adev
->gfx
.compute_ring
[ring
];
60 DRM_ERROR("only %d compute rings are supported now\n",
61 adev
->gfx
.num_compute_rings
);
65 case AMDGPU_HW_IP_DMA
:
66 if (ring
< adev
->sdma
.num_instances
) {
67 *out_ring
= &adev
->sdma
.instance
[ring
].ring
;
69 DRM_ERROR("only %d SDMA rings are supported\n",
70 adev
->sdma
.num_instances
);
74 case AMDGPU_HW_IP_UVD
:
75 *out_ring
= &adev
->uvd
.ring
;
77 case AMDGPU_HW_IP_VCE
:
79 *out_ring
= &adev
->vce
.ring
[ring
];
81 DRM_ERROR("only two VCE rings are supported\n");
89 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser
*p
,
90 struct drm_amdgpu_cs_chunk_fence
*data
,
93 struct drm_gem_object
*gobj
;
96 gobj
= drm_gem_object_lookup(p
->filp
, data
->handle
);
100 p
->uf_entry
.robj
= amdgpu_bo_ref(gem_to_amdgpu_bo(gobj
));
101 p
->uf_entry
.priority
= 0;
102 p
->uf_entry
.tv
.bo
= &p
->uf_entry
.robj
->tbo
;
103 p
->uf_entry
.tv
.shared
= true;
104 p
->uf_entry
.user_pages
= NULL
;
106 size
= amdgpu_bo_size(p
->uf_entry
.robj
);
107 if (size
!= PAGE_SIZE
|| (data
->offset
+ 8) > size
)
110 *offset
= data
->offset
;
112 drm_gem_object_unreference_unlocked(gobj
);
114 if (amdgpu_ttm_tt_get_usermm(p
->uf_entry
.robj
->tbo
.ttm
)) {
115 amdgpu_bo_unref(&p
->uf_entry
.robj
);
122 int amdgpu_cs_parser_init(struct amdgpu_cs_parser
*p
, void *data
)
124 struct amdgpu_fpriv
*fpriv
= p
->filp
->driver_priv
;
125 struct amdgpu_vm
*vm
= &fpriv
->vm
;
126 union drm_amdgpu_cs
*cs
= data
;
127 uint64_t *chunk_array_user
;
128 uint64_t *chunk_array
;
129 unsigned size
, num_ibs
= 0;
130 uint32_t uf_offset
= 0;
134 if (cs
->in
.num_chunks
== 0)
137 chunk_array
= kmalloc_array(cs
->in
.num_chunks
, sizeof(uint64_t), GFP_KERNEL
);
141 p
->ctx
= amdgpu_ctx_get(fpriv
, cs
->in
.ctx_id
);
148 chunk_array_user
= (uint64_t __user
*)(unsigned long)(cs
->in
.chunks
);
149 if (copy_from_user(chunk_array
, chunk_array_user
,
150 sizeof(uint64_t)*cs
->in
.num_chunks
)) {
155 p
->nchunks
= cs
->in
.num_chunks
;
156 p
->chunks
= kmalloc_array(p
->nchunks
, sizeof(struct amdgpu_cs_chunk
),
163 for (i
= 0; i
< p
->nchunks
; i
++) {
164 struct drm_amdgpu_cs_chunk __user
**chunk_ptr
= NULL
;
165 struct drm_amdgpu_cs_chunk user_chunk
;
166 uint32_t __user
*cdata
;
168 chunk_ptr
= (void __user
*)(unsigned long)chunk_array
[i
];
169 if (copy_from_user(&user_chunk
, chunk_ptr
,
170 sizeof(struct drm_amdgpu_cs_chunk
))) {
173 goto free_partial_kdata
;
175 p
->chunks
[i
].chunk_id
= user_chunk
.chunk_id
;
176 p
->chunks
[i
].length_dw
= user_chunk
.length_dw
;
178 size
= p
->chunks
[i
].length_dw
;
179 cdata
= (void __user
*)(unsigned long)user_chunk
.chunk_data
;
181 p
->chunks
[i
].kdata
= drm_malloc_ab(size
, sizeof(uint32_t));
182 if (p
->chunks
[i
].kdata
== NULL
) {
185 goto free_partial_kdata
;
187 size
*= sizeof(uint32_t);
188 if (copy_from_user(p
->chunks
[i
].kdata
, cdata
, size
)) {
190 goto free_partial_kdata
;
193 switch (p
->chunks
[i
].chunk_id
) {
194 case AMDGPU_CHUNK_ID_IB
:
198 case AMDGPU_CHUNK_ID_FENCE
:
199 size
= sizeof(struct drm_amdgpu_cs_chunk_fence
);
200 if (p
->chunks
[i
].length_dw
* sizeof(uint32_t) < size
) {
202 goto free_partial_kdata
;
205 ret
= amdgpu_cs_user_fence_chunk(p
, p
->chunks
[i
].kdata
,
208 goto free_partial_kdata
;
212 case AMDGPU_CHUNK_ID_DEPENDENCIES
:
217 goto free_partial_kdata
;
221 ret
= amdgpu_job_alloc(p
->adev
, num_ibs
, &p
->job
, vm
);
225 if (p
->uf_entry
.robj
)
226 p
->job
->uf_addr
= uf_offset
;
234 drm_free_large(p
->chunks
[i
].kdata
);
237 amdgpu_ctx_put(p
->ctx
);
244 /* Convert microseconds to bytes. */
245 static u64
us_to_bytes(struct amdgpu_device
*adev
, s64 us
)
247 if (us
<= 0 || !adev
->mm_stats
.log2_max_MBps
)
250 /* Since accum_us is incremented by a million per second, just
251 * multiply it by the number of MB/s to get the number of bytes.
253 return us
<< adev
->mm_stats
.log2_max_MBps
;
256 static s64
bytes_to_us(struct amdgpu_device
*adev
, u64 bytes
)
258 if (!adev
->mm_stats
.log2_max_MBps
)
261 return bytes
>> adev
->mm_stats
.log2_max_MBps
;
264 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
265 * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
266 * which means it can go over the threshold once. If that happens, the driver
267 * will be in debt and no other buffer migrations can be done until that debt
270 * This approach allows moving a buffer of any size (it's important to allow
273 * The currency is simply time in microseconds and it increases as the clock
274 * ticks. The accumulated microseconds (us) are converted to bytes and
277 static u64
amdgpu_cs_get_threshold_for_moves(struct amdgpu_device
*adev
)
279 s64 time_us
, increment_us
;
281 u64 free_vram
, total_vram
, used_vram
;
283 /* Allow a maximum of 200 accumulated ms. This is basically per-IB
286 * It means that in order to get full max MBps, at least 5 IBs per
287 * second must be submitted and not more than 200ms apart from each
290 const s64 us_upper_bound
= 200000;
292 if (!adev
->mm_stats
.log2_max_MBps
)
295 total_vram
= adev
->mc
.real_vram_size
- adev
->vram_pin_size
;
296 used_vram
= atomic64_read(&adev
->vram_usage
);
297 free_vram
= used_vram
>= total_vram
? 0 : total_vram
- used_vram
;
299 spin_lock(&adev
->mm_stats
.lock
);
301 /* Increase the amount of accumulated us. */
302 time_us
= ktime_to_us(ktime_get());
303 increment_us
= time_us
- adev
->mm_stats
.last_update_us
;
304 adev
->mm_stats
.last_update_us
= time_us
;
305 adev
->mm_stats
.accum_us
= min(adev
->mm_stats
.accum_us
+ increment_us
,
308 /* This prevents the short period of low performance when the VRAM
309 * usage is low and the driver is in debt or doesn't have enough
310 * accumulated us to fill VRAM quickly.
312 * The situation can occur in these cases:
313 * - a lot of VRAM is freed by userspace
314 * - the presence of a big buffer causes a lot of evictions
315 * (solution: split buffers into smaller ones)
317 * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
318 * accum_us to a positive number.
320 if (free_vram
>= 128 * 1024 * 1024 || free_vram
>= total_vram
/ 8) {
323 /* Be more aggresive on dGPUs. Try to fill a portion of free
326 if (!(adev
->flags
& AMD_IS_APU
))
327 min_us
= bytes_to_us(adev
, free_vram
/ 4);
329 min_us
= 0; /* Reset accum_us on APUs. */
331 adev
->mm_stats
.accum_us
= max(min_us
, adev
->mm_stats
.accum_us
);
334 /* This returns 0 if the driver is in debt to disallow (optional)
337 max_bytes
= us_to_bytes(adev
, adev
->mm_stats
.accum_us
);
339 spin_unlock(&adev
->mm_stats
.lock
);
343 /* Report how many bytes have really been moved for the last command
344 * submission. This can result in a debt that can stop buffer migrations
347 static void amdgpu_cs_report_moved_bytes(struct amdgpu_device
*adev
,
350 spin_lock(&adev
->mm_stats
.lock
);
351 adev
->mm_stats
.accum_us
-= bytes_to_us(adev
, num_bytes
);
352 spin_unlock(&adev
->mm_stats
.lock
);
355 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser
*p
,
356 struct amdgpu_bo
*bo
)
358 u64 initial_bytes_moved
;
365 /* Don't move this buffer if we have depleted our allowance
366 * to move it. Don't move anything if the threshold is zero.
368 if (p
->bytes_moved
< p
->bytes_moved_threshold
)
369 domain
= bo
->prefered_domains
;
371 domain
= bo
->allowed_domains
;
374 amdgpu_ttm_placement_from_domain(bo
, domain
);
375 initial_bytes_moved
= atomic64_read(&bo
->adev
->num_bytes_moved
);
376 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, true, false);
377 p
->bytes_moved
+= atomic64_read(&bo
->adev
->num_bytes_moved
) -
380 if (unlikely(r
== -ENOMEM
) && domain
!= bo
->allowed_domains
) {
381 domain
= bo
->allowed_domains
;
388 /* Last resort, try to evict something from the current working set */
389 static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser
*p
,
390 struct amdgpu_bo_list_entry
*lobj
)
392 uint32_t domain
= lobj
->robj
->allowed_domains
;
398 for (;&p
->evictable
->tv
.head
!= &p
->validated
;
399 p
->evictable
= list_prev_entry(p
->evictable
, tv
.head
)) {
401 struct amdgpu_bo_list_entry
*candidate
= p
->evictable
;
402 struct amdgpu_bo
*bo
= candidate
->robj
;
403 u64 initial_bytes_moved
;
406 /* If we reached our current BO we can forget it */
407 if (candidate
== lobj
)
410 other
= amdgpu_mem_type_to_domain(bo
->tbo
.mem
.mem_type
);
412 /* Check if this BO is in one of the domains we need space for */
413 if (!(other
& domain
))
416 /* Check if we can move this BO somewhere else */
417 other
= bo
->allowed_domains
& ~domain
;
421 /* Good we can try to move this BO somewhere else */
422 amdgpu_ttm_placement_from_domain(bo
, other
);
423 initial_bytes_moved
= atomic64_read(&bo
->adev
->num_bytes_moved
);
424 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, true, false);
425 p
->bytes_moved
+= atomic64_read(&bo
->adev
->num_bytes_moved
) -
431 p
->evictable
= list_prev_entry(p
->evictable
, tv
.head
);
432 list_move(&candidate
->tv
.head
, &p
->validated
);
440 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser
*p
,
441 struct list_head
*validated
)
443 struct amdgpu_bo_list_entry
*lobj
;
446 list_for_each_entry(lobj
, validated
, tv
.head
) {
447 struct amdgpu_bo
*bo
= lobj
->robj
;
448 bool binding_userptr
= false;
449 struct mm_struct
*usermm
;
451 usermm
= amdgpu_ttm_tt_get_usermm(bo
->tbo
.ttm
);
452 if (usermm
&& usermm
!= current
->mm
)
455 /* Check if we have user pages and nobody bound the BO already */
456 if (lobj
->user_pages
&& bo
->tbo
.ttm
->state
!= tt_bound
) {
457 size_t size
= sizeof(struct page
*);
459 size
*= bo
->tbo
.ttm
->num_pages
;
460 memcpy(bo
->tbo
.ttm
->pages
, lobj
->user_pages
, size
);
461 binding_userptr
= true;
464 if (p
->evictable
== lobj
)
468 r
= amdgpu_cs_bo_validate(p
, bo
);
469 } while (r
== -ENOMEM
&& amdgpu_cs_try_evict(p
, lobj
));
474 r
= amdgpu_cs_bo_validate(p
, bo
);
479 if (binding_userptr
) {
480 drm_free_large(lobj
->user_pages
);
481 lobj
->user_pages
= NULL
;
487 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser
*p
,
488 union drm_amdgpu_cs
*cs
)
490 struct amdgpu_fpriv
*fpriv
= p
->filp
->driver_priv
;
491 struct amdgpu_bo_list_entry
*e
;
492 struct list_head duplicates
;
493 bool need_mmap_lock
= false;
494 unsigned i
, tries
= 10;
497 INIT_LIST_HEAD(&p
->validated
);
499 p
->bo_list
= amdgpu_bo_list_get(fpriv
, cs
->in
.bo_list_handle
);
501 need_mmap_lock
= p
->bo_list
->first_userptr
!=
502 p
->bo_list
->num_entries
;
503 amdgpu_bo_list_get_list(p
->bo_list
, &p
->validated
);
506 INIT_LIST_HEAD(&duplicates
);
507 amdgpu_vm_get_pd_bo(&fpriv
->vm
, &p
->validated
, &p
->vm_pd
);
509 if (p
->uf_entry
.robj
)
510 list_add(&p
->uf_entry
.tv
.head
, &p
->validated
);
513 down_read(¤t
->mm
->mmap_sem
);
516 struct list_head need_pages
;
519 r
= ttm_eu_reserve_buffers(&p
->ticket
, &p
->validated
, true,
521 if (unlikely(r
!= 0)) {
522 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
523 goto error_free_pages
;
526 /* Without a BO list we don't have userptr BOs */
530 INIT_LIST_HEAD(&need_pages
);
531 for (i
= p
->bo_list
->first_userptr
;
532 i
< p
->bo_list
->num_entries
; ++i
) {
534 e
= &p
->bo_list
->array
[i
];
536 if (amdgpu_ttm_tt_userptr_invalidated(e
->robj
->tbo
.ttm
,
537 &e
->user_invalidated
) && e
->user_pages
) {
539 /* We acquired a page array, but somebody
540 * invalidated it. Free it an try again
542 release_pages(e
->user_pages
,
543 e
->robj
->tbo
.ttm
->num_pages
,
545 drm_free_large(e
->user_pages
);
546 e
->user_pages
= NULL
;
549 if (e
->robj
->tbo
.ttm
->state
!= tt_bound
&&
551 list_del(&e
->tv
.head
);
552 list_add(&e
->tv
.head
, &need_pages
);
554 amdgpu_bo_unreserve(e
->robj
);
558 if (list_empty(&need_pages
))
561 /* Unreserve everything again. */
562 ttm_eu_backoff_reservation(&p
->ticket
, &p
->validated
);
564 /* We tried too many times, just abort */
567 DRM_ERROR("deadlock in %s\n", __func__
);
568 goto error_free_pages
;
571 /* Fill the page arrays for all useptrs. */
572 list_for_each_entry(e
, &need_pages
, tv
.head
) {
573 struct ttm_tt
*ttm
= e
->robj
->tbo
.ttm
;
575 e
->user_pages
= drm_calloc_large(ttm
->num_pages
,
576 sizeof(struct page
*));
577 if (!e
->user_pages
) {
579 DRM_ERROR("calloc failure in %s\n", __func__
);
580 goto error_free_pages
;
583 r
= amdgpu_ttm_tt_get_user_pages(ttm
, e
->user_pages
);
585 DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n");
586 drm_free_large(e
->user_pages
);
587 e
->user_pages
= NULL
;
588 goto error_free_pages
;
593 list_splice(&need_pages
, &p
->validated
);
596 amdgpu_vm_get_pt_bos(p
->adev
, &fpriv
->vm
, &duplicates
);
598 p
->bytes_moved_threshold
= amdgpu_cs_get_threshold_for_moves(p
->adev
);
600 p
->evictable
= list_last_entry(&p
->validated
,
601 struct amdgpu_bo_list_entry
,
604 r
= amdgpu_cs_list_validate(p
, &duplicates
);
606 DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n");
610 r
= amdgpu_cs_list_validate(p
, &p
->validated
);
612 DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n");
616 amdgpu_cs_report_moved_bytes(p
->adev
, p
->bytes_moved
);
618 fpriv
->vm
.last_eviction_counter
=
619 atomic64_read(&p
->adev
->num_evictions
);
622 struct amdgpu_bo
*gds
= p
->bo_list
->gds_obj
;
623 struct amdgpu_bo
*gws
= p
->bo_list
->gws_obj
;
624 struct amdgpu_bo
*oa
= p
->bo_list
->oa_obj
;
625 struct amdgpu_vm
*vm
= &fpriv
->vm
;
628 for (i
= 0; i
< p
->bo_list
->num_entries
; i
++) {
629 struct amdgpu_bo
*bo
= p
->bo_list
->array
[i
].robj
;
631 p
->bo_list
->array
[i
].bo_va
= amdgpu_vm_bo_find(vm
, bo
);
635 p
->job
->gds_base
= amdgpu_bo_gpu_offset(gds
);
636 p
->job
->gds_size
= amdgpu_bo_size(gds
);
639 p
->job
->gws_base
= amdgpu_bo_gpu_offset(gws
);
640 p
->job
->gws_size
= amdgpu_bo_size(gws
);
643 p
->job
->oa_base
= amdgpu_bo_gpu_offset(oa
);
644 p
->job
->oa_size
= amdgpu_bo_size(oa
);
648 if (!r
&& p
->uf_entry
.robj
) {
649 struct amdgpu_bo
*uf
= p
->uf_entry
.robj
;
651 r
= amdgpu_ttm_bind(&uf
->tbo
, &uf
->tbo
.mem
);
652 p
->job
->uf_addr
+= amdgpu_bo_gpu_offset(uf
);
657 amdgpu_vm_move_pt_bos_in_lru(p
->adev
, &fpriv
->vm
);
658 ttm_eu_backoff_reservation(&p
->ticket
, &p
->validated
);
664 up_read(¤t
->mm
->mmap_sem
);
667 for (i
= p
->bo_list
->first_userptr
;
668 i
< p
->bo_list
->num_entries
; ++i
) {
669 e
= &p
->bo_list
->array
[i
];
674 release_pages(e
->user_pages
,
675 e
->robj
->tbo
.ttm
->num_pages
,
677 drm_free_large(e
->user_pages
);
684 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser
*p
)
686 struct amdgpu_bo_list_entry
*e
;
689 list_for_each_entry(e
, &p
->validated
, tv
.head
) {
690 struct reservation_object
*resv
= e
->robj
->tbo
.resv
;
691 r
= amdgpu_sync_resv(p
->adev
, &p
->job
->sync
, resv
, p
->filp
);
700 * cs_parser_fini() - clean parser states
701 * @parser: parser structure holding parsing context.
702 * @error: error number
704 * If error is set than unvalidate buffer, otherwise just free memory
705 * used by parsing context.
707 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser
*parser
, int error
, bool backoff
)
709 struct amdgpu_fpriv
*fpriv
= parser
->filp
->driver_priv
;
713 amdgpu_vm_move_pt_bos_in_lru(parser
->adev
, &fpriv
->vm
);
715 ttm_eu_fence_buffer_objects(&parser
->ticket
,
718 } else if (backoff
) {
719 ttm_eu_backoff_reservation(&parser
->ticket
,
722 fence_put(parser
->fence
);
725 amdgpu_ctx_put(parser
->ctx
);
727 amdgpu_bo_list_put(parser
->bo_list
);
729 for (i
= 0; i
< parser
->nchunks
; i
++)
730 drm_free_large(parser
->chunks
[i
].kdata
);
731 kfree(parser
->chunks
);
733 amdgpu_job_free(parser
->job
);
734 amdgpu_bo_unref(&parser
->uf_entry
.robj
);
737 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser
*p
,
738 struct amdgpu_vm
*vm
)
740 struct amdgpu_device
*adev
= p
->adev
;
741 struct amdgpu_bo_va
*bo_va
;
742 struct amdgpu_bo
*bo
;
745 r
= amdgpu_vm_update_page_directory(adev
, vm
);
749 r
= amdgpu_sync_fence(adev
, &p
->job
->sync
, vm
->page_directory_fence
);
753 r
= amdgpu_vm_clear_freed(adev
, vm
);
758 for (i
= 0; i
< p
->bo_list
->num_entries
; i
++) {
761 /* ignore duplicates */
762 bo
= p
->bo_list
->array
[i
].robj
;
766 bo_va
= p
->bo_list
->array
[i
].bo_va
;
770 r
= amdgpu_vm_bo_update(adev
, bo_va
, false);
774 f
= bo_va
->last_pt_update
;
775 r
= amdgpu_sync_fence(adev
, &p
->job
->sync
, f
);
782 r
= amdgpu_vm_clear_invalids(adev
, vm
, &p
->job
->sync
);
784 if (amdgpu_vm_debug
&& p
->bo_list
) {
785 /* Invalidate all BOs to test for userspace bugs */
786 for (i
= 0; i
< p
->bo_list
->num_entries
; i
++) {
787 /* ignore duplicates */
788 bo
= p
->bo_list
->array
[i
].robj
;
792 amdgpu_vm_bo_invalidate(adev
, bo
);
799 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device
*adev
,
800 struct amdgpu_cs_parser
*p
)
802 struct amdgpu_fpriv
*fpriv
= p
->filp
->driver_priv
;
803 struct amdgpu_vm
*vm
= &fpriv
->vm
;
804 struct amdgpu_ring
*ring
= p
->job
->ring
;
807 /* Only for UVD/VCE VM emulation */
808 if (ring
->funcs
->parse_cs
) {
810 for (i
= 0; i
< p
->job
->num_ibs
; i
++) {
811 r
= amdgpu_ring_parse_cs(ring
, p
, i
);
816 p
->job
->vm_pd_addr
= amdgpu_bo_gpu_offset(vm
->page_directory
);
818 r
= amdgpu_bo_vm_update_pte(p
, vm
);
823 return amdgpu_cs_sync_rings(p
);
826 static int amdgpu_cs_handle_lockup(struct amdgpu_device
*adev
, int r
)
829 r
= amdgpu_gpu_reset(adev
);
836 static int amdgpu_cs_ib_fill(struct amdgpu_device
*adev
,
837 struct amdgpu_cs_parser
*parser
)
839 struct amdgpu_fpriv
*fpriv
= parser
->filp
->driver_priv
;
840 struct amdgpu_vm
*vm
= &fpriv
->vm
;
844 for (i
= 0, j
= 0; i
< parser
->nchunks
&& j
< parser
->job
->num_ibs
; i
++) {
845 struct amdgpu_cs_chunk
*chunk
;
846 struct amdgpu_ib
*ib
;
847 struct drm_amdgpu_cs_chunk_ib
*chunk_ib
;
848 struct amdgpu_ring
*ring
;
850 chunk
= &parser
->chunks
[i
];
851 ib
= &parser
->job
->ibs
[j
];
852 chunk_ib
= (struct drm_amdgpu_cs_chunk_ib
*)chunk
->kdata
;
854 if (chunk
->chunk_id
!= AMDGPU_CHUNK_ID_IB
)
857 r
= amdgpu_cs_get_ring(adev
, chunk_ib
->ip_type
,
858 chunk_ib
->ip_instance
, chunk_ib
->ring
,
863 if (ib
->flags
& AMDGPU_IB_FLAG_PREAMBLE
) {
864 parser
->job
->preamble_status
|= AMDGPU_PREAMBLE_IB_PRESENT
;
865 if (!parser
->ctx
->preamble_presented
) {
866 parser
->job
->preamble_status
|= AMDGPU_PREAMBLE_IB_PRESENT_FIRST
;
867 parser
->ctx
->preamble_presented
= true;
871 if (parser
->job
->ring
&& parser
->job
->ring
!= ring
)
874 parser
->job
->ring
= ring
;
876 if (ring
->funcs
->parse_cs
) {
877 struct amdgpu_bo_va_mapping
*m
;
878 struct amdgpu_bo
*aobj
= NULL
;
882 m
= amdgpu_cs_find_mapping(parser
, chunk_ib
->va_start
,
885 DRM_ERROR("IB va_start is invalid\n");
889 if ((chunk_ib
->va_start
+ chunk_ib
->ib_bytes
) >
890 (m
->it
.last
+ 1) * AMDGPU_GPU_PAGE_SIZE
) {
891 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
895 /* the IB should be reserved at this point */
896 r
= amdgpu_bo_kmap(aobj
, (void **)&kptr
);
901 offset
= ((uint64_t)m
->it
.start
) * AMDGPU_GPU_PAGE_SIZE
;
902 kptr
+= chunk_ib
->va_start
- offset
;
904 r
= amdgpu_ib_get(adev
, NULL
, chunk_ib
->ib_bytes
, ib
);
906 DRM_ERROR("Failed to get ib !\n");
910 memcpy(ib
->ptr
, kptr
, chunk_ib
->ib_bytes
);
911 amdgpu_bo_kunmap(aobj
);
913 r
= amdgpu_ib_get(adev
, vm
, 0, ib
);
915 DRM_ERROR("Failed to get ib !\n");
919 ib
->gpu_addr
= chunk_ib
->va_start
;
922 ib
->length_dw
= chunk_ib
->ib_bytes
/ 4;
923 ib
->flags
= chunk_ib
->flags
;
927 /* UVD & VCE fw doesn't support user fences */
928 if (parser
->job
->uf_addr
&& (
929 parser
->job
->ring
->type
== AMDGPU_RING_TYPE_UVD
||
930 parser
->job
->ring
->type
== AMDGPU_RING_TYPE_VCE
))
936 static int amdgpu_cs_dependencies(struct amdgpu_device
*adev
,
937 struct amdgpu_cs_parser
*p
)
939 struct amdgpu_fpriv
*fpriv
= p
->filp
->driver_priv
;
942 for (i
= 0; i
< p
->nchunks
; ++i
) {
943 struct drm_amdgpu_cs_chunk_dep
*deps
;
944 struct amdgpu_cs_chunk
*chunk
;
947 chunk
= &p
->chunks
[i
];
949 if (chunk
->chunk_id
!= AMDGPU_CHUNK_ID_DEPENDENCIES
)
952 deps
= (struct drm_amdgpu_cs_chunk_dep
*)chunk
->kdata
;
953 num_deps
= chunk
->length_dw
* 4 /
954 sizeof(struct drm_amdgpu_cs_chunk_dep
);
956 for (j
= 0; j
< num_deps
; ++j
) {
957 struct amdgpu_ring
*ring
;
958 struct amdgpu_ctx
*ctx
;
961 r
= amdgpu_cs_get_ring(adev
, deps
[j
].ip_type
,
963 deps
[j
].ring
, &ring
);
967 ctx
= amdgpu_ctx_get(fpriv
, deps
[j
].ctx_id
);
971 fence
= amdgpu_ctx_get_fence(ctx
, ring
,
979 r
= amdgpu_sync_fence(adev
, &p
->job
->sync
,
992 static int amdgpu_cs_submit(struct amdgpu_cs_parser
*p
,
993 union drm_amdgpu_cs
*cs
)
995 struct amdgpu_ring
*ring
= p
->job
->ring
;
996 struct amd_sched_entity
*entity
= &p
->ctx
->rings
[ring
->idx
].entity
;
997 struct amdgpu_job
*job
;
1003 r
= amd_sched_job_init(&job
->base
, &ring
->sched
, entity
, p
->filp
);
1005 amdgpu_job_free(job
);
1009 job
->owner
= p
->filp
;
1010 job
->fence_ctx
= entity
->fence_context
;
1011 p
->fence
= fence_get(&job
->base
.s_fence
->finished
);
1012 cs
->out
.handle
= amdgpu_ctx_add_fence(p
->ctx
, ring
, p
->fence
);
1013 job
->uf_sequence
= cs
->out
.handle
;
1014 amdgpu_job_free_resources(job
);
1016 trace_amdgpu_cs_ioctl(job
);
1017 amd_sched_entity_push_job(&job
->base
);
1022 int amdgpu_cs_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
)
1024 struct amdgpu_device
*adev
= dev
->dev_private
;
1025 union drm_amdgpu_cs
*cs
= data
;
1026 struct amdgpu_cs_parser parser
= {};
1027 bool reserved_buffers
= false;
1030 if (!adev
->accel_working
)
1036 r
= amdgpu_cs_parser_init(&parser
, data
);
1038 DRM_ERROR("Failed to initialize parser !\n");
1039 amdgpu_cs_parser_fini(&parser
, r
, false);
1040 r
= amdgpu_cs_handle_lockup(adev
, r
);
1043 r
= amdgpu_cs_parser_bos(&parser
, data
);
1045 DRM_ERROR("Not enough memory for command submission!\n");
1046 else if (r
&& r
!= -ERESTARTSYS
)
1047 DRM_ERROR("Failed to process the buffer list %d!\n", r
);
1049 reserved_buffers
= true;
1050 r
= amdgpu_cs_ib_fill(adev
, &parser
);
1054 r
= amdgpu_cs_dependencies(adev
, &parser
);
1056 DRM_ERROR("Failed in the dependencies handling %d!\n", r
);
1062 for (i
= 0; i
< parser
.job
->num_ibs
; i
++)
1063 trace_amdgpu_cs(&parser
, i
);
1065 r
= amdgpu_cs_ib_vm_chunk(adev
, &parser
);
1069 r
= amdgpu_cs_submit(&parser
, cs
);
1072 amdgpu_cs_parser_fini(&parser
, r
, reserved_buffers
);
1073 r
= amdgpu_cs_handle_lockup(adev
, r
);
1078 * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1081 * @data: data from userspace
1082 * @filp: file private
1084 * Wait for the command submission identified by handle to finish.
1086 int amdgpu_cs_wait_ioctl(struct drm_device
*dev
, void *data
,
1087 struct drm_file
*filp
)
1089 union drm_amdgpu_wait_cs
*wait
= data
;
1090 struct amdgpu_device
*adev
= dev
->dev_private
;
1091 unsigned long timeout
= amdgpu_gem_timeout(wait
->in
.timeout
);
1092 struct amdgpu_ring
*ring
= NULL
;
1093 struct amdgpu_ctx
*ctx
;
1094 struct fence
*fence
;
1097 r
= amdgpu_cs_get_ring(adev
, wait
->in
.ip_type
, wait
->in
.ip_instance
,
1098 wait
->in
.ring
, &ring
);
1102 ctx
= amdgpu_ctx_get(filp
->driver_priv
, wait
->in
.ctx_id
);
1106 fence
= amdgpu_ctx_get_fence(ctx
, ring
, wait
->in
.handle
);
1110 r
= fence_wait_timeout(fence
, true, timeout
);
1115 amdgpu_ctx_put(ctx
);
1119 memset(wait
, 0, sizeof(*wait
));
1120 wait
->out
.status
= (r
== 0);
1126 * amdgpu_cs_find_bo_va - find bo_va for VM address
1128 * @parser: command submission parser context
1130 * @bo: resulting BO of the mapping found
1132 * Search the buffer objects in the command submission context for a certain
1133 * virtual memory address. Returns allocation structure when found, NULL
1136 struct amdgpu_bo_va_mapping
*
1137 amdgpu_cs_find_mapping(struct amdgpu_cs_parser
*parser
,
1138 uint64_t addr
, struct amdgpu_bo
**bo
)
1140 struct amdgpu_bo_va_mapping
*mapping
;
1143 if (!parser
->bo_list
)
1146 addr
/= AMDGPU_GPU_PAGE_SIZE
;
1148 for (i
= 0; i
< parser
->bo_list
->num_entries
; i
++) {
1149 struct amdgpu_bo_list_entry
*lobj
;
1151 lobj
= &parser
->bo_list
->array
[i
];
1155 list_for_each_entry(mapping
, &lobj
->bo_va
->valids
, list
) {
1156 if (mapping
->it
.start
> addr
||
1157 addr
> mapping
->it
.last
)
1160 *bo
= lobj
->bo_va
->bo
;
1164 list_for_each_entry(mapping
, &lobj
->bo_va
->invalids
, list
) {
1165 if (mapping
->it
.start
> addr
||
1166 addr
> mapping
->it
.last
)
1169 *bo
= lobj
->bo_va
->bo
;
1178 * amdgpu_cs_sysvm_access_required - make BOs accessible by the system VM
1180 * @parser: command submission parser context
1182 * Helper for UVD/VCE VM emulation, make sure BOs are accessible by the system VM.
1184 int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser
*parser
)
1189 if (!parser
->bo_list
)
1192 for (i
= 0; i
< parser
->bo_list
->num_entries
; i
++) {
1193 struct amdgpu_bo
*bo
= parser
->bo_list
->array
[i
].robj
;
1195 r
= amdgpu_ttm_bind(&bo
->tbo
, &bo
->tbo
.mem
);