2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/kthread.h>
29 #include <linux/console.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/amdgpu_drm.h>
36 #include <linux/vgaarb.h>
37 #include <linux/vga_switcheroo.h>
38 #include <linux/efi.h>
40 #include "amdgpu_trace.h"
41 #include "amdgpu_i2c.h"
43 #include "amdgpu_atombios.h"
44 #include "amdgpu_atomfirmware.h"
46 #ifdef CONFIG_DRM_AMDGPU_SI
49 #ifdef CONFIG_DRM_AMDGPU_CIK
54 #include "bif/bif_4_1_d.h"
55 #include <linux/pci.h>
56 #include <linux/firmware.h>
57 #include "amdgpu_vf_error.h"
59 #include "amdgpu_amdkfd.h"
61 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
62 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
64 #define AMDGPU_RESUME_MS 2000
66 static int amdgpu_debugfs_regs_init(struct amdgpu_device
*adev
);
67 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device
*adev
);
68 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device
*adev
);
69 static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device
*adev
);
71 static const char *amdgpu_asic_name
[] = {
95 bool amdgpu_device_is_px(struct drm_device
*dev
)
97 struct amdgpu_device
*adev
= dev
->dev_private
;
99 if (adev
->flags
& AMD_IS_PX
)
105 * MMIO register access helper functions.
107 uint32_t amdgpu_mm_rreg(struct amdgpu_device
*adev
, uint32_t reg
,
112 if (!(acc_flags
& AMDGPU_REGS_NO_KIQ
) && amdgpu_sriov_runtime(adev
)) {
113 BUG_ON(in_interrupt());
114 return amdgpu_virt_kiq_rreg(adev
, reg
);
117 if ((reg
* 4) < adev
->rmmio_size
&& !(acc_flags
& AMDGPU_REGS_IDX
))
118 ret
= readl(((void __iomem
*)adev
->rmmio
) + (reg
* 4));
122 spin_lock_irqsave(&adev
->mmio_idx_lock
, flags
);
123 writel((reg
* 4), ((void __iomem
*)adev
->rmmio
) + (mmMM_INDEX
* 4));
124 ret
= readl(((void __iomem
*)adev
->rmmio
) + (mmMM_DATA
* 4));
125 spin_unlock_irqrestore(&adev
->mmio_idx_lock
, flags
);
127 trace_amdgpu_mm_rreg(adev
->pdev
->device
, reg
, ret
);
131 void amdgpu_mm_wreg(struct amdgpu_device
*adev
, uint32_t reg
, uint32_t v
,
134 trace_amdgpu_mm_wreg(adev
->pdev
->device
, reg
, v
);
136 if (adev
->asic_type
>= CHIP_VEGA10
&& reg
== 0) {
137 adev
->last_mm_index
= v
;
140 if (!(acc_flags
& AMDGPU_REGS_NO_KIQ
) && amdgpu_sriov_runtime(adev
)) {
141 BUG_ON(in_interrupt());
142 return amdgpu_virt_kiq_wreg(adev
, reg
, v
);
145 if ((reg
* 4) < adev
->rmmio_size
&& !(acc_flags
& AMDGPU_REGS_IDX
))
146 writel(v
, ((void __iomem
*)adev
->rmmio
) + (reg
* 4));
150 spin_lock_irqsave(&adev
->mmio_idx_lock
, flags
);
151 writel((reg
* 4), ((void __iomem
*)adev
->rmmio
) + (mmMM_INDEX
* 4));
152 writel(v
, ((void __iomem
*)adev
->rmmio
) + (mmMM_DATA
* 4));
153 spin_unlock_irqrestore(&adev
->mmio_idx_lock
, flags
);
156 if (adev
->asic_type
>= CHIP_VEGA10
&& reg
== 1 && adev
->last_mm_index
== 0x5702C) {
161 u32
amdgpu_io_rreg(struct amdgpu_device
*adev
, u32 reg
)
163 if ((reg
* 4) < adev
->rio_mem_size
)
164 return ioread32(adev
->rio_mem
+ (reg
* 4));
166 iowrite32((reg
* 4), adev
->rio_mem
+ (mmMM_INDEX
* 4));
167 return ioread32(adev
->rio_mem
+ (mmMM_DATA
* 4));
171 void amdgpu_io_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
173 if (adev
->asic_type
>= CHIP_VEGA10
&& reg
== 0) {
174 adev
->last_mm_index
= v
;
177 if ((reg
* 4) < adev
->rio_mem_size
)
178 iowrite32(v
, adev
->rio_mem
+ (reg
* 4));
180 iowrite32((reg
* 4), adev
->rio_mem
+ (mmMM_INDEX
* 4));
181 iowrite32(v
, adev
->rio_mem
+ (mmMM_DATA
* 4));
184 if (adev
->asic_type
>= CHIP_VEGA10
&& reg
== 1 && adev
->last_mm_index
== 0x5702C) {
190 * amdgpu_mm_rdoorbell - read a doorbell dword
192 * @adev: amdgpu_device pointer
193 * @index: doorbell index
195 * Returns the value in the doorbell aperture at the
196 * requested doorbell index (CIK).
198 u32
amdgpu_mm_rdoorbell(struct amdgpu_device
*adev
, u32 index
)
200 if (index
< adev
->doorbell
.num_doorbells
) {
201 return readl(adev
->doorbell
.ptr
+ index
);
203 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index
);
209 * amdgpu_mm_wdoorbell - write a doorbell dword
211 * @adev: amdgpu_device pointer
212 * @index: doorbell index
215 * Writes @v to the doorbell aperture at the
216 * requested doorbell index (CIK).
218 void amdgpu_mm_wdoorbell(struct amdgpu_device
*adev
, u32 index
, u32 v
)
220 if (index
< adev
->doorbell
.num_doorbells
) {
221 writel(v
, adev
->doorbell
.ptr
+ index
);
223 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index
);
228 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
230 * @adev: amdgpu_device pointer
231 * @index: doorbell index
233 * Returns the value in the doorbell aperture at the
234 * requested doorbell index (VEGA10+).
236 u64
amdgpu_mm_rdoorbell64(struct amdgpu_device
*adev
, u32 index
)
238 if (index
< adev
->doorbell
.num_doorbells
) {
239 return atomic64_read((atomic64_t
*)(adev
->doorbell
.ptr
+ index
));
241 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index
);
247 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
249 * @adev: amdgpu_device pointer
250 * @index: doorbell index
253 * Writes @v to the doorbell aperture at the
254 * requested doorbell index (VEGA10+).
256 void amdgpu_mm_wdoorbell64(struct amdgpu_device
*adev
, u32 index
, u64 v
)
258 if (index
< adev
->doorbell
.num_doorbells
) {
259 atomic64_set((atomic64_t
*)(adev
->doorbell
.ptr
+ index
), v
);
261 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index
);
266 * amdgpu_invalid_rreg - dummy reg read function
268 * @adev: amdgpu device pointer
269 * @reg: offset of register
271 * Dummy register read function. Used for register blocks
272 * that certain asics don't have (all asics).
273 * Returns the value in the register.
275 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device
*adev
, uint32_t reg
)
277 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg
);
283 * amdgpu_invalid_wreg - dummy reg write function
285 * @adev: amdgpu device pointer
286 * @reg: offset of register
287 * @v: value to write to the register
289 * Dummy register read function. Used for register blocks
290 * that certain asics don't have (all asics).
292 static void amdgpu_invalid_wreg(struct amdgpu_device
*adev
, uint32_t reg
, uint32_t v
)
294 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
300 * amdgpu_block_invalid_rreg - dummy reg read function
302 * @adev: amdgpu device pointer
303 * @block: offset of instance
304 * @reg: offset of register
306 * Dummy register read function. Used for register blocks
307 * that certain asics don't have (all asics).
308 * Returns the value in the register.
310 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device
*adev
,
311 uint32_t block
, uint32_t reg
)
313 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
320 * amdgpu_block_invalid_wreg - dummy reg write function
322 * @adev: amdgpu device pointer
323 * @block: offset of instance
324 * @reg: offset of register
325 * @v: value to write to the register
327 * Dummy register read function. Used for register blocks
328 * that certain asics don't have (all asics).
330 static void amdgpu_block_invalid_wreg(struct amdgpu_device
*adev
,
332 uint32_t reg
, uint32_t v
)
334 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
339 static int amdgpu_vram_scratch_init(struct amdgpu_device
*adev
)
341 return amdgpu_bo_create_kernel(adev
, AMDGPU_GPU_PAGE_SIZE
,
342 PAGE_SIZE
, AMDGPU_GEM_DOMAIN_VRAM
,
343 &adev
->vram_scratch
.robj
,
344 &adev
->vram_scratch
.gpu_addr
,
345 (void **)&adev
->vram_scratch
.ptr
);
348 static void amdgpu_vram_scratch_fini(struct amdgpu_device
*adev
)
350 amdgpu_bo_free_kernel(&adev
->vram_scratch
.robj
, NULL
, NULL
);
354 * amdgpu_program_register_sequence - program an array of registers.
356 * @adev: amdgpu_device pointer
357 * @registers: pointer to the register array
358 * @array_size: size of the register array
360 * Programs an array or registers with and and or masks.
361 * This is a helper for setting golden registers.
363 void amdgpu_program_register_sequence(struct amdgpu_device
*adev
,
364 const u32
*registers
,
365 const u32 array_size
)
367 u32 tmp
, reg
, and_mask
, or_mask
;
373 for (i
= 0; i
< array_size
; i
+=3) {
374 reg
= registers
[i
+ 0];
375 and_mask
= registers
[i
+ 1];
376 or_mask
= registers
[i
+ 2];
378 if (and_mask
== 0xffffffff) {
389 void amdgpu_pci_config_reset(struct amdgpu_device
*adev
)
391 pci_write_config_dword(adev
->pdev
, 0x7c, AMDGPU_ASIC_RESET_DATA
);
395 * GPU doorbell aperture helpers function.
398 * amdgpu_doorbell_init - Init doorbell driver information.
400 * @adev: amdgpu_device pointer
402 * Init doorbell driver information (CIK)
403 * Returns 0 on success, error on failure.
405 static int amdgpu_doorbell_init(struct amdgpu_device
*adev
)
407 /* No doorbell on SI hardware generation */
408 if (adev
->asic_type
< CHIP_BONAIRE
) {
409 adev
->doorbell
.base
= 0;
410 adev
->doorbell
.size
= 0;
411 adev
->doorbell
.num_doorbells
= 0;
412 adev
->doorbell
.ptr
= NULL
;
416 /* doorbell bar mapping */
417 adev
->doorbell
.base
= pci_resource_start(adev
->pdev
, 2);
418 adev
->doorbell
.size
= pci_resource_len(adev
->pdev
, 2);
420 adev
->doorbell
.num_doorbells
= min_t(u32
, adev
->doorbell
.size
/ sizeof(u32
),
421 AMDGPU_DOORBELL_MAX_ASSIGNMENT
+1);
422 if (adev
->doorbell
.num_doorbells
== 0)
425 adev
->doorbell
.ptr
= ioremap(adev
->doorbell
.base
,
426 adev
->doorbell
.num_doorbells
*
428 if (adev
->doorbell
.ptr
== NULL
)
435 * amdgpu_doorbell_fini - Tear down doorbell driver information.
437 * @adev: amdgpu_device pointer
439 * Tear down doorbell driver information (CIK)
441 static void amdgpu_doorbell_fini(struct amdgpu_device
*adev
)
443 iounmap(adev
->doorbell
.ptr
);
444 adev
->doorbell
.ptr
= NULL
;
448 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
451 * @adev: amdgpu_device pointer
452 * @aperture_base: output returning doorbell aperture base physical address
453 * @aperture_size: output returning doorbell aperture size in bytes
454 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
456 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
457 * takes doorbells required for its own rings and reports the setup to amdkfd.
458 * amdgpu reserved doorbells are at the start of the doorbell aperture.
460 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device
*adev
,
461 phys_addr_t
*aperture_base
,
462 size_t *aperture_size
,
463 size_t *start_offset
)
466 * The first num_doorbells are used by amdgpu.
467 * amdkfd takes whatever's left in the aperture.
469 if (adev
->doorbell
.size
> adev
->doorbell
.num_doorbells
* sizeof(u32
)) {
470 *aperture_base
= adev
->doorbell
.base
;
471 *aperture_size
= adev
->doorbell
.size
;
472 *start_offset
= adev
->doorbell
.num_doorbells
* sizeof(u32
);
482 * Writeback is the method by which the GPU updates special pages in memory
483 * with the status of certain GPU events (fences, ring pointers,etc.).
487 * amdgpu_wb_fini - Disable Writeback and free memory
489 * @adev: amdgpu_device pointer
491 * Disables Writeback and frees the Writeback memory (all asics).
492 * Used at driver shutdown.
494 static void amdgpu_wb_fini(struct amdgpu_device
*adev
)
496 if (adev
->wb
.wb_obj
) {
497 amdgpu_bo_free_kernel(&adev
->wb
.wb_obj
,
499 (void **)&adev
->wb
.wb
);
500 adev
->wb
.wb_obj
= NULL
;
505 * amdgpu_wb_init- Init Writeback driver info and allocate memory
507 * @adev: amdgpu_device pointer
509 * Initializes writeback and allocates writeback memory (all asics).
510 * Used at driver startup.
511 * Returns 0 on success or an -error on failure.
513 static int amdgpu_wb_init(struct amdgpu_device
*adev
)
517 if (adev
->wb
.wb_obj
== NULL
) {
518 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
519 r
= amdgpu_bo_create_kernel(adev
, AMDGPU_MAX_WB
* sizeof(uint32_t) * 8,
520 PAGE_SIZE
, AMDGPU_GEM_DOMAIN_GTT
,
521 &adev
->wb
.wb_obj
, &adev
->wb
.gpu_addr
,
522 (void **)&adev
->wb
.wb
);
524 dev_warn(adev
->dev
, "(%d) create WB bo failed\n", r
);
528 adev
->wb
.num_wb
= AMDGPU_MAX_WB
;
529 memset(&adev
->wb
.used
, 0, sizeof(adev
->wb
.used
));
531 /* clear wb memory */
532 memset((char *)adev
->wb
.wb
, 0, AMDGPU_MAX_WB
* sizeof(uint32_t));
539 * amdgpu_wb_get - Allocate a wb entry
541 * @adev: amdgpu_device pointer
544 * Allocate a wb slot for use by the driver (all asics).
545 * Returns 0 on success or -EINVAL on failure.
547 int amdgpu_wb_get(struct amdgpu_device
*adev
, u32
*wb
)
549 unsigned long offset
= find_first_zero_bit(adev
->wb
.used
, adev
->wb
.num_wb
);
551 if (offset
< adev
->wb
.num_wb
) {
552 __set_bit(offset
, adev
->wb
.used
);
553 *wb
= offset
* 8; /* convert to dw offset */
561 * amdgpu_wb_free - Free a wb entry
563 * @adev: amdgpu_device pointer
566 * Free a wb slot allocated for use by the driver (all asics)
568 void amdgpu_wb_free(struct amdgpu_device
*adev
, u32 wb
)
570 if (wb
< adev
->wb
.num_wb
)
571 __clear_bit(wb
, adev
->wb
.used
);
575 * amdgpu_vram_location - try to find VRAM location
576 * @adev: amdgpu device structure holding all necessary informations
577 * @mc: memory controller structure holding memory informations
578 * @base: base address at which to put VRAM
580 * Function will try to place VRAM at base address provided
581 * as parameter (which is so far either PCI aperture address or
582 * for IGP TOM base address).
584 * If there is not enough space to fit the unvisible VRAM in the 32bits
585 * address space then we limit the VRAM size to the aperture.
587 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
588 * this shouldn't be a problem as we are using the PCI aperture as a reference.
589 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
592 * Note: we use mc_vram_size as on some board we need to program the mc to
593 * cover the whole aperture even if VRAM size is inferior to aperture size
594 * Novell bug 204882 + along with lots of ubuntu ones
596 * Note: when limiting vram it's safe to overwritte real_vram_size because
597 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
598 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
601 * Note: IGP TOM addr should be the same as the aperture addr, we don't
602 * explicitly check for that though.
604 * FIXME: when reducing VRAM size align new size on power of 2.
606 void amdgpu_vram_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
, u64 base
)
608 uint64_t limit
= (uint64_t)amdgpu_vram_limit
<< 20;
610 mc
->vram_start
= base
;
611 if (mc
->mc_vram_size
> (adev
->mc
.mc_mask
- base
+ 1)) {
612 dev_warn(adev
->dev
, "limiting VRAM to PCI aperture size\n");
613 mc
->real_vram_size
= mc
->aper_size
;
614 mc
->mc_vram_size
= mc
->aper_size
;
616 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
617 if (limit
&& limit
< mc
->real_vram_size
)
618 mc
->real_vram_size
= limit
;
619 dev_info(adev
->dev
, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
620 mc
->mc_vram_size
>> 20, mc
->vram_start
,
621 mc
->vram_end
, mc
->real_vram_size
>> 20);
625 * amdgpu_gart_location - try to find GTT location
626 * @adev: amdgpu device structure holding all necessary informations
627 * @mc: memory controller structure holding memory informations
629 * Function will place try to place GTT before or after VRAM.
631 * If GTT size is bigger than space left then we ajust GTT size.
632 * Thus function will never fails.
634 * FIXME: when reducing GTT size align new size on power of 2.
636 void amdgpu_gart_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
)
638 u64 size_af
, size_bf
;
640 size_af
= adev
->mc
.mc_mask
- mc
->vram_end
;
641 size_bf
= mc
->vram_start
;
642 if (size_bf
> size_af
) {
643 if (mc
->gart_size
> size_bf
) {
644 dev_warn(adev
->dev
, "limiting GTT\n");
645 mc
->gart_size
= size_bf
;
649 if (mc
->gart_size
> size_af
) {
650 dev_warn(adev
->dev
, "limiting GTT\n");
651 mc
->gart_size
= size_af
;
653 mc
->gart_start
= mc
->vram_end
+ 1;
655 mc
->gart_end
= mc
->gart_start
+ mc
->gart_size
- 1;
656 dev_info(adev
->dev
, "GTT: %lluM 0x%016llX - 0x%016llX\n",
657 mc
->gart_size
>> 20, mc
->gart_start
, mc
->gart_end
);
661 * GPU helpers function.
664 * amdgpu_need_post - check if the hw need post or not
666 * @adev: amdgpu_device pointer
668 * Check if the asic has been initialized (all asics) at driver startup
669 * or post is needed if hw reset is performed.
670 * Returns true if need or false if not.
672 bool amdgpu_need_post(struct amdgpu_device
*adev
)
676 if (adev
->has_hw_reset
) {
677 adev
->has_hw_reset
= false;
681 /* bios scratch used on CIK+ */
682 if (adev
->asic_type
>= CHIP_BONAIRE
)
683 return amdgpu_atombios_scratch_need_asic_init(adev
);
685 /* check MEM_SIZE for older asics */
686 reg
= amdgpu_asic_get_config_memsize(adev
);
688 if ((reg
!= 0) && (reg
!= 0xffffffff))
695 static bool amdgpu_vpost_needed(struct amdgpu_device
*adev
)
697 if (amdgpu_sriov_vf(adev
))
700 if (amdgpu_passthrough(adev
)) {
701 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
702 * some old smc fw still need driver do vPost otherwise gpu hang, while
703 * those smc fw version above 22.15 doesn't have this flaw, so we force
704 * vpost executed for smc version below 22.15
706 if (adev
->asic_type
== CHIP_FIJI
) {
709 err
= request_firmware(&adev
->pm
.fw
, "amdgpu/fiji_smc.bin", adev
->dev
);
710 /* force vPost if error occured */
714 fw_ver
= *((uint32_t *)adev
->pm
.fw
->data
+ 69);
715 if (fw_ver
< 0x00160e00)
719 return amdgpu_need_post(adev
);
723 * amdgpu_dummy_page_init - init dummy page used by the driver
725 * @adev: amdgpu_device pointer
727 * Allocate the dummy page used by the driver (all asics).
728 * This dummy page is used by the driver as a filler for gart entries
729 * when pages are taken out of the GART
730 * Returns 0 on sucess, -ENOMEM on failure.
732 int amdgpu_dummy_page_init(struct amdgpu_device
*adev
)
734 if (adev
->dummy_page
.page
)
736 adev
->dummy_page
.page
= alloc_page(GFP_DMA32
| GFP_KERNEL
| __GFP_ZERO
);
737 if (adev
->dummy_page
.page
== NULL
)
739 adev
->dummy_page
.addr
= pci_map_page(adev
->pdev
, adev
->dummy_page
.page
,
740 0, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
741 if (pci_dma_mapping_error(adev
->pdev
, adev
->dummy_page
.addr
)) {
742 dev_err(&adev
->pdev
->dev
, "Failed to DMA MAP the dummy page\n");
743 __free_page(adev
->dummy_page
.page
);
744 adev
->dummy_page
.page
= NULL
;
751 * amdgpu_dummy_page_fini - free dummy page used by the driver
753 * @adev: amdgpu_device pointer
755 * Frees the dummy page used by the driver (all asics).
757 void amdgpu_dummy_page_fini(struct amdgpu_device
*adev
)
759 if (adev
->dummy_page
.page
== NULL
)
761 pci_unmap_page(adev
->pdev
, adev
->dummy_page
.addr
,
762 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
763 __free_page(adev
->dummy_page
.page
);
764 adev
->dummy_page
.page
= NULL
;
768 /* ATOM accessor methods */
770 * ATOM is an interpreted byte code stored in tables in the vbios. The
771 * driver registers callbacks to access registers and the interpreter
772 * in the driver parses the tables and executes then to program specific
773 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
774 * atombios.h, and atom.c
778 * cail_pll_read - read PLL register
780 * @info: atom card_info pointer
781 * @reg: PLL register offset
783 * Provides a PLL register accessor for the atom interpreter (r4xx+).
784 * Returns the value of the PLL register.
786 static uint32_t cail_pll_read(struct card_info
*info
, uint32_t reg
)
792 * cail_pll_write - write PLL register
794 * @info: atom card_info pointer
795 * @reg: PLL register offset
796 * @val: value to write to the pll register
798 * Provides a PLL register accessor for the atom interpreter (r4xx+).
800 static void cail_pll_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
806 * cail_mc_read - read MC (Memory Controller) register
808 * @info: atom card_info pointer
809 * @reg: MC register offset
811 * Provides an MC register accessor for the atom interpreter (r4xx+).
812 * Returns the value of the MC register.
814 static uint32_t cail_mc_read(struct card_info
*info
, uint32_t reg
)
820 * cail_mc_write - write MC (Memory Controller) register
822 * @info: atom card_info pointer
823 * @reg: MC register offset
824 * @val: value to write to the pll register
826 * Provides a MC register accessor for the atom interpreter (r4xx+).
828 static void cail_mc_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
834 * cail_reg_write - write MMIO register
836 * @info: atom card_info pointer
837 * @reg: MMIO register offset
838 * @val: value to write to the pll register
840 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
842 static void cail_reg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
844 struct amdgpu_device
*adev
= info
->dev
->dev_private
;
850 * cail_reg_read - read MMIO register
852 * @info: atom card_info pointer
853 * @reg: MMIO register offset
855 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
856 * Returns the value of the MMIO register.
858 static uint32_t cail_reg_read(struct card_info
*info
, uint32_t reg
)
860 struct amdgpu_device
*adev
= info
->dev
->dev_private
;
868 * cail_ioreg_write - write IO register
870 * @info: atom card_info pointer
871 * @reg: IO register offset
872 * @val: value to write to the pll register
874 * Provides a IO register accessor for the atom interpreter (r4xx+).
876 static void cail_ioreg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
878 struct amdgpu_device
*adev
= info
->dev
->dev_private
;
884 * cail_ioreg_read - read IO register
886 * @info: atom card_info pointer
887 * @reg: IO register offset
889 * Provides an IO register accessor for the atom interpreter (r4xx+).
890 * Returns the value of the IO register.
892 static uint32_t cail_ioreg_read(struct card_info
*info
, uint32_t reg
)
894 struct amdgpu_device
*adev
= info
->dev
->dev_private
;
901 static ssize_t
amdgpu_atombios_get_vbios_version(struct device
*dev
,
902 struct device_attribute
*attr
,
905 struct drm_device
*ddev
= dev_get_drvdata(dev
);
906 struct amdgpu_device
*adev
= ddev
->dev_private
;
907 struct atom_context
*ctx
= adev
->mode_info
.atom_context
;
909 return snprintf(buf
, PAGE_SIZE
, "%s\n", ctx
->vbios_version
);
912 static DEVICE_ATTR(vbios_version
, 0444, amdgpu_atombios_get_vbios_version
,
916 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
918 * @adev: amdgpu_device pointer
920 * Frees the driver info and register access callbacks for the ATOM
921 * interpreter (r4xx+).
922 * Called at driver shutdown.
924 static void amdgpu_atombios_fini(struct amdgpu_device
*adev
)
926 if (adev
->mode_info
.atom_context
) {
927 kfree(adev
->mode_info
.atom_context
->scratch
);
928 kfree(adev
->mode_info
.atom_context
->iio
);
930 kfree(adev
->mode_info
.atom_context
);
931 adev
->mode_info
.atom_context
= NULL
;
932 kfree(adev
->mode_info
.atom_card_info
);
933 adev
->mode_info
.atom_card_info
= NULL
;
934 device_remove_file(adev
->dev
, &dev_attr_vbios_version
);
938 * amdgpu_atombios_init - init the driver info and callbacks for atombios
940 * @adev: amdgpu_device pointer
942 * Initializes the driver info and register access callbacks for the
943 * ATOM interpreter (r4xx+).
944 * Returns 0 on sucess, -ENOMEM on failure.
945 * Called at driver startup.
947 static int amdgpu_atombios_init(struct amdgpu_device
*adev
)
949 struct card_info
*atom_card_info
=
950 kzalloc(sizeof(struct card_info
), GFP_KERNEL
);
956 adev
->mode_info
.atom_card_info
= atom_card_info
;
957 atom_card_info
->dev
= adev
->ddev
;
958 atom_card_info
->reg_read
= cail_reg_read
;
959 atom_card_info
->reg_write
= cail_reg_write
;
960 /* needed for iio ops */
962 atom_card_info
->ioreg_read
= cail_ioreg_read
;
963 atom_card_info
->ioreg_write
= cail_ioreg_write
;
965 DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");
966 atom_card_info
->ioreg_read
= cail_reg_read
;
967 atom_card_info
->ioreg_write
= cail_reg_write
;
969 atom_card_info
->mc_read
= cail_mc_read
;
970 atom_card_info
->mc_write
= cail_mc_write
;
971 atom_card_info
->pll_read
= cail_pll_read
;
972 atom_card_info
->pll_write
= cail_pll_write
;
974 adev
->mode_info
.atom_context
= amdgpu_atom_parse(atom_card_info
, adev
->bios
);
975 if (!adev
->mode_info
.atom_context
) {
976 amdgpu_atombios_fini(adev
);
980 mutex_init(&adev
->mode_info
.atom_context
->mutex
);
981 if (adev
->is_atom_fw
) {
982 amdgpu_atomfirmware_scratch_regs_init(adev
);
983 amdgpu_atomfirmware_allocate_fb_scratch(adev
);
985 amdgpu_atombios_scratch_regs_init(adev
);
986 amdgpu_atombios_allocate_fb_scratch(adev
);
989 ret
= device_create_file(adev
->dev
, &dev_attr_vbios_version
);
991 DRM_ERROR("Failed to create device file for VBIOS version\n");
998 /* if we get transitioned to only one device, take VGA back */
1000 * amdgpu_vga_set_decode - enable/disable vga decode
1002 * @cookie: amdgpu_device pointer
1003 * @state: enable/disable vga decode
1005 * Enable/disable vga decode (all asics).
1006 * Returns VGA resource flags.
1008 static unsigned int amdgpu_vga_set_decode(void *cookie
, bool state
)
1010 struct amdgpu_device
*adev
= cookie
;
1011 amdgpu_asic_set_vga_state(adev
, state
);
1013 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
1014 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1016 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1019 static void amdgpu_check_block_size(struct amdgpu_device
*adev
)
1021 /* defines number of bits in page table versus page directory,
1022 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1023 * page table and the remaining bits are in the page directory */
1024 if (amdgpu_vm_block_size
== -1)
1027 if (amdgpu_vm_block_size
< 9) {
1028 dev_warn(adev
->dev
, "VM page table size (%d) too small\n",
1029 amdgpu_vm_block_size
);
1033 if (amdgpu_vm_block_size
> 24 ||
1034 (amdgpu_vm_size
* 1024) < (1ull << amdgpu_vm_block_size
)) {
1035 dev_warn(adev
->dev
, "VM page table size (%d) too large\n",
1036 amdgpu_vm_block_size
);
1043 amdgpu_vm_block_size
= -1;
1046 static void amdgpu_check_vm_size(struct amdgpu_device
*adev
)
1048 /* no need to check the default value */
1049 if (amdgpu_vm_size
== -1)
1052 if (!is_power_of_2(amdgpu_vm_size
)) {
1053 dev_warn(adev
->dev
, "VM size (%d) must be a power of 2\n",
1058 if (amdgpu_vm_size
< 1) {
1059 dev_warn(adev
->dev
, "VM size (%d) too small, min is 1GB\n",
1065 * Max GPUVM size for Cayman, SI, CI VI are 40 bits.
1067 if (amdgpu_vm_size
> 1024) {
1068 dev_warn(adev
->dev
, "VM size (%d) too large, max is 1TB\n",
1076 amdgpu_vm_size
= -1;
1080 * amdgpu_check_arguments - validate module params
1082 * @adev: amdgpu_device pointer
1084 * Validates certain module parameters and updates
1085 * the associated values used by the driver (all asics).
1087 static void amdgpu_check_arguments(struct amdgpu_device
*adev
)
1089 if (amdgpu_sched_jobs
< 4) {
1090 dev_warn(adev
->dev
, "sched jobs (%d) must be at least 4\n",
1092 amdgpu_sched_jobs
= 4;
1093 } else if (!is_power_of_2(amdgpu_sched_jobs
)){
1094 dev_warn(adev
->dev
, "sched jobs (%d) must be a power of 2\n",
1096 amdgpu_sched_jobs
= roundup_pow_of_two(amdgpu_sched_jobs
);
1099 if (amdgpu_gart_size
!= -1 && amdgpu_gart_size
< 32) {
1100 /* gart size must be greater or equal to 32M */
1101 dev_warn(adev
->dev
, "gart size (%d) too small\n",
1103 amdgpu_gart_size
= -1;
1106 if (amdgpu_gtt_size
!= -1 && amdgpu_gtt_size
< 32) {
1107 /* gtt size must be greater or equal to 32M */
1108 dev_warn(adev
->dev
, "gtt size (%d) too small\n",
1110 amdgpu_gtt_size
= -1;
1113 /* valid range is between 4 and 9 inclusive */
1114 if (amdgpu_vm_fragment_size
!= -1 &&
1115 (amdgpu_vm_fragment_size
> 9 || amdgpu_vm_fragment_size
< 4)) {
1116 dev_warn(adev
->dev
, "valid range is between 4 and 9\n");
1117 amdgpu_vm_fragment_size
= -1;
1120 amdgpu_check_vm_size(adev
);
1122 amdgpu_check_block_size(adev
);
1124 if (amdgpu_vram_page_split
!= -1 && (amdgpu_vram_page_split
< 16 ||
1125 !is_power_of_2(amdgpu_vram_page_split
))) {
1126 dev_warn(adev
->dev
, "invalid VRAM page split (%d)\n",
1127 amdgpu_vram_page_split
);
1128 amdgpu_vram_page_split
= 1024;
1133 * amdgpu_switcheroo_set_state - set switcheroo state
1135 * @pdev: pci dev pointer
1136 * @state: vga_switcheroo state
1138 * Callback for the switcheroo driver. Suspends or resumes the
1139 * the asics before or after it is powered up using ACPI methods.
1141 static void amdgpu_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
1143 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1145 if (amdgpu_device_is_px(dev
) && state
== VGA_SWITCHEROO_OFF
)
1148 if (state
== VGA_SWITCHEROO_ON
) {
1149 pr_info("amdgpu: switched on\n");
1150 /* don't suspend or resume card normally */
1151 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1153 amdgpu_device_resume(dev
, true, true);
1155 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
1156 drm_kms_helper_poll_enable(dev
);
1158 pr_info("amdgpu: switched off\n");
1159 drm_kms_helper_poll_disable(dev
);
1160 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1161 amdgpu_device_suspend(dev
, true, true);
1162 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
1167 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1169 * @pdev: pci dev pointer
1171 * Callback for the switcheroo driver. Check of the switcheroo
1172 * state can be changed.
1173 * Returns true if the state can be changed, false if not.
1175 static bool amdgpu_switcheroo_can_switch(struct pci_dev
*pdev
)
1177 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1180 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1181 * locking inversion with the driver load path. And the access here is
1182 * completely racy anyway. So don't bother with locking for now.
1184 return dev
->open_count
== 0;
1187 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops
= {
1188 .set_gpu_state
= amdgpu_switcheroo_set_state
,
1190 .can_switch
= amdgpu_switcheroo_can_switch
,
1193 int amdgpu_set_clockgating_state(struct amdgpu_device
*adev
,
1194 enum amd_ip_block_type block_type
,
1195 enum amd_clockgating_state state
)
1199 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1200 if (!adev
->ip_blocks
[i
].status
.valid
)
1202 if (adev
->ip_blocks
[i
].version
->type
!= block_type
)
1204 if (!adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state
)
1206 r
= adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state(
1207 (void *)adev
, state
);
1209 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1210 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1215 int amdgpu_set_powergating_state(struct amdgpu_device
*adev
,
1216 enum amd_ip_block_type block_type
,
1217 enum amd_powergating_state state
)
1221 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1222 if (!adev
->ip_blocks
[i
].status
.valid
)
1224 if (adev
->ip_blocks
[i
].version
->type
!= block_type
)
1226 if (!adev
->ip_blocks
[i
].version
->funcs
->set_powergating_state
)
1228 r
= adev
->ip_blocks
[i
].version
->funcs
->set_powergating_state(
1229 (void *)adev
, state
);
1231 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1232 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1237 void amdgpu_get_clockgating_state(struct amdgpu_device
*adev
, u32
*flags
)
1241 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1242 if (!adev
->ip_blocks
[i
].status
.valid
)
1244 if (adev
->ip_blocks
[i
].version
->funcs
->get_clockgating_state
)
1245 adev
->ip_blocks
[i
].version
->funcs
->get_clockgating_state((void *)adev
, flags
);
1249 int amdgpu_wait_for_idle(struct amdgpu_device
*adev
,
1250 enum amd_ip_block_type block_type
)
1254 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1255 if (!adev
->ip_blocks
[i
].status
.valid
)
1257 if (adev
->ip_blocks
[i
].version
->type
== block_type
) {
1258 r
= adev
->ip_blocks
[i
].version
->funcs
->wait_for_idle((void *)adev
);
1268 bool amdgpu_is_idle(struct amdgpu_device
*adev
,
1269 enum amd_ip_block_type block_type
)
1273 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1274 if (!adev
->ip_blocks
[i
].status
.valid
)
1276 if (adev
->ip_blocks
[i
].version
->type
== block_type
)
1277 return adev
->ip_blocks
[i
].version
->funcs
->is_idle((void *)adev
);
1283 struct amdgpu_ip_block
* amdgpu_get_ip_block(struct amdgpu_device
*adev
,
1284 enum amd_ip_block_type type
)
1288 for (i
= 0; i
< adev
->num_ip_blocks
; i
++)
1289 if (adev
->ip_blocks
[i
].version
->type
== type
)
1290 return &adev
->ip_blocks
[i
];
1296 * amdgpu_ip_block_version_cmp
1298 * @adev: amdgpu_device pointer
1299 * @type: enum amd_ip_block_type
1300 * @major: major version
1301 * @minor: minor version
1303 * return 0 if equal or greater
1304 * return 1 if smaller or the ip_block doesn't exist
1306 int amdgpu_ip_block_version_cmp(struct amdgpu_device
*adev
,
1307 enum amd_ip_block_type type
,
1308 u32 major
, u32 minor
)
1310 struct amdgpu_ip_block
*ip_block
= amdgpu_get_ip_block(adev
, type
);
1312 if (ip_block
&& ((ip_block
->version
->major
> major
) ||
1313 ((ip_block
->version
->major
== major
) &&
1314 (ip_block
->version
->minor
>= minor
))))
1321 * amdgpu_ip_block_add
1323 * @adev: amdgpu_device pointer
1324 * @ip_block_version: pointer to the IP to add
1326 * Adds the IP block driver information to the collection of IPs
1329 int amdgpu_ip_block_add(struct amdgpu_device
*adev
,
1330 const struct amdgpu_ip_block_version
*ip_block_version
)
1332 if (!ip_block_version
)
1335 DRM_DEBUG("add ip block number %d <%s>\n", adev
->num_ip_blocks
,
1336 ip_block_version
->funcs
->name
);
1338 adev
->ip_blocks
[adev
->num_ip_blocks
++].version
= ip_block_version
;
1343 static void amdgpu_device_enable_virtual_display(struct amdgpu_device
*adev
)
1345 adev
->enable_virtual_display
= false;
1347 if (amdgpu_virtual_display
) {
1348 struct drm_device
*ddev
= adev
->ddev
;
1349 const char *pci_address_name
= pci_name(ddev
->pdev
);
1350 char *pciaddstr
, *pciaddstr_tmp
, *pciaddname_tmp
, *pciaddname
;
1352 pciaddstr
= kstrdup(amdgpu_virtual_display
, GFP_KERNEL
);
1353 pciaddstr_tmp
= pciaddstr
;
1354 while ((pciaddname_tmp
= strsep(&pciaddstr_tmp
, ";"))) {
1355 pciaddname
= strsep(&pciaddname_tmp
, ",");
1356 if (!strcmp("all", pciaddname
)
1357 || !strcmp(pci_address_name
, pciaddname
)) {
1361 adev
->enable_virtual_display
= true;
1364 res
= kstrtol(pciaddname_tmp
, 10,
1372 adev
->mode_info
.num_crtc
= num_crtc
;
1374 adev
->mode_info
.num_crtc
= 1;
1380 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1381 amdgpu_virtual_display
, pci_address_name
,
1382 adev
->enable_virtual_display
, adev
->mode_info
.num_crtc
);
1388 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device
*adev
)
1390 const char *chip_name
;
1393 const struct gpu_info_firmware_header_v1_0
*hdr
;
1395 adev
->firmware
.gpu_info_fw
= NULL
;
1397 switch (adev
->asic_type
) {
1401 case CHIP_POLARIS11
:
1402 case CHIP_POLARIS10
:
1403 case CHIP_POLARIS12
:
1406 #ifdef CONFIG_DRM_AMDGPU_SI
1413 #ifdef CONFIG_DRM_AMDGPU_CIK
1423 chip_name
= "vega10";
1426 chip_name
= "raven";
1430 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_gpu_info.bin", chip_name
);
1431 err
= request_firmware(&adev
->firmware
.gpu_info_fw
, fw_name
, adev
->dev
);
1434 "Failed to load gpu_info firmware \"%s\"\n",
1438 err
= amdgpu_ucode_validate(adev
->firmware
.gpu_info_fw
);
1441 "Failed to validate gpu_info firmware \"%s\"\n",
1446 hdr
= (const struct gpu_info_firmware_header_v1_0
*)adev
->firmware
.gpu_info_fw
->data
;
1447 amdgpu_ucode_print_gpu_info_hdr(&hdr
->header
);
1449 switch (hdr
->version_major
) {
1452 const struct gpu_info_firmware_v1_0
*gpu_info_fw
=
1453 (const struct gpu_info_firmware_v1_0
*)(adev
->firmware
.gpu_info_fw
->data
+
1454 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
1456 adev
->gfx
.config
.max_shader_engines
= le32_to_cpu(gpu_info_fw
->gc_num_se
);
1457 adev
->gfx
.config
.max_cu_per_sh
= le32_to_cpu(gpu_info_fw
->gc_num_cu_per_sh
);
1458 adev
->gfx
.config
.max_sh_per_se
= le32_to_cpu(gpu_info_fw
->gc_num_sh_per_se
);
1459 adev
->gfx
.config
.max_backends_per_se
= le32_to_cpu(gpu_info_fw
->gc_num_rb_per_se
);
1460 adev
->gfx
.config
.max_texture_channel_caches
=
1461 le32_to_cpu(gpu_info_fw
->gc_num_tccs
);
1462 adev
->gfx
.config
.max_gprs
= le32_to_cpu(gpu_info_fw
->gc_num_gprs
);
1463 adev
->gfx
.config
.max_gs_threads
= le32_to_cpu(gpu_info_fw
->gc_num_max_gs_thds
);
1464 adev
->gfx
.config
.gs_vgt_table_depth
= le32_to_cpu(gpu_info_fw
->gc_gs_table_depth
);
1465 adev
->gfx
.config
.gs_prim_buffer_depth
= le32_to_cpu(gpu_info_fw
->gc_gsprim_buff_depth
);
1466 adev
->gfx
.config
.double_offchip_lds_buf
=
1467 le32_to_cpu(gpu_info_fw
->gc_double_offchip_lds_buffer
);
1468 adev
->gfx
.cu_info
.wave_front_size
= le32_to_cpu(gpu_info_fw
->gc_wave_size
);
1469 adev
->gfx
.cu_info
.max_waves_per_simd
=
1470 le32_to_cpu(gpu_info_fw
->gc_max_waves_per_simd
);
1471 adev
->gfx
.cu_info
.max_scratch_slots_per_cu
=
1472 le32_to_cpu(gpu_info_fw
->gc_max_scratch_slots_per_cu
);
1473 adev
->gfx
.cu_info
.lds_size
= le32_to_cpu(gpu_info_fw
->gc_lds_size
);
1478 "Unsupported gpu_info table %d\n", hdr
->header
.ucode_version
);
1486 static int amdgpu_early_init(struct amdgpu_device
*adev
)
1490 amdgpu_device_enable_virtual_display(adev
);
1492 switch (adev
->asic_type
) {
1496 case CHIP_POLARIS11
:
1497 case CHIP_POLARIS10
:
1498 case CHIP_POLARIS12
:
1501 if (adev
->asic_type
== CHIP_CARRIZO
|| adev
->asic_type
== CHIP_STONEY
)
1502 adev
->family
= AMDGPU_FAMILY_CZ
;
1504 adev
->family
= AMDGPU_FAMILY_VI
;
1506 r
= vi_set_ip_blocks(adev
);
1510 #ifdef CONFIG_DRM_AMDGPU_SI
1516 adev
->family
= AMDGPU_FAMILY_SI
;
1517 r
= si_set_ip_blocks(adev
);
1522 #ifdef CONFIG_DRM_AMDGPU_CIK
1528 if ((adev
->asic_type
== CHIP_BONAIRE
) || (adev
->asic_type
== CHIP_HAWAII
))
1529 adev
->family
= AMDGPU_FAMILY_CI
;
1531 adev
->family
= AMDGPU_FAMILY_KV
;
1533 r
= cik_set_ip_blocks(adev
);
1540 if (adev
->asic_type
== CHIP_RAVEN
)
1541 adev
->family
= AMDGPU_FAMILY_RV
;
1543 adev
->family
= AMDGPU_FAMILY_AI
;
1545 r
= soc15_set_ip_blocks(adev
);
1550 /* FIXME: not supported yet */
1554 r
= amdgpu_device_parse_gpu_info_fw(adev
);
1558 if (amdgpu_sriov_vf(adev
)) {
1559 r
= amdgpu_virt_request_full_gpu(adev
, true);
1564 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1565 if ((amdgpu_ip_block_mask
& (1 << i
)) == 0) {
1566 DRM_ERROR("disabled ip block: %d <%s>\n",
1567 i
, adev
->ip_blocks
[i
].version
->funcs
->name
);
1568 adev
->ip_blocks
[i
].status
.valid
= false;
1570 if (adev
->ip_blocks
[i
].version
->funcs
->early_init
) {
1571 r
= adev
->ip_blocks
[i
].version
->funcs
->early_init((void *)adev
);
1573 adev
->ip_blocks
[i
].status
.valid
= false;
1575 DRM_ERROR("early_init of IP block <%s> failed %d\n",
1576 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1579 adev
->ip_blocks
[i
].status
.valid
= true;
1582 adev
->ip_blocks
[i
].status
.valid
= true;
1587 adev
->cg_flags
&= amdgpu_cg_mask
;
1588 adev
->pg_flags
&= amdgpu_pg_mask
;
1593 static int amdgpu_init(struct amdgpu_device
*adev
)
1597 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1598 if (!adev
->ip_blocks
[i
].status
.valid
)
1600 r
= adev
->ip_blocks
[i
].version
->funcs
->sw_init((void *)adev
);
1602 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1603 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1606 adev
->ip_blocks
[i
].status
.sw
= true;
1607 /* need to do gmc hw init early so we can allocate gpu mem */
1608 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_GMC
) {
1609 r
= amdgpu_vram_scratch_init(adev
);
1611 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r
);
1614 r
= adev
->ip_blocks
[i
].version
->funcs
->hw_init((void *)adev
);
1616 DRM_ERROR("hw_init %d failed %d\n", i
, r
);
1619 r
= amdgpu_wb_init(adev
);
1621 DRM_ERROR("amdgpu_wb_init failed %d\n", r
);
1624 adev
->ip_blocks
[i
].status
.hw
= true;
1626 /* right after GMC hw init, we create CSA */
1627 if (amdgpu_sriov_vf(adev
)) {
1628 r
= amdgpu_allocate_static_csa(adev
);
1630 DRM_ERROR("allocate CSA failed %d\n", r
);
1637 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1638 if (!adev
->ip_blocks
[i
].status
.sw
)
1640 /* gmc hw init is done early */
1641 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_GMC
)
1643 r
= adev
->ip_blocks
[i
].version
->funcs
->hw_init((void *)adev
);
1645 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1646 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1649 adev
->ip_blocks
[i
].status
.hw
= true;
1655 static void amdgpu_fill_reset_magic(struct amdgpu_device
*adev
)
1657 memcpy(adev
->reset_magic
, adev
->gart
.ptr
, AMDGPU_RESET_MAGIC_NUM
);
1660 static bool amdgpu_check_vram_lost(struct amdgpu_device
*adev
)
1662 return !!memcmp(adev
->gart
.ptr
, adev
->reset_magic
,
1663 AMDGPU_RESET_MAGIC_NUM
);
1666 static int amdgpu_late_set_cg_state(struct amdgpu_device
*adev
)
1670 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1671 if (!adev
->ip_blocks
[i
].status
.valid
)
1673 /* skip CG for VCE/UVD, it's handled specially */
1674 if (adev
->ip_blocks
[i
].version
->type
!= AMD_IP_BLOCK_TYPE_UVD
&&
1675 adev
->ip_blocks
[i
].version
->type
!= AMD_IP_BLOCK_TYPE_VCE
) {
1676 /* enable clockgating to save power */
1677 r
= adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state((void *)adev
,
1680 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1681 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1689 static int amdgpu_late_init(struct amdgpu_device
*adev
)
1693 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1694 if (!adev
->ip_blocks
[i
].status
.valid
)
1696 if (adev
->ip_blocks
[i
].version
->funcs
->late_init
) {
1697 r
= adev
->ip_blocks
[i
].version
->funcs
->late_init((void *)adev
);
1699 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1700 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1703 adev
->ip_blocks
[i
].status
.late_initialized
= true;
1707 mod_delayed_work(system_wq
, &adev
->late_init_work
,
1708 msecs_to_jiffies(AMDGPU_RESUME_MS
));
1710 amdgpu_fill_reset_magic(adev
);
1715 static int amdgpu_fini(struct amdgpu_device
*adev
)
1719 /* need to disable SMC first */
1720 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1721 if (!adev
->ip_blocks
[i
].status
.hw
)
1723 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_SMC
) {
1724 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1725 r
= adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state((void *)adev
,
1726 AMD_CG_STATE_UNGATE
);
1728 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1729 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1732 r
= adev
->ip_blocks
[i
].version
->funcs
->hw_fini((void *)adev
);
1733 /* XXX handle errors */
1735 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1736 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1738 adev
->ip_blocks
[i
].status
.hw
= false;
1743 for (i
= adev
->num_ip_blocks
- 1; i
>= 0; i
--) {
1744 if (!adev
->ip_blocks
[i
].status
.hw
)
1746 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_GMC
) {
1747 amdgpu_wb_fini(adev
);
1748 amdgpu_vram_scratch_fini(adev
);
1751 if (adev
->ip_blocks
[i
].version
->type
!= AMD_IP_BLOCK_TYPE_UVD
&&
1752 adev
->ip_blocks
[i
].version
->type
!= AMD_IP_BLOCK_TYPE_VCE
) {
1753 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1754 r
= adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state((void *)adev
,
1755 AMD_CG_STATE_UNGATE
);
1757 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1758 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1763 r
= adev
->ip_blocks
[i
].version
->funcs
->hw_fini((void *)adev
);
1764 /* XXX handle errors */
1766 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1767 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1770 adev
->ip_blocks
[i
].status
.hw
= false;
1773 for (i
= adev
->num_ip_blocks
- 1; i
>= 0; i
--) {
1774 if (!adev
->ip_blocks
[i
].status
.sw
)
1776 r
= adev
->ip_blocks
[i
].version
->funcs
->sw_fini((void *)adev
);
1777 /* XXX handle errors */
1779 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1780 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1782 adev
->ip_blocks
[i
].status
.sw
= false;
1783 adev
->ip_blocks
[i
].status
.valid
= false;
1786 for (i
= adev
->num_ip_blocks
- 1; i
>= 0; i
--) {
1787 if (!adev
->ip_blocks
[i
].status
.late_initialized
)
1789 if (adev
->ip_blocks
[i
].version
->funcs
->late_fini
)
1790 adev
->ip_blocks
[i
].version
->funcs
->late_fini((void *)adev
);
1791 adev
->ip_blocks
[i
].status
.late_initialized
= false;
1794 if (amdgpu_sriov_vf(adev
))
1795 amdgpu_virt_release_full_gpu(adev
, false);
1800 static void amdgpu_late_init_func_handler(struct work_struct
*work
)
1802 struct amdgpu_device
*adev
=
1803 container_of(work
, struct amdgpu_device
, late_init_work
.work
);
1804 amdgpu_late_set_cg_state(adev
);
1807 int amdgpu_suspend(struct amdgpu_device
*adev
)
1811 if (amdgpu_sriov_vf(adev
))
1812 amdgpu_virt_request_full_gpu(adev
, false);
1814 /* ungate SMC block first */
1815 r
= amdgpu_set_clockgating_state(adev
, AMD_IP_BLOCK_TYPE_SMC
,
1816 AMD_CG_STATE_UNGATE
);
1818 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r
);
1821 for (i
= adev
->num_ip_blocks
- 1; i
>= 0; i
--) {
1822 if (!adev
->ip_blocks
[i
].status
.valid
)
1824 /* ungate blocks so that suspend can properly shut them down */
1825 if (i
!= AMD_IP_BLOCK_TYPE_SMC
) {
1826 r
= adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state((void *)adev
,
1827 AMD_CG_STATE_UNGATE
);
1829 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1830 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1833 /* XXX handle errors */
1834 r
= adev
->ip_blocks
[i
].version
->funcs
->suspend(adev
);
1835 /* XXX handle errors */
1837 DRM_ERROR("suspend of IP block <%s> failed %d\n",
1838 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1842 if (amdgpu_sriov_vf(adev
))
1843 amdgpu_virt_release_full_gpu(adev
, false);
1848 static int amdgpu_sriov_reinit_early(struct amdgpu_device
*adev
)
1852 static enum amd_ip_block_type ip_order
[] = {
1853 AMD_IP_BLOCK_TYPE_GMC
,
1854 AMD_IP_BLOCK_TYPE_COMMON
,
1855 AMD_IP_BLOCK_TYPE_IH
,
1858 for (i
= 0; i
< ARRAY_SIZE(ip_order
); i
++) {
1860 struct amdgpu_ip_block
*block
;
1862 for (j
= 0; j
< adev
->num_ip_blocks
; j
++) {
1863 block
= &adev
->ip_blocks
[j
];
1865 if (block
->version
->type
!= ip_order
[i
] ||
1866 !block
->status
.valid
)
1869 r
= block
->version
->funcs
->hw_init(adev
);
1870 DRM_INFO("RE-INIT: %s %s\n", block
->version
->funcs
->name
, r
?"failed":"successed");
1877 static int amdgpu_sriov_reinit_late(struct amdgpu_device
*adev
)
1881 static enum amd_ip_block_type ip_order
[] = {
1882 AMD_IP_BLOCK_TYPE_SMC
,
1883 AMD_IP_BLOCK_TYPE_DCE
,
1884 AMD_IP_BLOCK_TYPE_GFX
,
1885 AMD_IP_BLOCK_TYPE_SDMA
,
1886 AMD_IP_BLOCK_TYPE_UVD
,
1887 AMD_IP_BLOCK_TYPE_VCE
1890 for (i
= 0; i
< ARRAY_SIZE(ip_order
); i
++) {
1892 struct amdgpu_ip_block
*block
;
1894 for (j
= 0; j
< adev
->num_ip_blocks
; j
++) {
1895 block
= &adev
->ip_blocks
[j
];
1897 if (block
->version
->type
!= ip_order
[i
] ||
1898 !block
->status
.valid
)
1901 r
= block
->version
->funcs
->hw_init(adev
);
1902 DRM_INFO("RE-INIT: %s %s\n", block
->version
->funcs
->name
, r
?"failed":"successed");
1909 static int amdgpu_resume_phase1(struct amdgpu_device
*adev
)
1913 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1914 if (!adev
->ip_blocks
[i
].status
.valid
)
1916 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_COMMON
||
1917 adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_GMC
||
1918 adev
->ip_blocks
[i
].version
->type
==
1919 AMD_IP_BLOCK_TYPE_IH
) {
1920 r
= adev
->ip_blocks
[i
].version
->funcs
->resume(adev
);
1922 DRM_ERROR("resume of IP block <%s> failed %d\n",
1923 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1932 static int amdgpu_resume_phase2(struct amdgpu_device
*adev
)
1936 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1937 if (!adev
->ip_blocks
[i
].status
.valid
)
1939 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_COMMON
||
1940 adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_GMC
||
1941 adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_IH
)
1943 r
= adev
->ip_blocks
[i
].version
->funcs
->resume(adev
);
1945 DRM_ERROR("resume of IP block <%s> failed %d\n",
1946 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1954 static int amdgpu_resume(struct amdgpu_device
*adev
)
1958 r
= amdgpu_resume_phase1(adev
);
1961 r
= amdgpu_resume_phase2(adev
);
1966 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device
*adev
)
1968 if (adev
->is_atom_fw
) {
1969 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev
))
1970 adev
->virt
.caps
|= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS
;
1972 if (amdgpu_atombios_has_gpu_virtualization_table(adev
))
1973 adev
->virt
.caps
|= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS
;
1977 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type
)
1979 switch (asic_type
) {
1980 #if defined(CONFIG_DRM_AMD_DC)
1985 case CHIP_POLARIS11
:
1986 case CHIP_POLARIS10
:
1989 #if defined(CONFIG_DRM_AMD_DC_PRE_VEGA)
1990 return amdgpu_dc
!= 0;
1992 return amdgpu_dc
> 0;
2001 * amdgpu_device_has_dc_support - check if dc is supported
2003 * @adev: amdgpu_device_pointer
2005 * Returns true for supported, false for not supported
2007 bool amdgpu_device_has_dc_support(struct amdgpu_device
*adev
)
2009 return amdgpu_device_asic_has_dc_support(adev
->asic_type
);
2013 * amdgpu_device_init - initialize the driver
2015 * @adev: amdgpu_device pointer
2016 * @pdev: drm dev pointer
2017 * @pdev: pci dev pointer
2018 * @flags: driver flags
2020 * Initializes the driver info and hw (all asics).
2021 * Returns 0 for success or an error on failure.
2022 * Called at driver startup.
2024 int amdgpu_device_init(struct amdgpu_device
*adev
,
2025 struct drm_device
*ddev
,
2026 struct pci_dev
*pdev
,
2030 bool runtime
= false;
2033 adev
->shutdown
= false;
2034 adev
->dev
= &pdev
->dev
;
2037 adev
->flags
= flags
;
2038 adev
->asic_type
= flags
& AMD_ASIC_MASK
;
2039 adev
->usec_timeout
= AMDGPU_MAX_USEC_TIMEOUT
;
2040 adev
->mc
.gart_size
= 512 * 1024 * 1024;
2041 adev
->accel_working
= false;
2042 adev
->num_rings
= 0;
2043 adev
->mman
.buffer_funcs
= NULL
;
2044 adev
->mman
.buffer_funcs_ring
= NULL
;
2045 adev
->vm_manager
.vm_pte_funcs
= NULL
;
2046 adev
->vm_manager
.vm_pte_num_rings
= 0;
2047 adev
->gart
.gart_funcs
= NULL
;
2048 adev
->fence_context
= dma_fence_context_alloc(AMDGPU_MAX_RINGS
);
2050 adev
->smc_rreg
= &amdgpu_invalid_rreg
;
2051 adev
->smc_wreg
= &amdgpu_invalid_wreg
;
2052 adev
->pcie_rreg
= &amdgpu_invalid_rreg
;
2053 adev
->pcie_wreg
= &amdgpu_invalid_wreg
;
2054 adev
->pciep_rreg
= &amdgpu_invalid_rreg
;
2055 adev
->pciep_wreg
= &amdgpu_invalid_wreg
;
2056 adev
->uvd_ctx_rreg
= &amdgpu_invalid_rreg
;
2057 adev
->uvd_ctx_wreg
= &amdgpu_invalid_wreg
;
2058 adev
->didt_rreg
= &amdgpu_invalid_rreg
;
2059 adev
->didt_wreg
= &amdgpu_invalid_wreg
;
2060 adev
->gc_cac_rreg
= &amdgpu_invalid_rreg
;
2061 adev
->gc_cac_wreg
= &amdgpu_invalid_wreg
;
2062 adev
->audio_endpt_rreg
= &amdgpu_block_invalid_rreg
;
2063 adev
->audio_endpt_wreg
= &amdgpu_block_invalid_wreg
;
2066 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2067 amdgpu_asic_name
[adev
->asic_type
], pdev
->vendor
, pdev
->device
,
2068 pdev
->subsystem_vendor
, pdev
->subsystem_device
, pdev
->revision
);
2070 /* mutex initialization are all done here so we
2071 * can recall function without having locking issues */
2072 atomic_set(&adev
->irq
.ih
.lock
, 0);
2073 mutex_init(&adev
->firmware
.mutex
);
2074 mutex_init(&adev
->pm
.mutex
);
2075 mutex_init(&adev
->gfx
.gpu_clock_mutex
);
2076 mutex_init(&adev
->srbm_mutex
);
2077 mutex_init(&adev
->grbm_idx_mutex
);
2078 mutex_init(&adev
->mn_lock
);
2079 hash_init(adev
->mn_hash
);
2081 amdgpu_check_arguments(adev
);
2083 spin_lock_init(&adev
->mmio_idx_lock
);
2084 spin_lock_init(&adev
->smc_idx_lock
);
2085 spin_lock_init(&adev
->pcie_idx_lock
);
2086 spin_lock_init(&adev
->uvd_ctx_idx_lock
);
2087 spin_lock_init(&adev
->didt_idx_lock
);
2088 spin_lock_init(&adev
->gc_cac_idx_lock
);
2089 spin_lock_init(&adev
->se_cac_idx_lock
);
2090 spin_lock_init(&adev
->audio_endpt_idx_lock
);
2091 spin_lock_init(&adev
->mm_stats
.lock
);
2093 INIT_LIST_HEAD(&adev
->shadow_list
);
2094 mutex_init(&adev
->shadow_list_lock
);
2096 INIT_LIST_HEAD(&adev
->gtt_list
);
2097 spin_lock_init(&adev
->gtt_list_lock
);
2099 INIT_LIST_HEAD(&adev
->ring_lru_list
);
2100 spin_lock_init(&adev
->ring_lru_list_lock
);
2102 INIT_DELAYED_WORK(&adev
->late_init_work
, amdgpu_late_init_func_handler
);
2104 /* Registers mapping */
2105 /* TODO: block userspace mapping of io register */
2106 if (adev
->asic_type
>= CHIP_BONAIRE
) {
2107 adev
->rmmio_base
= pci_resource_start(adev
->pdev
, 5);
2108 adev
->rmmio_size
= pci_resource_len(adev
->pdev
, 5);
2110 adev
->rmmio_base
= pci_resource_start(adev
->pdev
, 2);
2111 adev
->rmmio_size
= pci_resource_len(adev
->pdev
, 2);
2114 adev
->rmmio
= ioremap(adev
->rmmio_base
, adev
->rmmio_size
);
2115 if (adev
->rmmio
== NULL
) {
2118 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev
->rmmio_base
);
2119 DRM_INFO("register mmio size: %u\n", (unsigned)adev
->rmmio_size
);
2121 /* doorbell bar mapping */
2122 amdgpu_doorbell_init(adev
);
2124 /* io port mapping */
2125 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
2126 if (pci_resource_flags(adev
->pdev
, i
) & IORESOURCE_IO
) {
2127 adev
->rio_mem_size
= pci_resource_len(adev
->pdev
, i
);
2128 adev
->rio_mem
= pci_iomap(adev
->pdev
, i
, adev
->rio_mem_size
);
2132 if (adev
->rio_mem
== NULL
)
2133 DRM_INFO("PCI I/O BAR is not found.\n");
2135 /* early init functions */
2136 r
= amdgpu_early_init(adev
);
2140 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2141 /* this will fail for cards that aren't VGA class devices, just
2143 vga_client_register(adev
->pdev
, adev
, NULL
, amdgpu_vga_set_decode
);
2145 if (amdgpu_runtime_pm
== 1)
2147 if (amdgpu_device_is_px(ddev
))
2149 if (!pci_is_thunderbolt_attached(adev
->pdev
))
2150 vga_switcheroo_register_client(adev
->pdev
,
2151 &amdgpu_switcheroo_ops
, runtime
);
2153 vga_switcheroo_init_domain_pm_ops(adev
->dev
, &adev
->vga_pm_domain
);
2156 if (!amdgpu_get_bios(adev
)) {
2161 r
= amdgpu_atombios_init(adev
);
2163 dev_err(adev
->dev
, "amdgpu_atombios_init failed\n");
2164 amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL
, 0, 0);
2168 /* detect if we are with an SRIOV vbios */
2169 amdgpu_device_detect_sriov_bios(adev
);
2171 /* Post card if necessary */
2172 if (amdgpu_vpost_needed(adev
)) {
2174 dev_err(adev
->dev
, "no vBIOS found\n");
2175 amdgpu_vf_error_put(AMDGIM_ERROR_VF_NO_VBIOS
, 0, 0);
2179 DRM_INFO("GPU posting now...\n");
2180 r
= amdgpu_atom_asic_init(adev
->mode_info
.atom_context
);
2182 dev_err(adev
->dev
, "gpu post error!\n");
2183 amdgpu_vf_error_put(AMDGIM_ERROR_VF_GPU_POST_ERROR
, 0, 0);
2187 DRM_INFO("GPU post is not needed\n");
2190 if (adev
->is_atom_fw
) {
2191 /* Initialize clocks */
2192 r
= amdgpu_atomfirmware_get_clock_info(adev
);
2194 dev_err(adev
->dev
, "amdgpu_atomfirmware_get_clock_info failed\n");
2195 amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL
, 0, 0);
2199 /* Initialize clocks */
2200 r
= amdgpu_atombios_get_clock_info(adev
);
2202 dev_err(adev
->dev
, "amdgpu_atombios_get_clock_info failed\n");
2203 amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL
, 0, 0);
2206 /* init i2c buses */
2207 if (!amdgpu_device_has_dc_support(adev
))
2208 amdgpu_atombios_i2c_init(adev
);
2212 r
= amdgpu_fence_driver_init(adev
);
2214 dev_err(adev
->dev
, "amdgpu_fence_driver_init failed\n");
2215 amdgpu_vf_error_put(AMDGIM_ERROR_VF_FENCE_INIT_FAIL
, 0, 0);
2219 /* init the mode config */
2220 drm_mode_config_init(adev
->ddev
);
2222 r
= amdgpu_init(adev
);
2224 dev_err(adev
->dev
, "amdgpu_init failed\n");
2225 amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL
, 0, 0);
2230 adev
->accel_working
= true;
2232 amdgpu_vm_check_compute_bug(adev
);
2234 /* Initialize the buffer migration limit. */
2235 if (amdgpu_moverate
>= 0)
2236 max_MBps
= amdgpu_moverate
;
2238 max_MBps
= 8; /* Allow 8 MB/s. */
2239 /* Get a log2 for easy divisions. */
2240 adev
->mm_stats
.log2_max_MBps
= ilog2(max(1u, max_MBps
));
2242 r
= amdgpu_ib_pool_init(adev
);
2244 dev_err(adev
->dev
, "IB initialization failed (%d).\n", r
);
2245 amdgpu_vf_error_put(AMDGIM_ERROR_VF_IB_INIT_FAIL
, 0, r
);
2249 r
= amdgpu_ib_ring_tests(adev
);
2251 DRM_ERROR("ib ring test failed (%d).\n", r
);
2253 amdgpu_fbdev_init(adev
);
2255 r
= amdgpu_gem_debugfs_init(adev
);
2257 DRM_ERROR("registering gem debugfs failed (%d).\n", r
);
2259 r
= amdgpu_debugfs_regs_init(adev
);
2261 DRM_ERROR("registering register debugfs failed (%d).\n", r
);
2263 r
= amdgpu_debugfs_test_ib_ring_init(adev
);
2265 DRM_ERROR("registering register test ib ring debugfs failed (%d).\n", r
);
2267 r
= amdgpu_debugfs_firmware_init(adev
);
2269 DRM_ERROR("registering firmware debugfs failed (%d).\n", r
);
2271 r
= amdgpu_debugfs_vbios_dump_init(adev
);
2273 DRM_ERROR("Creating vbios dump debugfs failed (%d).\n", r
);
2275 if ((amdgpu_testing
& 1)) {
2276 if (adev
->accel_working
)
2277 amdgpu_test_moves(adev
);
2279 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2281 if (amdgpu_benchmarking
) {
2282 if (adev
->accel_working
)
2283 amdgpu_benchmark(adev
, amdgpu_benchmarking
);
2285 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2288 /* enable clockgating, etc. after ib tests, etc. since some blocks require
2289 * explicit gating rather than handling it automatically.
2291 r
= amdgpu_late_init(adev
);
2293 dev_err(adev
->dev
, "amdgpu_late_init failed\n");
2294 amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL
, 0, r
);
2301 amdgpu_vf_error_trans_all(adev
);
2303 vga_switcheroo_fini_domain_pm_ops(adev
->dev
);
2308 * amdgpu_device_fini - tear down the driver
2310 * @adev: amdgpu_device pointer
2312 * Tear down the driver info (all asics).
2313 * Called at driver shutdown.
2315 void amdgpu_device_fini(struct amdgpu_device
*adev
)
2319 DRM_INFO("amdgpu: finishing device.\n");
2320 adev
->shutdown
= true;
2321 if (adev
->mode_info
.mode_config_initialized
)
2322 drm_crtc_force_disable_all(adev
->ddev
);
2323 /* evict vram memory */
2324 amdgpu_bo_evict_vram(adev
);
2325 amdgpu_ib_pool_fini(adev
);
2326 amdgpu_fence_driver_fini(adev
);
2327 amdgpu_fbdev_fini(adev
);
2328 r
= amdgpu_fini(adev
);
2329 if (adev
->firmware
.gpu_info_fw
) {
2330 release_firmware(adev
->firmware
.gpu_info_fw
);
2331 adev
->firmware
.gpu_info_fw
= NULL
;
2333 adev
->accel_working
= false;
2334 cancel_delayed_work_sync(&adev
->late_init_work
);
2335 /* free i2c buses */
2336 if (!amdgpu_device_has_dc_support(adev
))
2337 amdgpu_i2c_fini(adev
);
2338 amdgpu_atombios_fini(adev
);
2341 if (!pci_is_thunderbolt_attached(adev
->pdev
))
2342 vga_switcheroo_unregister_client(adev
->pdev
);
2343 if (adev
->flags
& AMD_IS_PX
)
2344 vga_switcheroo_fini_domain_pm_ops(adev
->dev
);
2345 vga_client_register(adev
->pdev
, NULL
, NULL
, NULL
);
2347 pci_iounmap(adev
->pdev
, adev
->rio_mem
);
2348 adev
->rio_mem
= NULL
;
2349 iounmap(adev
->rmmio
);
2351 amdgpu_doorbell_fini(adev
);
2352 amdgpu_debugfs_regs_cleanup(adev
);
2360 * amdgpu_device_suspend - initiate device suspend
2362 * @pdev: drm dev pointer
2363 * @state: suspend state
2365 * Puts the hw in the suspend state (all asics).
2366 * Returns 0 for success or an error on failure.
2367 * Called at driver suspend.
2369 int amdgpu_device_suspend(struct drm_device
*dev
, bool suspend
, bool fbcon
)
2371 struct amdgpu_device
*adev
;
2372 struct drm_crtc
*crtc
;
2373 struct drm_connector
*connector
;
2376 if (dev
== NULL
|| dev
->dev_private
== NULL
) {
2380 adev
= dev
->dev_private
;
2382 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2385 drm_kms_helper_poll_disable(dev
);
2387 if (!amdgpu_device_has_dc_support(adev
)) {
2388 /* turn off display hw */
2389 drm_modeset_lock_all(dev
);
2390 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
2391 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_OFF
);
2393 drm_modeset_unlock_all(dev
);
2396 amdgpu_amdkfd_suspend(adev
);
2398 /* unpin the front buffers and cursors */
2399 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2400 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2401 struct amdgpu_framebuffer
*rfb
= to_amdgpu_framebuffer(crtc
->primary
->fb
);
2402 struct amdgpu_bo
*robj
;
2404 if (amdgpu_crtc
->cursor_bo
) {
2405 struct amdgpu_bo
*aobj
= gem_to_amdgpu_bo(amdgpu_crtc
->cursor_bo
);
2406 r
= amdgpu_bo_reserve(aobj
, true);
2408 amdgpu_bo_unpin(aobj
);
2409 amdgpu_bo_unreserve(aobj
);
2413 if (rfb
== NULL
|| rfb
->obj
== NULL
) {
2416 robj
= gem_to_amdgpu_bo(rfb
->obj
);
2417 /* don't unpin kernel fb objects */
2418 if (!amdgpu_fbdev_robj_is_fb(adev
, robj
)) {
2419 r
= amdgpu_bo_reserve(robj
, true);
2421 amdgpu_bo_unpin(robj
);
2422 amdgpu_bo_unreserve(robj
);
2426 /* evict vram memory */
2427 amdgpu_bo_evict_vram(adev
);
2429 amdgpu_fence_driver_suspend(adev
);
2431 r
= amdgpu_suspend(adev
);
2433 /* evict remaining vram memory
2434 * This second call to evict vram is to evict the gart page table
2437 amdgpu_bo_evict_vram(adev
);
2439 amdgpu_atombios_scratch_regs_save(adev
);
2440 pci_save_state(dev
->pdev
);
2442 /* Shut down the device */
2443 pci_disable_device(dev
->pdev
);
2444 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
2446 r
= amdgpu_asic_reset(adev
);
2448 DRM_ERROR("amdgpu asic reset failed\n");
2453 amdgpu_fbdev_set_suspend(adev
, 1);
2460 * amdgpu_device_resume - initiate device resume
2462 * @pdev: drm dev pointer
2464 * Bring the hw back to operating state (all asics).
2465 * Returns 0 for success or an error on failure.
2466 * Called at driver resume.
2468 int amdgpu_device_resume(struct drm_device
*dev
, bool resume
, bool fbcon
)
2470 struct drm_connector
*connector
;
2471 struct amdgpu_device
*adev
= dev
->dev_private
;
2472 struct drm_crtc
*crtc
;
2475 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2482 pci_set_power_state(dev
->pdev
, PCI_D0
);
2483 pci_restore_state(dev
->pdev
);
2484 r
= pci_enable_device(dev
->pdev
);
2488 amdgpu_atombios_scratch_regs_restore(adev
);
2491 if (amdgpu_need_post(adev
)) {
2492 r
= amdgpu_atom_asic_init(adev
->mode_info
.atom_context
);
2494 DRM_ERROR("amdgpu asic init failed\n");
2497 r
= amdgpu_resume(adev
);
2499 DRM_ERROR("amdgpu_resume failed (%d).\n", r
);
2502 amdgpu_fence_driver_resume(adev
);
2505 r
= amdgpu_ib_ring_tests(adev
);
2507 DRM_ERROR("ib ring test failed (%d).\n", r
);
2510 r
= amdgpu_late_init(adev
);
2515 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2516 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2518 if (amdgpu_crtc
->cursor_bo
) {
2519 struct amdgpu_bo
*aobj
= gem_to_amdgpu_bo(amdgpu_crtc
->cursor_bo
);
2520 r
= amdgpu_bo_reserve(aobj
, true);
2522 r
= amdgpu_bo_pin(aobj
,
2523 AMDGPU_GEM_DOMAIN_VRAM
,
2524 &amdgpu_crtc
->cursor_addr
);
2526 DRM_ERROR("Failed to pin cursor BO (%d)\n", r
);
2527 amdgpu_bo_unreserve(aobj
);
2531 r
= amdgpu_amdkfd_resume(adev
);
2535 /* blat the mode back in */
2537 if (!amdgpu_device_has_dc_support(adev
)) {
2539 drm_helper_resume_force_mode(dev
);
2541 /* turn on display hw */
2542 drm_modeset_lock_all(dev
);
2543 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
2544 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_ON
);
2546 drm_modeset_unlock_all(dev
);
2549 * There is no equivalent atomic helper to turn on
2550 * display, so we defined our own function for this,
2551 * once suspend resume is supported by the atomic
2552 * framework this will be reworked
2554 amdgpu_dm_display_resume(adev
);
2558 drm_kms_helper_poll_enable(dev
);
2561 * Most of the connector probing functions try to acquire runtime pm
2562 * refs to ensure that the GPU is powered on when connector polling is
2563 * performed. Since we're calling this from a runtime PM callback,
2564 * trying to acquire rpm refs will cause us to deadlock.
2566 * Since we're guaranteed to be holding the rpm lock, it's safe to
2567 * temporarily disable the rpm helpers so this doesn't deadlock us.
2570 dev
->dev
->power
.disable_depth
++;
2572 if (!amdgpu_device_has_dc_support(adev
))
2573 drm_helper_hpd_irq_event(dev
);
2575 drm_kms_helper_hotplug_event(dev
);
2577 dev
->dev
->power
.disable_depth
--;
2581 amdgpu_fbdev_set_suspend(adev
, 0);
2590 static bool amdgpu_check_soft_reset(struct amdgpu_device
*adev
)
2593 bool asic_hang
= false;
2595 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
2596 if (!adev
->ip_blocks
[i
].status
.valid
)
2598 if (adev
->ip_blocks
[i
].version
->funcs
->check_soft_reset
)
2599 adev
->ip_blocks
[i
].status
.hang
=
2600 adev
->ip_blocks
[i
].version
->funcs
->check_soft_reset(adev
);
2601 if (adev
->ip_blocks
[i
].status
.hang
) {
2602 DRM_INFO("IP block:%s is hung!\n", adev
->ip_blocks
[i
].version
->funcs
->name
);
2609 static int amdgpu_pre_soft_reset(struct amdgpu_device
*adev
)
2613 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
2614 if (!adev
->ip_blocks
[i
].status
.valid
)
2616 if (adev
->ip_blocks
[i
].status
.hang
&&
2617 adev
->ip_blocks
[i
].version
->funcs
->pre_soft_reset
) {
2618 r
= adev
->ip_blocks
[i
].version
->funcs
->pre_soft_reset(adev
);
2627 static bool amdgpu_need_full_reset(struct amdgpu_device
*adev
)
2631 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
2632 if (!adev
->ip_blocks
[i
].status
.valid
)
2634 if ((adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_GMC
) ||
2635 (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_SMC
) ||
2636 (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_ACP
) ||
2637 (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_DCE
) ||
2638 adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_PSP
) {
2639 if (adev
->ip_blocks
[i
].status
.hang
) {
2640 DRM_INFO("Some block need full reset!\n");
2648 static int amdgpu_soft_reset(struct amdgpu_device
*adev
)
2652 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
2653 if (!adev
->ip_blocks
[i
].status
.valid
)
2655 if (adev
->ip_blocks
[i
].status
.hang
&&
2656 adev
->ip_blocks
[i
].version
->funcs
->soft_reset
) {
2657 r
= adev
->ip_blocks
[i
].version
->funcs
->soft_reset(adev
);
2666 static int amdgpu_post_soft_reset(struct amdgpu_device
*adev
)
2670 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
2671 if (!adev
->ip_blocks
[i
].status
.valid
)
2673 if (adev
->ip_blocks
[i
].status
.hang
&&
2674 adev
->ip_blocks
[i
].version
->funcs
->post_soft_reset
)
2675 r
= adev
->ip_blocks
[i
].version
->funcs
->post_soft_reset(adev
);
2683 bool amdgpu_need_backup(struct amdgpu_device
*adev
)
2685 if (adev
->flags
& AMD_IS_APU
)
2688 return amdgpu_lockup_timeout
> 0 ? true : false;
2691 static int amdgpu_recover_vram_from_shadow(struct amdgpu_device
*adev
,
2692 struct amdgpu_ring
*ring
,
2693 struct amdgpu_bo
*bo
,
2694 struct dma_fence
**fence
)
2702 r
= amdgpu_bo_reserve(bo
, true);
2705 domain
= amdgpu_mem_type_to_domain(bo
->tbo
.mem
.mem_type
);
2706 /* if bo has been evicted, then no need to recover */
2707 if (domain
== AMDGPU_GEM_DOMAIN_VRAM
) {
2708 r
= amdgpu_bo_validate(bo
->shadow
);
2710 DRM_ERROR("bo validate failed!\n");
2714 r
= amdgpu_bo_restore_from_shadow(adev
, ring
, bo
,
2717 DRM_ERROR("recover page table failed!\n");
2722 amdgpu_bo_unreserve(bo
);
2727 * amdgpu_sriov_gpu_reset - reset the asic
2729 * @adev: amdgpu device pointer
2730 * @job: which job trigger hang
2732 * Attempt the reset the GPU if it has hung (all asics).
2734 * Returns 0 for success or an error on failure.
2736 int amdgpu_sriov_gpu_reset(struct amdgpu_device
*adev
, struct amdgpu_job
*job
)
2740 struct amdgpu_bo
*bo
, *tmp
;
2741 struct amdgpu_ring
*ring
;
2742 struct dma_fence
*fence
= NULL
, *next
= NULL
;
2744 mutex_lock(&adev
->virt
.lock_reset
);
2745 atomic_inc(&adev
->gpu_reset_counter
);
2746 adev
->in_sriov_reset
= true;
2749 resched
= ttm_bo_lock_delayed_workqueue(&adev
->mman
.bdev
);
2751 /* we start from the ring trigger GPU hang */
2752 j
= job
? job
->ring
->idx
: 0;
2754 /* block scheduler */
2755 for (i
= j
; i
< j
+ AMDGPU_MAX_RINGS
; ++i
) {
2756 ring
= adev
->rings
[i
% AMDGPU_MAX_RINGS
];
2757 if (!ring
|| !ring
->sched
.thread
)
2760 kthread_park(ring
->sched
.thread
);
2765 /* here give the last chance to check if job removed from mirror-list
2766 * since we already pay some time on kthread_park */
2767 if (job
&& list_empty(&job
->base
.node
)) {
2768 kthread_unpark(ring
->sched
.thread
);
2772 if (amd_sched_invalidate_job(&job
->base
, amdgpu_job_hang_limit
))
2773 amd_sched_job_kickout(&job
->base
);
2775 /* only do job_reset on the hang ring if @job not NULL */
2776 amd_sched_hw_job_reset(&ring
->sched
);
2778 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2779 amdgpu_fence_driver_force_completion_ring(ring
);
2782 /* request to take full control of GPU before re-initialization */
2784 amdgpu_virt_reset_gpu(adev
);
2786 amdgpu_virt_request_full_gpu(adev
, true);
2789 /* Resume IP prior to SMC */
2790 amdgpu_sriov_reinit_early(adev
);
2792 /* we need recover gart prior to run SMC/CP/SDMA resume */
2793 amdgpu_ttm_recover_gart(adev
);
2795 /* now we are okay to resume SMC/CP/SDMA */
2796 amdgpu_sriov_reinit_late(adev
);
2798 amdgpu_irq_gpu_reset_resume_helper(adev
);
2800 if (amdgpu_ib_ring_tests(adev
))
2801 dev_err(adev
->dev
, "[GPU_RESET] ib ring test failed (%d).\n", r
);
2803 /* release full control of GPU after ib test */
2804 amdgpu_virt_release_full_gpu(adev
, true);
2806 DRM_INFO("recover vram bo from shadow\n");
2808 ring
= adev
->mman
.buffer_funcs_ring
;
2809 mutex_lock(&adev
->shadow_list_lock
);
2810 list_for_each_entry_safe(bo
, tmp
, &adev
->shadow_list
, shadow_list
) {
2812 amdgpu_recover_vram_from_shadow(adev
, ring
, bo
, &next
);
2814 r
= dma_fence_wait(fence
, false);
2816 WARN(r
, "recovery from shadow isn't completed\n");
2821 dma_fence_put(fence
);
2824 mutex_unlock(&adev
->shadow_list_lock
);
2827 r
= dma_fence_wait(fence
, false);
2829 WARN(r
, "recovery from shadow isn't completed\n");
2831 dma_fence_put(fence
);
2833 for (i
= j
; i
< j
+ AMDGPU_MAX_RINGS
; ++i
) {
2834 ring
= adev
->rings
[i
% AMDGPU_MAX_RINGS
];
2835 if (!ring
|| !ring
->sched
.thread
)
2838 if (job
&& j
!= i
) {
2839 kthread_unpark(ring
->sched
.thread
);
2843 amd_sched_job_recovery(&ring
->sched
);
2844 kthread_unpark(ring
->sched
.thread
);
2847 drm_helper_resume_force_mode(adev
->ddev
);
2849 ttm_bo_unlock_delayed_workqueue(&adev
->mman
.bdev
, resched
);
2851 /* bad news, how to tell it to userspace ? */
2852 dev_info(adev
->dev
, "GPU reset failed\n");
2854 dev_info(adev
->dev
, "GPU reset successed!\n");
2857 adev
->in_sriov_reset
= false;
2858 mutex_unlock(&adev
->virt
.lock_reset
);
2863 * amdgpu_gpu_reset - reset the asic
2865 * @adev: amdgpu device pointer
2867 * Attempt the reset the GPU if it has hung (all asics).
2868 * Returns 0 for success or an error on failure.
2870 int amdgpu_gpu_reset(struct amdgpu_device
*adev
)
2872 struct drm_atomic_state
*state
= NULL
;
2875 bool need_full_reset
, vram_lost
= false;
2877 if (!amdgpu_check_soft_reset(adev
)) {
2878 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2882 atomic_inc(&adev
->gpu_reset_counter
);
2885 resched
= ttm_bo_lock_delayed_workqueue(&adev
->mman
.bdev
);
2886 /* store modesetting */
2887 if (amdgpu_device_has_dc_support(adev
))
2888 state
= drm_atomic_helper_suspend(adev
->ddev
);
2890 /* block scheduler */
2891 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
2892 struct amdgpu_ring
*ring
= adev
->rings
[i
];
2894 if (!ring
|| !ring
->sched
.thread
)
2896 kthread_park(ring
->sched
.thread
);
2897 amd_sched_hw_job_reset(&ring
->sched
);
2899 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2900 amdgpu_fence_driver_force_completion(adev
);
2902 need_full_reset
= amdgpu_need_full_reset(adev
);
2904 if (!need_full_reset
) {
2905 amdgpu_pre_soft_reset(adev
);
2906 r
= amdgpu_soft_reset(adev
);
2907 amdgpu_post_soft_reset(adev
);
2908 if (r
|| amdgpu_check_soft_reset(adev
)) {
2909 DRM_INFO("soft reset failed, will fallback to full reset!\n");
2910 need_full_reset
= true;
2914 if (need_full_reset
) {
2915 r
= amdgpu_suspend(adev
);
2918 amdgpu_atombios_scratch_regs_save(adev
);
2919 r
= amdgpu_asic_reset(adev
);
2920 amdgpu_atombios_scratch_regs_restore(adev
);
2922 amdgpu_atom_asic_init(adev
->mode_info
.atom_context
);
2925 dev_info(adev
->dev
, "GPU reset succeeded, trying to resume\n");
2926 r
= amdgpu_resume_phase1(adev
);
2929 vram_lost
= amdgpu_check_vram_lost(adev
);
2931 DRM_ERROR("VRAM is lost!\n");
2932 atomic_inc(&adev
->vram_lost_counter
);
2934 r
= amdgpu_ttm_recover_gart(adev
);
2937 r
= amdgpu_resume_phase2(adev
);
2941 amdgpu_fill_reset_magic(adev
);
2946 amdgpu_irq_gpu_reset_resume_helper(adev
);
2947 r
= amdgpu_ib_ring_tests(adev
);
2949 dev_err(adev
->dev
, "ib ring test failed (%d).\n", r
);
2950 r
= amdgpu_suspend(adev
);
2951 need_full_reset
= true;
2955 * recovery vm page tables, since we cannot depend on VRAM is
2956 * consistent after gpu full reset.
2958 if (need_full_reset
&& amdgpu_need_backup(adev
)) {
2959 struct amdgpu_ring
*ring
= adev
->mman
.buffer_funcs_ring
;
2960 struct amdgpu_bo
*bo
, *tmp
;
2961 struct dma_fence
*fence
= NULL
, *next
= NULL
;
2963 DRM_INFO("recover vram bo from shadow\n");
2964 mutex_lock(&adev
->shadow_list_lock
);
2965 list_for_each_entry_safe(bo
, tmp
, &adev
->shadow_list
, shadow_list
) {
2967 amdgpu_recover_vram_from_shadow(adev
, ring
, bo
, &next
);
2969 r
= dma_fence_wait(fence
, false);
2971 WARN(r
, "recovery from shadow isn't completed\n");
2976 dma_fence_put(fence
);
2979 mutex_unlock(&adev
->shadow_list_lock
);
2981 r
= dma_fence_wait(fence
, false);
2983 WARN(r
, "recovery from shadow isn't completed\n");
2985 dma_fence_put(fence
);
2987 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
2988 struct amdgpu_ring
*ring
= adev
->rings
[i
];
2990 if (!ring
|| !ring
->sched
.thread
)
2993 amd_sched_job_recovery(&ring
->sched
);
2994 kthread_unpark(ring
->sched
.thread
);
2997 dev_err(adev
->dev
, "asic resume failed (%d).\n", r
);
2998 amdgpu_vf_error_put(AMDGIM_ERROR_VF_ASIC_RESUME_FAIL
, 0, r
);
2999 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
3000 if (adev
->rings
[i
] && adev
->rings
[i
]->sched
.thread
) {
3001 kthread_unpark(adev
->rings
[i
]->sched
.thread
);
3006 if (amdgpu_device_has_dc_support(adev
)) {
3007 r
= drm_atomic_helper_resume(adev
->ddev
, state
);
3008 amdgpu_dm_display_resume(adev
);
3010 drm_helper_resume_force_mode(adev
->ddev
);
3012 ttm_bo_unlock_delayed_workqueue(&adev
->mman
.bdev
, resched
);
3014 /* bad news, how to tell it to userspace ? */
3015 dev_info(adev
->dev
, "GPU reset failed\n");
3016 amdgpu_vf_error_put(AMDGIM_ERROR_VF_GPU_RESET_FAIL
, 0, r
);
3019 dev_info(adev
->dev
, "GPU reset successed!\n");
3022 amdgpu_vf_error_trans_all(adev
);
3026 void amdgpu_get_pcie_info(struct amdgpu_device
*adev
)
3031 if (amdgpu_pcie_gen_cap
)
3032 adev
->pm
.pcie_gen_mask
= amdgpu_pcie_gen_cap
;
3034 if (amdgpu_pcie_lane_cap
)
3035 adev
->pm
.pcie_mlw_mask
= amdgpu_pcie_lane_cap
;
3037 /* covers APUs as well */
3038 if (pci_is_root_bus(adev
->pdev
->bus
)) {
3039 if (adev
->pm
.pcie_gen_mask
== 0)
3040 adev
->pm
.pcie_gen_mask
= AMDGPU_DEFAULT_PCIE_GEN_MASK
;
3041 if (adev
->pm
.pcie_mlw_mask
== 0)
3042 adev
->pm
.pcie_mlw_mask
= AMDGPU_DEFAULT_PCIE_MLW_MASK
;
3046 if (adev
->pm
.pcie_gen_mask
== 0) {
3047 ret
= drm_pcie_get_speed_cap_mask(adev
->ddev
, &mask
);
3049 adev
->pm
.pcie_gen_mask
= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1
|
3050 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2
|
3051 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3
);
3053 if (mask
& DRM_PCIE_SPEED_25
)
3054 adev
->pm
.pcie_gen_mask
|= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1
;
3055 if (mask
& DRM_PCIE_SPEED_50
)
3056 adev
->pm
.pcie_gen_mask
|= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2
;
3057 if (mask
& DRM_PCIE_SPEED_80
)
3058 adev
->pm
.pcie_gen_mask
|= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3
;
3060 adev
->pm
.pcie_gen_mask
= AMDGPU_DEFAULT_PCIE_GEN_MASK
;
3063 if (adev
->pm
.pcie_mlw_mask
== 0) {
3064 ret
= drm_pcie_get_max_link_width(adev
->ddev
, &mask
);
3068 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32
|
3069 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16
|
3070 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12
|
3071 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8
|
3072 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4
|
3073 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
3074 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
3077 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16
|
3078 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12
|
3079 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8
|
3080 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4
|
3081 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
3082 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
3085 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12
|
3086 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8
|
3087 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4
|
3088 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
3089 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
3092 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8
|
3093 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4
|
3094 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
3095 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
3098 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4
|
3099 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
3100 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
3103 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
3104 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
3107 adev
->pm
.pcie_mlw_mask
= CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
;
3113 adev
->pm
.pcie_mlw_mask
= AMDGPU_DEFAULT_PCIE_MLW_MASK
;
3121 int amdgpu_debugfs_add_files(struct amdgpu_device
*adev
,
3122 const struct drm_info_list
*files
,
3127 for (i
= 0; i
< adev
->debugfs_count
; i
++) {
3128 if (adev
->debugfs
[i
].files
== files
) {
3129 /* Already registered */
3134 i
= adev
->debugfs_count
+ 1;
3135 if (i
> AMDGPU_DEBUGFS_MAX_COMPONENTS
) {
3136 DRM_ERROR("Reached maximum number of debugfs components.\n");
3137 DRM_ERROR("Report so we increase "
3138 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
3141 adev
->debugfs
[adev
->debugfs_count
].files
= files
;
3142 adev
->debugfs
[adev
->debugfs_count
].num_files
= nfiles
;
3143 adev
->debugfs_count
= i
;
3144 #if defined(CONFIG_DEBUG_FS)
3145 drm_debugfs_create_files(files
, nfiles
,
3146 adev
->ddev
->primary
->debugfs_root
,
3147 adev
->ddev
->primary
);
3152 #if defined(CONFIG_DEBUG_FS)
3154 static ssize_t
amdgpu_debugfs_regs_read(struct file
*f
, char __user
*buf
,
3155 size_t size
, loff_t
*pos
)
3157 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
3160 bool pm_pg_lock
, use_bank
;
3161 unsigned instance_bank
, sh_bank
, se_bank
;
3163 if (size
& 0x3 || *pos
& 0x3)
3166 /* are we reading registers for which a PG lock is necessary? */
3167 pm_pg_lock
= (*pos
>> 23) & 1;
3169 if (*pos
& (1ULL << 62)) {
3170 se_bank
= (*pos
>> 24) & 0x3FF;
3171 sh_bank
= (*pos
>> 34) & 0x3FF;
3172 instance_bank
= (*pos
>> 44) & 0x3FF;
3174 if (se_bank
== 0x3FF)
3175 se_bank
= 0xFFFFFFFF;
3176 if (sh_bank
== 0x3FF)
3177 sh_bank
= 0xFFFFFFFF;
3178 if (instance_bank
== 0x3FF)
3179 instance_bank
= 0xFFFFFFFF;
3185 *pos
&= (1UL << 22) - 1;
3188 if ((sh_bank
!= 0xFFFFFFFF && sh_bank
>= adev
->gfx
.config
.max_sh_per_se
) ||
3189 (se_bank
!= 0xFFFFFFFF && se_bank
>= adev
->gfx
.config
.max_shader_engines
))
3191 mutex_lock(&adev
->grbm_idx_mutex
);
3192 amdgpu_gfx_select_se_sh(adev
, se_bank
,
3193 sh_bank
, instance_bank
);
3197 mutex_lock(&adev
->pm
.mutex
);
3202 if (*pos
> adev
->rmmio_size
)
3205 value
= RREG32(*pos
>> 2);
3206 r
= put_user(value
, (uint32_t *)buf
);
3220 amdgpu_gfx_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
3221 mutex_unlock(&adev
->grbm_idx_mutex
);
3225 mutex_unlock(&adev
->pm
.mutex
);
3230 static ssize_t
amdgpu_debugfs_regs_write(struct file
*f
, const char __user
*buf
,
3231 size_t size
, loff_t
*pos
)
3233 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
3236 bool pm_pg_lock
, use_bank
;
3237 unsigned instance_bank
, sh_bank
, se_bank
;
3239 if (size
& 0x3 || *pos
& 0x3)
3242 /* are we reading registers for which a PG lock is necessary? */
3243 pm_pg_lock
= (*pos
>> 23) & 1;
3245 if (*pos
& (1ULL << 62)) {
3246 se_bank
= (*pos
>> 24) & 0x3FF;
3247 sh_bank
= (*pos
>> 34) & 0x3FF;
3248 instance_bank
= (*pos
>> 44) & 0x3FF;
3250 if (se_bank
== 0x3FF)
3251 se_bank
= 0xFFFFFFFF;
3252 if (sh_bank
== 0x3FF)
3253 sh_bank
= 0xFFFFFFFF;
3254 if (instance_bank
== 0x3FF)
3255 instance_bank
= 0xFFFFFFFF;
3261 *pos
&= (1UL << 22) - 1;
3264 if ((sh_bank
!= 0xFFFFFFFF && sh_bank
>= adev
->gfx
.config
.max_sh_per_se
) ||
3265 (se_bank
!= 0xFFFFFFFF && se_bank
>= adev
->gfx
.config
.max_shader_engines
))
3267 mutex_lock(&adev
->grbm_idx_mutex
);
3268 amdgpu_gfx_select_se_sh(adev
, se_bank
,
3269 sh_bank
, instance_bank
);
3273 mutex_lock(&adev
->pm
.mutex
);
3278 if (*pos
> adev
->rmmio_size
)
3281 r
= get_user(value
, (uint32_t *)buf
);
3285 WREG32(*pos
>> 2, value
);
3294 amdgpu_gfx_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
3295 mutex_unlock(&adev
->grbm_idx_mutex
);
3299 mutex_unlock(&adev
->pm
.mutex
);
3304 static ssize_t
amdgpu_debugfs_regs_pcie_read(struct file
*f
, char __user
*buf
,
3305 size_t size
, loff_t
*pos
)
3307 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
3311 if (size
& 0x3 || *pos
& 0x3)
3317 value
= RREG32_PCIE(*pos
>> 2);
3318 r
= put_user(value
, (uint32_t *)buf
);
3331 static ssize_t
amdgpu_debugfs_regs_pcie_write(struct file
*f
, const char __user
*buf
,
3332 size_t size
, loff_t
*pos
)
3334 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
3338 if (size
& 0x3 || *pos
& 0x3)
3344 r
= get_user(value
, (uint32_t *)buf
);
3348 WREG32_PCIE(*pos
>> 2, value
);
3359 static ssize_t
amdgpu_debugfs_regs_didt_read(struct file
*f
, char __user
*buf
,
3360 size_t size
, loff_t
*pos
)
3362 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
3366 if (size
& 0x3 || *pos
& 0x3)
3372 value
= RREG32_DIDT(*pos
>> 2);
3373 r
= put_user(value
, (uint32_t *)buf
);
3386 static ssize_t
amdgpu_debugfs_regs_didt_write(struct file
*f
, const char __user
*buf
,
3387 size_t size
, loff_t
*pos
)
3389 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
3393 if (size
& 0x3 || *pos
& 0x3)
3399 r
= get_user(value
, (uint32_t *)buf
);
3403 WREG32_DIDT(*pos
>> 2, value
);
3414 static ssize_t
amdgpu_debugfs_regs_smc_read(struct file
*f
, char __user
*buf
,
3415 size_t size
, loff_t
*pos
)
3417 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
3421 if (size
& 0x3 || *pos
& 0x3)
3427 value
= RREG32_SMC(*pos
);
3428 r
= put_user(value
, (uint32_t *)buf
);
3441 static ssize_t
amdgpu_debugfs_regs_smc_write(struct file
*f
, const char __user
*buf
,
3442 size_t size
, loff_t
*pos
)
3444 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
3448 if (size
& 0x3 || *pos
& 0x3)
3454 r
= get_user(value
, (uint32_t *)buf
);
3458 WREG32_SMC(*pos
, value
);
3469 static ssize_t
amdgpu_debugfs_gca_config_read(struct file
*f
, char __user
*buf
,
3470 size_t size
, loff_t
*pos
)
3472 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
3475 uint32_t *config
, no_regs
= 0;
3477 if (size
& 0x3 || *pos
& 0x3)
3480 config
= kmalloc_array(256, sizeof(*config
), GFP_KERNEL
);
3484 /* version, increment each time something is added */
3485 config
[no_regs
++] = 3;
3486 config
[no_regs
++] = adev
->gfx
.config
.max_shader_engines
;
3487 config
[no_regs
++] = adev
->gfx
.config
.max_tile_pipes
;
3488 config
[no_regs
++] = adev
->gfx
.config
.max_cu_per_sh
;
3489 config
[no_regs
++] = adev
->gfx
.config
.max_sh_per_se
;
3490 config
[no_regs
++] = adev
->gfx
.config
.max_backends_per_se
;
3491 config
[no_regs
++] = adev
->gfx
.config
.max_texture_channel_caches
;
3492 config
[no_regs
++] = adev
->gfx
.config
.max_gprs
;
3493 config
[no_regs
++] = adev
->gfx
.config
.max_gs_threads
;
3494 config
[no_regs
++] = adev
->gfx
.config
.max_hw_contexts
;
3495 config
[no_regs
++] = adev
->gfx
.config
.sc_prim_fifo_size_frontend
;
3496 config
[no_regs
++] = adev
->gfx
.config
.sc_prim_fifo_size_backend
;
3497 config
[no_regs
++] = adev
->gfx
.config
.sc_hiz_tile_fifo_size
;
3498 config
[no_regs
++] = adev
->gfx
.config
.sc_earlyz_tile_fifo_size
;
3499 config
[no_regs
++] = adev
->gfx
.config
.num_tile_pipes
;
3500 config
[no_regs
++] = adev
->gfx
.config
.backend_enable_mask
;
3501 config
[no_regs
++] = adev
->gfx
.config
.mem_max_burst_length_bytes
;
3502 config
[no_regs
++] = adev
->gfx
.config
.mem_row_size_in_kb
;
3503 config
[no_regs
++] = adev
->gfx
.config
.shader_engine_tile_size
;
3504 config
[no_regs
++] = adev
->gfx
.config
.num_gpus
;
3505 config
[no_regs
++] = adev
->gfx
.config
.multi_gpu_tile_size
;
3506 config
[no_regs
++] = adev
->gfx
.config
.mc_arb_ramcfg
;
3507 config
[no_regs
++] = adev
->gfx
.config
.gb_addr_config
;
3508 config
[no_regs
++] = adev
->gfx
.config
.num_rbs
;
3511 config
[no_regs
++] = adev
->rev_id
;
3512 config
[no_regs
++] = adev
->pg_flags
;
3513 config
[no_regs
++] = adev
->cg_flags
;
3516 config
[no_regs
++] = adev
->family
;
3517 config
[no_regs
++] = adev
->external_rev_id
;
3520 config
[no_regs
++] = adev
->pdev
->device
;
3521 config
[no_regs
++] = adev
->pdev
->revision
;
3522 config
[no_regs
++] = adev
->pdev
->subsystem_device
;
3523 config
[no_regs
++] = adev
->pdev
->subsystem_vendor
;
3525 while (size
&& (*pos
< no_regs
* 4)) {
3528 value
= config
[*pos
>> 2];
3529 r
= put_user(value
, (uint32_t *)buf
);
3545 static ssize_t
amdgpu_debugfs_sensor_read(struct file
*f
, char __user
*buf
,
3546 size_t size
, loff_t
*pos
)
3548 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
3549 int idx
, x
, outsize
, r
, valuesize
;
3550 uint32_t values
[16];
3552 if (size
& 3 || *pos
& 0x3)
3555 if (amdgpu_dpm
== 0)
3558 /* convert offset to sensor number */
3561 valuesize
= sizeof(values
);
3562 if (adev
->powerplay
.pp_funcs
&& adev
->powerplay
.pp_funcs
->read_sensor
)
3563 r
= amdgpu_dpm_read_sensor(adev
, idx
, &values
[0], &valuesize
);
3567 if (size
> valuesize
)
3574 r
= put_user(values
[x
++], (int32_t *)buf
);
3581 return !r
? outsize
: r
;
3584 static ssize_t
amdgpu_debugfs_wave_read(struct file
*f
, char __user
*buf
,
3585 size_t size
, loff_t
*pos
)
3587 struct amdgpu_device
*adev
= f
->f_inode
->i_private
;
3590 uint32_t offset
, se
, sh
, cu
, wave
, simd
, data
[32];
3592 if (size
& 3 || *pos
& 3)
3596 offset
= (*pos
& 0x7F);
3597 se
= ((*pos
>> 7) & 0xFF);
3598 sh
= ((*pos
>> 15) & 0xFF);
3599 cu
= ((*pos
>> 23) & 0xFF);
3600 wave
= ((*pos
>> 31) & 0xFF);
3601 simd
= ((*pos
>> 37) & 0xFF);
3603 /* switch to the specific se/sh/cu */
3604 mutex_lock(&adev
->grbm_idx_mutex
);
3605 amdgpu_gfx_select_se_sh(adev
, se
, sh
, cu
);
3608 if (adev
->gfx
.funcs
->read_wave_data
)
3609 adev
->gfx
.funcs
->read_wave_data(adev
, simd
, wave
, data
, &x
);
3611 amdgpu_gfx_select_se_sh(adev
, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3612 mutex_unlock(&adev
->grbm_idx_mutex
);
3617 while (size
&& (offset
< x
* 4)) {
3620 value
= data
[offset
>> 2];
3621 r
= put_user(value
, (uint32_t *)buf
);
3634 static ssize_t
amdgpu_debugfs_gpr_read(struct file
*f
, char __user
*buf
,
3635 size_t size
, loff_t
*pos
)
3637 struct amdgpu_device
*adev
= f
->f_inode
->i_private
;
3640 uint32_t offset
, se
, sh
, cu
, wave
, simd
, thread
, bank
, *data
;
3642 if (size
& 3 || *pos
& 3)
3646 offset
= (*pos
& 0xFFF); /* in dwords */
3647 se
= ((*pos
>> 12) & 0xFF);
3648 sh
= ((*pos
>> 20) & 0xFF);
3649 cu
= ((*pos
>> 28) & 0xFF);
3650 wave
= ((*pos
>> 36) & 0xFF);
3651 simd
= ((*pos
>> 44) & 0xFF);
3652 thread
= ((*pos
>> 52) & 0xFF);
3653 bank
= ((*pos
>> 60) & 1);
3655 data
= kmalloc_array(1024, sizeof(*data
), GFP_KERNEL
);
3659 /* switch to the specific se/sh/cu */
3660 mutex_lock(&adev
->grbm_idx_mutex
);
3661 amdgpu_gfx_select_se_sh(adev
, se
, sh
, cu
);
3664 if (adev
->gfx
.funcs
->read_wave_vgprs
)
3665 adev
->gfx
.funcs
->read_wave_vgprs(adev
, simd
, wave
, thread
, offset
, size
>>2, data
);
3667 if (adev
->gfx
.funcs
->read_wave_sgprs
)
3668 adev
->gfx
.funcs
->read_wave_sgprs(adev
, simd
, wave
, offset
, size
>>2, data
);
3671 amdgpu_gfx_select_se_sh(adev
, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3672 mutex_unlock(&adev
->grbm_idx_mutex
);
3677 value
= data
[offset
++];
3678 r
= put_user(value
, (uint32_t *)buf
);
3694 static const struct file_operations amdgpu_debugfs_regs_fops
= {
3695 .owner
= THIS_MODULE
,
3696 .read
= amdgpu_debugfs_regs_read
,
3697 .write
= amdgpu_debugfs_regs_write
,
3698 .llseek
= default_llseek
3700 static const struct file_operations amdgpu_debugfs_regs_didt_fops
= {
3701 .owner
= THIS_MODULE
,
3702 .read
= amdgpu_debugfs_regs_didt_read
,
3703 .write
= amdgpu_debugfs_regs_didt_write
,
3704 .llseek
= default_llseek
3706 static const struct file_operations amdgpu_debugfs_regs_pcie_fops
= {
3707 .owner
= THIS_MODULE
,
3708 .read
= amdgpu_debugfs_regs_pcie_read
,
3709 .write
= amdgpu_debugfs_regs_pcie_write
,
3710 .llseek
= default_llseek
3712 static const struct file_operations amdgpu_debugfs_regs_smc_fops
= {
3713 .owner
= THIS_MODULE
,
3714 .read
= amdgpu_debugfs_regs_smc_read
,
3715 .write
= amdgpu_debugfs_regs_smc_write
,
3716 .llseek
= default_llseek
3719 static const struct file_operations amdgpu_debugfs_gca_config_fops
= {
3720 .owner
= THIS_MODULE
,
3721 .read
= amdgpu_debugfs_gca_config_read
,
3722 .llseek
= default_llseek
3725 static const struct file_operations amdgpu_debugfs_sensors_fops
= {
3726 .owner
= THIS_MODULE
,
3727 .read
= amdgpu_debugfs_sensor_read
,
3728 .llseek
= default_llseek
3731 static const struct file_operations amdgpu_debugfs_wave_fops
= {
3732 .owner
= THIS_MODULE
,
3733 .read
= amdgpu_debugfs_wave_read
,
3734 .llseek
= default_llseek
3736 static const struct file_operations amdgpu_debugfs_gpr_fops
= {
3737 .owner
= THIS_MODULE
,
3738 .read
= amdgpu_debugfs_gpr_read
,
3739 .llseek
= default_llseek
3742 static const struct file_operations
*debugfs_regs
[] = {
3743 &amdgpu_debugfs_regs_fops
,
3744 &amdgpu_debugfs_regs_didt_fops
,
3745 &amdgpu_debugfs_regs_pcie_fops
,
3746 &amdgpu_debugfs_regs_smc_fops
,
3747 &amdgpu_debugfs_gca_config_fops
,
3748 &amdgpu_debugfs_sensors_fops
,
3749 &amdgpu_debugfs_wave_fops
,
3750 &amdgpu_debugfs_gpr_fops
,
3753 static const char *debugfs_regs_names
[] = {
3758 "amdgpu_gca_config",
3764 static int amdgpu_debugfs_regs_init(struct amdgpu_device
*adev
)
3766 struct drm_minor
*minor
= adev
->ddev
->primary
;
3767 struct dentry
*ent
, *root
= minor
->debugfs_root
;
3770 for (i
= 0; i
< ARRAY_SIZE(debugfs_regs
); i
++) {
3771 ent
= debugfs_create_file(debugfs_regs_names
[i
],
3772 S_IFREG
| S_IRUGO
, root
,
3773 adev
, debugfs_regs
[i
]);
3775 for (j
= 0; j
< i
; j
++) {
3776 debugfs_remove(adev
->debugfs_regs
[i
]);
3777 adev
->debugfs_regs
[i
] = NULL
;
3779 return PTR_ERR(ent
);
3783 i_size_write(ent
->d_inode
, adev
->rmmio_size
);
3784 adev
->debugfs_regs
[i
] = ent
;
3790 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device
*adev
)
3794 for (i
= 0; i
< ARRAY_SIZE(debugfs_regs
); i
++) {
3795 if (adev
->debugfs_regs
[i
]) {
3796 debugfs_remove(adev
->debugfs_regs
[i
]);
3797 adev
->debugfs_regs
[i
] = NULL
;
3802 static int amdgpu_debugfs_test_ib(struct seq_file
*m
, void *data
)
3804 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3805 struct drm_device
*dev
= node
->minor
->dev
;
3806 struct amdgpu_device
*adev
= dev
->dev_private
;
3809 /* hold on the scheduler */
3810 for (i
= 0; i
< AMDGPU_MAX_RINGS
; i
++) {
3811 struct amdgpu_ring
*ring
= adev
->rings
[i
];
3813 if (!ring
|| !ring
->sched
.thread
)
3815 kthread_park(ring
->sched
.thread
);
3818 seq_printf(m
, "run ib test:\n");
3819 r
= amdgpu_ib_ring_tests(adev
);
3821 seq_printf(m
, "ib ring tests failed (%d).\n", r
);
3823 seq_printf(m
, "ib ring tests passed.\n");
3825 /* go on the scheduler */
3826 for (i
= 0; i
< AMDGPU_MAX_RINGS
; i
++) {
3827 struct amdgpu_ring
*ring
= adev
->rings
[i
];
3829 if (!ring
|| !ring
->sched
.thread
)
3831 kthread_unpark(ring
->sched
.thread
);
3837 static const struct drm_info_list amdgpu_debugfs_test_ib_ring_list
[] = {
3838 {"amdgpu_test_ib", &amdgpu_debugfs_test_ib
}
3841 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device
*adev
)
3843 return amdgpu_debugfs_add_files(adev
,
3844 amdgpu_debugfs_test_ib_ring_list
, 1);
3847 int amdgpu_debugfs_init(struct drm_minor
*minor
)
3852 static int amdgpu_debugfs_get_vbios_dump(struct seq_file
*m
, void *data
)
3854 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3855 struct drm_device
*dev
= node
->minor
->dev
;
3856 struct amdgpu_device
*adev
= dev
->dev_private
;
3858 seq_write(m
, adev
->bios
, adev
->bios_size
);
3862 static const struct drm_info_list amdgpu_vbios_dump_list
[] = {
3864 amdgpu_debugfs_get_vbios_dump
,
3868 static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device
*adev
)
3870 return amdgpu_debugfs_add_files(adev
,
3871 amdgpu_vbios_dump_list
, 1);
3874 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device
*adev
)
3878 static int amdgpu_debugfs_regs_init(struct amdgpu_device
*adev
)
3882 static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device
*adev
)
3886 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device
*adev
) { }