2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/kthread.h>
29 #include <linux/console.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/amdgpu_drm.h>
35 #include <linux/vgaarb.h>
36 #include <linux/vga_switcheroo.h>
37 #include <linux/efi.h>
39 #include "amdgpu_trace.h"
40 #include "amdgpu_i2c.h"
42 #include "amdgpu_atombios.h"
44 #ifdef CONFIG_DRM_AMDGPU_SI
47 #ifdef CONFIG_DRM_AMDGPU_CIK
51 #include "bif/bif_4_1_d.h"
52 #include <linux/pci.h>
53 #include <linux/firmware.h>
55 static int amdgpu_debugfs_regs_init(struct amdgpu_device
*adev
);
56 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device
*adev
);
58 static const char *amdgpu_asic_name
[] = {
80 bool amdgpu_device_is_px(struct drm_device
*dev
)
82 struct amdgpu_device
*adev
= dev
->dev_private
;
84 if (adev
->flags
& AMD_IS_PX
)
90 * MMIO register access helper functions.
92 uint32_t amdgpu_mm_rreg(struct amdgpu_device
*adev
, uint32_t reg
,
97 if (amdgpu_sriov_runtime(adev
)) {
98 BUG_ON(in_interrupt());
99 return amdgpu_virt_kiq_rreg(adev
, reg
);
102 if ((reg
* 4) < adev
->rmmio_size
&& !always_indirect
)
103 ret
= readl(((void __iomem
*)adev
->rmmio
) + (reg
* 4));
107 spin_lock_irqsave(&adev
->mmio_idx_lock
, flags
);
108 writel((reg
* 4), ((void __iomem
*)adev
->rmmio
) + (mmMM_INDEX
* 4));
109 ret
= readl(((void __iomem
*)adev
->rmmio
) + (mmMM_DATA
* 4));
110 spin_unlock_irqrestore(&adev
->mmio_idx_lock
, flags
);
112 trace_amdgpu_mm_rreg(adev
->pdev
->device
, reg
, ret
);
116 void amdgpu_mm_wreg(struct amdgpu_device
*adev
, uint32_t reg
, uint32_t v
,
117 bool always_indirect
)
119 trace_amdgpu_mm_wreg(adev
->pdev
->device
, reg
, v
);
121 if (amdgpu_sriov_runtime(adev
)) {
122 BUG_ON(in_interrupt());
123 return amdgpu_virt_kiq_wreg(adev
, reg
, v
);
126 if ((reg
* 4) < adev
->rmmio_size
&& !always_indirect
)
127 writel(v
, ((void __iomem
*)adev
->rmmio
) + (reg
* 4));
131 spin_lock_irqsave(&adev
->mmio_idx_lock
, flags
);
132 writel((reg
* 4), ((void __iomem
*)adev
->rmmio
) + (mmMM_INDEX
* 4));
133 writel(v
, ((void __iomem
*)adev
->rmmio
) + (mmMM_DATA
* 4));
134 spin_unlock_irqrestore(&adev
->mmio_idx_lock
, flags
);
138 u32
amdgpu_io_rreg(struct amdgpu_device
*adev
, u32 reg
)
140 if ((reg
* 4) < adev
->rio_mem_size
)
141 return ioread32(adev
->rio_mem
+ (reg
* 4));
143 iowrite32((reg
* 4), adev
->rio_mem
+ (mmMM_INDEX
* 4));
144 return ioread32(adev
->rio_mem
+ (mmMM_DATA
* 4));
148 void amdgpu_io_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
151 if ((reg
* 4) < adev
->rio_mem_size
)
152 iowrite32(v
, adev
->rio_mem
+ (reg
* 4));
154 iowrite32((reg
* 4), adev
->rio_mem
+ (mmMM_INDEX
* 4));
155 iowrite32(v
, adev
->rio_mem
+ (mmMM_DATA
* 4));
160 * amdgpu_mm_rdoorbell - read a doorbell dword
162 * @adev: amdgpu_device pointer
163 * @index: doorbell index
165 * Returns the value in the doorbell aperture at the
166 * requested doorbell index (CIK).
168 u32
amdgpu_mm_rdoorbell(struct amdgpu_device
*adev
, u32 index
)
170 if (index
< adev
->doorbell
.num_doorbells
) {
171 return readl(adev
->doorbell
.ptr
+ index
);
173 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index
);
179 * amdgpu_mm_wdoorbell - write a doorbell dword
181 * @adev: amdgpu_device pointer
182 * @index: doorbell index
185 * Writes @v to the doorbell aperture at the
186 * requested doorbell index (CIK).
188 void amdgpu_mm_wdoorbell(struct amdgpu_device
*adev
, u32 index
, u32 v
)
190 if (index
< adev
->doorbell
.num_doorbells
) {
191 writel(v
, adev
->doorbell
.ptr
+ index
);
193 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index
);
198 * amdgpu_invalid_rreg - dummy reg read function
200 * @adev: amdgpu device pointer
201 * @reg: offset of register
203 * Dummy register read function. Used for register blocks
204 * that certain asics don't have (all asics).
205 * Returns the value in the register.
207 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device
*adev
, uint32_t reg
)
209 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg
);
215 * amdgpu_invalid_wreg - dummy reg write function
217 * @adev: amdgpu device pointer
218 * @reg: offset of register
219 * @v: value to write to the register
221 * Dummy register read function. Used for register blocks
222 * that certain asics don't have (all asics).
224 static void amdgpu_invalid_wreg(struct amdgpu_device
*adev
, uint32_t reg
, uint32_t v
)
226 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
232 * amdgpu_block_invalid_rreg - dummy reg read function
234 * @adev: amdgpu device pointer
235 * @block: offset of instance
236 * @reg: offset of register
238 * Dummy register read function. Used for register blocks
239 * that certain asics don't have (all asics).
240 * Returns the value in the register.
242 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device
*adev
,
243 uint32_t block
, uint32_t reg
)
245 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
252 * amdgpu_block_invalid_wreg - dummy reg write function
254 * @adev: amdgpu device pointer
255 * @block: offset of instance
256 * @reg: offset of register
257 * @v: value to write to the register
259 * Dummy register read function. Used for register blocks
260 * that certain asics don't have (all asics).
262 static void amdgpu_block_invalid_wreg(struct amdgpu_device
*adev
,
264 uint32_t reg
, uint32_t v
)
266 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
271 static int amdgpu_vram_scratch_init(struct amdgpu_device
*adev
)
275 if (adev
->vram_scratch
.robj
== NULL
) {
276 r
= amdgpu_bo_create(adev
, AMDGPU_GPU_PAGE_SIZE
,
277 PAGE_SIZE
, true, AMDGPU_GEM_DOMAIN_VRAM
,
278 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
|
279 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
,
280 NULL
, NULL
, &adev
->vram_scratch
.robj
);
286 r
= amdgpu_bo_reserve(adev
->vram_scratch
.robj
, false);
287 if (unlikely(r
!= 0))
289 r
= amdgpu_bo_pin(adev
->vram_scratch
.robj
,
290 AMDGPU_GEM_DOMAIN_VRAM
, &adev
->vram_scratch
.gpu_addr
);
292 amdgpu_bo_unreserve(adev
->vram_scratch
.robj
);
295 r
= amdgpu_bo_kmap(adev
->vram_scratch
.robj
,
296 (void **)&adev
->vram_scratch
.ptr
);
298 amdgpu_bo_unpin(adev
->vram_scratch
.robj
);
299 amdgpu_bo_unreserve(adev
->vram_scratch
.robj
);
304 static void amdgpu_vram_scratch_fini(struct amdgpu_device
*adev
)
308 if (adev
->vram_scratch
.robj
== NULL
) {
311 r
= amdgpu_bo_reserve(adev
->vram_scratch
.robj
, false);
312 if (likely(r
== 0)) {
313 amdgpu_bo_kunmap(adev
->vram_scratch
.robj
);
314 amdgpu_bo_unpin(adev
->vram_scratch
.robj
);
315 amdgpu_bo_unreserve(adev
->vram_scratch
.robj
);
317 amdgpu_bo_unref(&adev
->vram_scratch
.robj
);
321 * amdgpu_program_register_sequence - program an array of registers.
323 * @adev: amdgpu_device pointer
324 * @registers: pointer to the register array
325 * @array_size: size of the register array
327 * Programs an array or registers with and and or masks.
328 * This is a helper for setting golden registers.
330 void amdgpu_program_register_sequence(struct amdgpu_device
*adev
,
331 const u32
*registers
,
332 const u32 array_size
)
334 u32 tmp
, reg
, and_mask
, or_mask
;
340 for (i
= 0; i
< array_size
; i
+=3) {
341 reg
= registers
[i
+ 0];
342 and_mask
= registers
[i
+ 1];
343 or_mask
= registers
[i
+ 2];
345 if (and_mask
== 0xffffffff) {
356 void amdgpu_pci_config_reset(struct amdgpu_device
*adev
)
358 pci_write_config_dword(adev
->pdev
, 0x7c, AMDGPU_ASIC_RESET_DATA
);
362 * GPU doorbell aperture helpers function.
365 * amdgpu_doorbell_init - Init doorbell driver information.
367 * @adev: amdgpu_device pointer
369 * Init doorbell driver information (CIK)
370 * Returns 0 on success, error on failure.
372 static int amdgpu_doorbell_init(struct amdgpu_device
*adev
)
374 /* doorbell bar mapping */
375 adev
->doorbell
.base
= pci_resource_start(adev
->pdev
, 2);
376 adev
->doorbell
.size
= pci_resource_len(adev
->pdev
, 2);
378 adev
->doorbell
.num_doorbells
= min_t(u32
, adev
->doorbell
.size
/ sizeof(u32
),
379 AMDGPU_DOORBELL_MAX_ASSIGNMENT
+1);
380 if (adev
->doorbell
.num_doorbells
== 0)
383 adev
->doorbell
.ptr
= ioremap(adev
->doorbell
.base
, adev
->doorbell
.num_doorbells
* sizeof(u32
));
384 if (adev
->doorbell
.ptr
== NULL
) {
387 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev
->doorbell
.base
);
388 DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev
->doorbell
.size
);
394 * amdgpu_doorbell_fini - Tear down doorbell driver information.
396 * @adev: amdgpu_device pointer
398 * Tear down doorbell driver information (CIK)
400 static void amdgpu_doorbell_fini(struct amdgpu_device
*adev
)
402 iounmap(adev
->doorbell
.ptr
);
403 adev
->doorbell
.ptr
= NULL
;
407 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
410 * @adev: amdgpu_device pointer
411 * @aperture_base: output returning doorbell aperture base physical address
412 * @aperture_size: output returning doorbell aperture size in bytes
413 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
415 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
416 * takes doorbells required for its own rings and reports the setup to amdkfd.
417 * amdgpu reserved doorbells are at the start of the doorbell aperture.
419 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device
*adev
,
420 phys_addr_t
*aperture_base
,
421 size_t *aperture_size
,
422 size_t *start_offset
)
425 * The first num_doorbells are used by amdgpu.
426 * amdkfd takes whatever's left in the aperture.
428 if (adev
->doorbell
.size
> adev
->doorbell
.num_doorbells
* sizeof(u32
)) {
429 *aperture_base
= adev
->doorbell
.base
;
430 *aperture_size
= adev
->doorbell
.size
;
431 *start_offset
= adev
->doorbell
.num_doorbells
* sizeof(u32
);
441 * Writeback is the the method by which the the GPU updates special pages
442 * in memory with the status of certain GPU events (fences, ring pointers,
447 * amdgpu_wb_fini - Disable Writeback and free memory
449 * @adev: amdgpu_device pointer
451 * Disables Writeback and frees the Writeback memory (all asics).
452 * Used at driver shutdown.
454 static void amdgpu_wb_fini(struct amdgpu_device
*adev
)
456 if (adev
->wb
.wb_obj
) {
457 amdgpu_bo_free_kernel(&adev
->wb
.wb_obj
,
459 (void **)&adev
->wb
.wb
);
460 adev
->wb
.wb_obj
= NULL
;
465 * amdgpu_wb_init- Init Writeback driver info and allocate memory
467 * @adev: amdgpu_device pointer
469 * Disables Writeback and frees the Writeback memory (all asics).
470 * Used at driver startup.
471 * Returns 0 on success or an -error on failure.
473 static int amdgpu_wb_init(struct amdgpu_device
*adev
)
477 if (adev
->wb
.wb_obj
== NULL
) {
478 r
= amdgpu_bo_create_kernel(adev
, AMDGPU_MAX_WB
* sizeof(uint32_t),
479 PAGE_SIZE
, AMDGPU_GEM_DOMAIN_GTT
,
480 &adev
->wb
.wb_obj
, &adev
->wb
.gpu_addr
,
481 (void **)&adev
->wb
.wb
);
483 dev_warn(adev
->dev
, "(%d) create WB bo failed\n", r
);
487 adev
->wb
.num_wb
= AMDGPU_MAX_WB
;
488 memset(&adev
->wb
.used
, 0, sizeof(adev
->wb
.used
));
490 /* clear wb memory */
491 memset((char *)adev
->wb
.wb
, 0, AMDGPU_MAX_WB
* sizeof(uint32_t));
498 * amdgpu_wb_get - Allocate a wb entry
500 * @adev: amdgpu_device pointer
503 * Allocate a wb slot for use by the driver (all asics).
504 * Returns 0 on success or -EINVAL on failure.
506 int amdgpu_wb_get(struct amdgpu_device
*adev
, u32
*wb
)
508 unsigned long offset
= find_first_zero_bit(adev
->wb
.used
, adev
->wb
.num_wb
);
509 if (offset
< adev
->wb
.num_wb
) {
510 __set_bit(offset
, adev
->wb
.used
);
519 * amdgpu_wb_free - Free a wb entry
521 * @adev: amdgpu_device pointer
524 * Free a wb slot allocated for use by the driver (all asics)
526 void amdgpu_wb_free(struct amdgpu_device
*adev
, u32 wb
)
528 if (wb
< adev
->wb
.num_wb
)
529 __clear_bit(wb
, adev
->wb
.used
);
533 * amdgpu_vram_location - try to find VRAM location
534 * @adev: amdgpu device structure holding all necessary informations
535 * @mc: memory controller structure holding memory informations
536 * @base: base address at which to put VRAM
538 * Function will place try to place VRAM at base address provided
539 * as parameter (which is so far either PCI aperture address or
540 * for IGP TOM base address).
542 * If there is not enough space to fit the unvisible VRAM in the 32bits
543 * address space then we limit the VRAM size to the aperture.
545 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
546 * this shouldn't be a problem as we are using the PCI aperture as a reference.
547 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
550 * Note: we use mc_vram_size as on some board we need to program the mc to
551 * cover the whole aperture even if VRAM size is inferior to aperture size
552 * Novell bug 204882 + along with lots of ubuntu ones
554 * Note: when limiting vram it's safe to overwritte real_vram_size because
555 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
556 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
559 * Note: IGP TOM addr should be the same as the aperture addr, we don't
560 * explicitly check for that thought.
562 * FIXME: when reducing VRAM size align new size on power of 2.
564 void amdgpu_vram_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
, u64 base
)
566 uint64_t limit
= (uint64_t)amdgpu_vram_limit
<< 20;
568 mc
->vram_start
= base
;
569 if (mc
->mc_vram_size
> (adev
->mc
.mc_mask
- base
+ 1)) {
570 dev_warn(adev
->dev
, "limiting VRAM to PCI aperture size\n");
571 mc
->real_vram_size
= mc
->aper_size
;
572 mc
->mc_vram_size
= mc
->aper_size
;
574 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
575 if (limit
&& limit
< mc
->real_vram_size
)
576 mc
->real_vram_size
= limit
;
577 dev_info(adev
->dev
, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
578 mc
->mc_vram_size
>> 20, mc
->vram_start
,
579 mc
->vram_end
, mc
->real_vram_size
>> 20);
583 * amdgpu_gtt_location - try to find GTT location
584 * @adev: amdgpu device structure holding all necessary informations
585 * @mc: memory controller structure holding memory informations
587 * Function will place try to place GTT before or after VRAM.
589 * If GTT size is bigger than space left then we ajust GTT size.
590 * Thus function will never fails.
592 * FIXME: when reducing GTT size align new size on power of 2.
594 void amdgpu_gtt_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
)
596 u64 size_af
, size_bf
;
598 size_af
= ((adev
->mc
.mc_mask
- mc
->vram_end
) + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
599 size_bf
= mc
->vram_start
& ~mc
->gtt_base_align
;
600 if (size_bf
> size_af
) {
601 if (mc
->gtt_size
> size_bf
) {
602 dev_warn(adev
->dev
, "limiting GTT\n");
603 mc
->gtt_size
= size_bf
;
605 mc
->gtt_start
= (mc
->vram_start
& ~mc
->gtt_base_align
) - mc
->gtt_size
;
607 if (mc
->gtt_size
> size_af
) {
608 dev_warn(adev
->dev
, "limiting GTT\n");
609 mc
->gtt_size
= size_af
;
611 mc
->gtt_start
= (mc
->vram_end
+ 1 + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
613 mc
->gtt_end
= mc
->gtt_start
+ mc
->gtt_size
- 1;
614 dev_info(adev
->dev
, "GTT: %lluM 0x%016llX - 0x%016llX\n",
615 mc
->gtt_size
>> 20, mc
->gtt_start
, mc
->gtt_end
);
619 * GPU helpers function.
622 * amdgpu_need_post - check if the hw need post or not
624 * @adev: amdgpu_device pointer
626 * Check if the asic has been initialized (all asics) at driver startup
627 * or post is needed if hw reset is performed.
628 * Returns true if need or false if not.
630 bool amdgpu_need_post(struct amdgpu_device
*adev
)
634 if (adev
->has_hw_reset
) {
635 adev
->has_hw_reset
= false;
638 /* then check MEM_SIZE, in case the crtcs are off */
639 reg
= RREG32(mmCONFIG_MEMSIZE
);
648 static bool amdgpu_vpost_needed(struct amdgpu_device
*adev
)
650 if (amdgpu_sriov_vf(adev
))
653 if (amdgpu_passthrough(adev
)) {
654 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
655 * some old smc fw still need driver do vPost otherwise gpu hang, while
656 * those smc fw version above 22.15 doesn't have this flaw, so we force
657 * vpost executed for smc version below 22.15
659 if (adev
->asic_type
== CHIP_FIJI
) {
662 err
= request_firmware(&adev
->pm
.fw
, "amdgpu/fiji_smc.bin", adev
->dev
);
663 /* force vPost if error occured */
667 fw_ver
= *((uint32_t *)adev
->pm
.fw
->data
+ 69);
668 if (fw_ver
< 0x00160e00)
672 return amdgpu_need_post(adev
);
676 * amdgpu_dummy_page_init - init dummy page used by the driver
678 * @adev: amdgpu_device pointer
680 * Allocate the dummy page used by the driver (all asics).
681 * This dummy page is used by the driver as a filler for gart entries
682 * when pages are taken out of the GART
683 * Returns 0 on sucess, -ENOMEM on failure.
685 int amdgpu_dummy_page_init(struct amdgpu_device
*adev
)
687 if (adev
->dummy_page
.page
)
689 adev
->dummy_page
.page
= alloc_page(GFP_DMA32
| GFP_KERNEL
| __GFP_ZERO
);
690 if (adev
->dummy_page
.page
== NULL
)
692 adev
->dummy_page
.addr
= pci_map_page(adev
->pdev
, adev
->dummy_page
.page
,
693 0, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
694 if (pci_dma_mapping_error(adev
->pdev
, adev
->dummy_page
.addr
)) {
695 dev_err(&adev
->pdev
->dev
, "Failed to DMA MAP the dummy page\n");
696 __free_page(adev
->dummy_page
.page
);
697 adev
->dummy_page
.page
= NULL
;
704 * amdgpu_dummy_page_fini - free dummy page used by the driver
706 * @adev: amdgpu_device pointer
708 * Frees the dummy page used by the driver (all asics).
710 void amdgpu_dummy_page_fini(struct amdgpu_device
*adev
)
712 if (adev
->dummy_page
.page
== NULL
)
714 pci_unmap_page(adev
->pdev
, adev
->dummy_page
.addr
,
715 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
716 __free_page(adev
->dummy_page
.page
);
717 adev
->dummy_page
.page
= NULL
;
721 /* ATOM accessor methods */
723 * ATOM is an interpreted byte code stored in tables in the vbios. The
724 * driver registers callbacks to access registers and the interpreter
725 * in the driver parses the tables and executes then to program specific
726 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
727 * atombios.h, and atom.c
731 * cail_pll_read - read PLL register
733 * @info: atom card_info pointer
734 * @reg: PLL register offset
736 * Provides a PLL register accessor for the atom interpreter (r4xx+).
737 * Returns the value of the PLL register.
739 static uint32_t cail_pll_read(struct card_info
*info
, uint32_t reg
)
745 * cail_pll_write - write PLL register
747 * @info: atom card_info pointer
748 * @reg: PLL register offset
749 * @val: value to write to the pll register
751 * Provides a PLL register accessor for the atom interpreter (r4xx+).
753 static void cail_pll_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
759 * cail_mc_read - read MC (Memory Controller) register
761 * @info: atom card_info pointer
762 * @reg: MC register offset
764 * Provides an MC register accessor for the atom interpreter (r4xx+).
765 * Returns the value of the MC register.
767 static uint32_t cail_mc_read(struct card_info
*info
, uint32_t reg
)
773 * cail_mc_write - write MC (Memory Controller) register
775 * @info: atom card_info pointer
776 * @reg: MC register offset
777 * @val: value to write to the pll register
779 * Provides a MC register accessor for the atom interpreter (r4xx+).
781 static void cail_mc_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
787 * cail_reg_write - write MMIO register
789 * @info: atom card_info pointer
790 * @reg: MMIO register offset
791 * @val: value to write to the pll register
793 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
795 static void cail_reg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
797 struct amdgpu_device
*adev
= info
->dev
->dev_private
;
803 * cail_reg_read - read MMIO register
805 * @info: atom card_info pointer
806 * @reg: MMIO register offset
808 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
809 * Returns the value of the MMIO register.
811 static uint32_t cail_reg_read(struct card_info
*info
, uint32_t reg
)
813 struct amdgpu_device
*adev
= info
->dev
->dev_private
;
821 * cail_ioreg_write - write IO register
823 * @info: atom card_info pointer
824 * @reg: IO register offset
825 * @val: value to write to the pll register
827 * Provides a IO register accessor for the atom interpreter (r4xx+).
829 static void cail_ioreg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
831 struct amdgpu_device
*adev
= info
->dev
->dev_private
;
837 * cail_ioreg_read - read IO register
839 * @info: atom card_info pointer
840 * @reg: IO register offset
842 * Provides an IO register accessor for the atom interpreter (r4xx+).
843 * Returns the value of the IO register.
845 static uint32_t cail_ioreg_read(struct card_info
*info
, uint32_t reg
)
847 struct amdgpu_device
*adev
= info
->dev
->dev_private
;
855 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
857 * @adev: amdgpu_device pointer
859 * Frees the driver info and register access callbacks for the ATOM
860 * interpreter (r4xx+).
861 * Called at driver shutdown.
863 static void amdgpu_atombios_fini(struct amdgpu_device
*adev
)
865 if (adev
->mode_info
.atom_context
) {
866 kfree(adev
->mode_info
.atom_context
->scratch
);
867 kfree(adev
->mode_info
.atom_context
->iio
);
869 kfree(adev
->mode_info
.atom_context
);
870 adev
->mode_info
.atom_context
= NULL
;
871 kfree(adev
->mode_info
.atom_card_info
);
872 adev
->mode_info
.atom_card_info
= NULL
;
876 * amdgpu_atombios_init - init the driver info and callbacks for atombios
878 * @adev: amdgpu_device pointer
880 * Initializes the driver info and register access callbacks for the
881 * ATOM interpreter (r4xx+).
882 * Returns 0 on sucess, -ENOMEM on failure.
883 * Called at driver startup.
885 static int amdgpu_atombios_init(struct amdgpu_device
*adev
)
887 struct card_info
*atom_card_info
=
888 kzalloc(sizeof(struct card_info
), GFP_KERNEL
);
893 adev
->mode_info
.atom_card_info
= atom_card_info
;
894 atom_card_info
->dev
= adev
->ddev
;
895 atom_card_info
->reg_read
= cail_reg_read
;
896 atom_card_info
->reg_write
= cail_reg_write
;
897 /* needed for iio ops */
899 atom_card_info
->ioreg_read
= cail_ioreg_read
;
900 atom_card_info
->ioreg_write
= cail_ioreg_write
;
902 DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");
903 atom_card_info
->ioreg_read
= cail_reg_read
;
904 atom_card_info
->ioreg_write
= cail_reg_write
;
906 atom_card_info
->mc_read
= cail_mc_read
;
907 atom_card_info
->mc_write
= cail_mc_write
;
908 atom_card_info
->pll_read
= cail_pll_read
;
909 atom_card_info
->pll_write
= cail_pll_write
;
911 adev
->mode_info
.atom_context
= amdgpu_atom_parse(atom_card_info
, adev
->bios
);
912 if (!adev
->mode_info
.atom_context
) {
913 amdgpu_atombios_fini(adev
);
917 mutex_init(&adev
->mode_info
.atom_context
->mutex
);
918 amdgpu_atombios_scratch_regs_init(adev
);
919 amdgpu_atom_allocate_fb_scratch(adev
->mode_info
.atom_context
);
923 /* if we get transitioned to only one device, take VGA back */
925 * amdgpu_vga_set_decode - enable/disable vga decode
927 * @cookie: amdgpu_device pointer
928 * @state: enable/disable vga decode
930 * Enable/disable vga decode (all asics).
931 * Returns VGA resource flags.
933 static unsigned int amdgpu_vga_set_decode(void *cookie
, bool state
)
935 struct amdgpu_device
*adev
= cookie
;
936 amdgpu_asic_set_vga_state(adev
, state
);
938 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
939 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
941 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
945 * amdgpu_check_pot_argument - check that argument is a power of two
947 * @arg: value to check
949 * Validates that a certain argument is a power of two (all asics).
950 * Returns true if argument is valid.
952 static bool amdgpu_check_pot_argument(int arg
)
954 return (arg
& (arg
- 1)) == 0;
958 * amdgpu_check_arguments - validate module params
960 * @adev: amdgpu_device pointer
962 * Validates certain module parameters and updates
963 * the associated values used by the driver (all asics).
965 static void amdgpu_check_arguments(struct amdgpu_device
*adev
)
967 if (amdgpu_sched_jobs
< 4) {
968 dev_warn(adev
->dev
, "sched jobs (%d) must be at least 4\n",
970 amdgpu_sched_jobs
= 4;
971 } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs
)){
972 dev_warn(adev
->dev
, "sched jobs (%d) must be a power of 2\n",
974 amdgpu_sched_jobs
= roundup_pow_of_two(amdgpu_sched_jobs
);
977 if (amdgpu_gart_size
!= -1) {
978 /* gtt size must be greater or equal to 32M */
979 if (amdgpu_gart_size
< 32) {
980 dev_warn(adev
->dev
, "gart size (%d) too small\n",
982 amdgpu_gart_size
= -1;
986 if (!amdgpu_check_pot_argument(amdgpu_vm_size
)) {
987 dev_warn(adev
->dev
, "VM size (%d) must be a power of 2\n",
992 if (amdgpu_vm_size
< 1) {
993 dev_warn(adev
->dev
, "VM size (%d) too small, min is 1GB\n",
999 * Max GPUVM size for Cayman, SI and CI are 40 bits.
1001 if (amdgpu_vm_size
> 1024) {
1002 dev_warn(adev
->dev
, "VM size (%d) too large, max is 1TB\n",
1007 /* defines number of bits in page table versus page directory,
1008 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1009 * page table and the remaining bits are in the page directory */
1010 if (amdgpu_vm_block_size
== -1) {
1012 /* Total bits covered by PD + PTs */
1013 unsigned bits
= ilog2(amdgpu_vm_size
) + 18;
1015 /* Make sure the PD is 4K in size up to 8GB address space.
1016 Above that split equal between PD and PTs */
1017 if (amdgpu_vm_size
<= 8)
1018 amdgpu_vm_block_size
= bits
- 9;
1020 amdgpu_vm_block_size
= (bits
+ 3) / 2;
1022 } else if (amdgpu_vm_block_size
< 9) {
1023 dev_warn(adev
->dev
, "VM page table size (%d) too small\n",
1024 amdgpu_vm_block_size
);
1025 amdgpu_vm_block_size
= 9;
1028 if (amdgpu_vm_block_size
> 24 ||
1029 (amdgpu_vm_size
* 1024) < (1ull << amdgpu_vm_block_size
)) {
1030 dev_warn(adev
->dev
, "VM page table size (%d) too large\n",
1031 amdgpu_vm_block_size
);
1032 amdgpu_vm_block_size
= 9;
1035 if (amdgpu_vram_page_split
!= -1 && (amdgpu_vram_page_split
< 16 ||
1036 !amdgpu_check_pot_argument(amdgpu_vram_page_split
))) {
1037 dev_warn(adev
->dev
, "invalid VRAM page split (%d)\n",
1038 amdgpu_vram_page_split
);
1039 amdgpu_vram_page_split
= 1024;
1044 * amdgpu_switcheroo_set_state - set switcheroo state
1046 * @pdev: pci dev pointer
1047 * @state: vga_switcheroo state
1049 * Callback for the switcheroo driver. Suspends or resumes the
1050 * the asics before or after it is powered up using ACPI methods.
1052 static void amdgpu_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
1054 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1056 if (amdgpu_device_is_px(dev
) && state
== VGA_SWITCHEROO_OFF
)
1059 if (state
== VGA_SWITCHEROO_ON
) {
1060 unsigned d3_delay
= dev
->pdev
->d3_delay
;
1062 printk(KERN_INFO
"amdgpu: switched on\n");
1063 /* don't suspend or resume card normally */
1064 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1066 amdgpu_device_resume(dev
, true, true);
1068 dev
->pdev
->d3_delay
= d3_delay
;
1070 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
1071 drm_kms_helper_poll_enable(dev
);
1073 printk(KERN_INFO
"amdgpu: switched off\n");
1074 drm_kms_helper_poll_disable(dev
);
1075 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1076 amdgpu_device_suspend(dev
, true, true);
1077 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
1082 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1084 * @pdev: pci dev pointer
1086 * Callback for the switcheroo driver. Check of the switcheroo
1087 * state can be changed.
1088 * Returns true if the state can be changed, false if not.
1090 static bool amdgpu_switcheroo_can_switch(struct pci_dev
*pdev
)
1092 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1095 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1096 * locking inversion with the driver load path. And the access here is
1097 * completely racy anyway. So don't bother with locking for now.
1099 return dev
->open_count
== 0;
1102 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops
= {
1103 .set_gpu_state
= amdgpu_switcheroo_set_state
,
1105 .can_switch
= amdgpu_switcheroo_can_switch
,
1108 int amdgpu_set_clockgating_state(struct amdgpu_device
*adev
,
1109 enum amd_ip_block_type block_type
,
1110 enum amd_clockgating_state state
)
1114 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1115 if (!adev
->ip_blocks
[i
].status
.valid
)
1117 if (adev
->ip_blocks
[i
].version
->type
== block_type
) {
1118 r
= adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state((void *)adev
,
1128 int amdgpu_set_powergating_state(struct amdgpu_device
*adev
,
1129 enum amd_ip_block_type block_type
,
1130 enum amd_powergating_state state
)
1134 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1135 if (!adev
->ip_blocks
[i
].status
.valid
)
1137 if (adev
->ip_blocks
[i
].version
->type
== block_type
) {
1138 r
= adev
->ip_blocks
[i
].version
->funcs
->set_powergating_state((void *)adev
,
1148 void amdgpu_get_clockgating_state(struct amdgpu_device
*adev
, u32
*flags
)
1152 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1153 if (!adev
->ip_blocks
[i
].status
.valid
)
1155 if (adev
->ip_blocks
[i
].version
->funcs
->get_clockgating_state
)
1156 adev
->ip_blocks
[i
].version
->funcs
->get_clockgating_state((void *)adev
, flags
);
1160 int amdgpu_wait_for_idle(struct amdgpu_device
*adev
,
1161 enum amd_ip_block_type block_type
)
1165 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1166 if (!adev
->ip_blocks
[i
].status
.valid
)
1168 if (adev
->ip_blocks
[i
].version
->type
== block_type
) {
1169 r
= adev
->ip_blocks
[i
].version
->funcs
->wait_for_idle((void *)adev
);
1179 bool amdgpu_is_idle(struct amdgpu_device
*adev
,
1180 enum amd_ip_block_type block_type
)
1184 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1185 if (!adev
->ip_blocks
[i
].status
.valid
)
1187 if (adev
->ip_blocks
[i
].version
->type
== block_type
)
1188 return adev
->ip_blocks
[i
].version
->funcs
->is_idle((void *)adev
);
1194 struct amdgpu_ip_block
* amdgpu_get_ip_block(struct amdgpu_device
*adev
,
1195 enum amd_ip_block_type type
)
1199 for (i
= 0; i
< adev
->num_ip_blocks
; i
++)
1200 if (adev
->ip_blocks
[i
].version
->type
== type
)
1201 return &adev
->ip_blocks
[i
];
1207 * amdgpu_ip_block_version_cmp
1209 * @adev: amdgpu_device pointer
1210 * @type: enum amd_ip_block_type
1211 * @major: major version
1212 * @minor: minor version
1214 * return 0 if equal or greater
1215 * return 1 if smaller or the ip_block doesn't exist
1217 int amdgpu_ip_block_version_cmp(struct amdgpu_device
*adev
,
1218 enum amd_ip_block_type type
,
1219 u32 major
, u32 minor
)
1221 struct amdgpu_ip_block
*ip_block
= amdgpu_get_ip_block(adev
, type
);
1223 if (ip_block
&& ((ip_block
->version
->major
> major
) ||
1224 ((ip_block
->version
->major
== major
) &&
1225 (ip_block
->version
->minor
>= minor
))))
1232 * amdgpu_ip_block_add
1234 * @adev: amdgpu_device pointer
1235 * @ip_block_version: pointer to the IP to add
1237 * Adds the IP block driver information to the collection of IPs
1240 int amdgpu_ip_block_add(struct amdgpu_device
*adev
,
1241 const struct amdgpu_ip_block_version
*ip_block_version
)
1243 if (!ip_block_version
)
1246 adev
->ip_blocks
[adev
->num_ip_blocks
++].version
= ip_block_version
;
1251 static void amdgpu_device_enable_virtual_display(struct amdgpu_device
*adev
)
1253 adev
->enable_virtual_display
= false;
1255 if (amdgpu_virtual_display
) {
1256 struct drm_device
*ddev
= adev
->ddev
;
1257 const char *pci_address_name
= pci_name(ddev
->pdev
);
1258 char *pciaddstr
, *pciaddstr_tmp
, *pciaddname_tmp
, *pciaddname
;
1260 pciaddstr
= kstrdup(amdgpu_virtual_display
, GFP_KERNEL
);
1261 pciaddstr_tmp
= pciaddstr
;
1262 while ((pciaddname_tmp
= strsep(&pciaddstr_tmp
, ";"))) {
1263 pciaddname
= strsep(&pciaddname_tmp
, ",");
1264 if (!strcmp("all", pciaddname
)
1265 || !strcmp(pci_address_name
, pciaddname
)) {
1269 adev
->enable_virtual_display
= true;
1272 res
= kstrtol(pciaddname_tmp
, 10,
1280 adev
->mode_info
.num_crtc
= num_crtc
;
1282 adev
->mode_info
.num_crtc
= 1;
1288 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1289 amdgpu_virtual_display
, pci_address_name
,
1290 adev
->enable_virtual_display
, adev
->mode_info
.num_crtc
);
1296 static int amdgpu_early_init(struct amdgpu_device
*adev
)
1300 amdgpu_device_enable_virtual_display(adev
);
1302 switch (adev
->asic_type
) {
1306 case CHIP_POLARIS11
:
1307 case CHIP_POLARIS10
:
1308 case CHIP_POLARIS12
:
1311 if (adev
->asic_type
== CHIP_CARRIZO
|| adev
->asic_type
== CHIP_STONEY
)
1312 adev
->family
= AMDGPU_FAMILY_CZ
;
1314 adev
->family
= AMDGPU_FAMILY_VI
;
1316 r
= vi_set_ip_blocks(adev
);
1320 #ifdef CONFIG_DRM_AMDGPU_SI
1326 adev
->family
= AMDGPU_FAMILY_SI
;
1327 r
= si_set_ip_blocks(adev
);
1332 #ifdef CONFIG_DRM_AMDGPU_CIK
1338 if ((adev
->asic_type
== CHIP_BONAIRE
) || (adev
->asic_type
== CHIP_HAWAII
))
1339 adev
->family
= AMDGPU_FAMILY_CI
;
1341 adev
->family
= AMDGPU_FAMILY_KV
;
1343 r
= cik_set_ip_blocks(adev
);
1349 /* FIXME: not supported yet */
1353 if (amdgpu_sriov_vf(adev
)) {
1354 r
= amdgpu_virt_request_full_gpu(adev
, true);
1359 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1360 if ((amdgpu_ip_block_mask
& (1 << i
)) == 0) {
1361 DRM_ERROR("disabled ip block: %d\n", i
);
1362 adev
->ip_blocks
[i
].status
.valid
= false;
1364 if (adev
->ip_blocks
[i
].version
->funcs
->early_init
) {
1365 r
= adev
->ip_blocks
[i
].version
->funcs
->early_init((void *)adev
);
1367 adev
->ip_blocks
[i
].status
.valid
= false;
1369 DRM_ERROR("early_init of IP block <%s> failed %d\n",
1370 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1373 adev
->ip_blocks
[i
].status
.valid
= true;
1376 adev
->ip_blocks
[i
].status
.valid
= true;
1381 adev
->cg_flags
&= amdgpu_cg_mask
;
1382 adev
->pg_flags
&= amdgpu_pg_mask
;
1387 static int amdgpu_init(struct amdgpu_device
*adev
)
1391 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1392 if (!adev
->ip_blocks
[i
].status
.valid
)
1394 r
= adev
->ip_blocks
[i
].version
->funcs
->sw_init((void *)adev
);
1396 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1397 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1400 adev
->ip_blocks
[i
].status
.sw
= true;
1401 /* need to do gmc hw init early so we can allocate gpu mem */
1402 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_GMC
) {
1403 r
= amdgpu_vram_scratch_init(adev
);
1405 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r
);
1408 r
= adev
->ip_blocks
[i
].version
->funcs
->hw_init((void *)adev
);
1410 DRM_ERROR("hw_init %d failed %d\n", i
, r
);
1413 r
= amdgpu_wb_init(adev
);
1415 DRM_ERROR("amdgpu_wb_init failed %d\n", r
);
1418 adev
->ip_blocks
[i
].status
.hw
= true;
1420 /* right after GMC hw init, we create CSA */
1421 if (amdgpu_sriov_vf(adev
)) {
1422 r
= amdgpu_allocate_static_csa(adev
);
1424 DRM_ERROR("allocate CSA failed %d\n", r
);
1431 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1432 if (!adev
->ip_blocks
[i
].status
.sw
)
1434 /* gmc hw init is done early */
1435 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_GMC
)
1437 r
= adev
->ip_blocks
[i
].version
->funcs
->hw_init((void *)adev
);
1439 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1440 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1443 adev
->ip_blocks
[i
].status
.hw
= true;
1449 static int amdgpu_late_init(struct amdgpu_device
*adev
)
1453 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1454 if (!adev
->ip_blocks
[i
].status
.valid
)
1456 if (adev
->ip_blocks
[i
].version
->funcs
->late_init
) {
1457 r
= adev
->ip_blocks
[i
].version
->funcs
->late_init((void *)adev
);
1459 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1460 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1463 adev
->ip_blocks
[i
].status
.late_initialized
= true;
1465 /* skip CG for VCE/UVD, it's handled specially */
1466 if (adev
->ip_blocks
[i
].version
->type
!= AMD_IP_BLOCK_TYPE_UVD
&&
1467 adev
->ip_blocks
[i
].version
->type
!= AMD_IP_BLOCK_TYPE_VCE
) {
1468 /* enable clockgating to save power */
1469 r
= adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state((void *)adev
,
1472 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1473 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1482 static int amdgpu_fini(struct amdgpu_device
*adev
)
1486 /* need to disable SMC first */
1487 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1488 if (!adev
->ip_blocks
[i
].status
.hw
)
1490 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_SMC
) {
1491 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1492 r
= adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state((void *)adev
,
1493 AMD_CG_STATE_UNGATE
);
1495 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1496 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1499 r
= adev
->ip_blocks
[i
].version
->funcs
->hw_fini((void *)adev
);
1500 /* XXX handle errors */
1502 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1503 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1505 adev
->ip_blocks
[i
].status
.hw
= false;
1510 for (i
= adev
->num_ip_blocks
- 1; i
>= 0; i
--) {
1511 if (!adev
->ip_blocks
[i
].status
.hw
)
1513 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_GMC
) {
1514 amdgpu_wb_fini(adev
);
1515 amdgpu_vram_scratch_fini(adev
);
1518 if (adev
->ip_blocks
[i
].version
->type
!= AMD_IP_BLOCK_TYPE_UVD
&&
1519 adev
->ip_blocks
[i
].version
->type
!= AMD_IP_BLOCK_TYPE_VCE
) {
1520 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1521 r
= adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state((void *)adev
,
1522 AMD_CG_STATE_UNGATE
);
1524 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1525 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1530 r
= adev
->ip_blocks
[i
].version
->funcs
->hw_fini((void *)adev
);
1531 /* XXX handle errors */
1533 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1534 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1537 adev
->ip_blocks
[i
].status
.hw
= false;
1540 for (i
= adev
->num_ip_blocks
- 1; i
>= 0; i
--) {
1541 if (!adev
->ip_blocks
[i
].status
.sw
)
1543 r
= adev
->ip_blocks
[i
].version
->funcs
->sw_fini((void *)adev
);
1544 /* XXX handle errors */
1546 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1547 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1549 adev
->ip_blocks
[i
].status
.sw
= false;
1550 adev
->ip_blocks
[i
].status
.valid
= false;
1553 for (i
= adev
->num_ip_blocks
- 1; i
>= 0; i
--) {
1554 if (!adev
->ip_blocks
[i
].status
.late_initialized
)
1556 if (adev
->ip_blocks
[i
].version
->funcs
->late_fini
)
1557 adev
->ip_blocks
[i
].version
->funcs
->late_fini((void *)adev
);
1558 adev
->ip_blocks
[i
].status
.late_initialized
= false;
1561 if (amdgpu_sriov_vf(adev
)) {
1562 amdgpu_bo_free_kernel(&adev
->virt
.csa_obj
, &adev
->virt
.csa_vmid0_addr
, NULL
);
1563 amdgpu_virt_release_full_gpu(adev
, false);
1569 int amdgpu_suspend(struct amdgpu_device
*adev
)
1573 if (amdgpu_sriov_vf(adev
))
1574 amdgpu_virt_request_full_gpu(adev
, false);
1576 /* ungate SMC block first */
1577 r
= amdgpu_set_clockgating_state(adev
, AMD_IP_BLOCK_TYPE_SMC
,
1578 AMD_CG_STATE_UNGATE
);
1580 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r
);
1583 for (i
= adev
->num_ip_blocks
- 1; i
>= 0; i
--) {
1584 if (!adev
->ip_blocks
[i
].status
.valid
)
1586 /* ungate blocks so that suspend can properly shut them down */
1587 if (i
!= AMD_IP_BLOCK_TYPE_SMC
) {
1588 r
= adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state((void *)adev
,
1589 AMD_CG_STATE_UNGATE
);
1591 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1592 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1595 /* XXX handle errors */
1596 r
= adev
->ip_blocks
[i
].version
->funcs
->suspend(adev
);
1597 /* XXX handle errors */
1599 DRM_ERROR("suspend of IP block <%s> failed %d\n",
1600 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1604 if (amdgpu_sriov_vf(adev
))
1605 amdgpu_virt_release_full_gpu(adev
, false);
1610 static int amdgpu_resume(struct amdgpu_device
*adev
)
1614 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1615 if (!adev
->ip_blocks
[i
].status
.valid
)
1617 r
= adev
->ip_blocks
[i
].version
->funcs
->resume(adev
);
1619 DRM_ERROR("resume of IP block <%s> failed %d\n",
1620 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1628 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device
*adev
)
1630 if (amdgpu_atombios_has_gpu_virtualization_table(adev
))
1631 adev
->virt
.caps
|= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS
;
1635 * amdgpu_device_init - initialize the driver
1637 * @adev: amdgpu_device pointer
1638 * @pdev: drm dev pointer
1639 * @pdev: pci dev pointer
1640 * @flags: driver flags
1642 * Initializes the driver info and hw (all asics).
1643 * Returns 0 for success or an error on failure.
1644 * Called at driver startup.
1646 int amdgpu_device_init(struct amdgpu_device
*adev
,
1647 struct drm_device
*ddev
,
1648 struct pci_dev
*pdev
,
1652 bool runtime
= false;
1655 adev
->shutdown
= false;
1656 adev
->dev
= &pdev
->dev
;
1659 adev
->flags
= flags
;
1660 adev
->asic_type
= flags
& AMD_ASIC_MASK
;
1661 adev
->usec_timeout
= AMDGPU_MAX_USEC_TIMEOUT
;
1662 adev
->mc
.gtt_size
= 512 * 1024 * 1024;
1663 adev
->accel_working
= false;
1664 adev
->num_rings
= 0;
1665 adev
->mman
.buffer_funcs
= NULL
;
1666 adev
->mman
.buffer_funcs_ring
= NULL
;
1667 adev
->vm_manager
.vm_pte_funcs
= NULL
;
1668 adev
->vm_manager
.vm_pte_num_rings
= 0;
1669 adev
->gart
.gart_funcs
= NULL
;
1670 adev
->fence_context
= dma_fence_context_alloc(AMDGPU_MAX_RINGS
);
1672 adev
->smc_rreg
= &amdgpu_invalid_rreg
;
1673 adev
->smc_wreg
= &amdgpu_invalid_wreg
;
1674 adev
->pcie_rreg
= &amdgpu_invalid_rreg
;
1675 adev
->pcie_wreg
= &amdgpu_invalid_wreg
;
1676 adev
->pciep_rreg
= &amdgpu_invalid_rreg
;
1677 adev
->pciep_wreg
= &amdgpu_invalid_wreg
;
1678 adev
->uvd_ctx_rreg
= &amdgpu_invalid_rreg
;
1679 adev
->uvd_ctx_wreg
= &amdgpu_invalid_wreg
;
1680 adev
->didt_rreg
= &amdgpu_invalid_rreg
;
1681 adev
->didt_wreg
= &amdgpu_invalid_wreg
;
1682 adev
->gc_cac_rreg
= &amdgpu_invalid_rreg
;
1683 adev
->gc_cac_wreg
= &amdgpu_invalid_wreg
;
1684 adev
->audio_endpt_rreg
= &amdgpu_block_invalid_rreg
;
1685 adev
->audio_endpt_wreg
= &amdgpu_block_invalid_wreg
;
1688 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1689 amdgpu_asic_name
[adev
->asic_type
], pdev
->vendor
, pdev
->device
,
1690 pdev
->subsystem_vendor
, pdev
->subsystem_device
, pdev
->revision
);
1692 /* mutex initialization are all done here so we
1693 * can recall function without having locking issues */
1694 mutex_init(&adev
->vm_manager
.lock
);
1695 atomic_set(&adev
->irq
.ih
.lock
, 0);
1696 mutex_init(&adev
->pm
.mutex
);
1697 mutex_init(&adev
->gfx
.gpu_clock_mutex
);
1698 mutex_init(&adev
->srbm_mutex
);
1699 mutex_init(&adev
->grbm_idx_mutex
);
1700 mutex_init(&adev
->mn_lock
);
1701 hash_init(adev
->mn_hash
);
1703 amdgpu_check_arguments(adev
);
1705 /* Registers mapping */
1706 /* TODO: block userspace mapping of io register */
1707 spin_lock_init(&adev
->mmio_idx_lock
);
1708 spin_lock_init(&adev
->smc_idx_lock
);
1709 spin_lock_init(&adev
->pcie_idx_lock
);
1710 spin_lock_init(&adev
->uvd_ctx_idx_lock
);
1711 spin_lock_init(&adev
->didt_idx_lock
);
1712 spin_lock_init(&adev
->gc_cac_idx_lock
);
1713 spin_lock_init(&adev
->audio_endpt_idx_lock
);
1714 spin_lock_init(&adev
->mm_stats
.lock
);
1716 INIT_LIST_HEAD(&adev
->shadow_list
);
1717 mutex_init(&adev
->shadow_list_lock
);
1719 INIT_LIST_HEAD(&adev
->gtt_list
);
1720 spin_lock_init(&adev
->gtt_list_lock
);
1722 if (adev
->asic_type
>= CHIP_BONAIRE
) {
1723 adev
->rmmio_base
= pci_resource_start(adev
->pdev
, 5);
1724 adev
->rmmio_size
= pci_resource_len(adev
->pdev
, 5);
1726 adev
->rmmio_base
= pci_resource_start(adev
->pdev
, 2);
1727 adev
->rmmio_size
= pci_resource_len(adev
->pdev
, 2);
1730 adev
->rmmio
= ioremap(adev
->rmmio_base
, adev
->rmmio_size
);
1731 if (adev
->rmmio
== NULL
) {
1734 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev
->rmmio_base
);
1735 DRM_INFO("register mmio size: %u\n", (unsigned)adev
->rmmio_size
);
1737 if (adev
->asic_type
>= CHIP_BONAIRE
)
1738 /* doorbell bar mapping */
1739 amdgpu_doorbell_init(adev
);
1741 /* io port mapping */
1742 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
1743 if (pci_resource_flags(adev
->pdev
, i
) & IORESOURCE_IO
) {
1744 adev
->rio_mem_size
= pci_resource_len(adev
->pdev
, i
);
1745 adev
->rio_mem
= pci_iomap(adev
->pdev
, i
, adev
->rio_mem_size
);
1749 if (adev
->rio_mem
== NULL
)
1750 DRM_INFO("PCI I/O BAR is not found.\n");
1752 /* early init functions */
1753 r
= amdgpu_early_init(adev
);
1757 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1758 /* this will fail for cards that aren't VGA class devices, just
1760 vga_client_register(adev
->pdev
, adev
, NULL
, amdgpu_vga_set_decode
);
1762 if (amdgpu_runtime_pm
== 1)
1764 if (amdgpu_device_is_px(ddev
))
1766 vga_switcheroo_register_client(adev
->pdev
, &amdgpu_switcheroo_ops
, runtime
);
1768 vga_switcheroo_init_domain_pm_ops(adev
->dev
, &adev
->vga_pm_domain
);
1771 if (!amdgpu_get_bios(adev
)) {
1776 r
= amdgpu_atombios_init(adev
);
1778 dev_err(adev
->dev
, "amdgpu_atombios_init failed\n");
1782 /* detect if we are with an SRIOV vbios */
1783 amdgpu_device_detect_sriov_bios(adev
);
1785 /* Post card if necessary */
1786 if (amdgpu_vpost_needed(adev
)) {
1788 dev_err(adev
->dev
, "no vBIOS found\n");
1792 DRM_INFO("GPU posting now...\n");
1793 r
= amdgpu_atom_asic_init(adev
->mode_info
.atom_context
);
1795 dev_err(adev
->dev
, "gpu post error!\n");
1799 DRM_INFO("GPU post is not needed\n");
1802 /* Initialize clocks */
1803 r
= amdgpu_atombios_get_clock_info(adev
);
1805 dev_err(adev
->dev
, "amdgpu_atombios_get_clock_info failed\n");
1808 /* init i2c buses */
1809 amdgpu_atombios_i2c_init(adev
);
1812 r
= amdgpu_fence_driver_init(adev
);
1814 dev_err(adev
->dev
, "amdgpu_fence_driver_init failed\n");
1818 /* init the mode config */
1819 drm_mode_config_init(adev
->ddev
);
1821 r
= amdgpu_init(adev
);
1823 dev_err(adev
->dev
, "amdgpu_init failed\n");
1828 adev
->accel_working
= true;
1830 /* Initialize the buffer migration limit. */
1831 if (amdgpu_moverate
>= 0)
1832 max_MBps
= amdgpu_moverate
;
1834 max_MBps
= 8; /* Allow 8 MB/s. */
1835 /* Get a log2 for easy divisions. */
1836 adev
->mm_stats
.log2_max_MBps
= ilog2(max(1u, max_MBps
));
1838 amdgpu_fbdev_init(adev
);
1840 r
= amdgpu_ib_pool_init(adev
);
1842 dev_err(adev
->dev
, "IB initialization failed (%d).\n", r
);
1846 r
= amdgpu_ib_ring_tests(adev
);
1848 DRM_ERROR("ib ring test failed (%d).\n", r
);
1850 r
= amdgpu_gem_debugfs_init(adev
);
1852 DRM_ERROR("registering gem debugfs failed (%d).\n", r
);
1855 r
= amdgpu_debugfs_regs_init(adev
);
1857 DRM_ERROR("registering register debugfs failed (%d).\n", r
);
1860 r
= amdgpu_debugfs_firmware_init(adev
);
1862 DRM_ERROR("registering firmware debugfs failed (%d).\n", r
);
1866 if ((amdgpu_testing
& 1)) {
1867 if (adev
->accel_working
)
1868 amdgpu_test_moves(adev
);
1870 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1872 if ((amdgpu_testing
& 2)) {
1873 if (adev
->accel_working
)
1874 amdgpu_test_syncing(adev
);
1876 DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1878 if (amdgpu_benchmarking
) {
1879 if (adev
->accel_working
)
1880 amdgpu_benchmark(adev
, amdgpu_benchmarking
);
1882 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1885 /* enable clockgating, etc. after ib tests, etc. since some blocks require
1886 * explicit gating rather than handling it automatically.
1888 r
= amdgpu_late_init(adev
);
1890 dev_err(adev
->dev
, "amdgpu_late_init failed\n");
1898 vga_switcheroo_fini_domain_pm_ops(adev
->dev
);
1903 * amdgpu_device_fini - tear down the driver
1905 * @adev: amdgpu_device pointer
1907 * Tear down the driver info (all asics).
1908 * Called at driver shutdown.
1910 void amdgpu_device_fini(struct amdgpu_device
*adev
)
1914 DRM_INFO("amdgpu: finishing device.\n");
1915 adev
->shutdown
= true;
1916 drm_crtc_force_disable_all(adev
->ddev
);
1917 /* evict vram memory */
1918 amdgpu_bo_evict_vram(adev
);
1919 amdgpu_ib_pool_fini(adev
);
1920 amdgpu_fence_driver_fini(adev
);
1921 amdgpu_fbdev_fini(adev
);
1922 r
= amdgpu_fini(adev
);
1923 adev
->accel_working
= false;
1924 /* free i2c buses */
1925 amdgpu_i2c_fini(adev
);
1926 amdgpu_atombios_fini(adev
);
1929 vga_switcheroo_unregister_client(adev
->pdev
);
1930 if (adev
->flags
& AMD_IS_PX
)
1931 vga_switcheroo_fini_domain_pm_ops(adev
->dev
);
1932 vga_client_register(adev
->pdev
, NULL
, NULL
, NULL
);
1934 pci_iounmap(adev
->pdev
, adev
->rio_mem
);
1935 adev
->rio_mem
= NULL
;
1936 iounmap(adev
->rmmio
);
1938 if (adev
->asic_type
>= CHIP_BONAIRE
)
1939 amdgpu_doorbell_fini(adev
);
1940 amdgpu_debugfs_regs_cleanup(adev
);
1948 * amdgpu_device_suspend - initiate device suspend
1950 * @pdev: drm dev pointer
1951 * @state: suspend state
1953 * Puts the hw in the suspend state (all asics).
1954 * Returns 0 for success or an error on failure.
1955 * Called at driver suspend.
1957 int amdgpu_device_suspend(struct drm_device
*dev
, bool suspend
, bool fbcon
)
1959 struct amdgpu_device
*adev
;
1960 struct drm_crtc
*crtc
;
1961 struct drm_connector
*connector
;
1964 if (dev
== NULL
|| dev
->dev_private
== NULL
) {
1968 adev
= dev
->dev_private
;
1970 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1973 drm_kms_helper_poll_disable(dev
);
1975 /* turn off display hw */
1976 drm_modeset_lock_all(dev
);
1977 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1978 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_OFF
);
1980 drm_modeset_unlock_all(dev
);
1982 /* unpin the front buffers and cursors */
1983 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1984 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
1985 struct amdgpu_framebuffer
*rfb
= to_amdgpu_framebuffer(crtc
->primary
->fb
);
1986 struct amdgpu_bo
*robj
;
1988 if (amdgpu_crtc
->cursor_bo
) {
1989 struct amdgpu_bo
*aobj
= gem_to_amdgpu_bo(amdgpu_crtc
->cursor_bo
);
1990 r
= amdgpu_bo_reserve(aobj
, false);
1992 amdgpu_bo_unpin(aobj
);
1993 amdgpu_bo_unreserve(aobj
);
1997 if (rfb
== NULL
|| rfb
->obj
== NULL
) {
2000 robj
= gem_to_amdgpu_bo(rfb
->obj
);
2001 /* don't unpin kernel fb objects */
2002 if (!amdgpu_fbdev_robj_is_fb(adev
, robj
)) {
2003 r
= amdgpu_bo_reserve(robj
, false);
2005 amdgpu_bo_unpin(robj
);
2006 amdgpu_bo_unreserve(robj
);
2010 /* evict vram memory */
2011 amdgpu_bo_evict_vram(adev
);
2013 amdgpu_fence_driver_suspend(adev
);
2015 r
= amdgpu_suspend(adev
);
2017 /* evict remaining vram memory
2018 * This second call to evict vram is to evict the gart page table
2021 amdgpu_bo_evict_vram(adev
);
2023 amdgpu_atombios_scratch_regs_save(adev
);
2024 pci_save_state(dev
->pdev
);
2026 /* Shut down the device */
2027 pci_disable_device(dev
->pdev
);
2028 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
2030 r
= amdgpu_asic_reset(adev
);
2032 DRM_ERROR("amdgpu asic reset failed\n");
2037 amdgpu_fbdev_set_suspend(adev
, 1);
2044 * amdgpu_device_resume - initiate device resume
2046 * @pdev: drm dev pointer
2048 * Bring the hw back to operating state (all asics).
2049 * Returns 0 for success or an error on failure.
2050 * Called at driver resume.
2052 int amdgpu_device_resume(struct drm_device
*dev
, bool resume
, bool fbcon
)
2054 struct drm_connector
*connector
;
2055 struct amdgpu_device
*adev
= dev
->dev_private
;
2056 struct drm_crtc
*crtc
;
2059 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2066 pci_set_power_state(dev
->pdev
, PCI_D0
);
2067 pci_restore_state(dev
->pdev
);
2068 r
= pci_enable_device(dev
->pdev
);
2075 amdgpu_atombios_scratch_regs_restore(adev
);
2078 if (amdgpu_need_post(adev
)) {
2079 r
= amdgpu_atom_asic_init(adev
->mode_info
.atom_context
);
2081 DRM_ERROR("amdgpu asic init failed\n");
2084 r
= amdgpu_resume(adev
);
2086 DRM_ERROR("amdgpu_resume failed (%d).\n", r
);
2088 amdgpu_fence_driver_resume(adev
);
2091 r
= amdgpu_ib_ring_tests(adev
);
2093 DRM_ERROR("ib ring test failed (%d).\n", r
);
2096 r
= amdgpu_late_init(adev
);
2104 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2105 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2107 if (amdgpu_crtc
->cursor_bo
) {
2108 struct amdgpu_bo
*aobj
= gem_to_amdgpu_bo(amdgpu_crtc
->cursor_bo
);
2109 r
= amdgpu_bo_reserve(aobj
, false);
2111 r
= amdgpu_bo_pin(aobj
,
2112 AMDGPU_GEM_DOMAIN_VRAM
,
2113 &amdgpu_crtc
->cursor_addr
);
2115 DRM_ERROR("Failed to pin cursor BO (%d)\n", r
);
2116 amdgpu_bo_unreserve(aobj
);
2121 /* blat the mode back in */
2123 drm_helper_resume_force_mode(dev
);
2124 /* turn on display hw */
2125 drm_modeset_lock_all(dev
);
2126 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
2127 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_ON
);
2129 drm_modeset_unlock_all(dev
);
2132 drm_kms_helper_poll_enable(dev
);
2135 * Most of the connector probing functions try to acquire runtime pm
2136 * refs to ensure that the GPU is powered on when connector polling is
2137 * performed. Since we're calling this from a runtime PM callback,
2138 * trying to acquire rpm refs will cause us to deadlock.
2140 * Since we're guaranteed to be holding the rpm lock, it's safe to
2141 * temporarily disable the rpm helpers so this doesn't deadlock us.
2144 dev
->dev
->power
.disable_depth
++;
2146 drm_helper_hpd_irq_event(dev
);
2148 dev
->dev
->power
.disable_depth
--;
2152 amdgpu_fbdev_set_suspend(adev
, 0);
2159 static bool amdgpu_check_soft_reset(struct amdgpu_device
*adev
)
2162 bool asic_hang
= false;
2164 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
2165 if (!adev
->ip_blocks
[i
].status
.valid
)
2167 if (adev
->ip_blocks
[i
].version
->funcs
->check_soft_reset
)
2168 adev
->ip_blocks
[i
].status
.hang
=
2169 adev
->ip_blocks
[i
].version
->funcs
->check_soft_reset(adev
);
2170 if (adev
->ip_blocks
[i
].status
.hang
) {
2171 DRM_INFO("IP block:%s is hung!\n", adev
->ip_blocks
[i
].version
->funcs
->name
);
2178 static int amdgpu_pre_soft_reset(struct amdgpu_device
*adev
)
2182 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
2183 if (!adev
->ip_blocks
[i
].status
.valid
)
2185 if (adev
->ip_blocks
[i
].status
.hang
&&
2186 adev
->ip_blocks
[i
].version
->funcs
->pre_soft_reset
) {
2187 r
= adev
->ip_blocks
[i
].version
->funcs
->pre_soft_reset(adev
);
2196 static bool amdgpu_need_full_reset(struct amdgpu_device
*adev
)
2200 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
2201 if (!adev
->ip_blocks
[i
].status
.valid
)
2203 if ((adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_GMC
) ||
2204 (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_SMC
) ||
2205 (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_ACP
) ||
2206 (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_DCE
)) {
2207 if (adev
->ip_blocks
[i
].status
.hang
) {
2208 DRM_INFO("Some block need full reset!\n");
2216 static int amdgpu_soft_reset(struct amdgpu_device
*adev
)
2220 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
2221 if (!adev
->ip_blocks
[i
].status
.valid
)
2223 if (adev
->ip_blocks
[i
].status
.hang
&&
2224 adev
->ip_blocks
[i
].version
->funcs
->soft_reset
) {
2225 r
= adev
->ip_blocks
[i
].version
->funcs
->soft_reset(adev
);
2234 static int amdgpu_post_soft_reset(struct amdgpu_device
*adev
)
2238 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
2239 if (!adev
->ip_blocks
[i
].status
.valid
)
2241 if (adev
->ip_blocks
[i
].status
.hang
&&
2242 adev
->ip_blocks
[i
].version
->funcs
->post_soft_reset
)
2243 r
= adev
->ip_blocks
[i
].version
->funcs
->post_soft_reset(adev
);
2251 bool amdgpu_need_backup(struct amdgpu_device
*adev
)
2253 if (adev
->flags
& AMD_IS_APU
)
2256 return amdgpu_lockup_timeout
> 0 ? true : false;
2259 static int amdgpu_recover_vram_from_shadow(struct amdgpu_device
*adev
,
2260 struct amdgpu_ring
*ring
,
2261 struct amdgpu_bo
*bo
,
2262 struct dma_fence
**fence
)
2270 r
= amdgpu_bo_reserve(bo
, false);
2273 domain
= amdgpu_mem_type_to_domain(bo
->tbo
.mem
.mem_type
);
2274 /* if bo has been evicted, then no need to recover */
2275 if (domain
== AMDGPU_GEM_DOMAIN_VRAM
) {
2276 r
= amdgpu_bo_restore_from_shadow(adev
, ring
, bo
,
2279 DRM_ERROR("recover page table failed!\n");
2284 amdgpu_bo_unreserve(bo
);
2289 * amdgpu_gpu_reset - reset the asic
2291 * @adev: amdgpu device pointer
2293 * Attempt the reset the GPU if it has hung (all asics).
2294 * Returns 0 for success or an error on failure.
2296 int amdgpu_gpu_reset(struct amdgpu_device
*adev
)
2300 bool need_full_reset
;
2302 if (amdgpu_sriov_vf(adev
))
2305 if (!amdgpu_check_soft_reset(adev
)) {
2306 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2310 atomic_inc(&adev
->gpu_reset_counter
);
2313 resched
= ttm_bo_lock_delayed_workqueue(&adev
->mman
.bdev
);
2315 /* block scheduler */
2316 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
2317 struct amdgpu_ring
*ring
= adev
->rings
[i
];
2321 kthread_park(ring
->sched
.thread
);
2322 amd_sched_hw_job_reset(&ring
->sched
);
2324 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2325 amdgpu_fence_driver_force_completion(adev
);
2327 need_full_reset
= amdgpu_need_full_reset(adev
);
2329 if (!need_full_reset
) {
2330 amdgpu_pre_soft_reset(adev
);
2331 r
= amdgpu_soft_reset(adev
);
2332 amdgpu_post_soft_reset(adev
);
2333 if (r
|| amdgpu_check_soft_reset(adev
)) {
2334 DRM_INFO("soft reset failed, will fallback to full reset!\n");
2335 need_full_reset
= true;
2339 if (need_full_reset
) {
2340 r
= amdgpu_suspend(adev
);
2343 /* Disable fb access */
2344 if (adev
->mode_info
.num_crtc
) {
2345 struct amdgpu_mode_mc_save save
;
2346 amdgpu_display_stop_mc_access(adev
, &save
);
2347 amdgpu_wait_for_idle(adev
, AMD_IP_BLOCK_TYPE_GMC
);
2349 amdgpu_atombios_scratch_regs_save(adev
);
2350 r
= amdgpu_asic_reset(adev
);
2351 amdgpu_atombios_scratch_regs_restore(adev
);
2353 amdgpu_atom_asic_init(adev
->mode_info
.atom_context
);
2356 dev_info(adev
->dev
, "GPU reset succeeded, trying to resume\n");
2357 r
= amdgpu_resume(adev
);
2361 amdgpu_irq_gpu_reset_resume_helper(adev
);
2362 if (need_full_reset
&& amdgpu_need_backup(adev
)) {
2363 r
= amdgpu_ttm_recover_gart(adev
);
2365 DRM_ERROR("gart recovery failed!!!\n");
2367 r
= amdgpu_ib_ring_tests(adev
);
2369 dev_err(adev
->dev
, "ib ring test failed (%d).\n", r
);
2370 r
= amdgpu_suspend(adev
);
2371 need_full_reset
= true;
2375 * recovery vm page tables, since we cannot depend on VRAM is
2376 * consistent after gpu full reset.
2378 if (need_full_reset
&& amdgpu_need_backup(adev
)) {
2379 struct amdgpu_ring
*ring
= adev
->mman
.buffer_funcs_ring
;
2380 struct amdgpu_bo
*bo
, *tmp
;
2381 struct dma_fence
*fence
= NULL
, *next
= NULL
;
2383 DRM_INFO("recover vram bo from shadow\n");
2384 mutex_lock(&adev
->shadow_list_lock
);
2385 list_for_each_entry_safe(bo
, tmp
, &adev
->shadow_list
, shadow_list
) {
2386 amdgpu_recover_vram_from_shadow(adev
, ring
, bo
, &next
);
2388 r
= dma_fence_wait(fence
, false);
2390 WARN(r
, "recovery from shadow isn't comleted\n");
2395 dma_fence_put(fence
);
2398 mutex_unlock(&adev
->shadow_list_lock
);
2400 r
= dma_fence_wait(fence
, false);
2402 WARN(r
, "recovery from shadow isn't comleted\n");
2404 dma_fence_put(fence
);
2406 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
2407 struct amdgpu_ring
*ring
= adev
->rings
[i
];
2411 amd_sched_job_recovery(&ring
->sched
);
2412 kthread_unpark(ring
->sched
.thread
);
2415 dev_err(adev
->dev
, "asic resume failed (%d).\n", r
);
2416 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
2417 if (adev
->rings
[i
]) {
2418 kthread_unpark(adev
->rings
[i
]->sched
.thread
);
2423 drm_helper_resume_force_mode(adev
->ddev
);
2425 ttm_bo_unlock_delayed_workqueue(&adev
->mman
.bdev
, resched
);
2427 /* bad news, how to tell it to userspace ? */
2428 dev_info(adev
->dev
, "GPU reset failed\n");
2434 void amdgpu_get_pcie_info(struct amdgpu_device
*adev
)
2439 if (amdgpu_pcie_gen_cap
)
2440 adev
->pm
.pcie_gen_mask
= amdgpu_pcie_gen_cap
;
2442 if (amdgpu_pcie_lane_cap
)
2443 adev
->pm
.pcie_mlw_mask
= amdgpu_pcie_lane_cap
;
2445 /* covers APUs as well */
2446 if (pci_is_root_bus(adev
->pdev
->bus
)) {
2447 if (adev
->pm
.pcie_gen_mask
== 0)
2448 adev
->pm
.pcie_gen_mask
= AMDGPU_DEFAULT_PCIE_GEN_MASK
;
2449 if (adev
->pm
.pcie_mlw_mask
== 0)
2450 adev
->pm
.pcie_mlw_mask
= AMDGPU_DEFAULT_PCIE_MLW_MASK
;
2454 if (adev
->pm
.pcie_gen_mask
== 0) {
2455 ret
= drm_pcie_get_speed_cap_mask(adev
->ddev
, &mask
);
2457 adev
->pm
.pcie_gen_mask
= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1
|
2458 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2
|
2459 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3
);
2461 if (mask
& DRM_PCIE_SPEED_25
)
2462 adev
->pm
.pcie_gen_mask
|= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1
;
2463 if (mask
& DRM_PCIE_SPEED_50
)
2464 adev
->pm
.pcie_gen_mask
|= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2
;
2465 if (mask
& DRM_PCIE_SPEED_80
)
2466 adev
->pm
.pcie_gen_mask
|= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3
;
2468 adev
->pm
.pcie_gen_mask
= AMDGPU_DEFAULT_PCIE_GEN_MASK
;
2471 if (adev
->pm
.pcie_mlw_mask
== 0) {
2472 ret
= drm_pcie_get_max_link_width(adev
->ddev
, &mask
);
2476 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32
|
2477 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16
|
2478 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12
|
2479 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8
|
2480 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4
|
2481 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
2482 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
2485 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16
|
2486 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12
|
2487 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8
|
2488 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4
|
2489 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
2490 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
2493 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12
|
2494 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8
|
2495 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4
|
2496 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
2497 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
2500 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8
|
2501 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4
|
2502 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
2503 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
2506 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4
|
2507 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
2508 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
2511 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
2512 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
2515 adev
->pm
.pcie_mlw_mask
= CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
;
2521 adev
->pm
.pcie_mlw_mask
= AMDGPU_DEFAULT_PCIE_MLW_MASK
;
2529 int amdgpu_debugfs_add_files(struct amdgpu_device
*adev
,
2530 const struct drm_info_list
*files
,
2535 for (i
= 0; i
< adev
->debugfs_count
; i
++) {
2536 if (adev
->debugfs
[i
].files
== files
) {
2537 /* Already registered */
2542 i
= adev
->debugfs_count
+ 1;
2543 if (i
> AMDGPU_DEBUGFS_MAX_COMPONENTS
) {
2544 DRM_ERROR("Reached maximum number of debugfs components.\n");
2545 DRM_ERROR("Report so we increase "
2546 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
2549 adev
->debugfs
[adev
->debugfs_count
].files
= files
;
2550 adev
->debugfs
[adev
->debugfs_count
].num_files
= nfiles
;
2551 adev
->debugfs_count
= i
;
2552 #if defined(CONFIG_DEBUG_FS)
2553 drm_debugfs_create_files(files
, nfiles
,
2554 adev
->ddev
->primary
->debugfs_root
,
2555 adev
->ddev
->primary
);
2560 #if defined(CONFIG_DEBUG_FS)
2562 static ssize_t
amdgpu_debugfs_regs_read(struct file
*f
, char __user
*buf
,
2563 size_t size
, loff_t
*pos
)
2565 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
2568 bool pm_pg_lock
, use_bank
;
2569 unsigned instance_bank
, sh_bank
, se_bank
;
2571 if (size
& 0x3 || *pos
& 0x3)
2574 /* are we reading registers for which a PG lock is necessary? */
2575 pm_pg_lock
= (*pos
>> 23) & 1;
2577 if (*pos
& (1ULL << 62)) {
2578 se_bank
= (*pos
>> 24) & 0x3FF;
2579 sh_bank
= (*pos
>> 34) & 0x3FF;
2580 instance_bank
= (*pos
>> 44) & 0x3FF;
2582 if (se_bank
== 0x3FF)
2583 se_bank
= 0xFFFFFFFF;
2584 if (sh_bank
== 0x3FF)
2585 sh_bank
= 0xFFFFFFFF;
2586 if (instance_bank
== 0x3FF)
2587 instance_bank
= 0xFFFFFFFF;
2593 *pos
&= (1UL << 22) - 1;
2596 if ((sh_bank
!= 0xFFFFFFFF && sh_bank
>= adev
->gfx
.config
.max_sh_per_se
) ||
2597 (se_bank
!= 0xFFFFFFFF && se_bank
>= adev
->gfx
.config
.max_shader_engines
))
2599 mutex_lock(&adev
->grbm_idx_mutex
);
2600 amdgpu_gfx_select_se_sh(adev
, se_bank
,
2601 sh_bank
, instance_bank
);
2605 mutex_lock(&adev
->pm
.mutex
);
2610 if (*pos
> adev
->rmmio_size
)
2613 value
= RREG32(*pos
>> 2);
2614 r
= put_user(value
, (uint32_t *)buf
);
2628 amdgpu_gfx_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
2629 mutex_unlock(&adev
->grbm_idx_mutex
);
2633 mutex_unlock(&adev
->pm
.mutex
);
2638 static ssize_t
amdgpu_debugfs_regs_write(struct file
*f
, const char __user
*buf
,
2639 size_t size
, loff_t
*pos
)
2641 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
2644 bool pm_pg_lock
, use_bank
;
2645 unsigned instance_bank
, sh_bank
, se_bank
;
2647 if (size
& 0x3 || *pos
& 0x3)
2650 /* are we reading registers for which a PG lock is necessary? */
2651 pm_pg_lock
= (*pos
>> 23) & 1;
2653 if (*pos
& (1ULL << 62)) {
2654 se_bank
= (*pos
>> 24) & 0x3FF;
2655 sh_bank
= (*pos
>> 34) & 0x3FF;
2656 instance_bank
= (*pos
>> 44) & 0x3FF;
2658 if (se_bank
== 0x3FF)
2659 se_bank
= 0xFFFFFFFF;
2660 if (sh_bank
== 0x3FF)
2661 sh_bank
= 0xFFFFFFFF;
2662 if (instance_bank
== 0x3FF)
2663 instance_bank
= 0xFFFFFFFF;
2669 *pos
&= (1UL << 22) - 1;
2672 if ((sh_bank
!= 0xFFFFFFFF && sh_bank
>= adev
->gfx
.config
.max_sh_per_se
) ||
2673 (se_bank
!= 0xFFFFFFFF && se_bank
>= adev
->gfx
.config
.max_shader_engines
))
2675 mutex_lock(&adev
->grbm_idx_mutex
);
2676 amdgpu_gfx_select_se_sh(adev
, se_bank
,
2677 sh_bank
, instance_bank
);
2681 mutex_lock(&adev
->pm
.mutex
);
2686 if (*pos
> adev
->rmmio_size
)
2689 r
= get_user(value
, (uint32_t *)buf
);
2693 WREG32(*pos
>> 2, value
);
2702 amdgpu_gfx_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
2703 mutex_unlock(&adev
->grbm_idx_mutex
);
2707 mutex_unlock(&adev
->pm
.mutex
);
2712 static ssize_t
amdgpu_debugfs_regs_pcie_read(struct file
*f
, char __user
*buf
,
2713 size_t size
, loff_t
*pos
)
2715 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
2719 if (size
& 0x3 || *pos
& 0x3)
2725 value
= RREG32_PCIE(*pos
>> 2);
2726 r
= put_user(value
, (uint32_t *)buf
);
2739 static ssize_t
amdgpu_debugfs_regs_pcie_write(struct file
*f
, const char __user
*buf
,
2740 size_t size
, loff_t
*pos
)
2742 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
2746 if (size
& 0x3 || *pos
& 0x3)
2752 r
= get_user(value
, (uint32_t *)buf
);
2756 WREG32_PCIE(*pos
>> 2, value
);
2767 static ssize_t
amdgpu_debugfs_regs_didt_read(struct file
*f
, char __user
*buf
,
2768 size_t size
, loff_t
*pos
)
2770 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
2774 if (size
& 0x3 || *pos
& 0x3)
2780 value
= RREG32_DIDT(*pos
>> 2);
2781 r
= put_user(value
, (uint32_t *)buf
);
2794 static ssize_t
amdgpu_debugfs_regs_didt_write(struct file
*f
, const char __user
*buf
,
2795 size_t size
, loff_t
*pos
)
2797 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
2801 if (size
& 0x3 || *pos
& 0x3)
2807 r
= get_user(value
, (uint32_t *)buf
);
2811 WREG32_DIDT(*pos
>> 2, value
);
2822 static ssize_t
amdgpu_debugfs_regs_smc_read(struct file
*f
, char __user
*buf
,
2823 size_t size
, loff_t
*pos
)
2825 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
2829 if (size
& 0x3 || *pos
& 0x3)
2835 value
= RREG32_SMC(*pos
);
2836 r
= put_user(value
, (uint32_t *)buf
);
2849 static ssize_t
amdgpu_debugfs_regs_smc_write(struct file
*f
, const char __user
*buf
,
2850 size_t size
, loff_t
*pos
)
2852 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
2856 if (size
& 0x3 || *pos
& 0x3)
2862 r
= get_user(value
, (uint32_t *)buf
);
2866 WREG32_SMC(*pos
, value
);
2877 static ssize_t
amdgpu_debugfs_gca_config_read(struct file
*f
, char __user
*buf
,
2878 size_t size
, loff_t
*pos
)
2880 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
2883 uint32_t *config
, no_regs
= 0;
2885 if (size
& 0x3 || *pos
& 0x3)
2888 config
= kmalloc_array(256, sizeof(*config
), GFP_KERNEL
);
2892 /* version, increment each time something is added */
2893 config
[no_regs
++] = 3;
2894 config
[no_regs
++] = adev
->gfx
.config
.max_shader_engines
;
2895 config
[no_regs
++] = adev
->gfx
.config
.max_tile_pipes
;
2896 config
[no_regs
++] = adev
->gfx
.config
.max_cu_per_sh
;
2897 config
[no_regs
++] = adev
->gfx
.config
.max_sh_per_se
;
2898 config
[no_regs
++] = adev
->gfx
.config
.max_backends_per_se
;
2899 config
[no_regs
++] = adev
->gfx
.config
.max_texture_channel_caches
;
2900 config
[no_regs
++] = adev
->gfx
.config
.max_gprs
;
2901 config
[no_regs
++] = adev
->gfx
.config
.max_gs_threads
;
2902 config
[no_regs
++] = adev
->gfx
.config
.max_hw_contexts
;
2903 config
[no_regs
++] = adev
->gfx
.config
.sc_prim_fifo_size_frontend
;
2904 config
[no_regs
++] = adev
->gfx
.config
.sc_prim_fifo_size_backend
;
2905 config
[no_regs
++] = adev
->gfx
.config
.sc_hiz_tile_fifo_size
;
2906 config
[no_regs
++] = adev
->gfx
.config
.sc_earlyz_tile_fifo_size
;
2907 config
[no_regs
++] = adev
->gfx
.config
.num_tile_pipes
;
2908 config
[no_regs
++] = adev
->gfx
.config
.backend_enable_mask
;
2909 config
[no_regs
++] = adev
->gfx
.config
.mem_max_burst_length_bytes
;
2910 config
[no_regs
++] = adev
->gfx
.config
.mem_row_size_in_kb
;
2911 config
[no_regs
++] = adev
->gfx
.config
.shader_engine_tile_size
;
2912 config
[no_regs
++] = adev
->gfx
.config
.num_gpus
;
2913 config
[no_regs
++] = adev
->gfx
.config
.multi_gpu_tile_size
;
2914 config
[no_regs
++] = adev
->gfx
.config
.mc_arb_ramcfg
;
2915 config
[no_regs
++] = adev
->gfx
.config
.gb_addr_config
;
2916 config
[no_regs
++] = adev
->gfx
.config
.num_rbs
;
2919 config
[no_regs
++] = adev
->rev_id
;
2920 config
[no_regs
++] = adev
->pg_flags
;
2921 config
[no_regs
++] = adev
->cg_flags
;
2924 config
[no_regs
++] = adev
->family
;
2925 config
[no_regs
++] = adev
->external_rev_id
;
2928 config
[no_regs
++] = adev
->pdev
->device
;
2929 config
[no_regs
++] = adev
->pdev
->revision
;
2930 config
[no_regs
++] = adev
->pdev
->subsystem_device
;
2931 config
[no_regs
++] = adev
->pdev
->subsystem_vendor
;
2933 while (size
&& (*pos
< no_regs
* 4)) {
2936 value
= config
[*pos
>> 2];
2937 r
= put_user(value
, (uint32_t *)buf
);
2953 static ssize_t
amdgpu_debugfs_sensor_read(struct file
*f
, char __user
*buf
,
2954 size_t size
, loff_t
*pos
)
2956 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
2960 if (size
!= 4 || *pos
& 0x3)
2963 /* convert offset to sensor number */
2966 if (adev
->powerplay
.pp_funcs
&& adev
->powerplay
.pp_funcs
->read_sensor
)
2967 r
= adev
->powerplay
.pp_funcs
->read_sensor(adev
->powerplay
.pp_handle
, idx
, &value
);
2972 r
= put_user(value
, (int32_t *)buf
);
2977 static ssize_t
amdgpu_debugfs_wave_read(struct file
*f
, char __user
*buf
,
2978 size_t size
, loff_t
*pos
)
2980 struct amdgpu_device
*adev
= f
->f_inode
->i_private
;
2983 uint32_t offset
, se
, sh
, cu
, wave
, simd
, data
[32];
2985 if (size
& 3 || *pos
& 3)
2989 offset
= (*pos
& 0x7F);
2990 se
= ((*pos
>> 7) & 0xFF);
2991 sh
= ((*pos
>> 15) & 0xFF);
2992 cu
= ((*pos
>> 23) & 0xFF);
2993 wave
= ((*pos
>> 31) & 0xFF);
2994 simd
= ((*pos
>> 37) & 0xFF);
2996 /* switch to the specific se/sh/cu */
2997 mutex_lock(&adev
->grbm_idx_mutex
);
2998 amdgpu_gfx_select_se_sh(adev
, se
, sh
, cu
);
3001 if (adev
->gfx
.funcs
->read_wave_data
)
3002 adev
->gfx
.funcs
->read_wave_data(adev
, simd
, wave
, data
, &x
);
3004 amdgpu_gfx_select_se_sh(adev
, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3005 mutex_unlock(&adev
->grbm_idx_mutex
);
3010 while (size
&& (offset
< x
* 4)) {
3013 value
= data
[offset
>> 2];
3014 r
= put_user(value
, (uint32_t *)buf
);
3027 static ssize_t
amdgpu_debugfs_gpr_read(struct file
*f
, char __user
*buf
,
3028 size_t size
, loff_t
*pos
)
3030 struct amdgpu_device
*adev
= f
->f_inode
->i_private
;
3033 uint32_t offset
, se
, sh
, cu
, wave
, simd
, thread
, bank
, *data
;
3035 if (size
& 3 || *pos
& 3)
3039 offset
= (*pos
& 0xFFF); /* in dwords */
3040 se
= ((*pos
>> 12) & 0xFF);
3041 sh
= ((*pos
>> 20) & 0xFF);
3042 cu
= ((*pos
>> 28) & 0xFF);
3043 wave
= ((*pos
>> 36) & 0xFF);
3044 simd
= ((*pos
>> 44) & 0xFF);
3045 thread
= ((*pos
>> 52) & 0xFF);
3046 bank
= ((*pos
>> 60) & 1);
3048 data
= kmalloc_array(1024, sizeof(*data
), GFP_KERNEL
);
3052 /* switch to the specific se/sh/cu */
3053 mutex_lock(&adev
->grbm_idx_mutex
);
3054 amdgpu_gfx_select_se_sh(adev
, se
, sh
, cu
);
3057 if (adev
->gfx
.funcs
->read_wave_vgprs
)
3058 adev
->gfx
.funcs
->read_wave_vgprs(adev
, simd
, wave
, thread
, offset
, size
>>2, data
);
3060 if (adev
->gfx
.funcs
->read_wave_sgprs
)
3061 adev
->gfx
.funcs
->read_wave_sgprs(adev
, simd
, wave
, offset
, size
>>2, data
);
3064 amdgpu_gfx_select_se_sh(adev
, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3065 mutex_unlock(&adev
->grbm_idx_mutex
);
3070 value
= data
[offset
++];
3071 r
= put_user(value
, (uint32_t *)buf
);
3087 static const struct file_operations amdgpu_debugfs_regs_fops
= {
3088 .owner
= THIS_MODULE
,
3089 .read
= amdgpu_debugfs_regs_read
,
3090 .write
= amdgpu_debugfs_regs_write
,
3091 .llseek
= default_llseek
3093 static const struct file_operations amdgpu_debugfs_regs_didt_fops
= {
3094 .owner
= THIS_MODULE
,
3095 .read
= amdgpu_debugfs_regs_didt_read
,
3096 .write
= amdgpu_debugfs_regs_didt_write
,
3097 .llseek
= default_llseek
3099 static const struct file_operations amdgpu_debugfs_regs_pcie_fops
= {
3100 .owner
= THIS_MODULE
,
3101 .read
= amdgpu_debugfs_regs_pcie_read
,
3102 .write
= amdgpu_debugfs_regs_pcie_write
,
3103 .llseek
= default_llseek
3105 static const struct file_operations amdgpu_debugfs_regs_smc_fops
= {
3106 .owner
= THIS_MODULE
,
3107 .read
= amdgpu_debugfs_regs_smc_read
,
3108 .write
= amdgpu_debugfs_regs_smc_write
,
3109 .llseek
= default_llseek
3112 static const struct file_operations amdgpu_debugfs_gca_config_fops
= {
3113 .owner
= THIS_MODULE
,
3114 .read
= amdgpu_debugfs_gca_config_read
,
3115 .llseek
= default_llseek
3118 static const struct file_operations amdgpu_debugfs_sensors_fops
= {
3119 .owner
= THIS_MODULE
,
3120 .read
= amdgpu_debugfs_sensor_read
,
3121 .llseek
= default_llseek
3124 static const struct file_operations amdgpu_debugfs_wave_fops
= {
3125 .owner
= THIS_MODULE
,
3126 .read
= amdgpu_debugfs_wave_read
,
3127 .llseek
= default_llseek
3129 static const struct file_operations amdgpu_debugfs_gpr_fops
= {
3130 .owner
= THIS_MODULE
,
3131 .read
= amdgpu_debugfs_gpr_read
,
3132 .llseek
= default_llseek
3135 static const struct file_operations
*debugfs_regs
[] = {
3136 &amdgpu_debugfs_regs_fops
,
3137 &amdgpu_debugfs_regs_didt_fops
,
3138 &amdgpu_debugfs_regs_pcie_fops
,
3139 &amdgpu_debugfs_regs_smc_fops
,
3140 &amdgpu_debugfs_gca_config_fops
,
3141 &amdgpu_debugfs_sensors_fops
,
3142 &amdgpu_debugfs_wave_fops
,
3143 &amdgpu_debugfs_gpr_fops
,
3146 static const char *debugfs_regs_names
[] = {
3151 "amdgpu_gca_config",
3157 static int amdgpu_debugfs_regs_init(struct amdgpu_device
*adev
)
3159 struct drm_minor
*minor
= adev
->ddev
->primary
;
3160 struct dentry
*ent
, *root
= minor
->debugfs_root
;
3163 for (i
= 0; i
< ARRAY_SIZE(debugfs_regs
); i
++) {
3164 ent
= debugfs_create_file(debugfs_regs_names
[i
],
3165 S_IFREG
| S_IRUGO
, root
,
3166 adev
, debugfs_regs
[i
]);
3168 for (j
= 0; j
< i
; j
++) {
3169 debugfs_remove(adev
->debugfs_regs
[i
]);
3170 adev
->debugfs_regs
[i
] = NULL
;
3172 return PTR_ERR(ent
);
3176 i_size_write(ent
->d_inode
, adev
->rmmio_size
);
3177 adev
->debugfs_regs
[i
] = ent
;
3183 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device
*adev
)
3187 for (i
= 0; i
< ARRAY_SIZE(debugfs_regs
); i
++) {
3188 if (adev
->debugfs_regs
[i
]) {
3189 debugfs_remove(adev
->debugfs_regs
[i
]);
3190 adev
->debugfs_regs
[i
] = NULL
;
3195 int amdgpu_debugfs_init(struct drm_minor
*minor
)
3200 static int amdgpu_debugfs_regs_init(struct amdgpu_device
*adev
)
3204 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device
*adev
) { }