2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
29 #include <linux/slab.h>
30 #include <linux/debugfs.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/amdgpu_drm.h>
34 #include <linux/vgaarb.h>
35 #include <linux/vga_switcheroo.h>
36 #include <linux/efi.h>
38 #include "amdgpu_i2c.h"
40 #include "amdgpu_atombios.h"
41 #ifdef CONFIG_DRM_AMDGPU_CIK
45 #include "bif/bif_4_1_d.h"
47 static int amdgpu_debugfs_regs_init(struct amdgpu_device
*adev
);
48 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device
*adev
);
50 static const char *amdgpu_asic_name
[] = {
62 bool amdgpu_device_is_px(struct drm_device
*dev
)
64 struct amdgpu_device
*adev
= dev
->dev_private
;
66 if (adev
->flags
& AMDGPU_IS_PX
)
72 * MMIO register access helper functions.
74 uint32_t amdgpu_mm_rreg(struct amdgpu_device
*adev
, uint32_t reg
,
77 if ((reg
* 4) < adev
->rmmio_size
&& !always_indirect
)
78 return readl(((void __iomem
*)adev
->rmmio
) + (reg
* 4));
83 spin_lock_irqsave(&adev
->mmio_idx_lock
, flags
);
84 writel((reg
* 4), ((void __iomem
*)adev
->rmmio
) + (mmMM_INDEX
* 4));
85 ret
= readl(((void __iomem
*)adev
->rmmio
) + (mmMM_DATA
* 4));
86 spin_unlock_irqrestore(&adev
->mmio_idx_lock
, flags
);
92 void amdgpu_mm_wreg(struct amdgpu_device
*adev
, uint32_t reg
, uint32_t v
,
95 if ((reg
* 4) < adev
->rmmio_size
&& !always_indirect
)
96 writel(v
, ((void __iomem
*)adev
->rmmio
) + (reg
* 4));
100 spin_lock_irqsave(&adev
->mmio_idx_lock
, flags
);
101 writel((reg
* 4), ((void __iomem
*)adev
->rmmio
) + (mmMM_INDEX
* 4));
102 writel(v
, ((void __iomem
*)adev
->rmmio
) + (mmMM_DATA
* 4));
103 spin_unlock_irqrestore(&adev
->mmio_idx_lock
, flags
);
107 u32
amdgpu_io_rreg(struct amdgpu_device
*adev
, u32 reg
)
109 if ((reg
* 4) < adev
->rio_mem_size
)
110 return ioread32(adev
->rio_mem
+ (reg
* 4));
112 iowrite32((reg
* 4), adev
->rio_mem
+ (mmMM_INDEX
* 4));
113 return ioread32(adev
->rio_mem
+ (mmMM_DATA
* 4));
117 void amdgpu_io_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
120 if ((reg
* 4) < adev
->rio_mem_size
)
121 iowrite32(v
, adev
->rio_mem
+ (reg
* 4));
123 iowrite32((reg
* 4), adev
->rio_mem
+ (mmMM_INDEX
* 4));
124 iowrite32(v
, adev
->rio_mem
+ (mmMM_DATA
* 4));
129 * amdgpu_mm_rdoorbell - read a doorbell dword
131 * @adev: amdgpu_device pointer
132 * @index: doorbell index
134 * Returns the value in the doorbell aperture at the
135 * requested doorbell index (CIK).
137 u32
amdgpu_mm_rdoorbell(struct amdgpu_device
*adev
, u32 index
)
139 if (index
< adev
->doorbell
.num_doorbells
) {
140 return readl(adev
->doorbell
.ptr
+ index
);
142 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index
);
148 * amdgpu_mm_wdoorbell - write a doorbell dword
150 * @adev: amdgpu_device pointer
151 * @index: doorbell index
154 * Writes @v to the doorbell aperture at the
155 * requested doorbell index (CIK).
157 void amdgpu_mm_wdoorbell(struct amdgpu_device
*adev
, u32 index
, u32 v
)
159 if (index
< adev
->doorbell
.num_doorbells
) {
160 writel(v
, adev
->doorbell
.ptr
+ index
);
162 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index
);
167 * amdgpu_invalid_rreg - dummy reg read function
169 * @adev: amdgpu device pointer
170 * @reg: offset of register
172 * Dummy register read function. Used for register blocks
173 * that certain asics don't have (all asics).
174 * Returns the value in the register.
176 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device
*adev
, uint32_t reg
)
178 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg
);
184 * amdgpu_invalid_wreg - dummy reg write function
186 * @adev: amdgpu device pointer
187 * @reg: offset of register
188 * @v: value to write to the register
190 * Dummy register read function. Used for register blocks
191 * that certain asics don't have (all asics).
193 static void amdgpu_invalid_wreg(struct amdgpu_device
*adev
, uint32_t reg
, uint32_t v
)
195 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
201 * amdgpu_block_invalid_rreg - dummy reg read function
203 * @adev: amdgpu device pointer
204 * @block: offset of instance
205 * @reg: offset of register
207 * Dummy register read function. Used for register blocks
208 * that certain asics don't have (all asics).
209 * Returns the value in the register.
211 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device
*adev
,
212 uint32_t block
, uint32_t reg
)
214 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
221 * amdgpu_block_invalid_wreg - dummy reg write function
223 * @adev: amdgpu device pointer
224 * @block: offset of instance
225 * @reg: offset of register
226 * @v: value to write to the register
228 * Dummy register read function. Used for register blocks
229 * that certain asics don't have (all asics).
231 static void amdgpu_block_invalid_wreg(struct amdgpu_device
*adev
,
233 uint32_t reg
, uint32_t v
)
235 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
240 static int amdgpu_vram_scratch_init(struct amdgpu_device
*adev
)
244 if (adev
->vram_scratch
.robj
== NULL
) {
245 r
= amdgpu_bo_create(adev
, AMDGPU_GPU_PAGE_SIZE
,
246 PAGE_SIZE
, true, AMDGPU_GEM_DOMAIN_VRAM
, 0,
247 NULL
, &adev
->vram_scratch
.robj
);
253 r
= amdgpu_bo_reserve(adev
->vram_scratch
.robj
, false);
254 if (unlikely(r
!= 0))
256 r
= amdgpu_bo_pin(adev
->vram_scratch
.robj
,
257 AMDGPU_GEM_DOMAIN_VRAM
, &adev
->vram_scratch
.gpu_addr
);
259 amdgpu_bo_unreserve(adev
->vram_scratch
.robj
);
262 r
= amdgpu_bo_kmap(adev
->vram_scratch
.robj
,
263 (void **)&adev
->vram_scratch
.ptr
);
265 amdgpu_bo_unpin(adev
->vram_scratch
.robj
);
266 amdgpu_bo_unreserve(adev
->vram_scratch
.robj
);
271 static void amdgpu_vram_scratch_fini(struct amdgpu_device
*adev
)
275 if (adev
->vram_scratch
.robj
== NULL
) {
278 r
= amdgpu_bo_reserve(adev
->vram_scratch
.robj
, false);
279 if (likely(r
== 0)) {
280 amdgpu_bo_kunmap(adev
->vram_scratch
.robj
);
281 amdgpu_bo_unpin(adev
->vram_scratch
.robj
);
282 amdgpu_bo_unreserve(adev
->vram_scratch
.robj
);
284 amdgpu_bo_unref(&adev
->vram_scratch
.robj
);
288 * amdgpu_program_register_sequence - program an array of registers.
290 * @adev: amdgpu_device pointer
291 * @registers: pointer to the register array
292 * @array_size: size of the register array
294 * Programs an array or registers with and and or masks.
295 * This is a helper for setting golden registers.
297 void amdgpu_program_register_sequence(struct amdgpu_device
*adev
,
298 const u32
*registers
,
299 const u32 array_size
)
301 u32 tmp
, reg
, and_mask
, or_mask
;
307 for (i
= 0; i
< array_size
; i
+=3) {
308 reg
= registers
[i
+ 0];
309 and_mask
= registers
[i
+ 1];
310 or_mask
= registers
[i
+ 2];
312 if (and_mask
== 0xffffffff) {
323 void amdgpu_pci_config_reset(struct amdgpu_device
*adev
)
325 pci_write_config_dword(adev
->pdev
, 0x7c, AMDGPU_ASIC_RESET_DATA
);
329 * GPU doorbell aperture helpers function.
332 * amdgpu_doorbell_init - Init doorbell driver information.
334 * @adev: amdgpu_device pointer
336 * Init doorbell driver information (CIK)
337 * Returns 0 on success, error on failure.
339 static int amdgpu_doorbell_init(struct amdgpu_device
*adev
)
341 /* doorbell bar mapping */
342 adev
->doorbell
.base
= pci_resource_start(adev
->pdev
, 2);
343 adev
->doorbell
.size
= pci_resource_len(adev
->pdev
, 2);
345 adev
->doorbell
.num_doorbells
= min_t(u32
, adev
->doorbell
.size
/ sizeof(u32
),
346 AMDGPU_DOORBELL_MAX_ASSIGNMENT
+1);
347 if (adev
->doorbell
.num_doorbells
== 0)
350 adev
->doorbell
.ptr
= ioremap(adev
->doorbell
.base
, adev
->doorbell
.num_doorbells
* sizeof(u32
));
351 if (adev
->doorbell
.ptr
== NULL
) {
354 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev
->doorbell
.base
);
355 DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev
->doorbell
.size
);
361 * amdgpu_doorbell_fini - Tear down doorbell driver information.
363 * @adev: amdgpu_device pointer
365 * Tear down doorbell driver information (CIK)
367 static void amdgpu_doorbell_fini(struct amdgpu_device
*adev
)
369 iounmap(adev
->doorbell
.ptr
);
370 adev
->doorbell
.ptr
= NULL
;
374 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
377 * @adev: amdgpu_device pointer
378 * @aperture_base: output returning doorbell aperture base physical address
379 * @aperture_size: output returning doorbell aperture size in bytes
380 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
382 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
383 * takes doorbells required for its own rings and reports the setup to amdkfd.
384 * amdgpu reserved doorbells are at the start of the doorbell aperture.
386 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device
*adev
,
387 phys_addr_t
*aperture_base
,
388 size_t *aperture_size
,
389 size_t *start_offset
)
392 * The first num_doorbells are used by amdgpu.
393 * amdkfd takes whatever's left in the aperture.
395 if (adev
->doorbell
.size
> adev
->doorbell
.num_doorbells
* sizeof(u32
)) {
396 *aperture_base
= adev
->doorbell
.base
;
397 *aperture_size
= adev
->doorbell
.size
;
398 *start_offset
= adev
->doorbell
.num_doorbells
* sizeof(u32
);
408 * Writeback is the the method by which the the GPU updates special pages
409 * in memory with the status of certain GPU events (fences, ring pointers,
414 * amdgpu_wb_fini - Disable Writeback and free memory
416 * @adev: amdgpu_device pointer
418 * Disables Writeback and frees the Writeback memory (all asics).
419 * Used at driver shutdown.
421 static void amdgpu_wb_fini(struct amdgpu_device
*adev
)
423 if (adev
->wb
.wb_obj
) {
424 if (!amdgpu_bo_reserve(adev
->wb
.wb_obj
, false)) {
425 amdgpu_bo_kunmap(adev
->wb
.wb_obj
);
426 amdgpu_bo_unpin(adev
->wb
.wb_obj
);
427 amdgpu_bo_unreserve(adev
->wb
.wb_obj
);
429 amdgpu_bo_unref(&adev
->wb
.wb_obj
);
431 adev
->wb
.wb_obj
= NULL
;
436 * amdgpu_wb_init- Init Writeback driver info and allocate memory
438 * @adev: amdgpu_device pointer
440 * Disables Writeback and frees the Writeback memory (all asics).
441 * Used at driver startup.
442 * Returns 0 on success or an -error on failure.
444 static int amdgpu_wb_init(struct amdgpu_device
*adev
)
448 if (adev
->wb
.wb_obj
== NULL
) {
449 r
= amdgpu_bo_create(adev
, AMDGPU_MAX_WB
* 4, PAGE_SIZE
, true,
450 AMDGPU_GEM_DOMAIN_GTT
, 0, NULL
, &adev
->wb
.wb_obj
);
452 dev_warn(adev
->dev
, "(%d) create WB bo failed\n", r
);
455 r
= amdgpu_bo_reserve(adev
->wb
.wb_obj
, false);
456 if (unlikely(r
!= 0)) {
457 amdgpu_wb_fini(adev
);
460 r
= amdgpu_bo_pin(adev
->wb
.wb_obj
, AMDGPU_GEM_DOMAIN_GTT
,
463 amdgpu_bo_unreserve(adev
->wb
.wb_obj
);
464 dev_warn(adev
->dev
, "(%d) pin WB bo failed\n", r
);
465 amdgpu_wb_fini(adev
);
468 r
= amdgpu_bo_kmap(adev
->wb
.wb_obj
, (void **)&adev
->wb
.wb
);
469 amdgpu_bo_unreserve(adev
->wb
.wb_obj
);
471 dev_warn(adev
->dev
, "(%d) map WB bo failed\n", r
);
472 amdgpu_wb_fini(adev
);
476 adev
->wb
.num_wb
= AMDGPU_MAX_WB
;
477 memset(&adev
->wb
.used
, 0, sizeof(adev
->wb
.used
));
479 /* clear wb memory */
480 memset((char *)adev
->wb
.wb
, 0, AMDGPU_GPU_PAGE_SIZE
);
487 * amdgpu_wb_get - Allocate a wb entry
489 * @adev: amdgpu_device pointer
492 * Allocate a wb slot for use by the driver (all asics).
493 * Returns 0 on success or -EINVAL on failure.
495 int amdgpu_wb_get(struct amdgpu_device
*adev
, u32
*wb
)
497 unsigned long offset
= find_first_zero_bit(adev
->wb
.used
, adev
->wb
.num_wb
);
498 if (offset
< adev
->wb
.num_wb
) {
499 __set_bit(offset
, adev
->wb
.used
);
508 * amdgpu_wb_free - Free a wb entry
510 * @adev: amdgpu_device pointer
513 * Free a wb slot allocated for use by the driver (all asics)
515 void amdgpu_wb_free(struct amdgpu_device
*adev
, u32 wb
)
517 if (wb
< adev
->wb
.num_wb
)
518 __clear_bit(wb
, adev
->wb
.used
);
522 * amdgpu_vram_location - try to find VRAM location
523 * @adev: amdgpu device structure holding all necessary informations
524 * @mc: memory controller structure holding memory informations
525 * @base: base address at which to put VRAM
527 * Function will place try to place VRAM at base address provided
528 * as parameter (which is so far either PCI aperture address or
529 * for IGP TOM base address).
531 * If there is not enough space to fit the unvisible VRAM in the 32bits
532 * address space then we limit the VRAM size to the aperture.
534 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
535 * this shouldn't be a problem as we are using the PCI aperture as a reference.
536 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
539 * Note: we use mc_vram_size as on some board we need to program the mc to
540 * cover the whole aperture even if VRAM size is inferior to aperture size
541 * Novell bug 204882 + along with lots of ubuntu ones
543 * Note: when limiting vram it's safe to overwritte real_vram_size because
544 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
545 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
548 * Note: IGP TOM addr should be the same as the aperture addr, we don't
549 * explicitly check for that thought.
551 * FIXME: when reducing VRAM size align new size on power of 2.
553 void amdgpu_vram_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
, u64 base
)
555 uint64_t limit
= (uint64_t)amdgpu_vram_limit
<< 20;
557 mc
->vram_start
= base
;
558 if (mc
->mc_vram_size
> (adev
->mc
.mc_mask
- base
+ 1)) {
559 dev_warn(adev
->dev
, "limiting VRAM to PCI aperture size\n");
560 mc
->real_vram_size
= mc
->aper_size
;
561 mc
->mc_vram_size
= mc
->aper_size
;
563 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
564 if (limit
&& limit
< mc
->real_vram_size
)
565 mc
->real_vram_size
= limit
;
566 dev_info(adev
->dev
, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
567 mc
->mc_vram_size
>> 20, mc
->vram_start
,
568 mc
->vram_end
, mc
->real_vram_size
>> 20);
572 * amdgpu_gtt_location - try to find GTT location
573 * @adev: amdgpu device structure holding all necessary informations
574 * @mc: memory controller structure holding memory informations
576 * Function will place try to place GTT before or after VRAM.
578 * If GTT size is bigger than space left then we ajust GTT size.
579 * Thus function will never fails.
581 * FIXME: when reducing GTT size align new size on power of 2.
583 void amdgpu_gtt_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
)
585 u64 size_af
, size_bf
;
587 size_af
= ((adev
->mc
.mc_mask
- mc
->vram_end
) + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
588 size_bf
= mc
->vram_start
& ~mc
->gtt_base_align
;
589 if (size_bf
> size_af
) {
590 if (mc
->gtt_size
> size_bf
) {
591 dev_warn(adev
->dev
, "limiting GTT\n");
592 mc
->gtt_size
= size_bf
;
594 mc
->gtt_start
= (mc
->vram_start
& ~mc
->gtt_base_align
) - mc
->gtt_size
;
596 if (mc
->gtt_size
> size_af
) {
597 dev_warn(adev
->dev
, "limiting GTT\n");
598 mc
->gtt_size
= size_af
;
600 mc
->gtt_start
= (mc
->vram_end
+ 1 + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
602 mc
->gtt_end
= mc
->gtt_start
+ mc
->gtt_size
- 1;
603 dev_info(adev
->dev
, "GTT: %lluM 0x%016llX - 0x%016llX\n",
604 mc
->gtt_size
>> 20, mc
->gtt_start
, mc
->gtt_end
);
608 * GPU helpers function.
611 * amdgpu_card_posted - check if the hw has already been initialized
613 * @adev: amdgpu_device pointer
615 * Check if the asic has been initialized (all asics).
616 * Used at driver startup.
617 * Returns true if initialized or false if not.
619 bool amdgpu_card_posted(struct amdgpu_device
*adev
)
623 /* then check MEM_SIZE, in case the crtcs are off */
624 reg
= RREG32(mmCONFIG_MEMSIZE
);
634 * amdgpu_boot_test_post_card - check and possibly initialize the hw
636 * @adev: amdgpu_device pointer
638 * Check if the asic is initialized and if not, attempt to initialize
640 * Returns true if initialized or false if not.
642 bool amdgpu_boot_test_post_card(struct amdgpu_device
*adev
)
644 if (amdgpu_card_posted(adev
))
648 DRM_INFO("GPU not posted. posting now...\n");
649 if (adev
->is_atom_bios
)
650 amdgpu_atom_asic_init(adev
->mode_info
.atom_context
);
653 dev_err(adev
->dev
, "Card not posted and no BIOS - ignoring\n");
659 * amdgpu_dummy_page_init - init dummy page used by the driver
661 * @adev: amdgpu_device pointer
663 * Allocate the dummy page used by the driver (all asics).
664 * This dummy page is used by the driver as a filler for gart entries
665 * when pages are taken out of the GART
666 * Returns 0 on sucess, -ENOMEM on failure.
668 int amdgpu_dummy_page_init(struct amdgpu_device
*adev
)
670 if (adev
->dummy_page
.page
)
672 adev
->dummy_page
.page
= alloc_page(GFP_DMA32
| GFP_KERNEL
| __GFP_ZERO
);
673 if (adev
->dummy_page
.page
== NULL
)
675 adev
->dummy_page
.addr
= pci_map_page(adev
->pdev
, adev
->dummy_page
.page
,
676 0, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
677 if (pci_dma_mapping_error(adev
->pdev
, adev
->dummy_page
.addr
)) {
678 dev_err(&adev
->pdev
->dev
, "Failed to DMA MAP the dummy page\n");
679 __free_page(adev
->dummy_page
.page
);
680 adev
->dummy_page
.page
= NULL
;
687 * amdgpu_dummy_page_fini - free dummy page used by the driver
689 * @adev: amdgpu_device pointer
691 * Frees the dummy page used by the driver (all asics).
693 void amdgpu_dummy_page_fini(struct amdgpu_device
*adev
)
695 if (adev
->dummy_page
.page
== NULL
)
697 pci_unmap_page(adev
->pdev
, adev
->dummy_page
.addr
,
698 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
699 __free_page(adev
->dummy_page
.page
);
700 adev
->dummy_page
.page
= NULL
;
704 /* ATOM accessor methods */
706 * ATOM is an interpreted byte code stored in tables in the vbios. The
707 * driver registers callbacks to access registers and the interpreter
708 * in the driver parses the tables and executes then to program specific
709 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
710 * atombios.h, and atom.c
714 * cail_pll_read - read PLL register
716 * @info: atom card_info pointer
717 * @reg: PLL register offset
719 * Provides a PLL register accessor for the atom interpreter (r4xx+).
720 * Returns the value of the PLL register.
722 static uint32_t cail_pll_read(struct card_info
*info
, uint32_t reg
)
728 * cail_pll_write - write PLL register
730 * @info: atom card_info pointer
731 * @reg: PLL register offset
732 * @val: value to write to the pll register
734 * Provides a PLL register accessor for the atom interpreter (r4xx+).
736 static void cail_pll_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
742 * cail_mc_read - read MC (Memory Controller) register
744 * @info: atom card_info pointer
745 * @reg: MC register offset
747 * Provides an MC register accessor for the atom interpreter (r4xx+).
748 * Returns the value of the MC register.
750 static uint32_t cail_mc_read(struct card_info
*info
, uint32_t reg
)
756 * cail_mc_write - write MC (Memory Controller) register
758 * @info: atom card_info pointer
759 * @reg: MC register offset
760 * @val: value to write to the pll register
762 * Provides a MC register accessor for the atom interpreter (r4xx+).
764 static void cail_mc_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
770 * cail_reg_write - write MMIO register
772 * @info: atom card_info pointer
773 * @reg: MMIO register offset
774 * @val: value to write to the pll register
776 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
778 static void cail_reg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
780 struct amdgpu_device
*adev
= info
->dev
->dev_private
;
786 * cail_reg_read - read MMIO register
788 * @info: atom card_info pointer
789 * @reg: MMIO register offset
791 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
792 * Returns the value of the MMIO register.
794 static uint32_t cail_reg_read(struct card_info
*info
, uint32_t reg
)
796 struct amdgpu_device
*adev
= info
->dev
->dev_private
;
804 * cail_ioreg_write - write IO register
806 * @info: atom card_info pointer
807 * @reg: IO register offset
808 * @val: value to write to the pll register
810 * Provides a IO register accessor for the atom interpreter (r4xx+).
812 static void cail_ioreg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
814 struct amdgpu_device
*adev
= info
->dev
->dev_private
;
820 * cail_ioreg_read - read IO register
822 * @info: atom card_info pointer
823 * @reg: IO register offset
825 * Provides an IO register accessor for the atom interpreter (r4xx+).
826 * Returns the value of the IO register.
828 static uint32_t cail_ioreg_read(struct card_info
*info
, uint32_t reg
)
830 struct amdgpu_device
*adev
= info
->dev
->dev_private
;
838 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
840 * @adev: amdgpu_device pointer
842 * Frees the driver info and register access callbacks for the ATOM
843 * interpreter (r4xx+).
844 * Called at driver shutdown.
846 static void amdgpu_atombios_fini(struct amdgpu_device
*adev
)
848 if (adev
->mode_info
.atom_context
)
849 kfree(adev
->mode_info
.atom_context
->scratch
);
850 kfree(adev
->mode_info
.atom_context
);
851 adev
->mode_info
.atom_context
= NULL
;
852 kfree(adev
->mode_info
.atom_card_info
);
853 adev
->mode_info
.atom_card_info
= NULL
;
857 * amdgpu_atombios_init - init the driver info and callbacks for atombios
859 * @adev: amdgpu_device pointer
861 * Initializes the driver info and register access callbacks for the
862 * ATOM interpreter (r4xx+).
863 * Returns 0 on sucess, -ENOMEM on failure.
864 * Called at driver startup.
866 static int amdgpu_atombios_init(struct amdgpu_device
*adev
)
868 struct card_info
*atom_card_info
=
869 kzalloc(sizeof(struct card_info
), GFP_KERNEL
);
874 adev
->mode_info
.atom_card_info
= atom_card_info
;
875 atom_card_info
->dev
= adev
->ddev
;
876 atom_card_info
->reg_read
= cail_reg_read
;
877 atom_card_info
->reg_write
= cail_reg_write
;
878 /* needed for iio ops */
880 atom_card_info
->ioreg_read
= cail_ioreg_read
;
881 atom_card_info
->ioreg_write
= cail_ioreg_write
;
883 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
884 atom_card_info
->ioreg_read
= cail_reg_read
;
885 atom_card_info
->ioreg_write
= cail_reg_write
;
887 atom_card_info
->mc_read
= cail_mc_read
;
888 atom_card_info
->mc_write
= cail_mc_write
;
889 atom_card_info
->pll_read
= cail_pll_read
;
890 atom_card_info
->pll_write
= cail_pll_write
;
892 adev
->mode_info
.atom_context
= amdgpu_atom_parse(atom_card_info
, adev
->bios
);
893 if (!adev
->mode_info
.atom_context
) {
894 amdgpu_atombios_fini(adev
);
898 mutex_init(&adev
->mode_info
.atom_context
->mutex
);
899 amdgpu_atombios_scratch_regs_init(adev
);
900 amdgpu_atom_allocate_fb_scratch(adev
->mode_info
.atom_context
);
904 /* if we get transitioned to only one device, take VGA back */
906 * amdgpu_vga_set_decode - enable/disable vga decode
908 * @cookie: amdgpu_device pointer
909 * @state: enable/disable vga decode
911 * Enable/disable vga decode (all asics).
912 * Returns VGA resource flags.
914 static unsigned int amdgpu_vga_set_decode(void *cookie
, bool state
)
916 struct amdgpu_device
*adev
= cookie
;
917 amdgpu_asic_set_vga_state(adev
, state
);
919 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
920 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
922 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
926 * amdgpu_check_pot_argument - check that argument is a power of two
928 * @arg: value to check
930 * Validates that a certain argument is a power of two (all asics).
931 * Returns true if argument is valid.
933 static bool amdgpu_check_pot_argument(int arg
)
935 return (arg
& (arg
- 1)) == 0;
939 * amdgpu_check_arguments - validate module params
941 * @adev: amdgpu_device pointer
943 * Validates certain module parameters and updates
944 * the associated values used by the driver (all asics).
946 static void amdgpu_check_arguments(struct amdgpu_device
*adev
)
948 /* vramlimit must be a power of two */
949 if (!amdgpu_check_pot_argument(amdgpu_vram_limit
)) {
950 dev_warn(adev
->dev
, "vram limit (%d) must be a power of 2\n",
952 amdgpu_vram_limit
= 0;
955 if (amdgpu_gart_size
!= -1) {
956 /* gtt size must be power of two and greater or equal to 32M */
957 if (amdgpu_gart_size
< 32) {
958 dev_warn(adev
->dev
, "gart size (%d) too small\n",
960 amdgpu_gart_size
= -1;
961 } else if (!amdgpu_check_pot_argument(amdgpu_gart_size
)) {
962 dev_warn(adev
->dev
, "gart size (%d) must be a power of 2\n",
964 amdgpu_gart_size
= -1;
968 if (!amdgpu_check_pot_argument(amdgpu_vm_size
)) {
969 dev_warn(adev
->dev
, "VM size (%d) must be a power of 2\n",
974 if (amdgpu_vm_size
< 1) {
975 dev_warn(adev
->dev
, "VM size (%d) too small, min is 1GB\n",
981 * Max GPUVM size for Cayman, SI and CI are 40 bits.
983 if (amdgpu_vm_size
> 1024) {
984 dev_warn(adev
->dev
, "VM size (%d) too large, max is 1TB\n",
989 /* defines number of bits in page table versus page directory,
990 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
991 * page table and the remaining bits are in the page directory */
992 if (amdgpu_vm_block_size
== -1) {
994 /* Total bits covered by PD + PTs */
995 unsigned bits
= ilog2(amdgpu_vm_size
) + 18;
997 /* Make sure the PD is 4K in size up to 8GB address space.
998 Above that split equal between PD and PTs */
999 if (amdgpu_vm_size
<= 8)
1000 amdgpu_vm_block_size
= bits
- 9;
1002 amdgpu_vm_block_size
= (bits
+ 3) / 2;
1004 } else if (amdgpu_vm_block_size
< 9) {
1005 dev_warn(adev
->dev
, "VM page table size (%d) too small\n",
1006 amdgpu_vm_block_size
);
1007 amdgpu_vm_block_size
= 9;
1010 if (amdgpu_vm_block_size
> 24 ||
1011 (amdgpu_vm_size
* 1024) < (1ull << amdgpu_vm_block_size
)) {
1012 dev_warn(adev
->dev
, "VM page table size (%d) too large\n",
1013 amdgpu_vm_block_size
);
1014 amdgpu_vm_block_size
= 9;
1019 * amdgpu_switcheroo_set_state - set switcheroo state
1021 * @pdev: pci dev pointer
1022 * @state: vga switcheroo state
1024 * Callback for the switcheroo driver. Suspends or resumes the
1025 * the asics before or after it is powered up using ACPI methods.
1027 static void amdgpu_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
1029 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1031 if (amdgpu_device_is_px(dev
) && state
== VGA_SWITCHEROO_OFF
)
1034 if (state
== VGA_SWITCHEROO_ON
) {
1035 unsigned d3_delay
= dev
->pdev
->d3_delay
;
1037 printk(KERN_INFO
"amdgpu: switched on\n");
1038 /* don't suspend or resume card normally */
1039 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1041 amdgpu_resume_kms(dev
, true, true);
1043 dev
->pdev
->d3_delay
= d3_delay
;
1045 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
1046 drm_kms_helper_poll_enable(dev
);
1048 printk(KERN_INFO
"amdgpu: switched off\n");
1049 drm_kms_helper_poll_disable(dev
);
1050 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1051 amdgpu_suspend_kms(dev
, true, true);
1052 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
1057 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1059 * @pdev: pci dev pointer
1061 * Callback for the switcheroo driver. Check of the switcheroo
1062 * state can be changed.
1063 * Returns true if the state can be changed, false if not.
1065 static bool amdgpu_switcheroo_can_switch(struct pci_dev
*pdev
)
1067 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1070 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1071 * locking inversion with the driver load path. And the access here is
1072 * completely racy anyway. So don't bother with locking for now.
1074 return dev
->open_count
== 0;
1077 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops
= {
1078 .set_gpu_state
= amdgpu_switcheroo_set_state
,
1080 .can_switch
= amdgpu_switcheroo_can_switch
,
1083 int amdgpu_set_clockgating_state(struct amdgpu_device
*adev
,
1084 enum amd_ip_block_type block_type
,
1085 enum amd_clockgating_state state
)
1089 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1090 if (adev
->ip_blocks
[i
].type
== block_type
) {
1091 r
= adev
->ip_blocks
[i
].funcs
->set_clockgating_state((void *)adev
,
1100 int amdgpu_set_powergating_state(struct amdgpu_device
*adev
,
1101 enum amd_ip_block_type block_type
,
1102 enum amd_powergating_state state
)
1106 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1107 if (adev
->ip_blocks
[i
].type
== block_type
) {
1108 r
= adev
->ip_blocks
[i
].funcs
->set_powergating_state((void *)adev
,
1117 const struct amdgpu_ip_block_version
* amdgpu_get_ip_block(
1118 struct amdgpu_device
*adev
,
1119 enum amd_ip_block_type type
)
1123 for (i
= 0; i
< adev
->num_ip_blocks
; i
++)
1124 if (adev
->ip_blocks
[i
].type
== type
)
1125 return &adev
->ip_blocks
[i
];
1131 * amdgpu_ip_block_version_cmp
1133 * @adev: amdgpu_device pointer
1134 * @type: enum amd_ip_block_type
1135 * @major: major version
1136 * @minor: minor version
1138 * return 0 if equal or greater
1139 * return 1 if smaller or the ip_block doesn't exist
1141 int amdgpu_ip_block_version_cmp(struct amdgpu_device
*adev
,
1142 enum amd_ip_block_type type
,
1143 u32 major
, u32 minor
)
1145 const struct amdgpu_ip_block_version
*ip_block
;
1146 ip_block
= amdgpu_get_ip_block(adev
, type
);
1148 if (ip_block
&& ((ip_block
->major
> major
) ||
1149 ((ip_block
->major
== major
) &&
1150 (ip_block
->minor
>= minor
))))
1156 static int amdgpu_early_init(struct amdgpu_device
*adev
)
1160 switch (adev
->asic_type
) {
1164 if (adev
->asic_type
== CHIP_CARRIZO
)
1165 adev
->family
= AMDGPU_FAMILY_CZ
;
1167 adev
->family
= AMDGPU_FAMILY_VI
;
1169 r
= vi_set_ip_blocks(adev
);
1173 #ifdef CONFIG_DRM_AMDGPU_CIK
1179 if ((adev
->asic_type
== CHIP_BONAIRE
) || (adev
->asic_type
== CHIP_HAWAII
))
1180 adev
->family
= AMDGPU_FAMILY_CI
;
1182 adev
->family
= AMDGPU_FAMILY_KV
;
1184 r
= cik_set_ip_blocks(adev
);
1190 /* FIXME: not supported yet */
1196 if (adev
->ip_blocks
== NULL
) {
1197 DRM_ERROR("No IP blocks found!\n");
1201 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1202 if ((amdgpu_ip_block_mask
& (1 << i
)) == 0) {
1203 DRM_ERROR("disabled ip block: %d\n", i
);
1204 adev
->ip_block_enabled
[i
] = false;
1206 if (adev
->ip_blocks
[i
].funcs
->early_init
) {
1207 r
= adev
->ip_blocks
[i
].funcs
->early_init((void *)adev
);
1211 adev
->ip_block_enabled
[i
] = true;
1218 static int amdgpu_init(struct amdgpu_device
*adev
)
1222 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1223 if (!adev
->ip_block_enabled
[i
])
1225 r
= adev
->ip_blocks
[i
].funcs
->sw_init((void *)adev
);
1228 /* need to do gmc hw init early so we can allocate gpu mem */
1229 if (adev
->ip_blocks
[i
].type
== AMD_IP_BLOCK_TYPE_GMC
) {
1230 r
= amdgpu_vram_scratch_init(adev
);
1233 r
= adev
->ip_blocks
[i
].funcs
->hw_init((void *)adev
);
1236 r
= amdgpu_wb_init(adev
);
1242 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1243 if (!adev
->ip_block_enabled
[i
])
1245 /* gmc hw init is done early */
1246 if (adev
->ip_blocks
[i
].type
== AMD_IP_BLOCK_TYPE_GMC
)
1248 r
= adev
->ip_blocks
[i
].funcs
->hw_init((void *)adev
);
1256 static int amdgpu_late_init(struct amdgpu_device
*adev
)
1260 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1261 if (!adev
->ip_block_enabled
[i
])
1263 /* enable clockgating to save power */
1264 r
= adev
->ip_blocks
[i
].funcs
->set_clockgating_state((void *)adev
,
1268 if (adev
->ip_blocks
[i
].funcs
->late_init
) {
1269 r
= adev
->ip_blocks
[i
].funcs
->late_init((void *)adev
);
1278 static int amdgpu_fini(struct amdgpu_device
*adev
)
1282 for (i
= adev
->num_ip_blocks
- 1; i
>= 0; i
--) {
1283 if (!adev
->ip_block_enabled
[i
])
1285 if (adev
->ip_blocks
[i
].type
== AMD_IP_BLOCK_TYPE_GMC
) {
1286 amdgpu_wb_fini(adev
);
1287 amdgpu_vram_scratch_fini(adev
);
1289 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1290 r
= adev
->ip_blocks
[i
].funcs
->set_clockgating_state((void *)adev
,
1291 AMD_CG_STATE_UNGATE
);
1294 r
= adev
->ip_blocks
[i
].funcs
->hw_fini((void *)adev
);
1295 /* XXX handle errors */
1298 for (i
= adev
->num_ip_blocks
- 1; i
>= 0; i
--) {
1299 if (!adev
->ip_block_enabled
[i
])
1301 r
= adev
->ip_blocks
[i
].funcs
->sw_fini((void *)adev
);
1302 /* XXX handle errors */
1303 adev
->ip_block_enabled
[i
] = false;
1309 static int amdgpu_suspend(struct amdgpu_device
*adev
)
1313 for (i
= adev
->num_ip_blocks
- 1; i
>= 0; i
--) {
1314 if (!adev
->ip_block_enabled
[i
])
1316 /* ungate blocks so that suspend can properly shut them down */
1317 r
= adev
->ip_blocks
[i
].funcs
->set_clockgating_state((void *)adev
,
1318 AMD_CG_STATE_UNGATE
);
1319 /* XXX handle errors */
1320 r
= adev
->ip_blocks
[i
].funcs
->suspend(adev
);
1321 /* XXX handle errors */
1327 static int amdgpu_resume(struct amdgpu_device
*adev
)
1331 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1332 if (!adev
->ip_block_enabled
[i
])
1334 r
= adev
->ip_blocks
[i
].funcs
->resume(adev
);
1343 * amdgpu_device_init - initialize the driver
1345 * @adev: amdgpu_device pointer
1346 * @pdev: drm dev pointer
1347 * @pdev: pci dev pointer
1348 * @flags: driver flags
1350 * Initializes the driver info and hw (all asics).
1351 * Returns 0 for success or an error on failure.
1352 * Called at driver startup.
1354 int amdgpu_device_init(struct amdgpu_device
*adev
,
1355 struct drm_device
*ddev
,
1356 struct pci_dev
*pdev
,
1360 bool runtime
= false;
1362 adev
->shutdown
= false;
1363 adev
->dev
= &pdev
->dev
;
1366 adev
->flags
= flags
;
1367 adev
->asic_type
= flags
& AMDGPU_ASIC_MASK
;
1368 adev
->is_atom_bios
= false;
1369 adev
->usec_timeout
= AMDGPU_MAX_USEC_TIMEOUT
;
1370 adev
->mc
.gtt_size
= 512 * 1024 * 1024;
1371 adev
->accel_working
= false;
1372 adev
->num_rings
= 0;
1373 adev
->mman
.buffer_funcs
= NULL
;
1374 adev
->mman
.buffer_funcs_ring
= NULL
;
1375 adev
->vm_manager
.vm_pte_funcs
= NULL
;
1376 adev
->vm_manager
.vm_pte_funcs_ring
= NULL
;
1377 adev
->gart
.gart_funcs
= NULL
;
1378 adev
->fence_context
= fence_context_alloc(AMDGPU_MAX_RINGS
);
1380 adev
->smc_rreg
= &amdgpu_invalid_rreg
;
1381 adev
->smc_wreg
= &amdgpu_invalid_wreg
;
1382 adev
->pcie_rreg
= &amdgpu_invalid_rreg
;
1383 adev
->pcie_wreg
= &amdgpu_invalid_wreg
;
1384 adev
->uvd_ctx_rreg
= &amdgpu_invalid_rreg
;
1385 adev
->uvd_ctx_wreg
= &amdgpu_invalid_wreg
;
1386 adev
->didt_rreg
= &amdgpu_invalid_rreg
;
1387 adev
->didt_wreg
= &amdgpu_invalid_wreg
;
1388 adev
->audio_endpt_rreg
= &amdgpu_block_invalid_rreg
;
1389 adev
->audio_endpt_wreg
= &amdgpu_block_invalid_wreg
;
1391 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1392 amdgpu_asic_name
[adev
->asic_type
], pdev
->vendor
, pdev
->device
,
1393 pdev
->subsystem_vendor
, pdev
->subsystem_device
);
1395 /* mutex initialization are all done here so we
1396 * can recall function without having locking issues */
1397 mutex_init(&adev
->ring_lock
);
1398 atomic_set(&adev
->irq
.ih
.lock
, 0);
1399 mutex_init(&adev
->gem
.mutex
);
1400 mutex_init(&adev
->pm
.mutex
);
1401 mutex_init(&adev
->gfx
.gpu_clock_mutex
);
1402 mutex_init(&adev
->srbm_mutex
);
1403 mutex_init(&adev
->grbm_idx_mutex
);
1404 init_rwsem(&adev
->pm
.mclk_lock
);
1405 init_rwsem(&adev
->exclusive_lock
);
1406 mutex_init(&adev
->mn_lock
);
1407 hash_init(adev
->mn_hash
);
1409 amdgpu_check_arguments(adev
);
1411 /* Registers mapping */
1412 /* TODO: block userspace mapping of io register */
1413 spin_lock_init(&adev
->mmio_idx_lock
);
1414 spin_lock_init(&adev
->smc_idx_lock
);
1415 spin_lock_init(&adev
->pcie_idx_lock
);
1416 spin_lock_init(&adev
->uvd_ctx_idx_lock
);
1417 spin_lock_init(&adev
->didt_idx_lock
);
1418 spin_lock_init(&adev
->audio_endpt_idx_lock
);
1420 adev
->rmmio_base
= pci_resource_start(adev
->pdev
, 5);
1421 adev
->rmmio_size
= pci_resource_len(adev
->pdev
, 5);
1422 adev
->rmmio
= ioremap(adev
->rmmio_base
, adev
->rmmio_size
);
1423 if (adev
->rmmio
== NULL
) {
1426 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev
->rmmio_base
);
1427 DRM_INFO("register mmio size: %u\n", (unsigned)adev
->rmmio_size
);
1429 /* doorbell bar mapping */
1430 amdgpu_doorbell_init(adev
);
1432 /* io port mapping */
1433 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
1434 if (pci_resource_flags(adev
->pdev
, i
) & IORESOURCE_IO
) {
1435 adev
->rio_mem_size
= pci_resource_len(adev
->pdev
, i
);
1436 adev
->rio_mem
= pci_iomap(adev
->pdev
, i
, adev
->rio_mem_size
);
1440 if (adev
->rio_mem
== NULL
)
1441 DRM_ERROR("Unable to find PCI I/O BAR\n");
1443 /* early init functions */
1444 r
= amdgpu_early_init(adev
);
1448 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1449 /* this will fail for cards that aren't VGA class devices, just
1451 vga_client_register(adev
->pdev
, adev
, NULL
, amdgpu_vga_set_decode
);
1453 if (amdgpu_runtime_pm
== 1)
1455 if (amdgpu_device_is_px(ddev
))
1457 vga_switcheroo_register_client(adev
->pdev
, &amdgpu_switcheroo_ops
, runtime
);
1459 vga_switcheroo_init_domain_pm_ops(adev
->dev
, &adev
->vga_pm_domain
);
1462 if (!amdgpu_get_bios(adev
))
1464 /* Must be an ATOMBIOS */
1465 if (!adev
->is_atom_bios
) {
1466 dev_err(adev
->dev
, "Expecting atombios for GPU\n");
1469 r
= amdgpu_atombios_init(adev
);
1473 /* Post card if necessary */
1474 if (!amdgpu_card_posted(adev
)) {
1476 dev_err(adev
->dev
, "Card not posted and no BIOS - ignoring\n");
1479 DRM_INFO("GPU not posted. posting now...\n");
1480 amdgpu_atom_asic_init(adev
->mode_info
.atom_context
);
1483 /* Initialize clocks */
1484 r
= amdgpu_atombios_get_clock_info(adev
);
1487 /* init i2c buses */
1488 amdgpu_atombios_i2c_init(adev
);
1491 r
= amdgpu_fence_driver_init(adev
);
1495 /* init the mode config */
1496 drm_mode_config_init(adev
->ddev
);
1498 r
= amdgpu_init(adev
);
1504 adev
->accel_working
= true;
1506 amdgpu_fbdev_init(adev
);
1508 r
= amdgpu_ib_pool_init(adev
);
1510 dev_err(adev
->dev
, "IB initialization failed (%d).\n", r
);
1514 r
= amdgpu_ib_ring_tests(adev
);
1516 DRM_ERROR("ib ring test failed (%d).\n", r
);
1518 r
= amdgpu_gem_debugfs_init(adev
);
1520 DRM_ERROR("registering gem debugfs failed (%d).\n", r
);
1523 r
= amdgpu_debugfs_regs_init(adev
);
1525 DRM_ERROR("registering register debugfs failed (%d).\n", r
);
1528 if ((amdgpu_testing
& 1)) {
1529 if (adev
->accel_working
)
1530 amdgpu_test_moves(adev
);
1532 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1534 if ((amdgpu_testing
& 2)) {
1535 if (adev
->accel_working
)
1536 amdgpu_test_syncing(adev
);
1538 DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1540 if (amdgpu_benchmarking
) {
1541 if (adev
->accel_working
)
1542 amdgpu_benchmark(adev
, amdgpu_benchmarking
);
1544 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1547 /* enable clockgating, etc. after ib tests, etc. since some blocks require
1548 * explicit gating rather than handling it automatically.
1550 r
= amdgpu_late_init(adev
);
1557 static void amdgpu_debugfs_remove_files(struct amdgpu_device
*adev
);
1560 * amdgpu_device_fini - tear down the driver
1562 * @adev: amdgpu_device pointer
1564 * Tear down the driver info (all asics).
1565 * Called at driver shutdown.
1567 void amdgpu_device_fini(struct amdgpu_device
*adev
)
1571 DRM_INFO("amdgpu: finishing device.\n");
1572 adev
->shutdown
= true;
1573 /* evict vram memory */
1574 amdgpu_bo_evict_vram(adev
);
1575 amdgpu_ib_pool_fini(adev
);
1576 amdgpu_fence_driver_fini(adev
);
1577 amdgpu_fbdev_fini(adev
);
1578 r
= amdgpu_fini(adev
);
1579 if (adev
->ip_block_enabled
)
1580 kfree(adev
->ip_block_enabled
);
1581 adev
->ip_block_enabled
= NULL
;
1582 adev
->accel_working
= false;
1583 /* free i2c buses */
1584 amdgpu_i2c_fini(adev
);
1585 amdgpu_atombios_fini(adev
);
1588 vga_switcheroo_unregister_client(adev
->pdev
);
1589 vga_client_register(adev
->pdev
, NULL
, NULL
, NULL
);
1591 pci_iounmap(adev
->pdev
, adev
->rio_mem
);
1592 adev
->rio_mem
= NULL
;
1593 iounmap(adev
->rmmio
);
1595 amdgpu_doorbell_fini(adev
);
1596 amdgpu_debugfs_regs_cleanup(adev
);
1597 amdgpu_debugfs_remove_files(adev
);
1605 * amdgpu_suspend_kms - initiate device suspend
1607 * @pdev: drm dev pointer
1608 * @state: suspend state
1610 * Puts the hw in the suspend state (all asics).
1611 * Returns 0 for success or an error on failure.
1612 * Called at driver suspend.
1614 int amdgpu_suspend_kms(struct drm_device
*dev
, bool suspend
, bool fbcon
)
1616 struct amdgpu_device
*adev
;
1617 struct drm_crtc
*crtc
;
1618 struct drm_connector
*connector
;
1620 bool force_completion
= false;
1622 if (dev
== NULL
|| dev
->dev_private
== NULL
) {
1626 adev
= dev
->dev_private
;
1628 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1631 drm_kms_helper_poll_disable(dev
);
1633 /* turn off display hw */
1634 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1635 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_OFF
);
1638 /* unpin the front buffers */
1639 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1640 struct amdgpu_framebuffer
*rfb
= to_amdgpu_framebuffer(crtc
->primary
->fb
);
1641 struct amdgpu_bo
*robj
;
1643 if (rfb
== NULL
|| rfb
->obj
== NULL
) {
1646 robj
= gem_to_amdgpu_bo(rfb
->obj
);
1647 /* don't unpin kernel fb objects */
1648 if (!amdgpu_fbdev_robj_is_fb(adev
, robj
)) {
1649 r
= amdgpu_bo_reserve(robj
, false);
1651 amdgpu_bo_unpin(robj
);
1652 amdgpu_bo_unreserve(robj
);
1656 /* evict vram memory */
1657 amdgpu_bo_evict_vram(adev
);
1659 /* wait for gpu to finish processing current batch */
1660 for (i
= 0; i
< AMDGPU_MAX_RINGS
; i
++) {
1661 struct amdgpu_ring
*ring
= adev
->rings
[i
];
1665 r
= amdgpu_fence_wait_empty(ring
);
1667 /* delay GPU reset to resume */
1668 force_completion
= true;
1671 if (force_completion
) {
1672 amdgpu_fence_driver_force_completion(adev
);
1675 r
= amdgpu_suspend(adev
);
1677 /* evict remaining vram memory */
1678 amdgpu_bo_evict_vram(adev
);
1680 pci_save_state(dev
->pdev
);
1682 /* Shut down the device */
1683 pci_disable_device(dev
->pdev
);
1684 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
1689 amdgpu_fbdev_set_suspend(adev
, 1);
1696 * amdgpu_resume_kms - initiate device resume
1698 * @pdev: drm dev pointer
1700 * Bring the hw back to operating state (all asics).
1701 * Returns 0 for success or an error on failure.
1702 * Called at driver resume.
1704 int amdgpu_resume_kms(struct drm_device
*dev
, bool resume
, bool fbcon
)
1706 struct drm_connector
*connector
;
1707 struct amdgpu_device
*adev
= dev
->dev_private
;
1710 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1717 pci_set_power_state(dev
->pdev
, PCI_D0
);
1718 pci_restore_state(dev
->pdev
);
1719 if (pci_enable_device(dev
->pdev
)) {
1727 amdgpu_atom_asic_init(adev
->mode_info
.atom_context
);
1729 r
= amdgpu_resume(adev
);
1731 r
= amdgpu_ib_ring_tests(adev
);
1733 DRM_ERROR("ib ring test failed (%d).\n", r
);
1735 r
= amdgpu_late_init(adev
);
1739 /* blat the mode back in */
1741 drm_helper_resume_force_mode(dev
);
1742 /* turn on display hw */
1743 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1744 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_ON
);
1748 drm_kms_helper_poll_enable(dev
);
1751 amdgpu_fbdev_set_suspend(adev
, 0);
1759 * amdgpu_gpu_reset - reset the asic
1761 * @adev: amdgpu device pointer
1763 * Attempt the reset the GPU if it has hung (all asics).
1764 * Returns 0 for success or an error on failure.
1766 int amdgpu_gpu_reset(struct amdgpu_device
*adev
)
1768 unsigned ring_sizes
[AMDGPU_MAX_RINGS
];
1769 uint32_t *ring_data
[AMDGPU_MAX_RINGS
];
1776 down_write(&adev
->exclusive_lock
);
1778 if (!adev
->needs_reset
) {
1779 up_write(&adev
->exclusive_lock
);
1783 adev
->needs_reset
= false;
1784 atomic_inc(&adev
->gpu_reset_counter
);
1787 resched
= ttm_bo_lock_delayed_workqueue(&adev
->mman
.bdev
);
1789 r
= amdgpu_suspend(adev
);
1791 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
1792 struct amdgpu_ring
*ring
= adev
->rings
[i
];
1796 ring_sizes
[i
] = amdgpu_ring_backup(ring
, &ring_data
[i
]);
1797 if (ring_sizes
[i
]) {
1799 dev_info(adev
->dev
, "Saved %d dwords of commands "
1800 "on ring %d.\n", ring_sizes
[i
], i
);
1805 r
= amdgpu_asic_reset(adev
);
1807 dev_info(adev
->dev
, "GPU reset succeeded, trying to resume\n");
1808 r
= amdgpu_resume(adev
);
1812 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
1813 struct amdgpu_ring
*ring
= adev
->rings
[i
];
1817 amdgpu_ring_restore(ring
, ring_sizes
[i
], ring_data
[i
]);
1819 ring_data
[i
] = NULL
;
1822 r
= amdgpu_ib_ring_tests(adev
);
1824 dev_err(adev
->dev
, "ib ring test failed (%d).\n", r
);
1827 r
= amdgpu_suspend(adev
);
1832 amdgpu_fence_driver_force_completion(adev
);
1833 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
1835 kfree(ring_data
[i
]);
1839 drm_helper_resume_force_mode(adev
->ddev
);
1841 ttm_bo_unlock_delayed_workqueue(&adev
->mman
.bdev
, resched
);
1843 /* bad news, how to tell it to userspace ? */
1844 dev_info(adev
->dev
, "GPU reset failed\n");
1847 up_write(&adev
->exclusive_lock
);
1855 int amdgpu_debugfs_add_files(struct amdgpu_device
*adev
,
1856 struct drm_info_list
*files
,
1861 for (i
= 0; i
< adev
->debugfs_count
; i
++) {
1862 if (adev
->debugfs
[i
].files
== files
) {
1863 /* Already registered */
1868 i
= adev
->debugfs_count
+ 1;
1869 if (i
> AMDGPU_DEBUGFS_MAX_COMPONENTS
) {
1870 DRM_ERROR("Reached maximum number of debugfs components.\n");
1871 DRM_ERROR("Report so we increase "
1872 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
1875 adev
->debugfs
[adev
->debugfs_count
].files
= files
;
1876 adev
->debugfs
[adev
->debugfs_count
].num_files
= nfiles
;
1877 adev
->debugfs_count
= i
;
1878 #if defined(CONFIG_DEBUG_FS)
1879 drm_debugfs_create_files(files
, nfiles
,
1880 adev
->ddev
->control
->debugfs_root
,
1881 adev
->ddev
->control
);
1882 drm_debugfs_create_files(files
, nfiles
,
1883 adev
->ddev
->primary
->debugfs_root
,
1884 adev
->ddev
->primary
);
1889 static void amdgpu_debugfs_remove_files(struct amdgpu_device
*adev
)
1891 #if defined(CONFIG_DEBUG_FS)
1894 for (i
= 0; i
< adev
->debugfs_count
; i
++) {
1895 drm_debugfs_remove_files(adev
->debugfs
[i
].files
,
1896 adev
->debugfs
[i
].num_files
,
1897 adev
->ddev
->control
);
1898 drm_debugfs_remove_files(adev
->debugfs
[i
].files
,
1899 adev
->debugfs
[i
].num_files
,
1900 adev
->ddev
->primary
);
1905 #if defined(CONFIG_DEBUG_FS)
1907 static ssize_t
amdgpu_debugfs_regs_read(struct file
*f
, char __user
*buf
,
1908 size_t size
, loff_t
*pos
)
1910 struct amdgpu_device
*adev
= f
->f_inode
->i_private
;
1914 if (size
& 0x3 || *pos
& 0x3)
1920 if (*pos
> adev
->rmmio_size
)
1923 value
= RREG32(*pos
>> 2);
1924 r
= put_user(value
, (uint32_t *)buf
);
1937 static ssize_t
amdgpu_debugfs_regs_write(struct file
*f
, const char __user
*buf
,
1938 size_t size
, loff_t
*pos
)
1940 struct amdgpu_device
*adev
= f
->f_inode
->i_private
;
1944 if (size
& 0x3 || *pos
& 0x3)
1950 if (*pos
> adev
->rmmio_size
)
1953 r
= get_user(value
, (uint32_t *)buf
);
1957 WREG32(*pos
>> 2, value
);
1968 static const struct file_operations amdgpu_debugfs_regs_fops
= {
1969 .owner
= THIS_MODULE
,
1970 .read
= amdgpu_debugfs_regs_read
,
1971 .write
= amdgpu_debugfs_regs_write
,
1972 .llseek
= default_llseek
1975 static int amdgpu_debugfs_regs_init(struct amdgpu_device
*adev
)
1977 struct drm_minor
*minor
= adev
->ddev
->primary
;
1978 struct dentry
*ent
, *root
= minor
->debugfs_root
;
1980 ent
= debugfs_create_file("amdgpu_regs", S_IFREG
| S_IRUGO
, root
,
1981 adev
, &amdgpu_debugfs_regs_fops
);
1983 return PTR_ERR(ent
);
1984 i_size_write(ent
->d_inode
, adev
->rmmio_size
);
1985 adev
->debugfs_regs
= ent
;
1990 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device
*adev
)
1992 debugfs_remove(adev
->debugfs_regs
);
1993 adev
->debugfs_regs
= NULL
;
1996 int amdgpu_debugfs_init(struct drm_minor
*minor
)
2001 void amdgpu_debugfs_cleanup(struct drm_minor
*minor
)