2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef __AMDGPU_DPM_H__
24 #define __AMDGPU_DPM_H__
26 enum amdgpu_int_thermal_type
{
28 THERMAL_TYPE_EXTERNAL
,
29 THERMAL_TYPE_EXTERNAL_GPIO
,
32 THERMAL_TYPE_ADT7473_WITH_INTERNAL
,
33 THERMAL_TYPE_EVERGREEN
,
37 THERMAL_TYPE_EMC2103_WITH_INTERNAL
,
42 enum amdgpu_dpm_auto_throttle_src
{
43 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL
,
44 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
47 enum amdgpu_dpm_event_src
{
48 AMDGPU_DPM_EVENT_SRC_ANALOG
= 0,
49 AMDGPU_DPM_EVENT_SRC_EXTERNAL
= 1,
50 AMDGPU_DPM_EVENT_SRC_DIGITAL
= 2,
51 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL
= 3,
52 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL
= 4
55 #define SCLK_DEEP_SLEEP_MASK 0x8
58 u32 caps
; /* vbios flags */
59 u32
class; /* vbios flags */
60 u32 class2
; /* vbios flags */
68 enum amd_vce_level vce_level
;
73 struct amdgpu_dpm_thermal
{
74 /* thermal interrupt work */
75 struct work_struct work
;
76 /* low temperature threshold */
78 /* high temperature threshold */
80 /* was last interrupt low to high or high to low */
82 /* interrupt source */
83 struct amdgpu_irq_src irq
;
86 enum amdgpu_clk_action
92 struct amdgpu_blacklist_clocks
96 enum amdgpu_clk_action action
;
99 struct amdgpu_clock_and_voltage_limits
{
106 struct amdgpu_clock_array
{
111 struct amdgpu_clock_voltage_dependency_entry
{
116 struct amdgpu_clock_voltage_dependency_table
{
118 struct amdgpu_clock_voltage_dependency_entry
*entries
;
121 union amdgpu_cac_leakage_entry
{
133 struct amdgpu_cac_leakage_table
{
135 union amdgpu_cac_leakage_entry
*entries
;
138 struct amdgpu_phase_shedding_limits_entry
{
144 struct amdgpu_phase_shedding_limits_table
{
146 struct amdgpu_phase_shedding_limits_entry
*entries
;
149 struct amdgpu_uvd_clock_voltage_dependency_entry
{
155 struct amdgpu_uvd_clock_voltage_dependency_table
{
157 struct amdgpu_uvd_clock_voltage_dependency_entry
*entries
;
160 struct amdgpu_vce_clock_voltage_dependency_entry
{
166 struct amdgpu_vce_clock_voltage_dependency_table
{
168 struct amdgpu_vce_clock_voltage_dependency_entry
*entries
;
171 struct amdgpu_ppm_table
{
175 u32 small_ac_platform_tdp
;
177 u32 small_ac_platform_tdc
;
184 struct amdgpu_cac_tdp_table
{
186 u16 configurable_tdp
;
188 u16 battery_power_limit
;
189 u16 small_power_limit
;
191 u16 high_cac_leakage
;
192 u16 maximum_power_delivery_limit
;
195 struct amdgpu_dpm_dynamic_state
{
196 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk
;
197 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk
;
198 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk
;
199 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk
;
200 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk
;
201 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table
;
202 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table
;
203 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table
;
204 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table
;
205 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk
;
206 struct amdgpu_clock_array valid_sclk_values
;
207 struct amdgpu_clock_array valid_mclk_values
;
208 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc
;
209 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac
;
212 u16 vddc_vddci_delta
;
213 u16 min_vddc_for_pcie_gen2
;
214 struct amdgpu_cac_leakage_table cac_leakage_table
;
215 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table
;
216 struct amdgpu_ppm_table
*ppm_table
;
217 struct amdgpu_cac_tdp_table
*cac_tdp_table
;
220 struct amdgpu_dpm_fan
{
231 u16 default_max_fan_pwm
;
232 u16 default_fan_output_sensitivity
;
233 u16 fan_output_sensitivity
;
234 bool ucode_fan_control
;
237 enum amdgpu_pcie_gen
{
238 AMDGPU_PCIE_GEN1
= 0,
239 AMDGPU_PCIE_GEN2
= 1,
240 AMDGPU_PCIE_GEN3
= 2,
241 AMDGPU_PCIE_GEN_INVALID
= 0xffff
244 #define amdgpu_dpm_pre_set_power_state(adev) \
245 ((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle))
247 #define amdgpu_dpm_set_power_state(adev) \
248 ((adev)->powerplay.pp_funcs->set_power_state((adev)->powerplay.pp_handle))
250 #define amdgpu_dpm_post_set_power_state(adev) \
251 ((adev)->powerplay.pp_funcs->post_set_power_state((adev)->powerplay.pp_handle))
253 #define amdgpu_dpm_display_configuration_changed(adev) \
254 ((adev)->powerplay.pp_funcs->display_configuration_changed((adev)->powerplay.pp_handle))
256 #define amdgpu_dpm_print_power_state(adev, ps) \
257 ((adev)->powerplay.pp_funcs->print_power_state((adev)->powerplay.pp_handle, (ps)))
259 #define amdgpu_dpm_vblank_too_short(adev) \
260 ((adev)->powerplay.pp_funcs->vblank_too_short((adev)->powerplay.pp_handle))
262 #define amdgpu_dpm_enable_bapm(adev, e) \
263 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
265 #define amdgpu_dpm_read_sensor(adev, idx, value, size) \
266 ((adev)->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle, (idx), (value), (size)))
268 #define amdgpu_dpm_get_temperature(adev) \
269 ((adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle))
271 #define amdgpu_dpm_set_fan_control_mode(adev, m) \
272 ((adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)))
274 #define amdgpu_dpm_get_fan_control_mode(adev) \
275 ((adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle))
277 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \
278 ((adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)))
280 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \
281 ((adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)))
283 #define amdgpu_dpm_get_fan_speed_rpm(adev, s) \
284 ((adev)->powerplay.pp_funcs->get_fan_speed_rpm)((adev)->powerplay.pp_handle, (s))
286 #define amdgpu_dpm_get_sclk(adev, l) \
287 ((adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)))
289 #define amdgpu_dpm_get_mclk(adev, l) \
290 ((adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)))
292 #define amdgpu_dpm_force_performance_level(adev, l) \
293 ((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)))
295 #define amdgpu_dpm_powergate_uvd(adev, g) \
296 ((adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)))
298 #define amdgpu_dpm_powergate_vce(adev, g) \
299 ((adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)))
301 #define amdgpu_dpm_get_current_power_state(adev) \
302 ((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
304 #define amdgpu_dpm_get_pp_num_states(adev, data) \
305 ((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data))
307 #define amdgpu_dpm_get_pp_table(adev, table) \
308 ((adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table))
310 #define amdgpu_dpm_set_pp_table(adev, buf, size) \
311 ((adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size))
313 #define amdgpu_dpm_print_clock_levels(adev, type, buf) \
314 ((adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf))
316 #define amdgpu_dpm_force_clock_level(adev, type, level) \
317 ((adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level))
319 #define amdgpu_dpm_get_sclk_od(adev) \
320 ((adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle))
322 #define amdgpu_dpm_set_sclk_od(adev, value) \
323 ((adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value))
325 #define amdgpu_dpm_get_mclk_od(adev) \
326 ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
328 #define amdgpu_dpm_set_mclk_od(adev, value) \
329 ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
331 #define amdgpu_dpm_dispatch_task(adev, task_id, input, output) \
332 ((adev)->powerplay.pp_funcs->dispatch_tasks)((adev)->powerplay.pp_handle, (task_id), (input), (output))
334 #define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \
335 ((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal)))
337 #define amdgpu_dpm_get_vce_clock_state(adev, i) \
338 ((adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)))
340 #define amdgpu_dpm_get_performance_level(adev) \
341 ((adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle))
343 #define amdgpu_dpm_reset_power_profile_state(adev, request) \
344 ((adev)->powerplay.pp_funcs->reset_power_profile_state(\
345 (adev)->powerplay.pp_handle, request))
347 #define amdgpu_dpm_get_power_profile_state(adev, query) \
348 ((adev)->powerplay.pp_funcs->get_power_profile_state(\
349 (adev)->powerplay.pp_handle, query))
351 #define amdgpu_dpm_set_power_profile_state(adev, request) \
352 ((adev)->powerplay.pp_funcs->set_power_profile_state(\
353 (adev)->powerplay.pp_handle, request))
355 #define amdgpu_dpm_switch_power_profile(adev, type) \
356 ((adev)->powerplay.pp_funcs->switch_power_profile(\
357 (adev)->powerplay.pp_handle, type))
360 struct amdgpu_ps
*ps
;
361 /* number of valid power states */
363 /* current power state that is active */
364 struct amdgpu_ps
*current_ps
;
365 /* requested power state */
366 struct amdgpu_ps
*requested_ps
;
367 /* boot up power state */
368 struct amdgpu_ps
*boot_ps
;
369 /* default uvd power state */
370 struct amdgpu_ps
*uvd_ps
;
371 /* vce requirements */
372 u32 num_of_vce_states
;
373 struct amd_vce_state vce_states
[AMD_MAX_VCE_LEVELS
];
374 enum amd_vce_level vce_level
;
375 enum amd_pm_state_type state
;
376 enum amd_pm_state_type user_state
;
377 enum amd_pm_state_type last_state
;
378 enum amd_pm_state_type last_user_state
;
380 u32 voltage_response_time
;
381 u32 backbias_response_time
;
383 u32 new_active_crtcs
;
384 int new_active_crtc_count
;
385 u32 current_active_crtcs
;
386 int current_active_crtc_count
;
387 struct amdgpu_dpm_dynamic_state dyn_state
;
388 struct amdgpu_dpm_fan fan
;
391 u32 near_tdp_limit_adjusted
;
392 u32 sq_ramping_threshold
;
399 /* special states active */
403 /* thermal handling */
404 struct amdgpu_dpm_thermal thermal
;
406 enum amd_dpm_forced_level forced_level
;
415 struct amdgpu_i2c_chan
*i2c_bus
;
416 /* internal thermal controller on rv6xx+ */
417 enum amdgpu_int_thermal_type int_thermal_type
;
418 struct device
*int_hwmon_dev
;
419 /* fan control parameters */
421 u8 fan_pulses_per_revolution
;
426 bool sysfs_initialized
;
427 struct amdgpu_dpm dpm
;
428 const struct firmware
*fw
; /* SMC firmware */
430 uint32_t pcie_gen_mask
;
431 uint32_t pcie_mlw_mask
;
432 struct amd_pp_display_configuration pm_display_cfg
;/* set by DAL */
435 #define R600_SSTU_DFLT 0
436 #define R600_SST_DFLT 0x00C8
438 /* XXX are these ok? */
439 #define R600_TEMP_RANGE_MIN (90 * 1000)
440 #define R600_TEMP_RANGE_MAX (120 * 1000)
442 #define FDO_PWM_MODE_STATIC 1
443 #define FDO_PWM_MODE_STATIC_RPM 5
451 enum amdgpu_display_watermark
{
452 AMDGPU_DISPLAY_WATERMARK_LOW
= 0,
453 AMDGPU_DISPLAY_WATERMARK_HIGH
= 1,
456 enum amdgpu_display_gap
458 AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM
= 0,
459 AMDGPU_PM_DISPLAY_GAP_VBLANK
= 1,
460 AMDGPU_PM_DISPLAY_GAP_WATERMARK
= 2,
461 AMDGPU_PM_DISPLAY_GAP_IGNORE
= 3,
464 void amdgpu_dpm_print_class_info(u32
class, u32 class2
);
465 void amdgpu_dpm_print_cap_info(u32 caps
);
466 void amdgpu_dpm_print_ps_status(struct amdgpu_device
*adev
,
467 struct amdgpu_ps
*rps
);
468 u32
amdgpu_dpm_get_vblank_time(struct amdgpu_device
*adev
);
469 u32
amdgpu_dpm_get_vrefresh(struct amdgpu_device
*adev
);
470 bool amdgpu_is_uvd_state(u32
class, u32 class2
);
471 void amdgpu_calculate_u_and_p(u32 i
, u32 r_c
, u32 p_b
,
473 int amdgpu_calculate_at(u32 t
, u32 h
, u32 fh
, u32 fl
, u32
*tl
, u32
*th
);
475 bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor
);
477 int amdgpu_get_platform_caps(struct amdgpu_device
*adev
);
479 int amdgpu_parse_extended_power_table(struct amdgpu_device
*adev
);
480 void amdgpu_free_extended_power_table(struct amdgpu_device
*adev
);
482 void amdgpu_add_thermal_controller(struct amdgpu_device
*adev
);
484 enum amdgpu_pcie_gen
amdgpu_get_pcie_gen_support(struct amdgpu_device
*adev
,
486 enum amdgpu_pcie_gen asic_gen
,
487 enum amdgpu_pcie_gen default_gen
);
489 u16
amdgpu_get_pcie_lane_support(struct amdgpu_device
*adev
,
492 u8
amdgpu_encode_pci_lane_width(u32 lanes
);
494 struct amd_vce_state
*
495 amdgpu_get_vce_clock_state(void *handle
, u32 idx
);