5 * \author Gareth Hughes <gareth@valinux.com>
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
33 #include <drm/amdgpu_drm.h>
34 #include <drm/drm_gem.h>
35 #include "amdgpu_drv.h"
37 #include <drm/drm_pciids.h>
38 #include <linux/console.h>
39 #include <linux/module.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/vga_switcheroo.h>
42 #include <drm/drm_crtc_helper.h>
45 #include "amdgpu_irq.h"
47 #include "amdgpu_amdkfd.h"
51 * - 3.0.0 - initial driver
52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
55 * - 3.3.0 - Add VM support for UVD on supported hardware.
56 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
57 * - 3.5.0 - Add support for new UVD_NO_OP register.
58 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
59 * - 3.7.0 - Add support for VCE clock list packet
60 * - 3.8.0 - Add support raster config init in the kernel
61 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
62 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
63 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
64 * - 3.12.0 - Add query for double offchip LDS buffers
65 * - 3.13.0 - Add PRT support
66 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
67 * - 3.15.0 - Export more gpu info for gfx9
68 * - 3.16.0 - Add reserved vmid support
69 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
70 * - 3.18.0 - Export gpu always on cu bitmap
72 #define KMS_DRIVER_MAJOR 3
73 #define KMS_DRIVER_MINOR 18
74 #define KMS_DRIVER_PATCHLEVEL 0
76 int amdgpu_vram_limit
= 0;
77 int amdgpu_gart_size
= -1; /* auto */
78 int amdgpu_moverate
= -1; /* auto */
79 int amdgpu_benchmarking
= 0;
80 int amdgpu_testing
= 0;
81 int amdgpu_audio
= -1;
82 int amdgpu_disp_priority
= 0;
83 int amdgpu_hw_i2c
= 0;
84 int amdgpu_pcie_gen2
= -1;
86 int amdgpu_lockup_timeout
= 0;
88 int amdgpu_fw_load_type
= -1;
90 int amdgpu_runtime_pm
= -1;
91 unsigned amdgpu_ip_block_mask
= 0xffffffff;
93 int amdgpu_deep_color
= 0;
94 int amdgpu_vm_size
= -1;
95 int amdgpu_vm_block_size
= -1;
96 int amdgpu_vm_fault_stop
= 0;
97 int amdgpu_vm_debug
= 0;
98 int amdgpu_vram_page_split
= 512;
99 int amdgpu_vm_update_mode
= -1;
100 int amdgpu_exp_hw_support
= 0;
101 int amdgpu_sched_jobs
= 32;
102 int amdgpu_sched_hw_submission
= 2;
103 int amdgpu_no_evict
= 0;
104 int amdgpu_direct_gma_size
= 0;
105 unsigned amdgpu_pcie_gen_cap
= 0;
106 unsigned amdgpu_pcie_lane_cap
= 0;
107 unsigned amdgpu_cg_mask
= 0xffffffff;
108 unsigned amdgpu_pg_mask
= 0xffffffff;
109 char *amdgpu_disable_cu
= NULL
;
110 char *amdgpu_virtual_display
= NULL
;
111 unsigned amdgpu_pp_feature_mask
= 0xffffffff;
113 int amdgpu_prim_buf_per_se
= 0;
114 int amdgpu_pos_buf_per_se
= 0;
115 int amdgpu_cntl_sb_buf_per_se
= 0;
116 int amdgpu_param_buf_per_se
= 0;
117 int amdgpu_job_hang_limit
= 0;
118 int amdgpu_lbpw
= -1;
120 MODULE_PARM_DESC(vramlimit
, "Restrict VRAM for testing, in megabytes");
121 module_param_named(vramlimit
, amdgpu_vram_limit
, int, 0600);
123 MODULE_PARM_DESC(gartsize
, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
124 module_param_named(gartsize
, amdgpu_gart_size
, int, 0600);
126 MODULE_PARM_DESC(moverate
, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
127 module_param_named(moverate
, amdgpu_moverate
, int, 0600);
129 MODULE_PARM_DESC(benchmark
, "Run benchmark");
130 module_param_named(benchmark
, amdgpu_benchmarking
, int, 0444);
132 MODULE_PARM_DESC(test
, "Run tests");
133 module_param_named(test
, amdgpu_testing
, int, 0444);
135 MODULE_PARM_DESC(audio
, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
136 module_param_named(audio
, amdgpu_audio
, int, 0444);
138 MODULE_PARM_DESC(disp_priority
, "Display Priority (0 = auto, 1 = normal, 2 = high)");
139 module_param_named(disp_priority
, amdgpu_disp_priority
, int, 0444);
141 MODULE_PARM_DESC(hw_i2c
, "hw i2c engine enable (0 = disable)");
142 module_param_named(hw_i2c
, amdgpu_hw_i2c
, int, 0444);
144 MODULE_PARM_DESC(pcie_gen2
, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
145 module_param_named(pcie_gen2
, amdgpu_pcie_gen2
, int, 0444);
147 MODULE_PARM_DESC(msi
, "MSI support (1 = enable, 0 = disable, -1 = auto)");
148 module_param_named(msi
, amdgpu_msi
, int, 0444);
150 MODULE_PARM_DESC(lockup_timeout
, "GPU lockup timeout in ms (default 0 = disable)");
151 module_param_named(lockup_timeout
, amdgpu_lockup_timeout
, int, 0444);
153 MODULE_PARM_DESC(dpm
, "DPM support (1 = enable, 0 = disable, -1 = auto)");
154 module_param_named(dpm
, amdgpu_dpm
, int, 0444);
156 MODULE_PARM_DESC(fw_load_type
, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
157 module_param_named(fw_load_type
, amdgpu_fw_load_type
, int, 0444);
159 MODULE_PARM_DESC(aspm
, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
160 module_param_named(aspm
, amdgpu_aspm
, int, 0444);
162 MODULE_PARM_DESC(runpm
, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
163 module_param_named(runpm
, amdgpu_runtime_pm
, int, 0444);
165 MODULE_PARM_DESC(ip_block_mask
, "IP Block Mask (all blocks enabled (default))");
166 module_param_named(ip_block_mask
, amdgpu_ip_block_mask
, uint
, 0444);
168 MODULE_PARM_DESC(bapm
, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
169 module_param_named(bapm
, amdgpu_bapm
, int, 0444);
171 MODULE_PARM_DESC(deep_color
, "Deep Color support (1 = enable, 0 = disable (default))");
172 module_param_named(deep_color
, amdgpu_deep_color
, int, 0444);
174 MODULE_PARM_DESC(vm_size
, "VM address space size in gigabytes (default 64GB)");
175 module_param_named(vm_size
, amdgpu_vm_size
, int, 0444);
177 MODULE_PARM_DESC(vm_block_size
, "VM page table size in bits (default depending on vm_size)");
178 module_param_named(vm_block_size
, amdgpu_vm_block_size
, int, 0444);
180 MODULE_PARM_DESC(vm_fault_stop
, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
181 module_param_named(vm_fault_stop
, amdgpu_vm_fault_stop
, int, 0444);
183 MODULE_PARM_DESC(vm_debug
, "Debug VM handling (0 = disabled (default), 1 = enabled)");
184 module_param_named(vm_debug
, amdgpu_vm_debug
, int, 0644);
186 MODULE_PARM_DESC(vm_update_mode
, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
187 module_param_named(vm_update_mode
, amdgpu_vm_update_mode
, int, 0444);
189 MODULE_PARM_DESC(vram_page_split
, "Number of pages after we split VRAM allocations (default 1024, -1 = disable)");
190 module_param_named(vram_page_split
, amdgpu_vram_page_split
, int, 0444);
192 MODULE_PARM_DESC(exp_hw_support
, "experimental hw support (1 = enable, 0 = disable (default))");
193 module_param_named(exp_hw_support
, amdgpu_exp_hw_support
, int, 0444);
195 MODULE_PARM_DESC(sched_jobs
, "the max number of jobs supported in the sw queue (default 32)");
196 module_param_named(sched_jobs
, amdgpu_sched_jobs
, int, 0444);
198 MODULE_PARM_DESC(sched_hw_submission
, "the max number of HW submissions (default 2)");
199 module_param_named(sched_hw_submission
, amdgpu_sched_hw_submission
, int, 0444);
201 MODULE_PARM_DESC(ppfeaturemask
, "all power features enabled (default))");
202 module_param_named(ppfeaturemask
, amdgpu_pp_feature_mask
, int, 0444);
204 MODULE_PARM_DESC(no_evict
, "Support pinning request from user space (1 = enable, 0 = disable (default))");
205 module_param_named(no_evict
, amdgpu_no_evict
, int, 0444);
207 MODULE_PARM_DESC(direct_gma_size
, "Direct GMA size in megabytes (max 96MB)");
208 module_param_named(direct_gma_size
, amdgpu_direct_gma_size
, int, 0444);
210 MODULE_PARM_DESC(pcie_gen_cap
, "PCIE Gen Caps (0: autodetect (default))");
211 module_param_named(pcie_gen_cap
, amdgpu_pcie_gen_cap
, uint
, 0444);
213 MODULE_PARM_DESC(pcie_lane_cap
, "PCIE Lane Caps (0: autodetect (default))");
214 module_param_named(pcie_lane_cap
, amdgpu_pcie_lane_cap
, uint
, 0444);
216 MODULE_PARM_DESC(cg_mask
, "Clockgating flags mask (0 = disable clock gating)");
217 module_param_named(cg_mask
, amdgpu_cg_mask
, uint
, 0444);
219 MODULE_PARM_DESC(pg_mask
, "Powergating flags mask (0 = disable power gating)");
220 module_param_named(pg_mask
, amdgpu_pg_mask
, uint
, 0444);
222 MODULE_PARM_DESC(disable_cu
, "Disable CUs (se.sh.cu,...)");
223 module_param_named(disable_cu
, amdgpu_disable_cu
, charp
, 0444);
225 MODULE_PARM_DESC(virtual_display
,
226 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
227 module_param_named(virtual_display
, amdgpu_virtual_display
, charp
, 0444);
229 MODULE_PARM_DESC(ngg
, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))");
230 module_param_named(ngg
, amdgpu_ngg
, int, 0444);
232 MODULE_PARM_DESC(prim_buf_per_se
, "the size of Primitive Buffer per Shader Engine (default depending on gfx)");
233 module_param_named(prim_buf_per_se
, amdgpu_prim_buf_per_se
, int, 0444);
235 MODULE_PARM_DESC(pos_buf_per_se
, "the size of Position Buffer per Shader Engine (default depending on gfx)");
236 module_param_named(pos_buf_per_se
, amdgpu_pos_buf_per_se
, int, 0444);
238 MODULE_PARM_DESC(cntl_sb_buf_per_se
, "the size of Control Sideband per Shader Engine (default depending on gfx)");
239 module_param_named(cntl_sb_buf_per_se
, amdgpu_cntl_sb_buf_per_se
, int, 0444);
241 MODULE_PARM_DESC(param_buf_per_se
, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)");
242 module_param_named(param_buf_per_se
, amdgpu_param_buf_per_se
, int, 0444);
244 MODULE_PARM_DESC(job_hang_limit
, "how much time allow a job hang and not drop it (default 0)");
245 module_param_named(job_hang_limit
, amdgpu_job_hang_limit
, int ,0444);
247 MODULE_PARM_DESC(lbpw
, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
248 module_param_named(lbpw
, amdgpu_lbpw
, int, 0444);
250 #ifdef CONFIG_DRM_AMDGPU_SI
252 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
253 int amdgpu_si_support
= 0;
254 MODULE_PARM_DESC(si_support
, "SI support (1 = enabled, 0 = disabled (default))");
256 int amdgpu_si_support
= 1;
257 MODULE_PARM_DESC(si_support
, "SI support (1 = enabled (default), 0 = disabled)");
260 module_param_named(si_support
, amdgpu_si_support
, int, 0444);
263 #ifdef CONFIG_DRM_AMDGPU_CIK
265 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
266 int amdgpu_cik_support
= 0;
267 MODULE_PARM_DESC(cik_support
, "CIK support (1 = enabled, 0 = disabled (default))");
269 int amdgpu_cik_support
= 1;
270 MODULE_PARM_DESC(cik_support
, "CIK support (1 = enabled (default), 0 = disabled)");
273 module_param_named(cik_support
, amdgpu_cik_support
, int, 0444);
277 static const struct pci_device_id pciidlist
[] = {
278 #ifdef CONFIG_DRM_AMDGPU_SI
279 {0x1002, 0x6780, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
280 {0x1002, 0x6784, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
281 {0x1002, 0x6788, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
282 {0x1002, 0x678A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
283 {0x1002, 0x6790, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
284 {0x1002, 0x6791, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
285 {0x1002, 0x6792, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
286 {0x1002, 0x6798, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
287 {0x1002, 0x6799, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
288 {0x1002, 0x679A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
289 {0x1002, 0x679B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
290 {0x1002, 0x679E, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
291 {0x1002, 0x679F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
292 {0x1002, 0x6800, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
|AMD_IS_MOBILITY
},
293 {0x1002, 0x6801, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
|AMD_IS_MOBILITY
},
294 {0x1002, 0x6802, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
|AMD_IS_MOBILITY
},
295 {0x1002, 0x6806, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
},
296 {0x1002, 0x6808, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
},
297 {0x1002, 0x6809, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
},
298 {0x1002, 0x6810, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
},
299 {0x1002, 0x6811, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
},
300 {0x1002, 0x6816, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
},
301 {0x1002, 0x6817, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
},
302 {0x1002, 0x6818, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
},
303 {0x1002, 0x6819, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
},
304 {0x1002, 0x6600, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
305 {0x1002, 0x6601, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
306 {0x1002, 0x6602, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
307 {0x1002, 0x6603, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
308 {0x1002, 0x6604, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
309 {0x1002, 0x6605, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
310 {0x1002, 0x6606, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
311 {0x1002, 0x6607, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
312 {0x1002, 0x6608, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
},
313 {0x1002, 0x6610, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
},
314 {0x1002, 0x6611, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
},
315 {0x1002, 0x6613, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
},
316 {0x1002, 0x6617, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
317 {0x1002, 0x6620, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
318 {0x1002, 0x6621, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
319 {0x1002, 0x6623, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
320 {0x1002, 0x6631, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
},
321 {0x1002, 0x6820, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
322 {0x1002, 0x6821, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
323 {0x1002, 0x6822, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
324 {0x1002, 0x6823, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
325 {0x1002, 0x6824, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
326 {0x1002, 0x6825, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
327 {0x1002, 0x6826, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
328 {0x1002, 0x6827, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
329 {0x1002, 0x6828, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
},
330 {0x1002, 0x6829, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
},
331 {0x1002, 0x682A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
332 {0x1002, 0x682B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
333 {0x1002, 0x682C, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
},
334 {0x1002, 0x682D, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
335 {0x1002, 0x682F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
336 {0x1002, 0x6830, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
337 {0x1002, 0x6831, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
338 {0x1002, 0x6835, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
},
339 {0x1002, 0x6837, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
},
340 {0x1002, 0x6838, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
},
341 {0x1002, 0x6839, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
},
342 {0x1002, 0x683B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
},
343 {0x1002, 0x683D, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
},
344 {0x1002, 0x683F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
},
345 {0x1002, 0x6660, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAINAN
|AMD_IS_MOBILITY
},
346 {0x1002, 0x6663, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAINAN
|AMD_IS_MOBILITY
},
347 {0x1002, 0x6664, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAINAN
|AMD_IS_MOBILITY
},
348 {0x1002, 0x6665, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAINAN
|AMD_IS_MOBILITY
},
349 {0x1002, 0x6667, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAINAN
|AMD_IS_MOBILITY
},
350 {0x1002, 0x666F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAINAN
|AMD_IS_MOBILITY
},
352 #ifdef CONFIG_DRM_AMDGPU_CIK
354 {0x1002, 0x1304, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
355 {0x1002, 0x1305, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
356 {0x1002, 0x1306, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
357 {0x1002, 0x1307, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
358 {0x1002, 0x1309, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
359 {0x1002, 0x130A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
360 {0x1002, 0x130B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
361 {0x1002, 0x130C, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
362 {0x1002, 0x130D, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
363 {0x1002, 0x130E, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
364 {0x1002, 0x130F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
365 {0x1002, 0x1310, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
366 {0x1002, 0x1311, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
367 {0x1002, 0x1312, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
368 {0x1002, 0x1313, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
369 {0x1002, 0x1315, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
370 {0x1002, 0x1316, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
371 {0x1002, 0x1317, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
372 {0x1002, 0x1318, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
373 {0x1002, 0x131B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
374 {0x1002, 0x131C, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
375 {0x1002, 0x131D, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
377 {0x1002, 0x6640, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
|AMD_IS_MOBILITY
},
378 {0x1002, 0x6641, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
|AMD_IS_MOBILITY
},
379 {0x1002, 0x6646, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
|AMD_IS_MOBILITY
},
380 {0x1002, 0x6647, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
|AMD_IS_MOBILITY
},
381 {0x1002, 0x6649, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
},
382 {0x1002, 0x6650, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
},
383 {0x1002, 0x6651, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
},
384 {0x1002, 0x6658, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
},
385 {0x1002, 0x665c, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
},
386 {0x1002, 0x665d, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
},
387 {0x1002, 0x665f, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
},
389 {0x1002, 0x67A0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
390 {0x1002, 0x67A1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
391 {0x1002, 0x67A2, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
392 {0x1002, 0x67A8, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
393 {0x1002, 0x67A9, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
394 {0x1002, 0x67AA, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
395 {0x1002, 0x67B0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
396 {0x1002, 0x67B1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
397 {0x1002, 0x67B8, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
398 {0x1002, 0x67B9, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
399 {0x1002, 0x67BA, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
400 {0x1002, 0x67BE, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
402 {0x1002, 0x9830, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
403 {0x1002, 0x9831, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
404 {0x1002, 0x9832, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
405 {0x1002, 0x9833, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
406 {0x1002, 0x9834, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
407 {0x1002, 0x9835, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
408 {0x1002, 0x9836, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
409 {0x1002, 0x9837, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
410 {0x1002, 0x9838, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
411 {0x1002, 0x9839, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
412 {0x1002, 0x983a, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
413 {0x1002, 0x983b, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
414 {0x1002, 0x983c, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
415 {0x1002, 0x983d, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
416 {0x1002, 0x983e, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
417 {0x1002, 0x983f, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
419 {0x1002, 0x9850, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
420 {0x1002, 0x9851, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
421 {0x1002, 0x9852, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
422 {0x1002, 0x9853, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
423 {0x1002, 0x9854, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
424 {0x1002, 0x9855, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
425 {0x1002, 0x9856, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
426 {0x1002, 0x9857, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
427 {0x1002, 0x9858, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
428 {0x1002, 0x9859, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
429 {0x1002, 0x985A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
430 {0x1002, 0x985B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
431 {0x1002, 0x985C, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
432 {0x1002, 0x985D, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
433 {0x1002, 0x985E, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
434 {0x1002, 0x985F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
437 {0x1002, 0x6900, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TOPAZ
},
438 {0x1002, 0x6901, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TOPAZ
},
439 {0x1002, 0x6902, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TOPAZ
},
440 {0x1002, 0x6903, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TOPAZ
},
441 {0x1002, 0x6907, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TOPAZ
},
443 {0x1002, 0x6920, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
444 {0x1002, 0x6921, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
445 {0x1002, 0x6928, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
446 {0x1002, 0x6929, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
447 {0x1002, 0x692B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
448 {0x1002, 0x692F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
449 {0x1002, 0x6930, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
450 {0x1002, 0x6938, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
451 {0x1002, 0x6939, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
453 {0x1002, 0x7300, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_FIJI
},
454 {0x1002, 0x730F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_FIJI
},
456 {0x1002, 0x9870, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_CARRIZO
|AMD_IS_APU
},
457 {0x1002, 0x9874, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_CARRIZO
|AMD_IS_APU
},
458 {0x1002, 0x9875, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_CARRIZO
|AMD_IS_APU
},
459 {0x1002, 0x9876, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_CARRIZO
|AMD_IS_APU
},
460 {0x1002, 0x9877, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_CARRIZO
|AMD_IS_APU
},
462 {0x1002, 0x98E4, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_STONEY
|AMD_IS_APU
},
464 {0x1002, 0x67E0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
465 {0x1002, 0x67E3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
466 {0x1002, 0x67E8, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
467 {0x1002, 0x67EB, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
468 {0x1002, 0x67EF, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
469 {0x1002, 0x67FF, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
470 {0x1002, 0x67E1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
471 {0x1002, 0x67E7, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
472 {0x1002, 0x67E9, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
474 {0x1002, 0x67C0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
475 {0x1002, 0x67C1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
476 {0x1002, 0x67C2, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
477 {0x1002, 0x67C4, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
478 {0x1002, 0x67C7, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
479 {0x1002, 0x67D0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
480 {0x1002, 0x67DF, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
481 {0x1002, 0x67C8, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
482 {0x1002, 0x67C9, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
483 {0x1002, 0x67CA, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
484 {0x1002, 0x67CC, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
485 {0x1002, 0x67CF, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
487 {0x1002, 0x6980, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS12
},
488 {0x1002, 0x6981, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS12
},
489 {0x1002, 0x6985, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS12
},
490 {0x1002, 0x6986, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS12
},
491 {0x1002, 0x6987, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS12
},
492 {0x1002, 0x6995, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS12
},
493 {0x1002, 0x6997, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS12
},
494 {0x1002, 0x699F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS12
},
496 {0x1002, 0x6860, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
|AMD_EXP_HW_SUPPORT
},
497 {0x1002, 0x6861, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
|AMD_EXP_HW_SUPPORT
},
498 {0x1002, 0x6862, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
|AMD_EXP_HW_SUPPORT
},
499 {0x1002, 0x6863, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
|AMD_EXP_HW_SUPPORT
},
500 {0x1002, 0x6864, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
|AMD_EXP_HW_SUPPORT
},
501 {0x1002, 0x6867, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
|AMD_EXP_HW_SUPPORT
},
502 {0x1002, 0x6868, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
|AMD_EXP_HW_SUPPORT
},
503 {0x1002, 0x686c, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
|AMD_EXP_HW_SUPPORT
},
504 {0x1002, 0x687f, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
|AMD_EXP_HW_SUPPORT
},
506 {0x1002, 0x15dd, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_RAVEN
|AMD_IS_APU
|AMD_EXP_HW_SUPPORT
},
511 MODULE_DEVICE_TABLE(pci
, pciidlist
);
513 static struct drm_driver kms_driver
;
515 static int amdgpu_kick_out_firmware_fb(struct pci_dev
*pdev
)
517 struct apertures_struct
*ap
;
518 bool primary
= false;
520 ap
= alloc_apertures(1);
524 ap
->ranges
[0].base
= pci_resource_start(pdev
, 0);
525 ap
->ranges
[0].size
= pci_resource_len(pdev
, 0);
528 primary
= pdev
->resource
[PCI_ROM_RESOURCE
].flags
& IORESOURCE_ROM_SHADOW
;
530 drm_fb_helper_remove_conflicting_framebuffers(ap
, "amdgpudrmfb", primary
);
536 static int amdgpu_pci_probe(struct pci_dev
*pdev
,
537 const struct pci_device_id
*ent
)
539 struct drm_device
*dev
;
540 unsigned long flags
= ent
->driver_data
;
543 if ((flags
& AMD_EXP_HW_SUPPORT
) && !amdgpu_exp_hw_support
) {
544 DRM_INFO("This hardware requires experimental hardware support.\n"
545 "See modparam exp_hw_support\n");
550 * Initialize amdkfd before starting radeon. If it was not loaded yet,
551 * defer radeon probing
553 ret
= amdgpu_amdkfd_init();
554 if (ret
== -EPROBE_DEFER
)
557 /* Get rid of things like offb */
558 ret
= amdgpu_kick_out_firmware_fb(pdev
);
562 dev
= drm_dev_alloc(&kms_driver
, &pdev
->dev
);
566 ret
= pci_enable_device(pdev
);
572 pci_set_drvdata(pdev
, dev
);
574 ret
= drm_dev_register(dev
, ent
->driver_data
);
581 pci_disable_device(pdev
);
588 amdgpu_pci_remove(struct pci_dev
*pdev
)
590 struct drm_device
*dev
= pci_get_drvdata(pdev
);
592 drm_dev_unregister(dev
);
597 amdgpu_pci_shutdown(struct pci_dev
*pdev
)
599 struct drm_device
*dev
= pci_get_drvdata(pdev
);
600 struct amdgpu_device
*adev
= dev
->dev_private
;
602 /* if we are running in a VM, make sure the device
603 * torn down properly on reboot/shutdown.
604 * unfortunately we can't detect certain
605 * hypervisors so just do this all the time.
607 amdgpu_suspend(adev
);
610 static int amdgpu_pmops_suspend(struct device
*dev
)
612 struct pci_dev
*pdev
= to_pci_dev(dev
);
614 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
615 return amdgpu_device_suspend(drm_dev
, true, true);
618 static int amdgpu_pmops_resume(struct device
*dev
)
620 struct pci_dev
*pdev
= to_pci_dev(dev
);
621 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
623 /* GPU comes up enabled by the bios on resume */
624 if (amdgpu_device_is_px(drm_dev
)) {
625 pm_runtime_disable(dev
);
626 pm_runtime_set_active(dev
);
627 pm_runtime_enable(dev
);
630 return amdgpu_device_resume(drm_dev
, true, true);
633 static int amdgpu_pmops_freeze(struct device
*dev
)
635 struct pci_dev
*pdev
= to_pci_dev(dev
);
637 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
638 return amdgpu_device_suspend(drm_dev
, false, true);
641 static int amdgpu_pmops_thaw(struct device
*dev
)
643 struct pci_dev
*pdev
= to_pci_dev(dev
);
645 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
646 return amdgpu_device_resume(drm_dev
, false, true);
649 static int amdgpu_pmops_poweroff(struct device
*dev
)
651 struct pci_dev
*pdev
= to_pci_dev(dev
);
653 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
654 return amdgpu_device_suspend(drm_dev
, true, true);
657 static int amdgpu_pmops_restore(struct device
*dev
)
659 struct pci_dev
*pdev
= to_pci_dev(dev
);
661 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
662 return amdgpu_device_resume(drm_dev
, false, true);
665 static int amdgpu_pmops_runtime_suspend(struct device
*dev
)
667 struct pci_dev
*pdev
= to_pci_dev(dev
);
668 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
671 if (!amdgpu_device_is_px(drm_dev
)) {
672 pm_runtime_forbid(dev
);
676 drm_dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
677 drm_kms_helper_poll_disable(drm_dev
);
678 vga_switcheroo_set_dynamic_switch(pdev
, VGA_SWITCHEROO_OFF
);
680 ret
= amdgpu_device_suspend(drm_dev
, false, false);
681 pci_save_state(pdev
);
682 pci_disable_device(pdev
);
683 pci_ignore_hotplug(pdev
);
684 if (amdgpu_is_atpx_hybrid())
685 pci_set_power_state(pdev
, PCI_D3cold
);
686 else if (!amdgpu_has_atpx_dgpu_power_cntl())
687 pci_set_power_state(pdev
, PCI_D3hot
);
688 drm_dev
->switch_power_state
= DRM_SWITCH_POWER_DYNAMIC_OFF
;
693 static int amdgpu_pmops_runtime_resume(struct device
*dev
)
695 struct pci_dev
*pdev
= to_pci_dev(dev
);
696 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
699 if (!amdgpu_device_is_px(drm_dev
))
702 drm_dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
704 if (amdgpu_is_atpx_hybrid() ||
705 !amdgpu_has_atpx_dgpu_power_cntl())
706 pci_set_power_state(pdev
, PCI_D0
);
707 pci_restore_state(pdev
);
708 ret
= pci_enable_device(pdev
);
711 pci_set_master(pdev
);
713 ret
= amdgpu_device_resume(drm_dev
, false, false);
714 drm_kms_helper_poll_enable(drm_dev
);
715 vga_switcheroo_set_dynamic_switch(pdev
, VGA_SWITCHEROO_ON
);
716 drm_dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
720 static int amdgpu_pmops_runtime_idle(struct device
*dev
)
722 struct pci_dev
*pdev
= to_pci_dev(dev
);
723 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
724 struct drm_crtc
*crtc
;
726 if (!amdgpu_device_is_px(drm_dev
)) {
727 pm_runtime_forbid(dev
);
731 list_for_each_entry(crtc
, &drm_dev
->mode_config
.crtc_list
, head
) {
733 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
738 pm_runtime_mark_last_busy(dev
);
739 pm_runtime_autosuspend(dev
);
740 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
744 long amdgpu_drm_ioctl(struct file
*filp
,
745 unsigned int cmd
, unsigned long arg
)
747 struct drm_file
*file_priv
= filp
->private_data
;
748 struct drm_device
*dev
;
750 dev
= file_priv
->minor
->dev
;
751 ret
= pm_runtime_get_sync(dev
->dev
);
755 ret
= drm_ioctl(filp
, cmd
, arg
);
757 pm_runtime_mark_last_busy(dev
->dev
);
758 pm_runtime_put_autosuspend(dev
->dev
);
762 static const struct dev_pm_ops amdgpu_pm_ops
= {
763 .suspend
= amdgpu_pmops_suspend
,
764 .resume
= amdgpu_pmops_resume
,
765 .freeze
= amdgpu_pmops_freeze
,
766 .thaw
= amdgpu_pmops_thaw
,
767 .poweroff
= amdgpu_pmops_poweroff
,
768 .restore
= amdgpu_pmops_restore
,
769 .runtime_suspend
= amdgpu_pmops_runtime_suspend
,
770 .runtime_resume
= amdgpu_pmops_runtime_resume
,
771 .runtime_idle
= amdgpu_pmops_runtime_idle
,
774 static const struct file_operations amdgpu_driver_kms_fops
= {
775 .owner
= THIS_MODULE
,
777 .release
= drm_release
,
778 .unlocked_ioctl
= amdgpu_drm_ioctl
,
783 .compat_ioctl
= amdgpu_kms_compat_ioctl
,
788 amdgpu_get_crtc_scanout_position(struct drm_device
*dev
, unsigned int pipe
,
789 bool in_vblank_irq
, int *vpos
, int *hpos
,
790 ktime_t
*stime
, ktime_t
*etime
,
791 const struct drm_display_mode
*mode
)
793 return amdgpu_get_crtc_scanoutpos(dev
, pipe
, 0, vpos
, hpos
,
797 static struct drm_driver kms_driver
= {
800 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
|
801 DRIVER_PRIME
| DRIVER_RENDER
| DRIVER_MODESET
| DRIVER_SYNCOBJ
,
802 .load
= amdgpu_driver_load_kms
,
803 .open
= amdgpu_driver_open_kms
,
804 .postclose
= amdgpu_driver_postclose_kms
,
805 .lastclose
= amdgpu_driver_lastclose_kms
,
806 .set_busid
= drm_pci_set_busid
,
807 .unload
= amdgpu_driver_unload_kms
,
808 .get_vblank_counter
= amdgpu_get_vblank_counter_kms
,
809 .enable_vblank
= amdgpu_enable_vblank_kms
,
810 .disable_vblank
= amdgpu_disable_vblank_kms
,
811 .get_vblank_timestamp
= drm_calc_vbltimestamp_from_scanoutpos
,
812 .get_scanout_position
= amdgpu_get_crtc_scanout_position
,
813 #if defined(CONFIG_DEBUG_FS)
814 .debugfs_init
= amdgpu_debugfs_init
,
816 .irq_preinstall
= amdgpu_irq_preinstall
,
817 .irq_postinstall
= amdgpu_irq_postinstall
,
818 .irq_uninstall
= amdgpu_irq_uninstall
,
819 .irq_handler
= amdgpu_irq_handler
,
820 .ioctls
= amdgpu_ioctls_kms
,
821 .gem_free_object_unlocked
= amdgpu_gem_object_free
,
822 .gem_open_object
= amdgpu_gem_object_open
,
823 .gem_close_object
= amdgpu_gem_object_close
,
824 .dumb_create
= amdgpu_mode_dumb_create
,
825 .dumb_map_offset
= amdgpu_mode_dumb_mmap
,
826 .dumb_destroy
= drm_gem_dumb_destroy
,
827 .fops
= &amdgpu_driver_kms_fops
,
829 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
830 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
831 .gem_prime_export
= amdgpu_gem_prime_export
,
832 .gem_prime_import
= drm_gem_prime_import
,
833 .gem_prime_pin
= amdgpu_gem_prime_pin
,
834 .gem_prime_unpin
= amdgpu_gem_prime_unpin
,
835 .gem_prime_res_obj
= amdgpu_gem_prime_res_obj
,
836 .gem_prime_get_sg_table
= amdgpu_gem_prime_get_sg_table
,
837 .gem_prime_import_sg_table
= amdgpu_gem_prime_import_sg_table
,
838 .gem_prime_vmap
= amdgpu_gem_prime_vmap
,
839 .gem_prime_vunmap
= amdgpu_gem_prime_vunmap
,
844 .major
= KMS_DRIVER_MAJOR
,
845 .minor
= KMS_DRIVER_MINOR
,
846 .patchlevel
= KMS_DRIVER_PATCHLEVEL
,
849 static struct drm_driver
*driver
;
850 static struct pci_driver
*pdriver
;
852 static struct pci_driver amdgpu_kms_pci_driver
= {
854 .id_table
= pciidlist
,
855 .probe
= amdgpu_pci_probe
,
856 .remove
= amdgpu_pci_remove
,
857 .shutdown
= amdgpu_pci_shutdown
,
858 .driver
.pm
= &amdgpu_pm_ops
,
863 static int __init
amdgpu_init(void)
867 r
= amdgpu_sync_init();
871 r
= amdgpu_fence_slab_init();
875 r
= amd_sched_fence_slab_init();
879 if (vgacon_text_force()) {
880 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
883 DRM_INFO("amdgpu kernel modesetting enabled.\n");
884 driver
= &kms_driver
;
885 pdriver
= &amdgpu_kms_pci_driver
;
886 driver
->num_ioctls
= amdgpu_max_kms_ioctl
;
887 amdgpu_register_atpx_handler();
888 /* let modprobe override vga console setting */
889 return pci_register_driver(pdriver
);
892 amdgpu_fence_slab_fini();
901 static void __exit
amdgpu_exit(void)
903 amdgpu_amdkfd_fini();
904 pci_unregister_driver(pdriver
);
905 amdgpu_unregister_atpx_handler();
907 amd_sched_fence_slab_fini();
908 amdgpu_fence_slab_fini();
911 module_init(amdgpu_init
);
912 module_exit(amdgpu_exit
);
914 MODULE_AUTHOR(DRIVER_AUTHOR
);
915 MODULE_DESCRIPTION(DRIVER_DESC
);
916 MODULE_LICENSE("GPL and additional rights");