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1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/ktime.h>
29 #include <linux/module.h>
30 #include <linux/pagemap.h>
31 #include <linux/pci.h>
32
33 #include <drm/amdgpu_drm.h>
34 #include <drm/drm_debugfs.h>
35
36 #include "amdgpu.h"
37 #include "amdgpu_display.h"
38 #include "amdgpu_xgmi.h"
39
40 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
41 {
42 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
43
44 if (robj) {
45 amdgpu_mn_unregister(robj);
46 amdgpu_bo_unref(&robj);
47 }
48 }
49
50 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
51 int alignment, u32 initial_domain,
52 u64 flags, enum ttm_bo_type type,
53 struct reservation_object *resv,
54 struct drm_gem_object **obj)
55 {
56 struct amdgpu_bo *bo;
57 struct amdgpu_bo_param bp;
58 int r;
59
60 memset(&bp, 0, sizeof(bp));
61 *obj = NULL;
62
63 bp.size = size;
64 bp.byte_align = alignment;
65 bp.type = type;
66 bp.resv = resv;
67 bp.preferred_domain = initial_domain;
68 retry:
69 bp.flags = flags;
70 bp.domain = initial_domain;
71 r = amdgpu_bo_create(adev, &bp, &bo);
72 if (r) {
73 if (r != -ERESTARTSYS) {
74 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
75 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
76 goto retry;
77 }
78
79 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
80 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
81 goto retry;
82 }
83 DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
84 size, initial_domain, alignment, r);
85 }
86 return r;
87 }
88 *obj = &bo->gem_base;
89
90 return 0;
91 }
92
93 void amdgpu_gem_force_release(struct amdgpu_device *adev)
94 {
95 struct drm_device *ddev = adev->ddev;
96 struct drm_file *file;
97
98 mutex_lock(&ddev->filelist_mutex);
99
100 list_for_each_entry(file, &ddev->filelist, lhead) {
101 struct drm_gem_object *gobj;
102 int handle;
103
104 WARN_ONCE(1, "Still active user space clients!\n");
105 spin_lock(&file->table_lock);
106 idr_for_each_entry(&file->object_idr, gobj, handle) {
107 WARN_ONCE(1, "And also active allocations!\n");
108 drm_gem_object_put_unlocked(gobj);
109 }
110 idr_destroy(&file->object_idr);
111 spin_unlock(&file->table_lock);
112 }
113
114 mutex_unlock(&ddev->filelist_mutex);
115 }
116
117 /*
118 * Call from drm_gem_handle_create which appear in both new and open ioctl
119 * case.
120 */
121 int amdgpu_gem_object_open(struct drm_gem_object *obj,
122 struct drm_file *file_priv)
123 {
124 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
125 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
126 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
127 struct amdgpu_vm *vm = &fpriv->vm;
128 struct amdgpu_bo_va *bo_va;
129 struct mm_struct *mm;
130 int r;
131
132 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
133 if (mm && mm != current->mm)
134 return -EPERM;
135
136 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
137 abo->tbo.resv != vm->root.base.bo->tbo.resv)
138 return -EPERM;
139
140 r = amdgpu_bo_reserve(abo, false);
141 if (r)
142 return r;
143
144 bo_va = amdgpu_vm_bo_find(vm, abo);
145 if (!bo_va) {
146 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
147 } else {
148 ++bo_va->ref_count;
149 }
150 amdgpu_bo_unreserve(abo);
151 return 0;
152 }
153
154 void amdgpu_gem_object_close(struct drm_gem_object *obj,
155 struct drm_file *file_priv)
156 {
157 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
158 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
159 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
160 struct amdgpu_vm *vm = &fpriv->vm;
161
162 struct amdgpu_bo_list_entry vm_pd;
163 struct list_head list, duplicates;
164 struct ttm_validate_buffer tv;
165 struct ww_acquire_ctx ticket;
166 struct amdgpu_bo_va *bo_va;
167 int r;
168
169 INIT_LIST_HEAD(&list);
170 INIT_LIST_HEAD(&duplicates);
171
172 tv.bo = &bo->tbo;
173 tv.num_shared = 1;
174 list_add(&tv.head, &list);
175
176 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
177
178 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates, false);
179 if (r) {
180 dev_err(adev->dev, "leaking bo va because "
181 "we fail to reserve bo (%d)\n", r);
182 return;
183 }
184 bo_va = amdgpu_vm_bo_find(vm, bo);
185 if (bo_va && --bo_va->ref_count == 0) {
186 amdgpu_vm_bo_rmv(adev, bo_va);
187
188 if (amdgpu_vm_ready(vm)) {
189 struct dma_fence *fence = NULL;
190
191 r = amdgpu_vm_clear_freed(adev, vm, &fence);
192 if (unlikely(r)) {
193 dev_err(adev->dev, "failed to clear page "
194 "tables on GEM object close (%d)\n", r);
195 }
196
197 if (fence) {
198 amdgpu_bo_fence(bo, fence, true);
199 dma_fence_put(fence);
200 }
201 }
202 }
203 ttm_eu_backoff_reservation(&ticket, &list);
204 }
205
206 /*
207 * GEM ioctls.
208 */
209 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
210 struct drm_file *filp)
211 {
212 struct amdgpu_device *adev = dev->dev_private;
213 struct amdgpu_fpriv *fpriv = filp->driver_priv;
214 struct amdgpu_vm *vm = &fpriv->vm;
215 union drm_amdgpu_gem_create *args = data;
216 uint64_t flags = args->in.domain_flags;
217 uint64_t size = args->in.bo_size;
218 struct reservation_object *resv = NULL;
219 struct drm_gem_object *gobj;
220 uint32_t handle;
221 int r;
222
223 /* reject invalid gem flags */
224 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
225 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
226 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
227 AMDGPU_GEM_CREATE_VRAM_CLEARED |
228 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
229 AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
230
231 return -EINVAL;
232
233 /* reject invalid gem domains */
234 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
235 return -EINVAL;
236
237 /* create a gem object to contain this object in */
238 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
239 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
240 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
241 /* if gds bo is created from user space, it must be
242 * passed to bo list
243 */
244 DRM_ERROR("GDS bo cannot be per-vm-bo\n");
245 return -EINVAL;
246 }
247 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
248 }
249
250 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
251 r = amdgpu_bo_reserve(vm->root.base.bo, false);
252 if (r)
253 return r;
254
255 resv = vm->root.base.bo->tbo.resv;
256 }
257
258 r = amdgpu_gem_object_create(adev, size, args->in.alignment,
259 (u32)(0xffffffff & args->in.domains),
260 flags, ttm_bo_type_device, resv, &gobj);
261 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
262 if (!r) {
263 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
264
265 abo->parent = amdgpu_bo_ref(vm->root.base.bo);
266 }
267 amdgpu_bo_unreserve(vm->root.base.bo);
268 }
269 if (r)
270 return r;
271
272 r = drm_gem_handle_create(filp, gobj, &handle);
273 /* drop reference from allocate - handle holds it now */
274 drm_gem_object_put_unlocked(gobj);
275 if (r)
276 return r;
277
278 memset(args, 0, sizeof(*args));
279 args->out.handle = handle;
280 return 0;
281 }
282
283 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
284 struct drm_file *filp)
285 {
286 struct ttm_operation_ctx ctx = { true, false };
287 struct amdgpu_device *adev = dev->dev_private;
288 struct drm_amdgpu_gem_userptr *args = data;
289 struct drm_gem_object *gobj;
290 struct amdgpu_bo *bo;
291 uint32_t handle;
292 int r;
293
294 if (offset_in_page(args->addr | args->size))
295 return -EINVAL;
296
297 /* reject unknown flag values */
298 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
299 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
300 AMDGPU_GEM_USERPTR_REGISTER))
301 return -EINVAL;
302
303 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
304 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
305
306 /* if we want to write to it we must install a MMU notifier */
307 return -EACCES;
308 }
309
310 /* create a gem object to contain this object in */
311 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
312 0, ttm_bo_type_device, NULL, &gobj);
313 if (r)
314 return r;
315
316 bo = gem_to_amdgpu_bo(gobj);
317 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
318 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
319 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
320 if (r)
321 goto release_object;
322
323 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
324 r = amdgpu_mn_register(bo, args->addr);
325 if (r)
326 goto release_object;
327 }
328
329 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
330 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
331 bo->tbo.ttm->pages);
332 if (r)
333 goto release_object;
334
335 r = amdgpu_bo_reserve(bo, true);
336 if (r)
337 goto user_pages_done;
338
339 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
340 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
341 amdgpu_bo_unreserve(bo);
342 if (r)
343 goto user_pages_done;
344 }
345
346 r = drm_gem_handle_create(filp, gobj, &handle);
347 if (r)
348 goto user_pages_done;
349
350 args->handle = handle;
351
352 user_pages_done:
353 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE)
354 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
355
356 release_object:
357 drm_gem_object_put_unlocked(gobj);
358
359 return r;
360 }
361
362 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
363 struct drm_device *dev,
364 uint32_t handle, uint64_t *offset_p)
365 {
366 struct drm_gem_object *gobj;
367 struct amdgpu_bo *robj;
368
369 gobj = drm_gem_object_lookup(filp, handle);
370 if (gobj == NULL) {
371 return -ENOENT;
372 }
373 robj = gem_to_amdgpu_bo(gobj);
374 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
375 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
376 drm_gem_object_put_unlocked(gobj);
377 return -EPERM;
378 }
379 *offset_p = amdgpu_bo_mmap_offset(robj);
380 drm_gem_object_put_unlocked(gobj);
381 return 0;
382 }
383
384 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
385 struct drm_file *filp)
386 {
387 union drm_amdgpu_gem_mmap *args = data;
388 uint32_t handle = args->in.handle;
389 memset(args, 0, sizeof(*args));
390 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
391 }
392
393 /**
394 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
395 *
396 * @timeout_ns: timeout in ns
397 *
398 * Calculate the timeout in jiffies from an absolute timeout in ns.
399 */
400 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
401 {
402 unsigned long timeout_jiffies;
403 ktime_t timeout;
404
405 /* clamp timeout if it's to large */
406 if (((int64_t)timeout_ns) < 0)
407 return MAX_SCHEDULE_TIMEOUT;
408
409 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
410 if (ktime_to_ns(timeout) < 0)
411 return 0;
412
413 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
414 /* clamp timeout to avoid unsigned-> signed overflow */
415 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
416 return MAX_SCHEDULE_TIMEOUT - 1;
417
418 return timeout_jiffies;
419 }
420
421 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
422 struct drm_file *filp)
423 {
424 union drm_amdgpu_gem_wait_idle *args = data;
425 struct drm_gem_object *gobj;
426 struct amdgpu_bo *robj;
427 uint32_t handle = args->in.handle;
428 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
429 int r = 0;
430 long ret;
431
432 gobj = drm_gem_object_lookup(filp, handle);
433 if (gobj == NULL) {
434 return -ENOENT;
435 }
436 robj = gem_to_amdgpu_bo(gobj);
437 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true,
438 timeout);
439
440 /* ret == 0 means not signaled,
441 * ret > 0 means signaled
442 * ret < 0 means interrupted before timeout
443 */
444 if (ret >= 0) {
445 memset(args, 0, sizeof(*args));
446 args->out.status = (ret == 0);
447 } else
448 r = ret;
449
450 drm_gem_object_put_unlocked(gobj);
451 return r;
452 }
453
454 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
455 struct drm_file *filp)
456 {
457 struct drm_amdgpu_gem_metadata *args = data;
458 struct drm_gem_object *gobj;
459 struct amdgpu_bo *robj;
460 int r = -1;
461
462 DRM_DEBUG("%d \n", args->handle);
463 gobj = drm_gem_object_lookup(filp, args->handle);
464 if (gobj == NULL)
465 return -ENOENT;
466 robj = gem_to_amdgpu_bo(gobj);
467
468 r = amdgpu_bo_reserve(robj, false);
469 if (unlikely(r != 0))
470 goto out;
471
472 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
473 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
474 r = amdgpu_bo_get_metadata(robj, args->data.data,
475 sizeof(args->data.data),
476 &args->data.data_size_bytes,
477 &args->data.flags);
478 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
479 if (args->data.data_size_bytes > sizeof(args->data.data)) {
480 r = -EINVAL;
481 goto unreserve;
482 }
483 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
484 if (!r)
485 r = amdgpu_bo_set_metadata(robj, args->data.data,
486 args->data.data_size_bytes,
487 args->data.flags);
488 }
489
490 unreserve:
491 amdgpu_bo_unreserve(robj);
492 out:
493 drm_gem_object_put_unlocked(gobj);
494 return r;
495 }
496
497 /**
498 * amdgpu_gem_va_update_vm -update the bo_va in its VM
499 *
500 * @adev: amdgpu_device pointer
501 * @vm: vm to update
502 * @bo_va: bo_va to update
503 * @operation: map, unmap or clear
504 *
505 * Update the bo_va directly after setting its address. Errors are not
506 * vital here, so they are not reported back to userspace.
507 */
508 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
509 struct amdgpu_vm *vm,
510 struct amdgpu_bo_va *bo_va,
511 uint32_t operation)
512 {
513 int r;
514
515 if (!amdgpu_vm_ready(vm))
516 return;
517
518 r = amdgpu_vm_clear_freed(adev, vm, NULL);
519 if (r)
520 goto error;
521
522 if (operation == AMDGPU_VA_OP_MAP ||
523 operation == AMDGPU_VA_OP_REPLACE) {
524 r = amdgpu_vm_bo_update(adev, bo_va, false);
525 if (r)
526 goto error;
527 }
528
529 r = amdgpu_vm_update_directories(adev, vm);
530
531 error:
532 if (r && r != -ERESTARTSYS)
533 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
534 }
535
536 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
537 struct drm_file *filp)
538 {
539 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
540 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
541 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK;
542 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
543 AMDGPU_VM_PAGE_PRT;
544
545 struct drm_amdgpu_gem_va *args = data;
546 struct drm_gem_object *gobj;
547 struct amdgpu_device *adev = dev->dev_private;
548 struct amdgpu_fpriv *fpriv = filp->driver_priv;
549 struct amdgpu_bo *abo;
550 struct amdgpu_bo_va *bo_va;
551 struct amdgpu_bo_list_entry vm_pd;
552 struct ttm_validate_buffer tv;
553 struct ww_acquire_ctx ticket;
554 struct list_head list, duplicates;
555 uint64_t va_flags;
556 int r = 0;
557
558 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
559 dev_dbg(&dev->pdev->dev,
560 "va_address 0x%LX is in reserved area 0x%LX\n",
561 args->va_address, AMDGPU_VA_RESERVED_SIZE);
562 return -EINVAL;
563 }
564
565 if (args->va_address >= AMDGPU_GMC_HOLE_START &&
566 args->va_address < AMDGPU_GMC_HOLE_END) {
567 dev_dbg(&dev->pdev->dev,
568 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
569 args->va_address, AMDGPU_GMC_HOLE_START,
570 AMDGPU_GMC_HOLE_END);
571 return -EINVAL;
572 }
573
574 args->va_address &= AMDGPU_GMC_HOLE_MASK;
575
576 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
577 dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
578 args->flags);
579 return -EINVAL;
580 }
581
582 switch (args->operation) {
583 case AMDGPU_VA_OP_MAP:
584 case AMDGPU_VA_OP_UNMAP:
585 case AMDGPU_VA_OP_CLEAR:
586 case AMDGPU_VA_OP_REPLACE:
587 break;
588 default:
589 dev_dbg(&dev->pdev->dev, "unsupported operation %d\n",
590 args->operation);
591 return -EINVAL;
592 }
593
594 INIT_LIST_HEAD(&list);
595 INIT_LIST_HEAD(&duplicates);
596 if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
597 !(args->flags & AMDGPU_VM_PAGE_PRT)) {
598 gobj = drm_gem_object_lookup(filp, args->handle);
599 if (gobj == NULL)
600 return -ENOENT;
601 abo = gem_to_amdgpu_bo(gobj);
602 tv.bo = &abo->tbo;
603 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
604 tv.num_shared = 1;
605 else
606 tv.num_shared = 0;
607 list_add(&tv.head, &list);
608 } else {
609 gobj = NULL;
610 abo = NULL;
611 }
612
613 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
614
615 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates, false);
616 if (r)
617 goto error_unref;
618
619 if (abo) {
620 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
621 if (!bo_va) {
622 r = -ENOENT;
623 goto error_backoff;
624 }
625 } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
626 bo_va = fpriv->prt_va;
627 } else {
628 bo_va = NULL;
629 }
630
631 switch (args->operation) {
632 case AMDGPU_VA_OP_MAP:
633 va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags);
634 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
635 args->offset_in_bo, args->map_size,
636 va_flags);
637 break;
638 case AMDGPU_VA_OP_UNMAP:
639 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
640 break;
641
642 case AMDGPU_VA_OP_CLEAR:
643 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
644 args->va_address,
645 args->map_size);
646 break;
647 case AMDGPU_VA_OP_REPLACE:
648 va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags);
649 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
650 args->offset_in_bo, args->map_size,
651 va_flags);
652 break;
653 default:
654 break;
655 }
656 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
657 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va,
658 args->operation);
659
660 error_backoff:
661 ttm_eu_backoff_reservation(&ticket, &list);
662
663 error_unref:
664 drm_gem_object_put_unlocked(gobj);
665 return r;
666 }
667
668 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
669 struct drm_file *filp)
670 {
671 struct amdgpu_device *adev = dev->dev_private;
672 struct drm_amdgpu_gem_op *args = data;
673 struct drm_gem_object *gobj;
674 struct amdgpu_vm_bo_base *base;
675 struct amdgpu_bo *robj;
676 int r;
677
678 gobj = drm_gem_object_lookup(filp, args->handle);
679 if (gobj == NULL) {
680 return -ENOENT;
681 }
682 robj = gem_to_amdgpu_bo(gobj);
683
684 r = amdgpu_bo_reserve(robj, false);
685 if (unlikely(r))
686 goto out;
687
688 switch (args->op) {
689 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
690 struct drm_amdgpu_gem_create_in info;
691 void __user *out = u64_to_user_ptr(args->value);
692
693 info.bo_size = robj->gem_base.size;
694 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
695 info.domains = robj->preferred_domains;
696 info.domain_flags = robj->flags;
697 amdgpu_bo_unreserve(robj);
698 if (copy_to_user(out, &info, sizeof(info)))
699 r = -EFAULT;
700 break;
701 }
702 case AMDGPU_GEM_OP_SET_PLACEMENT:
703 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) {
704 r = -EINVAL;
705 amdgpu_bo_unreserve(robj);
706 break;
707 }
708 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
709 r = -EPERM;
710 amdgpu_bo_unreserve(robj);
711 break;
712 }
713 for (base = robj->vm_bo; base; base = base->next)
714 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev),
715 amdgpu_ttm_adev(base->vm->root.base.bo->tbo.bdev))) {
716 r = -EINVAL;
717 amdgpu_bo_unreserve(robj);
718 goto out;
719 }
720
721
722 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
723 AMDGPU_GEM_DOMAIN_GTT |
724 AMDGPU_GEM_DOMAIN_CPU);
725 robj->allowed_domains = robj->preferred_domains;
726 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
727 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
728
729 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
730 amdgpu_vm_bo_invalidate(adev, robj, true);
731
732 amdgpu_bo_unreserve(robj);
733 break;
734 default:
735 amdgpu_bo_unreserve(robj);
736 r = -EINVAL;
737 }
738
739 out:
740 drm_gem_object_put_unlocked(gobj);
741 return r;
742 }
743
744 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
745 struct drm_device *dev,
746 struct drm_mode_create_dumb *args)
747 {
748 struct amdgpu_device *adev = dev->dev_private;
749 struct drm_gem_object *gobj;
750 uint32_t handle;
751 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
752 u32 domain;
753 int r;
754
755 /*
756 * The buffer returned from this function should be cleared, but
757 * it can only be done if the ring is enabled or we'll fail to
758 * create the buffer.
759 */
760 if (adev->mman.buffer_funcs_enabled)
761 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;
762
763 args->pitch = amdgpu_align_pitch(adev, args->width,
764 DIV_ROUND_UP(args->bpp, 8), 0);
765 args->size = (u64)args->pitch * args->height;
766 args->size = ALIGN(args->size, PAGE_SIZE);
767 domain = amdgpu_bo_get_preferred_pin_domain(adev,
768 amdgpu_display_supported_domains(adev));
769 r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags,
770 ttm_bo_type_device, NULL, &gobj);
771 if (r)
772 return -ENOMEM;
773
774 r = drm_gem_handle_create(file_priv, gobj, &handle);
775 /* drop reference from allocate - handle holds it now */
776 drm_gem_object_put_unlocked(gobj);
777 if (r) {
778 return r;
779 }
780 args->handle = handle;
781 return 0;
782 }
783
784 #if defined(CONFIG_DEBUG_FS)
785
786 #define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag) \
787 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \
788 seq_printf((m), " " #flag); \
789 }
790
791 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
792 {
793 struct drm_gem_object *gobj = ptr;
794 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
795 struct seq_file *m = data;
796
797 struct dma_buf_attachment *attachment;
798 struct dma_buf *dma_buf;
799 unsigned domain;
800 const char *placement;
801 unsigned pin_count;
802
803 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
804 switch (domain) {
805 case AMDGPU_GEM_DOMAIN_VRAM:
806 placement = "VRAM";
807 break;
808 case AMDGPU_GEM_DOMAIN_GTT:
809 placement = " GTT";
810 break;
811 case AMDGPU_GEM_DOMAIN_CPU:
812 default:
813 placement = " CPU";
814 break;
815 }
816 seq_printf(m, "\t0x%08x: %12ld byte %s",
817 id, amdgpu_bo_size(bo), placement);
818
819 pin_count = READ_ONCE(bo->pin_count);
820 if (pin_count)
821 seq_printf(m, " pin count %d", pin_count);
822
823 dma_buf = READ_ONCE(bo->gem_base.dma_buf);
824 attachment = READ_ONCE(bo->gem_base.import_attach);
825
826 if (attachment)
827 seq_printf(m, " imported from %p", dma_buf);
828 else if (dma_buf)
829 seq_printf(m, " exported as %p", dma_buf);
830
831 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED);
832 amdgpu_debugfs_gem_bo_print_flag(m, bo, NO_CPU_ACCESS);
833 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_GTT_USWC);
834 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CLEARED);
835 amdgpu_debugfs_gem_bo_print_flag(m, bo, SHADOW);
836 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
837 amdgpu_debugfs_gem_bo_print_flag(m, bo, VM_ALWAYS_VALID);
838 amdgpu_debugfs_gem_bo_print_flag(m, bo, EXPLICIT_SYNC);
839
840 seq_printf(m, "\n");
841
842 return 0;
843 }
844
845 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
846 {
847 struct drm_info_node *node = (struct drm_info_node *)m->private;
848 struct drm_device *dev = node->minor->dev;
849 struct drm_file *file;
850 int r;
851
852 r = mutex_lock_interruptible(&dev->filelist_mutex);
853 if (r)
854 return r;
855
856 list_for_each_entry(file, &dev->filelist, lhead) {
857 struct task_struct *task;
858
859 /*
860 * Although we have a valid reference on file->pid, that does
861 * not guarantee that the task_struct who called get_pid() is
862 * still alive (e.g. get_pid(current) => fork() => exit()).
863 * Therefore, we need to protect this ->comm access using RCU.
864 */
865 rcu_read_lock();
866 task = pid_task(file->pid, PIDTYPE_PID);
867 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
868 task ? task->comm : "<unknown>");
869 rcu_read_unlock();
870
871 spin_lock(&file->table_lock);
872 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
873 spin_unlock(&file->table_lock);
874 }
875
876 mutex_unlock(&dev->filelist_mutex);
877 return 0;
878 }
879
880 static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
881 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
882 };
883 #endif
884
885 int amdgpu_debugfs_gem_init(struct amdgpu_device *adev)
886 {
887 #if defined(CONFIG_DEBUG_FS)
888 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);
889 #endif
890 return 0;
891 }