drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/ktime.h>
  29 #include <linux/pagemap.h>
  30 #include <drm/drmP.h>
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu.h"
  33
  34 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
  35 {
  36         struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
  37
  38         if (robj) {
  39                 if (robj->gem_base.import_attach)
  40                         drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
  41                 amdgpu_mn_unregister(robj);
  42                 amdgpu_bo_unref(&robj);
  43         }
  44 }
  45
  46 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
  47                                 int alignment, u32 initial_domain,
  48                                 u64 flags, bool kernel,
  49                                 struct drm_gem_object **obj)
  50 {
  51         struct amdgpu_bo *robj;
  52         unsigned long max_size;
  53         int r;
  54
  55         *obj = NULL;
  56         /* At least align on page size */
  57         if (alignment < PAGE_SIZE) {
  58                 alignment = PAGE_SIZE;
  59         }
  60
  61         if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) {
  62                 /* Maximum bo size is the unpinned gtt size since we use the gtt to
  63                  * handle vram to system pool migrations.
  64                  */
  65                 max_size = adev->mc.gtt_size - adev->gart_pin_size;
  66                 if (size > max_size) {
  67                         DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n",
  68                                   size >> 20, max_size >> 20);
  69                         return -ENOMEM;
  70                 }
  71         }
  72 retry:
  73         r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
  74                              flags, NULL, NULL, &robj);
  75         if (r) {
  76                 if (r != -ERESTARTSYS) {
  77                         if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
  78                                 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
  79                                 goto retry;
  80                         }
  81                         DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
  82                                   size, initial_domain, alignment, r);
  83                 }
  84                 return r;
  85         }
  86         *obj = &robj->gem_base;
  87
  88         return 0;
  89 }
  90
  91 void amdgpu_gem_force_release(struct amdgpu_device *adev)
  92 {
  93         struct drm_device *ddev = adev->ddev;
  94         struct drm_file *file;
  95
  96         mutex_lock(&ddev->filelist_mutex);
  97
  98         list_for_each_entry(file, &ddev->filelist, lhead) {
  99                 struct drm_gem_object *gobj;
 100                 int handle;
 101
 102                 WARN_ONCE(1, "Still active user space clients!\n");
 103                 spin_lock(&file->table_lock);
 104                 idr_for_each_entry(&file->object_idr, gobj, handle) {
 105                         WARN_ONCE(1, "And also active allocations!\n");
 106                         drm_gem_object_unreference_unlocked(gobj);
 107                 }
 108                 idr_destroy(&file->object_idr);
 109                 spin_unlock(&file->table_lock);
 110         }
 111
 112         mutex_unlock(&ddev->filelist_mutex);
 113 }
 114
 115 /*
 116  * Call from drm_gem_handle_create which appear in both new and open ioctl
 117  * case.
 118  */
 119 int amdgpu_gem_object_open(struct drm_gem_object *obj,
 120                            struct drm_file *file_priv)
 121 {
 122         struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
 123         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
 124         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 125         struct amdgpu_vm *vm = &fpriv->vm;
 126         struct amdgpu_bo_va *bo_va;
 127         int r;
 128         r = amdgpu_bo_reserve(abo, false);
 129         if (r)
 130                 return r;
 131
 132         bo_va = amdgpu_vm_bo_find(vm, abo);
 133         if (!bo_va) {
 134                 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
 135         } else {
 136                 ++bo_va->ref_count;
 137         }
 138         amdgpu_bo_unreserve(abo);
 139         return 0;
 140 }
 141
 142 void amdgpu_gem_object_close(struct drm_gem_object *obj,
 143                              struct drm_file *file_priv)
 144 {
 145         struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 146         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 147         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 148         struct amdgpu_vm *vm = &fpriv->vm;
 149
 150         struct amdgpu_bo_list_entry vm_pd;
 151         struct list_head list, duplicates;
 152         struct ttm_validate_buffer tv;
 153         struct ww_acquire_ctx ticket;
 154         struct amdgpu_bo_va *bo_va;
 155         int r;
 156
 157         INIT_LIST_HEAD(&list);
 158         INIT_LIST_HEAD(&duplicates);
 159
 160         tv.bo = &bo->tbo;
 161         tv.shared = true;
 162         list_add(&tv.head, &list);
 163
 164         amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
 165
 166         r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
 167         if (r) {
 168                 dev_err(adev->dev, "leaking bo va because "
 169                         "we fail to reserve bo (%d)\n", r);
 170                 return;
 171         }
 172         bo_va = amdgpu_vm_bo_find(vm, bo);
 173         if (bo_va) {
 174                 if (--bo_va->ref_count == 0) {
 175                         amdgpu_vm_bo_rmv(adev, bo_va);
 176                 }
 177         }
 178         ttm_eu_backoff_reservation(&ticket, &list);
 179 }
 180
 181 static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r)
 182 {
 183         if (r == -EDEADLK) {
 184                 r = amdgpu_gpu_reset(adev);
 185                 if (!r)
 186                         r = -EAGAIN;
 187         }
 188         return r;
 189 }
 190
 191 /*
 192  * GEM ioctls.
 193  */
 194 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
 195                             struct drm_file *filp)
 196 {
 197         struct amdgpu_device *adev = dev->dev_private;
 198         union drm_amdgpu_gem_create *args = data;
 199         uint64_t size = args->in.bo_size;
 200         struct drm_gem_object *gobj;
 201         uint32_t handle;
 202         bool kernel = false;
 203         int r;
 204
 205         /* create a gem object to contain this object in */
 206         if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
 207             AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
 208                 kernel = true;
 209                 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
 210                         size = size << AMDGPU_GDS_SHIFT;
 211                 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
 212                         size = size << AMDGPU_GWS_SHIFT;
 213                 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
 214                         size = size << AMDGPU_OA_SHIFT;
 215                 else {
 216                         r = -EINVAL;
 217                         goto error_unlock;
 218                 }
 219         }
 220         size = roundup(size, PAGE_SIZE);
 221
 222         r = amdgpu_gem_object_create(adev, size, args->in.alignment,
 223                                      (u32)(0xffffffff & args->in.domains),
 224                                      args->in.domain_flags,
 225                                      kernel, &gobj);
 226         if (r)
 227                 goto error_unlock;
 228
 229         r = drm_gem_handle_create(filp, gobj, &handle);
 230         /* drop reference from allocate - handle holds it now */
 231         drm_gem_object_unreference_unlocked(gobj);
 232         if (r)
 233                 goto error_unlock;
 234
 235         memset(args, 0, sizeof(*args));
 236         args->out.handle = handle;
 237         return 0;
 238
 239 error_unlock:
 240         r = amdgpu_gem_handle_lockup(adev, r);
 241         return r;
 242 }
 243
 244 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
 245                              struct drm_file *filp)
 246 {
 247         struct amdgpu_device *adev = dev->dev_private;
 248         struct drm_amdgpu_gem_userptr *args = data;
 249         struct drm_gem_object *gobj;
 250         struct amdgpu_bo *bo;
 251         uint32_t handle;
 252         int r;
 253
 254         if (offset_in_page(args->addr | args->size))
 255                 return -EINVAL;
 256
 257         /* reject unknown flag values */
 258         if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
 259             AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
 260             AMDGPU_GEM_USERPTR_REGISTER))
 261                 return -EINVAL;
 262
 263         if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
 264              !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
 265
 266                 /* if we want to write to it we must install a MMU notifier */
 267                 return -EACCES;
 268         }
 269
 270         /* create a gem object to contain this object in */
 271         r = amdgpu_gem_object_create(adev, args->size, 0,
 272                                      AMDGPU_GEM_DOMAIN_CPU, 0,
 273                                      0, &gobj);
 274         if (r)
 275                 goto handle_lockup;
 276
 277         bo = gem_to_amdgpu_bo(gobj);
 278         bo->prefered_domains = AMDGPU_GEM_DOMAIN_GTT;
 279         bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
 280         r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
 281         if (r)
 282                 goto release_object;
 283
 284         if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
 285                 r = amdgpu_mn_register(bo, args->addr);
 286                 if (r)
 287                         goto release_object;
 288         }
 289
 290         if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
 291                 down_read(&current->mm->mmap_sem);
 292
 293                 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
 294                                                  bo->tbo.ttm->pages);
 295                 if (r)
 296                         goto unlock_mmap_sem;
 297
 298                 r = amdgpu_bo_reserve(bo, true);
 299                 if (r)
 300                         goto free_pages;
 301
 302                 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
 303                 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 304                 amdgpu_bo_unreserve(bo);
 305                 if (r)
 306                         goto free_pages;
 307
 308                 up_read(&current->mm->mmap_sem);
 309         }
 310
 311         r = drm_gem_handle_create(filp, gobj, &handle);
 312         /* drop reference from allocate - handle holds it now */
 313         drm_gem_object_unreference_unlocked(gobj);
 314         if (r)
 315                 goto handle_lockup;
 316
 317         args->handle = handle;
 318         return 0;
 319
 320 free_pages:
 321         release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages, false);
 322
 323 unlock_mmap_sem:
 324         up_read(&current->mm->mmap_sem);
 325
 326 release_object:
 327         drm_gem_object_unreference_unlocked(gobj);
 328
 329 handle_lockup:
 330         r = amdgpu_gem_handle_lockup(adev, r);
 331
 332         return r;
 333 }
 334
 335 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
 336                           struct drm_device *dev,
 337                           uint32_t handle, uint64_t *offset_p)
 338 {
 339         struct drm_gem_object *gobj;
 340         struct amdgpu_bo *robj;
 341
 342         gobj = drm_gem_object_lookup(filp, handle);
 343         if (gobj == NULL) {
 344                 return -ENOENT;
 345         }
 346         robj = gem_to_amdgpu_bo(gobj);
 347         if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
 348             (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
 349                 drm_gem_object_unreference_unlocked(gobj);
 350                 return -EPERM;
 351         }
 352         *offset_p = amdgpu_bo_mmap_offset(robj);
 353         drm_gem_object_unreference_unlocked(gobj);
 354         return 0;
 355 }
 356
 357 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
 358                           struct drm_file *filp)
 359 {
 360         union drm_amdgpu_gem_mmap *args = data;
 361         uint32_t handle = args->in.handle;
 362         memset(args, 0, sizeof(*args));
 363         return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
 364 }
 365
 366 /**
 367  * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
 368  *
 369  * @timeout_ns: timeout in ns
 370  *
 371  * Calculate the timeout in jiffies from an absolute timeout in ns.
 372  */
 373 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
 374 {
 375         unsigned long timeout_jiffies;
 376         ktime_t timeout;
 377
 378         /* clamp timeout if it's to large */
 379         if (((int64_t)timeout_ns) < 0)
 380                 return MAX_SCHEDULE_TIMEOUT;
 381
 382         timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
 383         if (ktime_to_ns(timeout) < 0)
 384                 return 0;
 385
 386         timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
 387         /*  clamp timeout to avoid unsigned-> signed overflow */
 388         if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
 389                 return MAX_SCHEDULE_TIMEOUT - 1;
 390
 391         return timeout_jiffies;
 392 }
 393
 394 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 395                               struct drm_file *filp)
 396 {
 397         struct amdgpu_device *adev = dev->dev_private;
 398         union drm_amdgpu_gem_wait_idle *args = data;
 399         struct drm_gem_object *gobj;
 400         struct amdgpu_bo *robj;
 401         uint32_t handle = args->in.handle;
 402         unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
 403         int r = 0;
 404         long ret;
 405
 406         gobj = drm_gem_object_lookup(filp, handle);
 407         if (gobj == NULL) {
 408                 return -ENOENT;
 409         }
 410         robj = gem_to_amdgpu_bo(gobj);
 411         ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true,
 412                                                   timeout);
 413
 414         /* ret == 0 means not signaled,
 415          * ret > 0 means signaled
 416          * ret < 0 means interrupted before timeout
 417          */
 418         if (ret >= 0) {
 419                 memset(args, 0, sizeof(*args));
 420                 args->out.status = (ret == 0);
 421         } else
 422                 r = ret;
 423
 424         drm_gem_object_unreference_unlocked(gobj);
 425         r = amdgpu_gem_handle_lockup(adev, r);
 426         return r;
 427 }
 428
 429 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
 430                                 struct drm_file *filp)
 431 {
 432         struct drm_amdgpu_gem_metadata *args = data;
 433         struct drm_gem_object *gobj;
 434         struct amdgpu_bo *robj;
 435         int r = -1;
 436
 437         DRM_DEBUG("%d \n", args->handle);
 438         gobj = drm_gem_object_lookup(filp, args->handle);
 439         if (gobj == NULL)
 440                 return -ENOENT;
 441         robj = gem_to_amdgpu_bo(gobj);
 442
 443         r = amdgpu_bo_reserve(robj, false);
 444         if (unlikely(r != 0))
 445                 goto out;
 446
 447         if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
 448                 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
 449                 r = amdgpu_bo_get_metadata(robj, args->data.data,
 450                                            sizeof(args->data.data),
 451                                            &args->data.data_size_bytes,
 452                                            &args->data.flags);
 453         } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
 454                 if (args->data.data_size_bytes > sizeof(args->data.data)) {
 455                         r = -EINVAL;
 456                         goto unreserve;
 457                 }
 458                 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
 459                 if (!r)
 460                         r = amdgpu_bo_set_metadata(robj, args->data.data,
 461                                                    args->data.data_size_bytes,
 462                                                    args->data.flags);
 463         }
 464
 465 unreserve:
 466         amdgpu_bo_unreserve(robj);
 467 out:
 468         drm_gem_object_unreference_unlocked(gobj);
 469         return r;
 470 }
 471
 472 static int amdgpu_gem_va_check(void *param, struct amdgpu_bo *bo)
 473 {
 474         /* if anything is swapped out don't swap it in here,
 475            just abort and wait for the next CS */
 476         if (!amdgpu_bo_gpu_accessible(bo))
 477                 return -ERESTARTSYS;
 478
 479         if (bo->shadow && !amdgpu_bo_gpu_accessible(bo->shadow))
 480                 return -ERESTARTSYS;
 481
 482         return 0;
 483 }
 484
 485 /**
 486  * amdgpu_gem_va_update_vm -update the bo_va in its VM
 487  *
 488  * @adev: amdgpu_device pointer
 489  * @bo_va: bo_va to update
 490  * @list: validation list
 491  * @operation: map or unmap
 492  *
 493  * Update the bo_va directly after setting its address. Errors are not
 494  * vital here, so they are not reported back to userspace.
 495  */
 496 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
 497                                     struct amdgpu_bo_va *bo_va,
 498                                     struct list_head *list,
 499                                     uint32_t operation)
 500 {
 501         struct ttm_validate_buffer *entry;
 502         int r = -ERESTARTSYS;
 503
 504         list_for_each_entry(entry, list, head) {
 505                 struct amdgpu_bo *bo =
 506                         container_of(entry->bo, struct amdgpu_bo, tbo);
 507                 if (amdgpu_gem_va_check(NULL, bo))
 508                         goto error;
 509         }
 510
 511         r = amdgpu_vm_validate_pt_bos(adev, bo_va->vm, amdgpu_gem_va_check,
 512                                       NULL);
 513         if (r)
 514                 goto error;
 515
 516         r = amdgpu_vm_update_page_directory(adev, bo_va->vm);
 517         if (r)
 518                 goto error;
 519
 520         r = amdgpu_vm_clear_freed(adev, bo_va->vm);
 521         if (r)
 522                 goto error;
 523
 524         if (operation == AMDGPU_VA_OP_MAP)
 525                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 526
 527 error:
 528         if (r && r != -ERESTARTSYS)
 529                 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
 530 }
 531
 532 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 533                           struct drm_file *filp)
 534 {
 535         struct drm_amdgpu_gem_va *args = data;
 536         struct drm_gem_object *gobj;
 537         struct amdgpu_device *adev = dev->dev_private;
 538         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 539         struct amdgpu_bo *abo;
 540         struct amdgpu_bo_va *bo_va;
 541         struct amdgpu_bo_list_entry vm_pd;
 542         struct ttm_validate_buffer tv;
 543         struct ww_acquire_ctx ticket;
 544         struct list_head list;
 545         uint32_t invalid_flags, va_flags = 0;
 546         int r = 0;
 547
 548         if (!adev->vm_manager.enabled)
 549                 return -ENOTTY;
 550
 551         if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
 552                 dev_err(&dev->pdev->dev,
 553                         "va_address 0x%lX is in reserved area 0x%X\n",
 554                         (unsigned long)args->va_address,
 555                         AMDGPU_VA_RESERVED_SIZE);
 556                 return -EINVAL;
 557         }
 558
 559         invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE | AMDGPU_VM_PAGE_READABLE |
 560                         AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE);
 561         if ((args->flags & invalid_flags)) {
 562                 dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
 563                         args->flags, invalid_flags);
 564                 return -EINVAL;
 565         }
 566
 567         switch (args->operation) {
 568         case AMDGPU_VA_OP_MAP:
 569         case AMDGPU_VA_OP_UNMAP:
 570                 break;
 571         default:
 572                 dev_err(&dev->pdev->dev, "unsupported operation %d\n",
 573                         args->operation);
 574                 return -EINVAL;
 575         }
 576
 577         gobj = drm_gem_object_lookup(filp, args->handle);
 578         if (gobj == NULL)
 579                 return -ENOENT;
 580         abo = gem_to_amdgpu_bo(gobj);
 581         INIT_LIST_HEAD(&list);
 582         tv.bo = &abo->tbo;
 583         tv.shared = false;
 584         list_add(&tv.head, &list);
 585
 586         amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
 587
 588         r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
 589         if (r) {
 590                 drm_gem_object_unreference_unlocked(gobj);
 591                 return r;
 592         }
 593
 594         bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
 595         if (!bo_va) {
 596                 ttm_eu_backoff_reservation(&ticket, &list);
 597                 drm_gem_object_unreference_unlocked(gobj);
 598                 return -ENOENT;
 599         }
 600
 601         switch (args->operation) {
 602         case AMDGPU_VA_OP_MAP:
 603                 if (args->flags & AMDGPU_VM_PAGE_READABLE)
 604                         va_flags |= AMDGPU_PTE_READABLE;
 605                 if (args->flags & AMDGPU_VM_PAGE_WRITEABLE)
 606                         va_flags |= AMDGPU_PTE_WRITEABLE;
 607                 if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE)
 608                         va_flags |= AMDGPU_PTE_EXECUTABLE;
 609                 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
 610                                      args->offset_in_bo, args->map_size,
 611                                      va_flags);
 612                 break;
 613         case AMDGPU_VA_OP_UNMAP:
 614                 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
 615                 break;
 616         default:
 617                 break;
 618         }
 619         if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) &&
 620             !amdgpu_vm_debug)
 621                 amdgpu_gem_va_update_vm(adev, bo_va, &list, args->operation);
 622         ttm_eu_backoff_reservation(&ticket, &list);
 623
 624         drm_gem_object_unreference_unlocked(gobj);
 625         return r;
 626 }
 627
 628 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
 629                         struct drm_file *filp)
 630 {
 631         struct drm_amdgpu_gem_op *args = data;
 632         struct drm_gem_object *gobj;
 633         struct amdgpu_bo *robj;
 634         int r;
 635
 636         gobj = drm_gem_object_lookup(filp, args->handle);
 637         if (gobj == NULL) {
 638                 return -ENOENT;
 639         }
 640         robj = gem_to_amdgpu_bo(gobj);
 641
 642         r = amdgpu_bo_reserve(robj, false);
 643         if (unlikely(r))
 644                 goto out;
 645
 646         switch (args->op) {
 647         case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
 648                 struct drm_amdgpu_gem_create_in info;
 649                 void __user *out = (void __user *)(long)args->value;
 650
 651                 info.bo_size = robj->gem_base.size;
 652                 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
 653                 info.domains = robj->prefered_domains;
 654                 info.domain_flags = robj->flags;
 655                 amdgpu_bo_unreserve(robj);
 656                 if (copy_to_user(out, &info, sizeof(info)))
 657                         r = -EFAULT;
 658                 break;
 659         }
 660         case AMDGPU_GEM_OP_SET_PLACEMENT:
 661                 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
 662                         r = -EPERM;
 663                         amdgpu_bo_unreserve(robj);
 664                         break;
 665                 }
 666                 robj->prefered_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
 667                                                         AMDGPU_GEM_DOMAIN_GTT |
 668                                                         AMDGPU_GEM_DOMAIN_CPU);
 669                 robj->allowed_domains = robj->prefered_domains;
 670                 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 671                         robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 672
 673                 amdgpu_bo_unreserve(robj);
 674                 break;
 675         default:
 676                 amdgpu_bo_unreserve(robj);
 677                 r = -EINVAL;
 678         }
 679
 680 out:
 681         drm_gem_object_unreference_unlocked(gobj);
 682         return r;
 683 }
 684
 685 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
 686                             struct drm_device *dev,
 687                             struct drm_mode_create_dumb *args)
 688 {
 689         struct amdgpu_device *adev = dev->dev_private;
 690         struct drm_gem_object *gobj;
 691         uint32_t handle;
 692         int r;
 693
 694         args->pitch = amdgpu_align_pitch(adev, args->width,
 695                                          DIV_ROUND_UP(args->bpp, 8), 0);
 696         args->size = (u64)args->pitch * args->height;
 697         args->size = ALIGN(args->size, PAGE_SIZE);
 698
 699         r = amdgpu_gem_object_create(adev, args->size, 0,
 700                                      AMDGPU_GEM_DOMAIN_VRAM,
 701                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 702                                      ttm_bo_type_device,
 703                                      &gobj);
 704         if (r)
 705                 return -ENOMEM;
 706
 707         r = drm_gem_handle_create(file_priv, gobj, &handle);
 708         /* drop reference from allocate - handle holds it now */
 709         drm_gem_object_unreference_unlocked(gobj);
 710         if (r) {
 711                 return r;
 712         }
 713         args->handle = handle;
 714         return 0;
 715 }
 716
 717 #if defined(CONFIG_DEBUG_FS)
 718 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
 719 {
 720         struct drm_gem_object *gobj = ptr;
 721         struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
 722         struct seq_file *m = data;
 723
 724         unsigned domain;
 725         const char *placement;
 726         unsigned pin_count;
 727
 728         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 729         switch (domain) {
 730         case AMDGPU_GEM_DOMAIN_VRAM:
 731                 placement = "VRAM";
 732                 break;
 733         case AMDGPU_GEM_DOMAIN_GTT:
 734                 placement = " GTT";
 735                 break;
 736         case AMDGPU_GEM_DOMAIN_CPU:
 737         default:
 738                 placement = " CPU";
 739                 break;
 740         }
 741         seq_printf(m, "\t0x%08x: %12ld byte %s @ 0x%010Lx",
 742                    id, amdgpu_bo_size(bo), placement,
 743                    amdgpu_bo_gpu_offset(bo));
 744
 745         pin_count = ACCESS_ONCE(bo->pin_count);
 746         if (pin_count)
 747                 seq_printf(m, " pin count %d", pin_count);
 748         seq_printf(m, "\n");
 749
 750         return 0;
 751 }
 752
 753 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
 754 {
 755         struct drm_info_node *node = (struct drm_info_node *)m->private;
 756         struct drm_device *dev = node->minor->dev;
 757         struct drm_file *file;
 758         int r;
 759
 760         r = mutex_lock_interruptible(&dev->filelist_mutex);
 761         if (r)
 762                 return r;
 763
 764         list_for_each_entry(file, &dev->filelist, lhead) {
 765                 struct task_struct *task;
 766
 767                 /*
 768                  * Although we have a valid reference on file->pid, that does
 769                  * not guarantee that the task_struct who called get_pid() is
 770                  * still alive (e.g. get_pid(current) => fork() => exit()).
 771                  * Therefore, we need to protect this ->comm access using RCU.
 772                  */
 773                 rcu_read_lock();
 774                 task = pid_task(file->pid, PIDTYPE_PID);
 775                 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
 776                            task ? task->comm : "<unknown>");
 777                 rcu_read_unlock();
 778
 779                 spin_lock(&file->table_lock);
 780                 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
 781                 spin_unlock(&file->table_lock);
 782         }
 783
 784         mutex_unlock(&dev->filelist_mutex);
 785         return 0;
 786 }
 787
 788 static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
 789         {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
 790 };
 791 #endif
 792
 793 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev)
 794 {
 795 #if defined(CONFIG_DEBUG_FS)
 796         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);
 797 #endif
 798         return 0;
 799 }