drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/ktime.h>
  29 #include <drm/drmP.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu.h"
  32
  33 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
  34 {
  35         struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
  36
  37         if (robj) {
  38                 if (robj->gem_base.import_attach)
  39                         drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
  40                 amdgpu_mn_unregister(robj);
  41                 amdgpu_bo_unref(&robj);
  42         }
  43 }
  44
  45 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
  46                                 int alignment, u32 initial_domain,
  47                                 u64 flags, bool kernel,
  48                                 struct drm_gem_object **obj)
  49 {
  50         struct amdgpu_bo *robj;
  51         unsigned long max_size;
  52         int r;
  53
  54         *obj = NULL;
  55         /* At least align on page size */
  56         if (alignment < PAGE_SIZE) {
  57                 alignment = PAGE_SIZE;
  58         }
  59
  60         if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) {
  61                 /* Maximum bo size is the unpinned gtt size since we use the gtt to
  62                  * handle vram to system pool migrations.
  63                  */
  64                 max_size = adev->mc.gtt_size - adev->gart_pin_size;
  65                 if (size > max_size) {
  66                         DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n",
  67                                   size >> 20, max_size >> 20);
  68                         return -ENOMEM;
  69                 }
  70         }
  71 retry:
  72         r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain, flags, NULL, &robj);
  73         if (r) {
  74                 if (r != -ERESTARTSYS) {
  75                         if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
  76                                 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
  77                                 goto retry;
  78                         }
  79                         DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
  80                                   size, initial_domain, alignment, r);
  81                 }
  82                 return r;
  83         }
  84         *obj = &robj->gem_base;
  85         robj->pid = task_pid_nr(current);
  86
  87         mutex_lock(&adev->gem.mutex);
  88         list_add_tail(&robj->list, &adev->gem.objects);
  89         mutex_unlock(&adev->gem.mutex);
  90
  91         return 0;
  92 }
  93
  94 int amdgpu_gem_init(struct amdgpu_device *adev)
  95 {
  96         INIT_LIST_HEAD(&adev->gem.objects);
  97         return 0;
  98 }
  99
 100 void amdgpu_gem_fini(struct amdgpu_device *adev)
 101 {
 102         amdgpu_bo_force_delete(adev);
 103 }
 104
 105 /*
 106  * Call from drm_gem_handle_create which appear in both new and open ioctl
 107  * case.
 108  */
 109 int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv)
 110 {
 111         struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj);
 112         struct amdgpu_device *adev = rbo->adev;
 113         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 114         struct amdgpu_vm *vm = &fpriv->vm;
 115         struct amdgpu_bo_va *bo_va;
 116         int r;
 117
 118         r = amdgpu_bo_reserve(rbo, false);
 119         if (r) {
 120                 return r;
 121         }
 122
 123         bo_va = amdgpu_vm_bo_find(vm, rbo);
 124         if (!bo_va) {
 125                 bo_va = amdgpu_vm_bo_add(adev, vm, rbo);
 126         } else {
 127                 ++bo_va->ref_count;
 128         }
 129         amdgpu_bo_unreserve(rbo);
 130
 131         return 0;
 132 }
 133
 134 void amdgpu_gem_object_close(struct drm_gem_object *obj,
 135                              struct drm_file *file_priv)
 136 {
 137         struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj);
 138         struct amdgpu_device *adev = rbo->adev;
 139         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 140         struct amdgpu_vm *vm = &fpriv->vm;
 141         struct amdgpu_bo_va *bo_va;
 142         int r;
 143
 144         r = amdgpu_bo_reserve(rbo, true);
 145         if (r) {
 146                 dev_err(adev->dev, "leaking bo va because "
 147                         "we fail to reserve bo (%d)\n", r);
 148                 return;
 149         }
 150         bo_va = amdgpu_vm_bo_find(vm, rbo);
 151         if (bo_va) {
 152                 if (--bo_va->ref_count == 0) {
 153                         amdgpu_vm_bo_rmv(adev, bo_va);
 154                 }
 155         }
 156         amdgpu_bo_unreserve(rbo);
 157 }
 158
 159 static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r)
 160 {
 161         if (r == -EDEADLK) {
 162                 r = amdgpu_gpu_reset(adev);
 163                 if (!r)
 164                         r = -EAGAIN;
 165         }
 166         return r;
 167 }
 168
 169 /*
 170  * GEM ioctls.
 171  */
 172 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
 173                             struct drm_file *filp)
 174 {
 175         struct amdgpu_device *adev = dev->dev_private;
 176         union drm_amdgpu_gem_create *args = data;
 177         uint64_t size = args->in.bo_size;
 178         struct drm_gem_object *gobj;
 179         uint32_t handle;
 180         bool kernel = false;
 181         int r;
 182
 183         down_read(&adev->exclusive_lock);
 184         /* create a gem object to contain this object in */
 185         if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
 186             AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
 187                 kernel = true;
 188                 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
 189                         size = size << AMDGPU_GDS_SHIFT;
 190                 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
 191                         size = size << AMDGPU_GWS_SHIFT;
 192                 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
 193                         size = size << AMDGPU_OA_SHIFT;
 194                 else {
 195                         r = -EINVAL;
 196                         goto error_unlock;
 197                 }
 198         }
 199         size = roundup(size, PAGE_SIZE);
 200
 201         r = amdgpu_gem_object_create(adev, size, args->in.alignment,
 202                                      (u32)(0xffffffff & args->in.domains),
 203                                      args->in.domain_flags,
 204                                      kernel, &gobj);
 205         if (r)
 206                 goto error_unlock;
 207
 208         r = drm_gem_handle_create(filp, gobj, &handle);
 209         /* drop reference from allocate - handle holds it now */
 210         drm_gem_object_unreference_unlocked(gobj);
 211         if (r)
 212                 goto error_unlock;
 213
 214         memset(args, 0, sizeof(*args));
 215         args->out.handle = handle;
 216         up_read(&adev->exclusive_lock);
 217         return 0;
 218
 219 error_unlock:
 220         up_read(&adev->exclusive_lock);
 221         r = amdgpu_gem_handle_lockup(adev, r);
 222         return r;
 223 }
 224
 225 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
 226                              struct drm_file *filp)
 227 {
 228         struct amdgpu_device *adev = dev->dev_private;
 229         struct drm_amdgpu_gem_userptr *args = data;
 230         struct drm_gem_object *gobj;
 231         struct amdgpu_bo *bo;
 232         uint32_t handle;
 233         int r;
 234
 235         if (offset_in_page(args->addr | args->size))
 236                 return -EINVAL;
 237
 238         /* reject unknown flag values */
 239         if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
 240             AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
 241             AMDGPU_GEM_USERPTR_REGISTER))
 242                 return -EINVAL;
 243
 244         if (!(args->flags & AMDGPU_GEM_USERPTR_ANONONLY) ||
 245                    !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
 246
 247                 /* if we want to write to it we must require anonymous
 248                    memory and install a MMU notifier */
 249                 return -EACCES;
 250         }
 251
 252         down_read(&adev->exclusive_lock);
 253
 254         /* create a gem object to contain this object in */
 255         r = amdgpu_gem_object_create(adev, args->size, 0,
 256                                      AMDGPU_GEM_DOMAIN_CPU, 0,
 257                                      0, &gobj);
 258         if (r)
 259                 goto handle_lockup;
 260
 261         bo = gem_to_amdgpu_bo(gobj);
 262         r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
 263         if (r)
 264                 goto release_object;
 265
 266         if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
 267                 r = amdgpu_mn_register(bo, args->addr);
 268                 if (r)
 269                         goto release_object;
 270         }
 271
 272         if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
 273                 down_read(&current->mm->mmap_sem);
 274                 r = amdgpu_bo_reserve(bo, true);
 275                 if (r) {
 276                         up_read(&current->mm->mmap_sem);
 277                         goto release_object;
 278                 }
 279
 280                 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
 281                 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 282                 amdgpu_bo_unreserve(bo);
 283                 up_read(&current->mm->mmap_sem);
 284                 if (r)
 285                         goto release_object;
 286         }
 287
 288         r = drm_gem_handle_create(filp, gobj, &handle);
 289         /* drop reference from allocate - handle holds it now */
 290         drm_gem_object_unreference_unlocked(gobj);
 291         if (r)
 292                 goto handle_lockup;
 293
 294         args->handle = handle;
 295         up_read(&adev->exclusive_lock);
 296         return 0;
 297
 298 release_object:
 299         drm_gem_object_unreference_unlocked(gobj);
 300
 301 handle_lockup:
 302         up_read(&adev->exclusive_lock);
 303         r = amdgpu_gem_handle_lockup(adev, r);
 304
 305         return r;
 306 }
 307
 308 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
 309                           struct drm_device *dev,
 310                           uint32_t handle, uint64_t *offset_p)
 311 {
 312         struct drm_gem_object *gobj;
 313         struct amdgpu_bo *robj;
 314
 315         gobj = drm_gem_object_lookup(dev, filp, handle);
 316         if (gobj == NULL) {
 317                 return -ENOENT;
 318         }
 319         robj = gem_to_amdgpu_bo(gobj);
 320         if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm) ||
 321             (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
 322                 drm_gem_object_unreference_unlocked(gobj);
 323                 return -EPERM;
 324         }
 325         *offset_p = amdgpu_bo_mmap_offset(robj);
 326         drm_gem_object_unreference_unlocked(gobj);
 327         return 0;
 328 }
 329
 330 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
 331                           struct drm_file *filp)
 332 {
 333         union drm_amdgpu_gem_mmap *args = data;
 334         uint32_t handle = args->in.handle;
 335         memset(args, 0, sizeof(*args));
 336         return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
 337 }
 338
 339 /**
 340  * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
 341  *
 342  * @timeout_ns: timeout in ns
 343  *
 344  * Calculate the timeout in jiffies from an absolute timeout in ns.
 345  */
 346 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
 347 {
 348         unsigned long timeout_jiffies;
 349         ktime_t timeout;
 350
 351         /* clamp timeout if it's to large */
 352         if (((int64_t)timeout_ns) < 0)
 353                 return MAX_SCHEDULE_TIMEOUT;
 354
 355         timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
 356         if (ktime_to_ns(timeout) < 0)
 357                 return 0;
 358
 359         timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
 360         /*  clamp timeout to avoid unsigned-> signed overflow */
 361         if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
 362                 return MAX_SCHEDULE_TIMEOUT - 1;
 363
 364         return timeout_jiffies;
 365 }
 366
 367 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 368                               struct drm_file *filp)
 369 {
 370         struct amdgpu_device *adev = dev->dev_private;
 371         union drm_amdgpu_gem_wait_idle *args = data;
 372         struct drm_gem_object *gobj;
 373         struct amdgpu_bo *robj;
 374         uint32_t handle = args->in.handle;
 375         unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
 376         int r = 0;
 377         long ret;
 378
 379         gobj = drm_gem_object_lookup(dev, filp, handle);
 380         if (gobj == NULL) {
 381                 return -ENOENT;
 382         }
 383         robj = gem_to_amdgpu_bo(gobj);
 384         if (timeout == 0)
 385                 ret = reservation_object_test_signaled_rcu(robj->tbo.resv, true);
 386         else
 387                 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, timeout);
 388
 389         /* ret == 0 means not signaled,
 390          * ret > 0 means signaled
 391          * ret < 0 means interrupted before timeout
 392          */
 393         if (ret >= 0) {
 394                 memset(args, 0, sizeof(*args));
 395                 args->out.status = (ret == 0);
 396         } else
 397                 r = ret;
 398
 399         drm_gem_object_unreference_unlocked(gobj);
 400         r = amdgpu_gem_handle_lockup(adev, r);
 401         return r;
 402 }
 403
 404 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
 405                                 struct drm_file *filp)
 406 {
 407         struct drm_amdgpu_gem_metadata *args = data;
 408         struct drm_gem_object *gobj;
 409         struct amdgpu_bo *robj;
 410         int r = -1;
 411
 412         DRM_DEBUG("%d \n", args->handle);
 413         gobj = drm_gem_object_lookup(dev, filp, args->handle);
 414         if (gobj == NULL)
 415                 return -ENOENT;
 416         robj = gem_to_amdgpu_bo(gobj);
 417
 418         r = amdgpu_bo_reserve(robj, false);
 419         if (unlikely(r != 0))
 420                 goto out;
 421
 422         if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
 423                 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
 424                 r = amdgpu_bo_get_metadata(robj, args->data.data,
 425                                            sizeof(args->data.data),
 426                                            &args->data.data_size_bytes,
 427                                            &args->data.flags);
 428         } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
 429                 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
 430                 if (!r)
 431                         r = amdgpu_bo_set_metadata(robj, args->data.data,
 432                                                    args->data.data_size_bytes,
 433                                                    args->data.flags);
 434         }
 435
 436         amdgpu_bo_unreserve(robj);
 437 out:
 438         drm_gem_object_unreference_unlocked(gobj);
 439         return r;
 440 }
 441
 442 /**
 443  * amdgpu_gem_va_update_vm -update the bo_va in its VM
 444  *
 445  * @adev: amdgpu_device pointer
 446  * @bo_va: bo_va to update
 447  *
 448  * Update the bo_va directly after setting it's address. Errors are not
 449  * vital here, so they are not reported back to userspace.
 450  */
 451 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
 452                                     struct amdgpu_bo_va *bo_va, uint32_t operation)
 453 {
 454         struct ttm_validate_buffer tv, *entry;
 455         struct amdgpu_bo_list_entry *vm_bos;
 456         struct ww_acquire_ctx ticket;
 457         struct list_head list;
 458         unsigned domain;
 459         int r;
 460
 461         INIT_LIST_HEAD(&list);
 462
 463         tv.bo = &bo_va->bo->tbo;
 464         tv.shared = true;
 465         list_add(&tv.head, &list);
 466
 467         vm_bos = amdgpu_vm_get_bos(adev, bo_va->vm, &list);
 468         if (!vm_bos)
 469                 return;
 470
 471         r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
 472         if (r)
 473                 goto error_free;
 474
 475         list_for_each_entry(entry, &list, head) {
 476                 domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type);
 477                 /* if anything is swapped out don't swap it in here,
 478                    just abort and wait for the next CS */
 479                 if (domain == AMDGPU_GEM_DOMAIN_CPU)
 480                         goto error_unreserve;
 481         }
 482
 483         mutex_lock(&bo_va->vm->mutex);
 484         r = amdgpu_vm_clear_freed(adev, bo_va->vm);
 485         if (r)
 486                 goto error_unlock;
 487
 488
 489         if (operation == AMDGPU_VA_OP_MAP)
 490                 r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem);
 491
 492 error_unlock:
 493         mutex_unlock(&bo_va->vm->mutex);
 494
 495 error_unreserve:
 496         ttm_eu_backoff_reservation(&ticket, &list);
 497
 498 error_free:
 499         drm_free_large(vm_bos);
 500
 501         if (r && r != -ERESTARTSYS)
 502                 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
 503 }
 504
 505
 506
 507 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 508                           struct drm_file *filp)
 509 {
 510         struct drm_amdgpu_gem_va *args = data;
 511         struct drm_gem_object *gobj;
 512         struct amdgpu_device *adev = dev->dev_private;
 513         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 514         struct amdgpu_bo *rbo;
 515         struct amdgpu_bo_va *bo_va;
 516         uint32_t invalid_flags, va_flags = 0;
 517         int r = 0;
 518
 519         if (!adev->vm_manager.enabled)
 520                 return -ENOTTY;
 521
 522         if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
 523                 dev_err(&dev->pdev->dev,
 524                         "va_address 0x%lX is in reserved area 0x%X\n",
 525                         (unsigned long)args->va_address,
 526                         AMDGPU_VA_RESERVED_SIZE);
 527                 return -EINVAL;
 528         }
 529
 530         invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE | AMDGPU_VM_PAGE_READABLE |
 531                         AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE);
 532         if ((args->flags & invalid_flags)) {
 533                 dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
 534                         args->flags, invalid_flags);
 535                 return -EINVAL;
 536         }
 537
 538         switch (args->operation) {
 539         case AMDGPU_VA_OP_MAP:
 540         case AMDGPU_VA_OP_UNMAP:
 541                 break;
 542         default:
 543                 dev_err(&dev->pdev->dev, "unsupported operation %d\n",
 544                         args->operation);
 545                 return -EINVAL;
 546         }
 547
 548         gobj = drm_gem_object_lookup(dev, filp, args->handle);
 549         if (gobj == NULL)
 550                 return -ENOENT;
 551
 552         rbo = gem_to_amdgpu_bo(gobj);
 553         r = amdgpu_bo_reserve(rbo, false);
 554         if (r) {
 555                 drm_gem_object_unreference_unlocked(gobj);
 556                 return r;
 557         }
 558
 559         bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo);
 560         if (!bo_va) {
 561                 amdgpu_bo_unreserve(rbo);
 562                 return -ENOENT;
 563         }
 564
 565         switch (args->operation) {
 566         case AMDGPU_VA_OP_MAP:
 567                 if (args->flags & AMDGPU_VM_PAGE_READABLE)
 568                         va_flags |= AMDGPU_PTE_READABLE;
 569                 if (args->flags & AMDGPU_VM_PAGE_WRITEABLE)
 570                         va_flags |= AMDGPU_PTE_WRITEABLE;
 571                 if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE)
 572                         va_flags |= AMDGPU_PTE_EXECUTABLE;
 573                 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
 574                                      args->offset_in_bo, args->map_size,
 575                                      va_flags);
 576                 break;
 577         case AMDGPU_VA_OP_UNMAP:
 578                 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
 579                 break;
 580         default:
 581                 break;
 582         }
 583
 584         if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE))
 585                 amdgpu_gem_va_update_vm(adev, bo_va, args->operation);
 586
 587         drm_gem_object_unreference_unlocked(gobj);
 588         return r;
 589 }
 590
 591 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
 592                         struct drm_file *filp)
 593 {
 594         struct drm_amdgpu_gem_op *args = data;
 595         struct drm_gem_object *gobj;
 596         struct amdgpu_bo *robj;
 597         int r;
 598
 599         gobj = drm_gem_object_lookup(dev, filp, args->handle);
 600         if (gobj == NULL) {
 601                 return -ENOENT;
 602         }
 603         robj = gem_to_amdgpu_bo(gobj);
 604
 605         r = amdgpu_bo_reserve(robj, false);
 606         if (unlikely(r))
 607                 goto out;
 608
 609         switch (args->op) {
 610         case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
 611                 struct drm_amdgpu_gem_create_in info;
 612                 void __user *out = (void __user *)(long)args->value;
 613
 614                 info.bo_size = robj->gem_base.size;
 615                 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
 616                 info.domains = robj->initial_domain;
 617                 info.domain_flags = robj->flags;
 618                 amdgpu_bo_unreserve(robj);
 619                 if (copy_to_user(out, &info, sizeof(info)))
 620                         r = -EFAULT;
 621                 break;
 622         }
 623         case AMDGPU_GEM_OP_SET_PLACEMENT:
 624                 if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm)) {
 625                         r = -EPERM;
 626                         amdgpu_bo_unreserve(robj);
 627                         break;
 628                 }
 629                 robj->initial_domain = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
 630                                                       AMDGPU_GEM_DOMAIN_GTT |
 631                                                       AMDGPU_GEM_DOMAIN_CPU);
 632                 amdgpu_bo_unreserve(robj);
 633                 break;
 634         default:
 635                 amdgpu_bo_unreserve(robj);
 636                 r = -EINVAL;
 637         }
 638
 639 out:
 640         drm_gem_object_unreference_unlocked(gobj);
 641         return r;
 642 }
 643
 644 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
 645                             struct drm_device *dev,
 646                             struct drm_mode_create_dumb *args)
 647 {
 648         struct amdgpu_device *adev = dev->dev_private;
 649         struct drm_gem_object *gobj;
 650         uint32_t handle;
 651         int r;
 652
 653         args->pitch = amdgpu_align_pitch(adev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8);
 654         args->size = args->pitch * args->height;
 655         args->size = ALIGN(args->size, PAGE_SIZE);
 656
 657         r = amdgpu_gem_object_create(adev, args->size, 0,
 658                                      AMDGPU_GEM_DOMAIN_VRAM,
 659                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 660                                      ttm_bo_type_device,
 661                                      &gobj);
 662         if (r)
 663                 return -ENOMEM;
 664
 665         r = drm_gem_handle_create(file_priv, gobj, &handle);
 666         /* drop reference from allocate - handle holds it now */
 667         drm_gem_object_unreference_unlocked(gobj);
 668         if (r) {
 669                 return r;
 670         }
 671         args->handle = handle;
 672         return 0;
 673 }
 674
 675 #if defined(CONFIG_DEBUG_FS)
 676 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
 677 {
 678         struct drm_info_node *node = (struct drm_info_node *)m->private;
 679         struct drm_device *dev = node->minor->dev;
 680         struct amdgpu_device *adev = dev->dev_private;
 681         struct amdgpu_bo *rbo;
 682         unsigned i = 0;
 683
 684         mutex_lock(&adev->gem.mutex);
 685         list_for_each_entry(rbo, &adev->gem.objects, list) {
 686                 unsigned domain;
 687                 const char *placement;
 688
 689                 domain = amdgpu_mem_type_to_domain(rbo->tbo.mem.mem_type);
 690                 switch (domain) {
 691                 case AMDGPU_GEM_DOMAIN_VRAM:
 692                         placement = "VRAM";
 693                         break;
 694                 case AMDGPU_GEM_DOMAIN_GTT:
 695                         placement = " GTT";
 696                         break;
 697                 case AMDGPU_GEM_DOMAIN_CPU:
 698                 default:
 699                         placement = " CPU";
 700                         break;
 701                 }
 702                 seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n",
 703                            i, amdgpu_bo_size(rbo) >> 10, amdgpu_bo_size(rbo) >> 20,
 704                            placement, (unsigned long)rbo->pid);
 705                 i++;
 706         }
 707         mutex_unlock(&adev->gem.mutex);
 708         return 0;
 709 }
 710
 711 static struct drm_info_list amdgpu_debugfs_gem_list[] = {
 712         {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
 713 };
 714 #endif
 715
 716 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev)
 717 {
 718 #if defined(CONFIG_DEBUG_FS)
 719         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);
 720 #endif
 721         return 0;
 722 }