2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/ktime.h>
29 #include <linux/module.h>
30 #include <linux/pagemap.h>
31 #include <linux/pci.h>
33 #include <drm/amdgpu_drm.h>
34 #include <drm/drm_debugfs.h>
37 #include "amdgpu_display.h"
38 #include "amdgpu_xgmi.h"
40 void amdgpu_gem_object_free(struct drm_gem_object
*gobj
)
42 struct amdgpu_bo
*robj
= gem_to_amdgpu_bo(gobj
);
45 amdgpu_mn_unregister(robj
);
46 amdgpu_bo_unref(&robj
);
50 int amdgpu_gem_object_create(struct amdgpu_device
*adev
, unsigned long size
,
51 int alignment
, u32 initial_domain
,
52 u64 flags
, enum ttm_bo_type type
,
53 struct reservation_object
*resv
,
54 struct drm_gem_object
**obj
)
57 struct amdgpu_bo_param bp
;
60 memset(&bp
, 0, sizeof(bp
));
64 bp
.byte_align
= alignment
;
67 bp
.preferred_domain
= initial_domain
;
70 bp
.domain
= initial_domain
;
71 r
= amdgpu_bo_create(adev
, &bp
, &bo
);
73 if (r
!= -ERESTARTSYS
) {
74 if (flags
& AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
) {
75 flags
&= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
;
79 if (initial_domain
== AMDGPU_GEM_DOMAIN_VRAM
) {
80 initial_domain
|= AMDGPU_GEM_DOMAIN_GTT
;
83 DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
84 size
, initial_domain
, alignment
, r
);
93 void amdgpu_gem_force_release(struct amdgpu_device
*adev
)
95 struct drm_device
*ddev
= adev
->ddev
;
96 struct drm_file
*file
;
98 mutex_lock(&ddev
->filelist_mutex
);
100 list_for_each_entry(file
, &ddev
->filelist
, lhead
) {
101 struct drm_gem_object
*gobj
;
104 WARN_ONCE(1, "Still active user space clients!\n");
105 spin_lock(&file
->table_lock
);
106 idr_for_each_entry(&file
->object_idr
, gobj
, handle
) {
107 WARN_ONCE(1, "And also active allocations!\n");
108 drm_gem_object_put_unlocked(gobj
);
110 idr_destroy(&file
->object_idr
);
111 spin_unlock(&file
->table_lock
);
114 mutex_unlock(&ddev
->filelist_mutex
);
118 * Call from drm_gem_handle_create which appear in both new and open ioctl
121 int amdgpu_gem_object_open(struct drm_gem_object
*obj
,
122 struct drm_file
*file_priv
)
124 struct amdgpu_bo
*abo
= gem_to_amdgpu_bo(obj
);
125 struct amdgpu_device
*adev
= amdgpu_ttm_adev(abo
->tbo
.bdev
);
126 struct amdgpu_fpriv
*fpriv
= file_priv
->driver_priv
;
127 struct amdgpu_vm
*vm
= &fpriv
->vm
;
128 struct amdgpu_bo_va
*bo_va
;
129 struct mm_struct
*mm
;
132 mm
= amdgpu_ttm_tt_get_usermm(abo
->tbo
.ttm
);
133 if (mm
&& mm
!= current
->mm
)
136 if (abo
->flags
& AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
&&
137 abo
->tbo
.resv
!= vm
->root
.base
.bo
->tbo
.resv
)
140 r
= amdgpu_bo_reserve(abo
, false);
144 bo_va
= amdgpu_vm_bo_find(vm
, abo
);
146 bo_va
= amdgpu_vm_bo_add(adev
, vm
, abo
);
150 amdgpu_bo_unreserve(abo
);
154 void amdgpu_gem_object_close(struct drm_gem_object
*obj
,
155 struct drm_file
*file_priv
)
157 struct amdgpu_bo
*bo
= gem_to_amdgpu_bo(obj
);
158 struct amdgpu_device
*adev
= amdgpu_ttm_adev(bo
->tbo
.bdev
);
159 struct amdgpu_fpriv
*fpriv
= file_priv
->driver_priv
;
160 struct amdgpu_vm
*vm
= &fpriv
->vm
;
162 struct amdgpu_bo_list_entry vm_pd
;
163 struct list_head list
, duplicates
;
164 struct ttm_validate_buffer tv
;
165 struct ww_acquire_ctx ticket
;
166 struct amdgpu_bo_va
*bo_va
;
169 INIT_LIST_HEAD(&list
);
170 INIT_LIST_HEAD(&duplicates
);
174 list_add(&tv
.head
, &list
);
176 amdgpu_vm_get_pd_bo(vm
, &list
, &vm_pd
);
178 r
= ttm_eu_reserve_buffers(&ticket
, &list
, false, &duplicates
, false);
180 dev_err(adev
->dev
, "leaking bo va because "
181 "we fail to reserve bo (%d)\n", r
);
184 bo_va
= amdgpu_vm_bo_find(vm
, bo
);
185 if (bo_va
&& --bo_va
->ref_count
== 0) {
186 amdgpu_vm_bo_rmv(adev
, bo_va
);
188 if (amdgpu_vm_ready(vm
)) {
189 struct dma_fence
*fence
= NULL
;
191 r
= amdgpu_vm_clear_freed(adev
, vm
, &fence
);
193 dev_err(adev
->dev
, "failed to clear page "
194 "tables on GEM object close (%d)\n", r
);
198 amdgpu_bo_fence(bo
, fence
, true);
199 dma_fence_put(fence
);
203 ttm_eu_backoff_reservation(&ticket
, &list
);
209 int amdgpu_gem_create_ioctl(struct drm_device
*dev
, void *data
,
210 struct drm_file
*filp
)
212 struct amdgpu_device
*adev
= dev
->dev_private
;
213 struct amdgpu_fpriv
*fpriv
= filp
->driver_priv
;
214 struct amdgpu_vm
*vm
= &fpriv
->vm
;
215 union drm_amdgpu_gem_create
*args
= data
;
216 uint64_t flags
= args
->in
.domain_flags
;
217 uint64_t size
= args
->in
.bo_size
;
218 struct reservation_object
*resv
= NULL
;
219 struct drm_gem_object
*gobj
;
223 /* reject invalid gem flags */
224 if (flags
& ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
|
225 AMDGPU_GEM_CREATE_NO_CPU_ACCESS
|
226 AMDGPU_GEM_CREATE_CPU_GTT_USWC
|
227 AMDGPU_GEM_CREATE_VRAM_CLEARED
|
228 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
|
229 AMDGPU_GEM_CREATE_EXPLICIT_SYNC
))
233 /* reject invalid gem domains */
234 if (args
->in
.domains
& ~AMDGPU_GEM_DOMAIN_MASK
)
237 /* create a gem object to contain this object in */
238 if (args
->in
.domains
& (AMDGPU_GEM_DOMAIN_GDS
|
239 AMDGPU_GEM_DOMAIN_GWS
| AMDGPU_GEM_DOMAIN_OA
)) {
240 if (flags
& AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
) {
241 /* if gds bo is created from user space, it must be
244 DRM_ERROR("GDS bo cannot be per-vm-bo\n");
247 flags
|= AMDGPU_GEM_CREATE_NO_CPU_ACCESS
;
250 if (flags
& AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
) {
251 r
= amdgpu_bo_reserve(vm
->root
.base
.bo
, false);
255 resv
= vm
->root
.base
.bo
->tbo
.resv
;
258 r
= amdgpu_gem_object_create(adev
, size
, args
->in
.alignment
,
259 (u32
)(0xffffffff & args
->in
.domains
),
260 flags
, ttm_bo_type_device
, resv
, &gobj
);
261 if (flags
& AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
) {
263 struct amdgpu_bo
*abo
= gem_to_amdgpu_bo(gobj
);
265 abo
->parent
= amdgpu_bo_ref(vm
->root
.base
.bo
);
267 amdgpu_bo_unreserve(vm
->root
.base
.bo
);
272 r
= drm_gem_handle_create(filp
, gobj
, &handle
);
273 /* drop reference from allocate - handle holds it now */
274 drm_gem_object_put_unlocked(gobj
);
278 memset(args
, 0, sizeof(*args
));
279 args
->out
.handle
= handle
;
283 int amdgpu_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
284 struct drm_file
*filp
)
286 struct ttm_operation_ctx ctx
= { true, false };
287 struct amdgpu_device
*adev
= dev
->dev_private
;
288 struct drm_amdgpu_gem_userptr
*args
= data
;
289 struct drm_gem_object
*gobj
;
290 struct amdgpu_bo
*bo
;
294 if (offset_in_page(args
->addr
| args
->size
))
297 /* reject unknown flag values */
298 if (args
->flags
& ~(AMDGPU_GEM_USERPTR_READONLY
|
299 AMDGPU_GEM_USERPTR_ANONONLY
| AMDGPU_GEM_USERPTR_VALIDATE
|
300 AMDGPU_GEM_USERPTR_REGISTER
))
303 if (!(args
->flags
& AMDGPU_GEM_USERPTR_READONLY
) &&
304 !(args
->flags
& AMDGPU_GEM_USERPTR_REGISTER
)) {
306 /* if we want to write to it we must install a MMU notifier */
310 /* create a gem object to contain this object in */
311 r
= amdgpu_gem_object_create(adev
, args
->size
, 0, AMDGPU_GEM_DOMAIN_CPU
,
312 0, ttm_bo_type_device
, NULL
, &gobj
);
316 bo
= gem_to_amdgpu_bo(gobj
);
317 bo
->preferred_domains
= AMDGPU_GEM_DOMAIN_GTT
;
318 bo
->allowed_domains
= AMDGPU_GEM_DOMAIN_GTT
;
319 r
= amdgpu_ttm_tt_set_userptr(bo
->tbo
.ttm
, args
->addr
, args
->flags
);
323 if (args
->flags
& AMDGPU_GEM_USERPTR_REGISTER
) {
324 r
= amdgpu_mn_register(bo
, args
->addr
);
329 if (args
->flags
& AMDGPU_GEM_USERPTR_VALIDATE
) {
330 r
= amdgpu_ttm_tt_get_user_pages(bo
, bo
->tbo
.ttm
->pages
);
334 r
= amdgpu_bo_reserve(bo
, true);
336 goto user_pages_done
;
338 amdgpu_bo_placement_from_domain(bo
, AMDGPU_GEM_DOMAIN_GTT
);
339 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, &ctx
);
340 amdgpu_bo_unreserve(bo
);
342 goto user_pages_done
;
345 r
= drm_gem_handle_create(filp
, gobj
, &handle
);
347 goto user_pages_done
;
349 args
->handle
= handle
;
352 if (args
->flags
& AMDGPU_GEM_USERPTR_VALIDATE
)
353 amdgpu_ttm_tt_get_user_pages_done(bo
->tbo
.ttm
);
356 drm_gem_object_put_unlocked(gobj
);
361 int amdgpu_mode_dumb_mmap(struct drm_file
*filp
,
362 struct drm_device
*dev
,
363 uint32_t handle
, uint64_t *offset_p
)
365 struct drm_gem_object
*gobj
;
366 struct amdgpu_bo
*robj
;
368 gobj
= drm_gem_object_lookup(filp
, handle
);
372 robj
= gem_to_amdgpu_bo(gobj
);
373 if (amdgpu_ttm_tt_get_usermm(robj
->tbo
.ttm
) ||
374 (robj
->flags
& AMDGPU_GEM_CREATE_NO_CPU_ACCESS
)) {
375 drm_gem_object_put_unlocked(gobj
);
378 *offset_p
= amdgpu_bo_mmap_offset(robj
);
379 drm_gem_object_put_unlocked(gobj
);
383 int amdgpu_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
384 struct drm_file
*filp
)
386 union drm_amdgpu_gem_mmap
*args
= data
;
387 uint32_t handle
= args
->in
.handle
;
388 memset(args
, 0, sizeof(*args
));
389 return amdgpu_mode_dumb_mmap(filp
, dev
, handle
, &args
->out
.addr_ptr
);
393 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
395 * @timeout_ns: timeout in ns
397 * Calculate the timeout in jiffies from an absolute timeout in ns.
399 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns
)
401 unsigned long timeout_jiffies
;
404 /* clamp timeout if it's to large */
405 if (((int64_t)timeout_ns
) < 0)
406 return MAX_SCHEDULE_TIMEOUT
;
408 timeout
= ktime_sub(ns_to_ktime(timeout_ns
), ktime_get());
409 if (ktime_to_ns(timeout
) < 0)
412 timeout_jiffies
= nsecs_to_jiffies(ktime_to_ns(timeout
));
413 /* clamp timeout to avoid unsigned-> signed overflow */
414 if (timeout_jiffies
> MAX_SCHEDULE_TIMEOUT
)
415 return MAX_SCHEDULE_TIMEOUT
- 1;
417 return timeout_jiffies
;
420 int amdgpu_gem_wait_idle_ioctl(struct drm_device
*dev
, void *data
,
421 struct drm_file
*filp
)
423 union drm_amdgpu_gem_wait_idle
*args
= data
;
424 struct drm_gem_object
*gobj
;
425 struct amdgpu_bo
*robj
;
426 uint32_t handle
= args
->in
.handle
;
427 unsigned long timeout
= amdgpu_gem_timeout(args
->in
.timeout
);
431 gobj
= drm_gem_object_lookup(filp
, handle
);
435 robj
= gem_to_amdgpu_bo(gobj
);
436 ret
= reservation_object_wait_timeout_rcu(robj
->tbo
.resv
, true, true,
439 /* ret == 0 means not signaled,
440 * ret > 0 means signaled
441 * ret < 0 means interrupted before timeout
444 memset(args
, 0, sizeof(*args
));
445 args
->out
.status
= (ret
== 0);
449 drm_gem_object_put_unlocked(gobj
);
453 int amdgpu_gem_metadata_ioctl(struct drm_device
*dev
, void *data
,
454 struct drm_file
*filp
)
456 struct drm_amdgpu_gem_metadata
*args
= data
;
457 struct drm_gem_object
*gobj
;
458 struct amdgpu_bo
*robj
;
461 DRM_DEBUG("%d \n", args
->handle
);
462 gobj
= drm_gem_object_lookup(filp
, args
->handle
);
465 robj
= gem_to_amdgpu_bo(gobj
);
467 r
= amdgpu_bo_reserve(robj
, false);
468 if (unlikely(r
!= 0))
471 if (args
->op
== AMDGPU_GEM_METADATA_OP_GET_METADATA
) {
472 amdgpu_bo_get_tiling_flags(robj
, &args
->data
.tiling_info
);
473 r
= amdgpu_bo_get_metadata(robj
, args
->data
.data
,
474 sizeof(args
->data
.data
),
475 &args
->data
.data_size_bytes
,
477 } else if (args
->op
== AMDGPU_GEM_METADATA_OP_SET_METADATA
) {
478 if (args
->data
.data_size_bytes
> sizeof(args
->data
.data
)) {
482 r
= amdgpu_bo_set_tiling_flags(robj
, args
->data
.tiling_info
);
484 r
= amdgpu_bo_set_metadata(robj
, args
->data
.data
,
485 args
->data
.data_size_bytes
,
490 amdgpu_bo_unreserve(robj
);
492 drm_gem_object_put_unlocked(gobj
);
497 * amdgpu_gem_va_update_vm -update the bo_va in its VM
499 * @adev: amdgpu_device pointer
501 * @bo_va: bo_va to update
502 * @operation: map, unmap or clear
504 * Update the bo_va directly after setting its address. Errors are not
505 * vital here, so they are not reported back to userspace.
507 static void amdgpu_gem_va_update_vm(struct amdgpu_device
*adev
,
508 struct amdgpu_vm
*vm
,
509 struct amdgpu_bo_va
*bo_va
,
514 if (!amdgpu_vm_ready(vm
))
517 r
= amdgpu_vm_clear_freed(adev
, vm
, NULL
);
521 if (operation
== AMDGPU_VA_OP_MAP
||
522 operation
== AMDGPU_VA_OP_REPLACE
) {
523 r
= amdgpu_vm_bo_update(adev
, bo_va
, false);
528 r
= amdgpu_vm_update_directories(adev
, vm
);
531 if (r
&& r
!= -ERESTARTSYS
)
532 DRM_ERROR("Couldn't update BO_VA (%d)\n", r
);
535 int amdgpu_gem_va_ioctl(struct drm_device
*dev
, void *data
,
536 struct drm_file
*filp
)
538 const uint32_t valid_flags
= AMDGPU_VM_DELAY_UPDATE
|
539 AMDGPU_VM_PAGE_READABLE
| AMDGPU_VM_PAGE_WRITEABLE
|
540 AMDGPU_VM_PAGE_EXECUTABLE
| AMDGPU_VM_MTYPE_MASK
;
541 const uint32_t prt_flags
= AMDGPU_VM_DELAY_UPDATE
|
544 struct drm_amdgpu_gem_va
*args
= data
;
545 struct drm_gem_object
*gobj
;
546 struct amdgpu_device
*adev
= dev
->dev_private
;
547 struct amdgpu_fpriv
*fpriv
= filp
->driver_priv
;
548 struct amdgpu_bo
*abo
;
549 struct amdgpu_bo_va
*bo_va
;
550 struct amdgpu_bo_list_entry vm_pd
;
551 struct ttm_validate_buffer tv
;
552 struct ww_acquire_ctx ticket
;
553 struct list_head list
, duplicates
;
557 if (args
->va_address
< AMDGPU_VA_RESERVED_SIZE
) {
558 dev_dbg(&dev
->pdev
->dev
,
559 "va_address 0x%LX is in reserved area 0x%LX\n",
560 args
->va_address
, AMDGPU_VA_RESERVED_SIZE
);
564 if (args
->va_address
>= AMDGPU_GMC_HOLE_START
&&
565 args
->va_address
< AMDGPU_GMC_HOLE_END
) {
566 dev_dbg(&dev
->pdev
->dev
,
567 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
568 args
->va_address
, AMDGPU_GMC_HOLE_START
,
569 AMDGPU_GMC_HOLE_END
);
573 args
->va_address
&= AMDGPU_GMC_HOLE_MASK
;
575 if ((args
->flags
& ~valid_flags
) && (args
->flags
& ~prt_flags
)) {
576 dev_dbg(&dev
->pdev
->dev
, "invalid flags combination 0x%08X\n",
581 switch (args
->operation
) {
582 case AMDGPU_VA_OP_MAP
:
583 case AMDGPU_VA_OP_UNMAP
:
584 case AMDGPU_VA_OP_CLEAR
:
585 case AMDGPU_VA_OP_REPLACE
:
588 dev_dbg(&dev
->pdev
->dev
, "unsupported operation %d\n",
593 INIT_LIST_HEAD(&list
);
594 INIT_LIST_HEAD(&duplicates
);
595 if ((args
->operation
!= AMDGPU_VA_OP_CLEAR
) &&
596 !(args
->flags
& AMDGPU_VM_PAGE_PRT
)) {
597 gobj
= drm_gem_object_lookup(filp
, args
->handle
);
600 abo
= gem_to_amdgpu_bo(gobj
);
602 if (abo
->flags
& AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
)
606 list_add(&tv
.head
, &list
);
612 amdgpu_vm_get_pd_bo(&fpriv
->vm
, &list
, &vm_pd
);
614 r
= ttm_eu_reserve_buffers(&ticket
, &list
, true, &duplicates
, false);
619 bo_va
= amdgpu_vm_bo_find(&fpriv
->vm
, abo
);
624 } else if (args
->operation
!= AMDGPU_VA_OP_CLEAR
) {
625 bo_va
= fpriv
->prt_va
;
630 switch (args
->operation
) {
631 case AMDGPU_VA_OP_MAP
:
632 va_flags
= amdgpu_gmc_get_pte_flags(adev
, args
->flags
);
633 r
= amdgpu_vm_bo_map(adev
, bo_va
, args
->va_address
,
634 args
->offset_in_bo
, args
->map_size
,
637 case AMDGPU_VA_OP_UNMAP
:
638 r
= amdgpu_vm_bo_unmap(adev
, bo_va
, args
->va_address
);
641 case AMDGPU_VA_OP_CLEAR
:
642 r
= amdgpu_vm_bo_clear_mappings(adev
, &fpriv
->vm
,
646 case AMDGPU_VA_OP_REPLACE
:
647 va_flags
= amdgpu_gmc_get_pte_flags(adev
, args
->flags
);
648 r
= amdgpu_vm_bo_replace_map(adev
, bo_va
, args
->va_address
,
649 args
->offset_in_bo
, args
->map_size
,
655 if (!r
&& !(args
->flags
& AMDGPU_VM_DELAY_UPDATE
) && !amdgpu_vm_debug
)
656 amdgpu_gem_va_update_vm(adev
, &fpriv
->vm
, bo_va
,
660 ttm_eu_backoff_reservation(&ticket
, &list
);
663 drm_gem_object_put_unlocked(gobj
);
667 int amdgpu_gem_op_ioctl(struct drm_device
*dev
, void *data
,
668 struct drm_file
*filp
)
670 struct amdgpu_device
*adev
= dev
->dev_private
;
671 struct drm_amdgpu_gem_op
*args
= data
;
672 struct drm_gem_object
*gobj
;
673 struct amdgpu_vm_bo_base
*base
;
674 struct amdgpu_bo
*robj
;
677 gobj
= drm_gem_object_lookup(filp
, args
->handle
);
681 robj
= gem_to_amdgpu_bo(gobj
);
683 r
= amdgpu_bo_reserve(robj
, false);
688 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO
: {
689 struct drm_amdgpu_gem_create_in info
;
690 void __user
*out
= u64_to_user_ptr(args
->value
);
692 info
.bo_size
= robj
->gem_base
.size
;
693 info
.alignment
= robj
->tbo
.mem
.page_alignment
<< PAGE_SHIFT
;
694 info
.domains
= robj
->preferred_domains
;
695 info
.domain_flags
= robj
->flags
;
696 amdgpu_bo_unreserve(robj
);
697 if (copy_to_user(out
, &info
, sizeof(info
)))
701 case AMDGPU_GEM_OP_SET_PLACEMENT
:
702 if (robj
->prime_shared_count
&& (args
->value
& AMDGPU_GEM_DOMAIN_VRAM
)) {
704 amdgpu_bo_unreserve(robj
);
707 if (amdgpu_ttm_tt_get_usermm(robj
->tbo
.ttm
)) {
709 amdgpu_bo_unreserve(robj
);
712 for (base
= robj
->vm_bo
; base
; base
= base
->next
)
713 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj
->tbo
.bdev
),
714 amdgpu_ttm_adev(base
->vm
->root
.base
.bo
->tbo
.bdev
))) {
716 amdgpu_bo_unreserve(robj
);
721 robj
->preferred_domains
= args
->value
& (AMDGPU_GEM_DOMAIN_VRAM
|
722 AMDGPU_GEM_DOMAIN_GTT
|
723 AMDGPU_GEM_DOMAIN_CPU
);
724 robj
->allowed_domains
= robj
->preferred_domains
;
725 if (robj
->allowed_domains
== AMDGPU_GEM_DOMAIN_VRAM
)
726 robj
->allowed_domains
|= AMDGPU_GEM_DOMAIN_GTT
;
728 if (robj
->flags
& AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
)
729 amdgpu_vm_bo_invalidate(adev
, robj
, true);
731 amdgpu_bo_unreserve(robj
);
734 amdgpu_bo_unreserve(robj
);
739 drm_gem_object_put_unlocked(gobj
);
743 int amdgpu_mode_dumb_create(struct drm_file
*file_priv
,
744 struct drm_device
*dev
,
745 struct drm_mode_create_dumb
*args
)
747 struct amdgpu_device
*adev
= dev
->dev_private
;
748 struct drm_gem_object
*gobj
;
750 u64 flags
= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
;
755 * The buffer returned from this function should be cleared, but
756 * it can only be done if the ring is enabled or we'll fail to
759 if (adev
->mman
.buffer_funcs_enabled
)
760 flags
|= AMDGPU_GEM_CREATE_VRAM_CLEARED
;
762 args
->pitch
= amdgpu_align_pitch(adev
, args
->width
,
763 DIV_ROUND_UP(args
->bpp
, 8), 0);
764 args
->size
= (u64
)args
->pitch
* args
->height
;
765 args
->size
= ALIGN(args
->size
, PAGE_SIZE
);
766 domain
= amdgpu_bo_get_preferred_pin_domain(adev
,
767 amdgpu_display_supported_domains(adev
));
768 r
= amdgpu_gem_object_create(adev
, args
->size
, 0, domain
, flags
,
769 ttm_bo_type_device
, NULL
, &gobj
);
773 r
= drm_gem_handle_create(file_priv
, gobj
, &handle
);
774 /* drop reference from allocate - handle holds it now */
775 drm_gem_object_put_unlocked(gobj
);
779 args
->handle
= handle
;
783 #if defined(CONFIG_DEBUG_FS)
785 #define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag) \
786 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \
787 seq_printf((m), " " #flag); \
790 static int amdgpu_debugfs_gem_bo_info(int id
, void *ptr
, void *data
)
792 struct drm_gem_object
*gobj
= ptr
;
793 struct amdgpu_bo
*bo
= gem_to_amdgpu_bo(gobj
);
794 struct seq_file
*m
= data
;
796 struct dma_buf_attachment
*attachment
;
797 struct dma_buf
*dma_buf
;
799 const char *placement
;
802 domain
= amdgpu_mem_type_to_domain(bo
->tbo
.mem
.mem_type
);
804 case AMDGPU_GEM_DOMAIN_VRAM
:
807 case AMDGPU_GEM_DOMAIN_GTT
:
810 case AMDGPU_GEM_DOMAIN_CPU
:
815 seq_printf(m
, "\t0x%08x: %12ld byte %s",
816 id
, amdgpu_bo_size(bo
), placement
);
818 pin_count
= READ_ONCE(bo
->pin_count
);
820 seq_printf(m
, " pin count %d", pin_count
);
822 dma_buf
= READ_ONCE(bo
->gem_base
.dma_buf
);
823 attachment
= READ_ONCE(bo
->gem_base
.import_attach
);
826 seq_printf(m
, " imported from %p", dma_buf
);
828 seq_printf(m
, " exported as %p", dma_buf
);
830 amdgpu_debugfs_gem_bo_print_flag(m
, bo
, CPU_ACCESS_REQUIRED
);
831 amdgpu_debugfs_gem_bo_print_flag(m
, bo
, NO_CPU_ACCESS
);
832 amdgpu_debugfs_gem_bo_print_flag(m
, bo
, CPU_GTT_USWC
);
833 amdgpu_debugfs_gem_bo_print_flag(m
, bo
, VRAM_CLEARED
);
834 amdgpu_debugfs_gem_bo_print_flag(m
, bo
, SHADOW
);
835 amdgpu_debugfs_gem_bo_print_flag(m
, bo
, VRAM_CONTIGUOUS
);
836 amdgpu_debugfs_gem_bo_print_flag(m
, bo
, VM_ALWAYS_VALID
);
837 amdgpu_debugfs_gem_bo_print_flag(m
, bo
, EXPLICIT_SYNC
);
844 static int amdgpu_debugfs_gem_info(struct seq_file
*m
, void *data
)
846 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
847 struct drm_device
*dev
= node
->minor
->dev
;
848 struct drm_file
*file
;
851 r
= mutex_lock_interruptible(&dev
->filelist_mutex
);
855 list_for_each_entry(file
, &dev
->filelist
, lhead
) {
856 struct task_struct
*task
;
859 * Although we have a valid reference on file->pid, that does
860 * not guarantee that the task_struct who called get_pid() is
861 * still alive (e.g. get_pid(current) => fork() => exit()).
862 * Therefore, we need to protect this ->comm access using RCU.
865 task
= pid_task(file
->pid
, PIDTYPE_PID
);
866 seq_printf(m
, "pid %8d command %s:\n", pid_nr(file
->pid
),
867 task
? task
->comm
: "<unknown>");
870 spin_lock(&file
->table_lock
);
871 idr_for_each(&file
->object_idr
, amdgpu_debugfs_gem_bo_info
, m
);
872 spin_unlock(&file
->table_lock
);
875 mutex_unlock(&dev
->filelist_mutex
);
879 static const struct drm_info_list amdgpu_debugfs_gem_list
[] = {
880 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info
, 0, NULL
},
884 int amdgpu_debugfs_gem_init(struct amdgpu_device
*adev
)
886 #if defined(CONFIG_DEBUG_FS)
887 return amdgpu_debugfs_add_files(adev
, amdgpu_debugfs_gem_list
, 1);