2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <linux/list.h>
33 #include <linux/slab.h>
34 #include <linux/dma-buf.h>
36 #include <drm/amdgpu_drm.h>
37 #include <drm/drm_cache.h>
39 #include "amdgpu_trace.h"
40 #include "amdgpu_amdkfd.h"
45 * This defines the interfaces to operate on an &amdgpu_bo buffer object which
46 * represents memory used by driver (VRAM, system memory, etc.). The driver
47 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces
48 * to create/destroy/set buffer object which are then managed by the kernel TTM
50 * The interfaces are also used internally by kernel clients, including gfx,
51 * uvd, etc. for kernel managed allocations used by the GPU.
55 static void amdgpu_bo_destroy(struct ttm_buffer_object
*tbo
)
57 struct amdgpu_device
*adev
= amdgpu_ttm_adev(tbo
->bdev
);
58 struct amdgpu_bo
*bo
= ttm_to_amdgpu_bo(tbo
);
59 struct amdgpu_bo_user
*ubo
;
63 if (bo
->tbo
.base
.import_attach
)
64 drm_prime_gem_destroy(&bo
->tbo
.base
, bo
->tbo
.sg
);
65 drm_gem_object_release(&bo
->tbo
.base
);
66 /* in case amdgpu_device_recover_vram got NULL of bo->parent */
67 if (!list_empty(&bo
->shadow_list
)) {
68 mutex_lock(&adev
->shadow_list_lock
);
69 list_del_init(&bo
->shadow_list
);
70 mutex_unlock(&adev
->shadow_list_lock
);
72 amdgpu_bo_unref(&bo
->parent
);
74 if (bo
->tbo
.type
== ttm_bo_type_device
) {
75 ubo
= to_amdgpu_bo_user(bo
);
83 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo
84 * @bo: buffer object to be checked
86 * Uses destroy function associated with the object to determine if this is
90 * true if the object belongs to &amdgpu_bo, false if not.
92 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object
*bo
)
94 if (bo
->destroy
== &amdgpu_bo_destroy
)
100 * amdgpu_bo_placement_from_domain - set buffer's placement
101 * @abo: &amdgpu_bo buffer object whose placement is to be set
102 * @domain: requested domain
104 * Sets buffer's placement according to requested domain and the buffer's
107 void amdgpu_bo_placement_from_domain(struct amdgpu_bo
*abo
, u32 domain
)
109 struct amdgpu_device
*adev
= amdgpu_ttm_adev(abo
->tbo
.bdev
);
110 struct ttm_placement
*placement
= &abo
->placement
;
111 struct ttm_place
*places
= abo
->placements
;
112 u64 flags
= abo
->flags
;
115 if (domain
& AMDGPU_GEM_DOMAIN_VRAM
) {
116 unsigned visible_pfn
= adev
->gmc
.visible_vram_size
>> PAGE_SHIFT
;
120 places
[c
].mem_type
= TTM_PL_VRAM
;
123 if (flags
& AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
)
124 places
[c
].lpfn
= visible_pfn
;
126 places
[c
].flags
|= TTM_PL_FLAG_TOPDOWN
;
128 if (flags
& AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
)
129 places
[c
].flags
|= TTM_PL_FLAG_CONTIGUOUS
;
133 if (domain
& AMDGPU_GEM_DOMAIN_GTT
) {
136 places
[c
].mem_type
= TTM_PL_TT
;
141 if (domain
& AMDGPU_GEM_DOMAIN_CPU
) {
144 places
[c
].mem_type
= TTM_PL_SYSTEM
;
149 if (domain
& AMDGPU_GEM_DOMAIN_GDS
) {
152 places
[c
].mem_type
= AMDGPU_PL_GDS
;
157 if (domain
& AMDGPU_GEM_DOMAIN_GWS
) {
160 places
[c
].mem_type
= AMDGPU_PL_GWS
;
165 if (domain
& AMDGPU_GEM_DOMAIN_OA
) {
168 places
[c
].mem_type
= AMDGPU_PL_OA
;
176 places
[c
].mem_type
= TTM_PL_SYSTEM
;
181 BUG_ON(c
>= AMDGPU_BO_MAX_PLACEMENTS
);
183 placement
->num_placement
= c
;
184 placement
->placement
= places
;
186 placement
->num_busy_placement
= c
;
187 placement
->busy_placement
= places
;
191 * amdgpu_bo_create_reserved - create reserved BO for kernel use
193 * @adev: amdgpu device object
194 * @size: size for the new BO
195 * @align: alignment for the new BO
196 * @domain: where to place it
197 * @bo_ptr: used to initialize BOs in structures
198 * @gpu_addr: GPU addr of the pinned BO
199 * @cpu_addr: optional CPU address mapping
201 * Allocates and pins a BO for kernel internal use, and returns it still
204 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
207 * 0 on success, negative error code otherwise.
209 int amdgpu_bo_create_reserved(struct amdgpu_device
*adev
,
210 unsigned long size
, int align
,
211 u32 domain
, struct amdgpu_bo
**bo_ptr
,
212 u64
*gpu_addr
, void **cpu_addr
)
214 struct amdgpu_bo_param bp
;
219 amdgpu_bo_unref(bo_ptr
);
223 memset(&bp
, 0, sizeof(bp
));
225 bp
.byte_align
= align
;
227 bp
.flags
= cpu_addr
? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
228 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS
;
229 bp
.flags
|= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
;
230 bp
.type
= ttm_bo_type_kernel
;
232 bp
.bo_ptr_size
= sizeof(struct amdgpu_bo
);
235 r
= amdgpu_bo_create(adev
, &bp
, bo_ptr
);
237 dev_err(adev
->dev
, "(%d) failed to allocate kernel bo\n",
244 r
= amdgpu_bo_reserve(*bo_ptr
, false);
246 dev_err(adev
->dev
, "(%d) failed to reserve kernel bo\n", r
);
250 r
= amdgpu_bo_pin(*bo_ptr
, domain
);
252 dev_err(adev
->dev
, "(%d) kernel bo pin failed\n", r
);
253 goto error_unreserve
;
256 r
= amdgpu_ttm_alloc_gart(&(*bo_ptr
)->tbo
);
258 dev_err(adev
->dev
, "%p bind failed\n", *bo_ptr
);
263 *gpu_addr
= amdgpu_bo_gpu_offset(*bo_ptr
);
266 r
= amdgpu_bo_kmap(*bo_ptr
, cpu_addr
);
268 dev_err(adev
->dev
, "(%d) kernel bo map failed\n", r
);
276 amdgpu_bo_unpin(*bo_ptr
);
278 amdgpu_bo_unreserve(*bo_ptr
);
282 amdgpu_bo_unref(bo_ptr
);
288 * amdgpu_bo_create_kernel - create BO for kernel use
290 * @adev: amdgpu device object
291 * @size: size for the new BO
292 * @align: alignment for the new BO
293 * @domain: where to place it
294 * @bo_ptr: used to initialize BOs in structures
295 * @gpu_addr: GPU addr of the pinned BO
296 * @cpu_addr: optional CPU address mapping
298 * Allocates and pins a BO for kernel internal use.
300 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
303 * 0 on success, negative error code otherwise.
305 int amdgpu_bo_create_kernel(struct amdgpu_device
*adev
,
306 unsigned long size
, int align
,
307 u32 domain
, struct amdgpu_bo
**bo_ptr
,
308 u64
*gpu_addr
, void **cpu_addr
)
312 r
= amdgpu_bo_create_reserved(adev
, size
, align
, domain
, bo_ptr
,
319 amdgpu_bo_unreserve(*bo_ptr
);
325 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location
327 * @adev: amdgpu device object
328 * @offset: offset of the BO
329 * @size: size of the BO
330 * @domain: where to place it
331 * @bo_ptr: used to initialize BOs in structures
332 * @cpu_addr: optional CPU address mapping
334 * Creates a kernel BO at a specific offset in the address space of the domain.
337 * 0 on success, negative error code otherwise.
339 int amdgpu_bo_create_kernel_at(struct amdgpu_device
*adev
,
340 uint64_t offset
, uint64_t size
, uint32_t domain
,
341 struct amdgpu_bo
**bo_ptr
, void **cpu_addr
)
343 struct ttm_operation_ctx ctx
= { false, false };
348 size
= ALIGN(size
, PAGE_SIZE
);
350 r
= amdgpu_bo_create_reserved(adev
, size
, PAGE_SIZE
, domain
, bo_ptr
,
355 if ((*bo_ptr
) == NULL
)
359 * Remove the original mem node and create a new one at the request
363 amdgpu_bo_kunmap(*bo_ptr
);
365 ttm_resource_free(&(*bo_ptr
)->tbo
, &(*bo_ptr
)->tbo
.mem
);
367 for (i
= 0; i
< (*bo_ptr
)->placement
.num_placement
; ++i
) {
368 (*bo_ptr
)->placements
[i
].fpfn
= offset
>> PAGE_SHIFT
;
369 (*bo_ptr
)->placements
[i
].lpfn
= (offset
+ size
) >> PAGE_SHIFT
;
371 r
= ttm_bo_mem_space(&(*bo_ptr
)->tbo
, &(*bo_ptr
)->placement
,
372 &(*bo_ptr
)->tbo
.mem
, &ctx
);
377 r
= amdgpu_bo_kmap(*bo_ptr
, cpu_addr
);
382 amdgpu_bo_unreserve(*bo_ptr
);
386 amdgpu_bo_unreserve(*bo_ptr
);
387 amdgpu_bo_unref(bo_ptr
);
392 * amdgpu_bo_free_kernel - free BO for kernel use
394 * @bo: amdgpu BO to free
395 * @gpu_addr: pointer to where the BO's GPU memory space address was stored
396 * @cpu_addr: pointer to where the BO's CPU memory space address was stored
398 * unmaps and unpin a BO for kernel internal use.
400 void amdgpu_bo_free_kernel(struct amdgpu_bo
**bo
, u64
*gpu_addr
,
406 if (likely(amdgpu_bo_reserve(*bo
, true) == 0)) {
408 amdgpu_bo_kunmap(*bo
);
410 amdgpu_bo_unpin(*bo
);
411 amdgpu_bo_unreserve(*bo
);
422 /* Validate bo size is bit bigger then the request domain */
423 static bool amdgpu_bo_validate_size(struct amdgpu_device
*adev
,
424 unsigned long size
, u32 domain
)
426 struct ttm_resource_manager
*man
= NULL
;
429 * If GTT is part of requested domains the check must succeed to
430 * allow fall back to GTT
432 if (domain
& AMDGPU_GEM_DOMAIN_GTT
) {
433 man
= ttm_manager_type(&adev
->mman
.bdev
, TTM_PL_TT
);
435 if (size
< (man
->size
<< PAGE_SHIFT
))
441 if (domain
& AMDGPU_GEM_DOMAIN_VRAM
) {
442 man
= ttm_manager_type(&adev
->mman
.bdev
, TTM_PL_VRAM
);
444 if (size
< (man
->size
<< PAGE_SHIFT
))
451 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
455 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size
,
456 man
->size
<< PAGE_SHIFT
);
460 bool amdgpu_bo_support_uswc(u64 bo_flags
)
464 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
465 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
468 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
469 /* Don't try to enable write-combining when it can't work, or things
471 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
474 #ifndef CONFIG_COMPILE_TEST
475 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
476 thanks to write-combining
479 if (bo_flags
& AMDGPU_GEM_CREATE_CPU_GTT_USWC
)
480 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
481 "better performance thanks to write-combining\n");
484 /* For architectures that don't support WC memory,
485 * mask out the WC flag from the BO
487 if (!drm_arch_can_wc_memory())
495 * amdgpu_bo_create - create an &amdgpu_bo buffer object
496 * @adev: amdgpu device object
497 * @bp: parameters to be used for the buffer object
498 * @bo_ptr: pointer to the buffer object pointer
500 * Creates an &amdgpu_bo buffer object.
503 * 0 for success or a negative error code on failure.
505 int amdgpu_bo_create(struct amdgpu_device
*adev
,
506 struct amdgpu_bo_param
*bp
,
507 struct amdgpu_bo
**bo_ptr
)
509 struct ttm_operation_ctx ctx
= {
510 .interruptible
= (bp
->type
!= ttm_bo_type_kernel
),
511 .no_wait_gpu
= bp
->no_wait_gpu
,
512 /* We opt to avoid OOM on system pages allocations */
513 .gfp_retry_mayfail
= true,
514 .allow_res_evict
= bp
->type
!= ttm_bo_type_kernel
,
517 struct amdgpu_bo
*bo
;
518 unsigned long page_align
, size
= bp
->size
;
521 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */
522 if (bp
->domain
& (AMDGPU_GEM_DOMAIN_GWS
| AMDGPU_GEM_DOMAIN_OA
)) {
523 /* GWS and OA don't need any alignment. */
524 page_align
= bp
->byte_align
;
526 } else if (bp
->domain
& AMDGPU_GEM_DOMAIN_GDS
) {
527 /* Both size and alignment must be a multiple of 4. */
528 page_align
= ALIGN(bp
->byte_align
, 4);
529 size
= ALIGN(size
, 4) << PAGE_SHIFT
;
531 /* Memory should be aligned at least to a page size. */
532 page_align
= ALIGN(bp
->byte_align
, PAGE_SIZE
) >> PAGE_SHIFT
;
533 size
= ALIGN(size
, PAGE_SIZE
);
536 if (!amdgpu_bo_validate_size(adev
, size
, bp
->domain
))
539 BUG_ON(bp
->bo_ptr_size
< sizeof(struct amdgpu_bo
));
542 bo
= kzalloc(bp
->bo_ptr_size
, GFP_KERNEL
);
545 drm_gem_private_object_init(adev_to_drm(adev
), &bo
->tbo
.base
, size
);
546 INIT_LIST_HEAD(&bo
->shadow_list
);
548 bo
->preferred_domains
= bp
->preferred_domain
? bp
->preferred_domain
:
550 bo
->allowed_domains
= bo
->preferred_domains
;
551 if (bp
->type
!= ttm_bo_type_kernel
&&
552 bo
->allowed_domains
== AMDGPU_GEM_DOMAIN_VRAM
)
553 bo
->allowed_domains
|= AMDGPU_GEM_DOMAIN_GTT
;
555 bo
->flags
= bp
->flags
;
557 if (!amdgpu_bo_support_uswc(bo
->flags
))
558 bo
->flags
&= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
560 bo
->tbo
.bdev
= &adev
->mman
.bdev
;
561 if (bp
->domain
& (AMDGPU_GEM_DOMAIN_GWS
| AMDGPU_GEM_DOMAIN_OA
|
562 AMDGPU_GEM_DOMAIN_GDS
))
563 amdgpu_bo_placement_from_domain(bo
, AMDGPU_GEM_DOMAIN_CPU
);
565 amdgpu_bo_placement_from_domain(bo
, bp
->domain
);
566 if (bp
->type
== ttm_bo_type_kernel
)
567 bo
->tbo
.priority
= 1;
569 r
= ttm_bo_init_reserved(&adev
->mman
.bdev
, &bo
->tbo
, size
, bp
->type
,
570 &bo
->placement
, page_align
, &ctx
, NULL
,
571 bp
->resv
, &amdgpu_bo_destroy
);
572 if (unlikely(r
!= 0))
575 if (!amdgpu_gmc_vram_full_visible(&adev
->gmc
) &&
576 bo
->tbo
.mem
.mem_type
== TTM_PL_VRAM
&&
577 bo
->tbo
.mem
.start
< adev
->gmc
.visible_vram_size
>> PAGE_SHIFT
)
578 amdgpu_cs_report_moved_bytes(adev
, ctx
.bytes_moved
,
581 amdgpu_cs_report_moved_bytes(adev
, ctx
.bytes_moved
, 0);
583 if (bp
->flags
& AMDGPU_GEM_CREATE_VRAM_CLEARED
&&
584 bo
->tbo
.mem
.mem_type
== TTM_PL_VRAM
) {
585 struct dma_fence
*fence
;
587 r
= amdgpu_fill_buffer(bo
, 0, bo
->tbo
.base
.resv
, &fence
);
591 amdgpu_bo_fence(bo
, fence
, false);
592 dma_fence_put(bo
->tbo
.moving
);
593 bo
->tbo
.moving
= dma_fence_get(fence
);
594 dma_fence_put(fence
);
597 amdgpu_bo_unreserve(bo
);
600 trace_amdgpu_bo_create(bo
);
602 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
603 if (bp
->type
== ttm_bo_type_device
)
604 bo
->flags
&= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
;
610 dma_resv_unlock(bo
->tbo
.base
.resv
);
611 amdgpu_bo_unref(&bo
);
615 int amdgpu_bo_create_shadow(struct amdgpu_device
*adev
,
617 struct amdgpu_bo
*bo
)
619 struct amdgpu_bo_param bp
;
625 memset(&bp
, 0, sizeof(bp
));
627 bp
.domain
= AMDGPU_GEM_DOMAIN_GTT
;
628 bp
.flags
= AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
629 bp
.type
= ttm_bo_type_kernel
;
630 bp
.resv
= bo
->tbo
.base
.resv
;
631 bp
.bo_ptr_size
= sizeof(struct amdgpu_bo
);
633 r
= amdgpu_bo_create(adev
, &bp
, &bo
->shadow
);
635 bo
->shadow
->parent
= amdgpu_bo_ref(bo
);
636 mutex_lock(&adev
->shadow_list_lock
);
637 list_add_tail(&bo
->shadow
->shadow_list
, &adev
->shadow_list
);
638 mutex_unlock(&adev
->shadow_list_lock
);
645 * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object
646 * @adev: amdgpu device object
647 * @bp: parameters to be used for the buffer object
648 * @ubo_ptr: pointer to the buffer object pointer
650 * Create a BO to be used by user application;
653 * 0 for success or a negative error code on failure.
656 int amdgpu_bo_create_user(struct amdgpu_device
*adev
,
657 struct amdgpu_bo_param
*bp
,
658 struct amdgpu_bo_user
**ubo_ptr
)
660 struct amdgpu_bo
*bo_ptr
;
663 bp
->bo_ptr_size
= sizeof(struct amdgpu_bo_user
);
664 r
= amdgpu_bo_create(adev
, bp
, &bo_ptr
);
668 *ubo_ptr
= to_amdgpu_bo_user(bo_ptr
);
672 * amdgpu_bo_validate - validate an &amdgpu_bo buffer object
673 * @bo: pointer to the buffer object
675 * Sets placement according to domain; and changes placement and caching
676 * policy of the buffer object according to the placement.
677 * This is used for validating shadow bos. It calls ttm_bo_validate() to
678 * make sure the buffer is resident where it needs to be.
681 * 0 for success or a negative error code on failure.
683 int amdgpu_bo_validate(struct amdgpu_bo
*bo
)
685 struct ttm_operation_ctx ctx
= { false, false };
689 if (bo
->tbo
.pin_count
)
692 domain
= bo
->preferred_domains
;
695 amdgpu_bo_placement_from_domain(bo
, domain
);
696 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, &ctx
);
697 if (unlikely(r
== -ENOMEM
) && domain
!= bo
->allowed_domains
) {
698 domain
= bo
->allowed_domains
;
706 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow
708 * @shadow: &amdgpu_bo shadow to be restored
709 * @fence: dma_fence associated with the operation
711 * Copies a buffer object's shadow content back to the object.
712 * This is used for recovering a buffer from its shadow in case of a gpu
713 * reset where vram context may be lost.
716 * 0 for success or a negative error code on failure.
718 int amdgpu_bo_restore_shadow(struct amdgpu_bo
*shadow
, struct dma_fence
**fence
)
721 struct amdgpu_device
*adev
= amdgpu_ttm_adev(shadow
->tbo
.bdev
);
722 struct amdgpu_ring
*ring
= adev
->mman
.buffer_funcs_ring
;
723 uint64_t shadow_addr
, parent_addr
;
725 shadow_addr
= amdgpu_bo_gpu_offset(shadow
);
726 parent_addr
= amdgpu_bo_gpu_offset(shadow
->parent
);
728 return amdgpu_copy_buffer(ring
, shadow_addr
, parent_addr
,
729 amdgpu_bo_size(shadow
), NULL
, fence
,
734 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object
735 * @bo: &amdgpu_bo buffer object to be mapped
736 * @ptr: kernel virtual address to be returned
738 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls
739 * amdgpu_bo_kptr() to get the kernel virtual address.
742 * 0 for success or a negative error code on failure.
744 int amdgpu_bo_kmap(struct amdgpu_bo
*bo
, void **ptr
)
749 if (bo
->flags
& AMDGPU_GEM_CREATE_NO_CPU_ACCESS
)
752 kptr
= amdgpu_bo_kptr(bo
);
759 r
= dma_resv_wait_timeout_rcu(bo
->tbo
.base
.resv
, false, false,
760 MAX_SCHEDULE_TIMEOUT
);
764 r
= ttm_bo_kmap(&bo
->tbo
, 0, bo
->tbo
.mem
.num_pages
, &bo
->kmap
);
769 *ptr
= amdgpu_bo_kptr(bo
);
775 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object
776 * @bo: &amdgpu_bo buffer object
778 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address
781 * the virtual address of a buffer object area.
783 void *amdgpu_bo_kptr(struct amdgpu_bo
*bo
)
787 return ttm_kmap_obj_virtual(&bo
->kmap
, &is_iomem
);
791 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object
792 * @bo: &amdgpu_bo buffer object to be unmapped
794 * Unmaps a kernel map set up by amdgpu_bo_kmap().
796 void amdgpu_bo_kunmap(struct amdgpu_bo
*bo
)
799 ttm_bo_kunmap(&bo
->kmap
);
803 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object
804 * @bo: &amdgpu_bo buffer object
806 * References the contained &ttm_buffer_object.
809 * a refcounted pointer to the &amdgpu_bo buffer object.
811 struct amdgpu_bo
*amdgpu_bo_ref(struct amdgpu_bo
*bo
)
816 ttm_bo_get(&bo
->tbo
);
821 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object
822 * @bo: &amdgpu_bo buffer object
824 * Unreferences the contained &ttm_buffer_object and clear the pointer
826 void amdgpu_bo_unref(struct amdgpu_bo
**bo
)
828 struct ttm_buffer_object
*tbo
;
839 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object
840 * @bo: &amdgpu_bo buffer object to be pinned
841 * @domain: domain to be pinned to
842 * @min_offset: the start of requested address range
843 * @max_offset: the end of requested address range
845 * Pins the buffer object according to requested domain and address range. If
846 * the memory is unbound gart memory, binds the pages into gart table. Adjusts
847 * pin_count and pin_size accordingly.
849 * Pinning means to lock pages in memory along with keeping them at a fixed
850 * offset. It is required when a buffer can not be moved, for example, when
851 * a display buffer is being scanned out.
853 * Compared with amdgpu_bo_pin(), this function gives more flexibility on
854 * where to pin a buffer if there are specific restrictions on where a buffer
858 * 0 for success or a negative error code on failure.
860 int amdgpu_bo_pin_restricted(struct amdgpu_bo
*bo
, u32 domain
,
861 u64 min_offset
, u64 max_offset
)
863 struct amdgpu_device
*adev
= amdgpu_ttm_adev(bo
->tbo
.bdev
);
864 struct ttm_operation_ctx ctx
= { false, false };
867 if (amdgpu_ttm_tt_get_usermm(bo
->tbo
.ttm
))
870 if (WARN_ON_ONCE(min_offset
> max_offset
))
873 /* A shared bo cannot be migrated to VRAM */
874 if (bo
->prime_shared_count
|| bo
->tbo
.base
.import_attach
) {
875 if (domain
& AMDGPU_GEM_DOMAIN_GTT
)
876 domain
= AMDGPU_GEM_DOMAIN_GTT
;
881 /* This assumes only APU display buffers are pinned with (VRAM|GTT).
882 * See function amdgpu_display_supported_domains()
884 domain
= amdgpu_bo_get_preferred_pin_domain(adev
, domain
);
886 if (bo
->tbo
.pin_count
) {
887 uint32_t mem_type
= bo
->tbo
.mem
.mem_type
;
888 uint32_t mem_flags
= bo
->tbo
.mem
.placement
;
890 if (!(domain
& amdgpu_mem_type_to_domain(mem_type
)))
893 if ((mem_type
== TTM_PL_VRAM
) &&
894 (bo
->flags
& AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
) &&
895 !(mem_flags
& TTM_PL_FLAG_CONTIGUOUS
))
898 ttm_bo_pin(&bo
->tbo
);
900 if (max_offset
!= 0) {
901 u64 domain_start
= amdgpu_ttm_domain_start(adev
,
903 WARN_ON_ONCE(max_offset
<
904 (amdgpu_bo_gpu_offset(bo
) - domain_start
));
910 if (bo
->tbo
.base
.import_attach
)
911 dma_buf_pin(bo
->tbo
.base
.import_attach
);
913 /* force to pin into visible video ram */
914 if (!(bo
->flags
& AMDGPU_GEM_CREATE_NO_CPU_ACCESS
))
915 bo
->flags
|= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
;
916 amdgpu_bo_placement_from_domain(bo
, domain
);
917 for (i
= 0; i
< bo
->placement
.num_placement
; i
++) {
920 fpfn
= min_offset
>> PAGE_SHIFT
;
921 lpfn
= max_offset
>> PAGE_SHIFT
;
923 if (fpfn
> bo
->placements
[i
].fpfn
)
924 bo
->placements
[i
].fpfn
= fpfn
;
925 if (!bo
->placements
[i
].lpfn
||
926 (lpfn
&& lpfn
< bo
->placements
[i
].lpfn
))
927 bo
->placements
[i
].lpfn
= lpfn
;
930 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, &ctx
);
932 dev_err(adev
->dev
, "%p pin failed\n", bo
);
936 ttm_bo_pin(&bo
->tbo
);
938 domain
= amdgpu_mem_type_to_domain(bo
->tbo
.mem
.mem_type
);
939 if (domain
== AMDGPU_GEM_DOMAIN_VRAM
) {
940 atomic64_add(amdgpu_bo_size(bo
), &adev
->vram_pin_size
);
941 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo
),
942 &adev
->visible_pin_size
);
943 } else if (domain
== AMDGPU_GEM_DOMAIN_GTT
) {
944 atomic64_add(amdgpu_bo_size(bo
), &adev
->gart_pin_size
);
952 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object
953 * @bo: &amdgpu_bo buffer object to be pinned
954 * @domain: domain to be pinned to
956 * A simple wrapper to amdgpu_bo_pin_restricted().
957 * Provides a simpler API for buffers that do not have any strict restrictions
958 * on where a buffer must be located.
961 * 0 for success or a negative error code on failure.
963 int amdgpu_bo_pin(struct amdgpu_bo
*bo
, u32 domain
)
965 bo
->flags
|= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
;
966 return amdgpu_bo_pin_restricted(bo
, domain
, 0, 0);
970 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object
971 * @bo: &amdgpu_bo buffer object to be unpinned
973 * Decreases the pin_count, and clears the flags if pin_count reaches 0.
974 * Changes placement and pin size accordingly.
977 * 0 for success or a negative error code on failure.
979 void amdgpu_bo_unpin(struct amdgpu_bo
*bo
)
981 struct amdgpu_device
*adev
= amdgpu_ttm_adev(bo
->tbo
.bdev
);
983 ttm_bo_unpin(&bo
->tbo
);
984 if (bo
->tbo
.pin_count
)
987 if (bo
->tbo
.base
.import_attach
)
988 dma_buf_unpin(bo
->tbo
.base
.import_attach
);
990 if (bo
->tbo
.mem
.mem_type
== TTM_PL_VRAM
) {
991 atomic64_sub(amdgpu_bo_size(bo
), &adev
->vram_pin_size
);
992 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo
),
993 &adev
->visible_pin_size
);
994 } else if (bo
->tbo
.mem
.mem_type
== TTM_PL_TT
) {
995 atomic64_sub(amdgpu_bo_size(bo
), &adev
->gart_pin_size
);
1000 * amdgpu_bo_evict_vram - evict VRAM buffers
1001 * @adev: amdgpu device object
1003 * Evicts all VRAM buffers on the lru list of the memory type.
1004 * Mainly used for evicting vram at suspend time.
1007 * 0 for success or a negative error code on failure.
1009 int amdgpu_bo_evict_vram(struct amdgpu_device
*adev
)
1011 struct ttm_resource_manager
*man
;
1013 if (adev
->in_s3
&& (adev
->flags
& AMD_IS_APU
)) {
1014 /* No need to evict vram on APUs for suspend to ram */
1018 man
= ttm_manager_type(&adev
->mman
.bdev
, TTM_PL_VRAM
);
1019 return ttm_resource_manager_evict_all(&adev
->mman
.bdev
, man
);
1022 static const char *amdgpu_vram_names
[] = {
1037 * amdgpu_bo_init - initialize memory manager
1038 * @adev: amdgpu device object
1040 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager.
1043 * 0 for success or a negative error code on failure.
1045 int amdgpu_bo_init(struct amdgpu_device
*adev
)
1047 /* On A+A platform, VRAM can be mapped as WB */
1048 if (!adev
->gmc
.xgmi
.connected_to_cpu
) {
1049 /* reserve PAT memory space to WC for VRAM */
1050 arch_io_reserve_memtype_wc(adev
->gmc
.aper_base
,
1051 adev
->gmc
.aper_size
);
1053 /* Add an MTRR for the VRAM */
1054 adev
->gmc
.vram_mtrr
= arch_phys_wc_add(adev
->gmc
.aper_base
,
1055 adev
->gmc
.aper_size
);
1058 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
1059 adev
->gmc
.mc_vram_size
>> 20,
1060 (unsigned long long)adev
->gmc
.aper_size
>> 20);
1061 DRM_INFO("RAM width %dbits %s\n",
1062 adev
->gmc
.vram_width
, amdgpu_vram_names
[adev
->gmc
.vram_type
]);
1063 return amdgpu_ttm_init(adev
);
1067 * amdgpu_bo_fini - tear down memory manager
1068 * @adev: amdgpu device object
1070 * Reverses amdgpu_bo_init() to tear down memory manager.
1072 void amdgpu_bo_fini(struct amdgpu_device
*adev
)
1074 amdgpu_ttm_fini(adev
);
1075 if (!adev
->gmc
.xgmi
.connected_to_cpu
) {
1076 arch_phys_wc_del(adev
->gmc
.vram_mtrr
);
1077 arch_io_free_memtype_wc(adev
->gmc
.aper_base
, adev
->gmc
.aper_size
);
1082 * amdgpu_bo_set_tiling_flags - set tiling flags
1083 * @bo: &amdgpu_bo buffer object
1084 * @tiling_flags: new flags
1086 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or
1087 * kernel driver to set the tiling flags on a buffer.
1090 * 0 for success or a negative error code on failure.
1092 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo
*bo
, u64 tiling_flags
)
1094 struct amdgpu_device
*adev
= amdgpu_ttm_adev(bo
->tbo
.bdev
);
1095 struct amdgpu_bo_user
*ubo
;
1097 BUG_ON(bo
->tbo
.type
== ttm_bo_type_kernel
);
1098 if (adev
->family
<= AMDGPU_FAMILY_CZ
&&
1099 AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
) > 6)
1102 ubo
= to_amdgpu_bo_user(bo
);
1103 ubo
->tiling_flags
= tiling_flags
;
1108 * amdgpu_bo_get_tiling_flags - get tiling flags
1109 * @bo: &amdgpu_bo buffer object
1110 * @tiling_flags: returned flags
1112 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to
1113 * set the tiling flags on a buffer.
1115 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo
*bo
, u64
*tiling_flags
)
1117 struct amdgpu_bo_user
*ubo
;
1119 BUG_ON(bo
->tbo
.type
== ttm_bo_type_kernel
);
1120 dma_resv_assert_held(bo
->tbo
.base
.resv
);
1121 ubo
= to_amdgpu_bo_user(bo
);
1124 *tiling_flags
= ubo
->tiling_flags
;
1128 * amdgpu_bo_set_metadata - set metadata
1129 * @bo: &amdgpu_bo buffer object
1130 * @metadata: new metadata
1131 * @metadata_size: size of the new metadata
1132 * @flags: flags of the new metadata
1134 * Sets buffer object's metadata, its size and flags.
1135 * Used via GEM ioctl.
1138 * 0 for success or a negative error code on failure.
1140 int amdgpu_bo_set_metadata (struct amdgpu_bo
*bo
, void *metadata
,
1141 uint32_t metadata_size
, uint64_t flags
)
1143 struct amdgpu_bo_user
*ubo
;
1146 BUG_ON(bo
->tbo
.type
== ttm_bo_type_kernel
);
1147 ubo
= to_amdgpu_bo_user(bo
);
1148 if (!metadata_size
) {
1149 if (ubo
->metadata_size
) {
1150 kfree(ubo
->metadata
);
1151 ubo
->metadata
= NULL
;
1152 ubo
->metadata_size
= 0;
1157 if (metadata
== NULL
)
1160 buffer
= kmemdup(metadata
, metadata_size
, GFP_KERNEL
);
1164 kfree(ubo
->metadata
);
1165 ubo
->metadata_flags
= flags
;
1166 ubo
->metadata
= buffer
;
1167 ubo
->metadata_size
= metadata_size
;
1173 * amdgpu_bo_get_metadata - get metadata
1174 * @bo: &amdgpu_bo buffer object
1175 * @buffer: returned metadata
1176 * @buffer_size: size of the buffer
1177 * @metadata_size: size of the returned metadata
1178 * @flags: flags of the returned metadata
1180 * Gets buffer object's metadata, its size and flags. buffer_size shall not be
1181 * less than metadata_size.
1182 * Used via GEM ioctl.
1185 * 0 for success or a negative error code on failure.
1187 int amdgpu_bo_get_metadata(struct amdgpu_bo
*bo
, void *buffer
,
1188 size_t buffer_size
, uint32_t *metadata_size
,
1191 struct amdgpu_bo_user
*ubo
;
1193 if (!buffer
&& !metadata_size
)
1196 BUG_ON(bo
->tbo
.type
== ttm_bo_type_kernel
);
1197 ubo
= to_amdgpu_bo_user(bo
);
1199 if (buffer_size
< ubo
->metadata_size
)
1202 if (ubo
->metadata_size
)
1203 memcpy(buffer
, ubo
->metadata
, ubo
->metadata_size
);
1207 *metadata_size
= ubo
->metadata_size
;
1209 *flags
= ubo
->metadata_flags
;
1215 * amdgpu_bo_move_notify - notification about a memory move
1216 * @bo: pointer to a buffer object
1217 * @evict: if this move is evicting the buffer from the graphics address space
1218 * @new_mem: new information of the bufer object
1220 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs
1222 * TTM driver callback which is called when ttm moves a buffer.
1224 void amdgpu_bo_move_notify(struct ttm_buffer_object
*bo
,
1226 struct ttm_resource
*new_mem
)
1228 struct amdgpu_device
*adev
= amdgpu_ttm_adev(bo
->bdev
);
1229 struct amdgpu_bo
*abo
;
1230 struct ttm_resource
*old_mem
= &bo
->mem
;
1232 if (!amdgpu_bo_is_amdgpu_bo(bo
))
1235 abo
= ttm_to_amdgpu_bo(bo
);
1236 amdgpu_vm_bo_invalidate(adev
, abo
, evict
);
1238 amdgpu_bo_kunmap(abo
);
1240 if (abo
->tbo
.base
.dma_buf
&& !abo
->tbo
.base
.import_attach
&&
1241 bo
->mem
.mem_type
!= TTM_PL_SYSTEM
)
1242 dma_buf_move_notify(abo
->tbo
.base
.dma_buf
);
1244 /* remember the eviction */
1246 atomic64_inc(&adev
->num_evictions
);
1248 /* update statistics */
1252 /* move_notify is called before move happens */
1253 trace_amdgpu_bo_move(abo
, new_mem
->mem_type
, old_mem
->mem_type
);
1256 void amdgpu_bo_get_memory(struct amdgpu_bo
*bo
, uint64_t *vram_mem
,
1257 uint64_t *gtt_mem
, uint64_t *cpu_mem
)
1259 unsigned int domain
;
1261 domain
= amdgpu_mem_type_to_domain(bo
->tbo
.mem
.mem_type
);
1263 case AMDGPU_GEM_DOMAIN_VRAM
:
1264 *vram_mem
+= amdgpu_bo_size(bo
);
1266 case AMDGPU_GEM_DOMAIN_GTT
:
1267 *gtt_mem
+= amdgpu_bo_size(bo
);
1269 case AMDGPU_GEM_DOMAIN_CPU
:
1271 *cpu_mem
+= amdgpu_bo_size(bo
);
1277 * amdgpu_bo_release_notify - notification about a BO being released
1278 * @bo: pointer to a buffer object
1280 * Wipes VRAM buffers whose contents should not be leaked before the
1281 * memory is released.
1283 void amdgpu_bo_release_notify(struct ttm_buffer_object
*bo
)
1285 struct dma_fence
*fence
= NULL
;
1286 struct amdgpu_bo
*abo
;
1289 if (!amdgpu_bo_is_amdgpu_bo(bo
))
1292 abo
= ttm_to_amdgpu_bo(bo
);
1295 amdgpu_amdkfd_unreserve_memory_limit(abo
);
1297 /* We only remove the fence if the resv has individualized. */
1298 WARN_ON_ONCE(bo
->type
== ttm_bo_type_kernel
1299 && bo
->base
.resv
!= &bo
->base
._resv
);
1300 if (bo
->base
.resv
== &bo
->base
._resv
)
1301 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo
);
1303 if (bo
->mem
.mem_type
!= TTM_PL_VRAM
|| !bo
->mem
.mm_node
||
1304 !(abo
->flags
& AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE
))
1307 dma_resv_lock(bo
->base
.resv
, NULL
);
1309 r
= amdgpu_fill_buffer(abo
, AMDGPU_POISON
, bo
->base
.resv
, &fence
);
1311 amdgpu_bo_fence(abo
, fence
, false);
1312 dma_fence_put(fence
);
1315 dma_resv_unlock(bo
->base
.resv
);
1319 * amdgpu_bo_fault_reserve_notify - notification about a memory fault
1320 * @bo: pointer to a buffer object
1322 * Notifies the driver we are taking a fault on this BO and have reserved it,
1323 * also performs bookkeeping.
1324 * TTM driver callback for dealing with vm faults.
1327 * 0 for success or a negative error code on failure.
1329 vm_fault_t
amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object
*bo
)
1331 struct amdgpu_device
*adev
= amdgpu_ttm_adev(bo
->bdev
);
1332 struct ttm_operation_ctx ctx
= { false, false };
1333 struct amdgpu_bo
*abo
= ttm_to_amdgpu_bo(bo
);
1334 unsigned long offset
;
1337 /* Remember that this BO was accessed by the CPU */
1338 abo
->flags
|= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
;
1340 if (bo
->mem
.mem_type
!= TTM_PL_VRAM
)
1343 offset
= bo
->mem
.start
<< PAGE_SHIFT
;
1344 if ((offset
+ bo
->base
.size
) <= adev
->gmc
.visible_vram_size
)
1347 /* Can't move a pinned BO to visible VRAM */
1348 if (abo
->tbo
.pin_count
> 0)
1349 return VM_FAULT_SIGBUS
;
1351 /* hurrah the memory is not visible ! */
1352 atomic64_inc(&adev
->num_vram_cpu_page_faults
);
1353 amdgpu_bo_placement_from_domain(abo
, AMDGPU_GEM_DOMAIN_VRAM
|
1354 AMDGPU_GEM_DOMAIN_GTT
);
1356 /* Avoid costly evictions; only set GTT as a busy placement */
1357 abo
->placement
.num_busy_placement
= 1;
1358 abo
->placement
.busy_placement
= &abo
->placements
[1];
1360 r
= ttm_bo_validate(bo
, &abo
->placement
, &ctx
);
1361 if (unlikely(r
== -EBUSY
|| r
== -ERESTARTSYS
))
1362 return VM_FAULT_NOPAGE
;
1363 else if (unlikely(r
))
1364 return VM_FAULT_SIGBUS
;
1366 offset
= bo
->mem
.start
<< PAGE_SHIFT
;
1367 /* this should never happen */
1368 if (bo
->mem
.mem_type
== TTM_PL_VRAM
&&
1369 (offset
+ bo
->base
.size
) > adev
->gmc
.visible_vram_size
)
1370 return VM_FAULT_SIGBUS
;
1372 ttm_bo_move_to_lru_tail_unlocked(bo
);
1377 * amdgpu_bo_fence - add fence to buffer object
1379 * @bo: buffer object in question
1380 * @fence: fence to add
1381 * @shared: true if fence should be added shared
1384 void amdgpu_bo_fence(struct amdgpu_bo
*bo
, struct dma_fence
*fence
,
1387 struct dma_resv
*resv
= bo
->tbo
.base
.resv
;
1390 dma_resv_add_shared_fence(resv
, fence
);
1392 dma_resv_add_excl_fence(resv
, fence
);
1396 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences
1398 * @adev: amdgpu device pointer
1399 * @resv: reservation object to sync to
1400 * @sync_mode: synchronization mode
1401 * @owner: fence owner
1402 * @intr: Whether the wait is interruptible
1404 * Extract the fences from the reservation object and waits for them to finish.
1407 * 0 on success, errno otherwise.
1409 int amdgpu_bo_sync_wait_resv(struct amdgpu_device
*adev
, struct dma_resv
*resv
,
1410 enum amdgpu_sync_mode sync_mode
, void *owner
,
1413 struct amdgpu_sync sync
;
1416 amdgpu_sync_create(&sync
);
1417 amdgpu_sync_resv(adev
, &sync
, resv
, sync_mode
, owner
);
1418 r
= amdgpu_sync_wait(&sync
, intr
);
1419 amdgpu_sync_free(&sync
);
1424 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv
1425 * @bo: buffer object to wait for
1426 * @owner: fence owner
1427 * @intr: Whether the wait is interruptible
1429 * Wrapper to wait for fences in a BO.
1431 * 0 on success, errno otherwise.
1433 int amdgpu_bo_sync_wait(struct amdgpu_bo
*bo
, void *owner
, bool intr
)
1435 struct amdgpu_device
*adev
= amdgpu_ttm_adev(bo
->tbo
.bdev
);
1437 return amdgpu_bo_sync_wait_resv(adev
, bo
->tbo
.base
.resv
,
1438 AMDGPU_SYNC_NE_OWNER
, owner
, intr
);
1442 * amdgpu_bo_gpu_offset - return GPU offset of bo
1443 * @bo: amdgpu object for which we query the offset
1445 * Note: object should either be pinned or reserved when calling this
1446 * function, it might be useful to add check for this for debugging.
1449 * current GPU offset of the object.
1451 u64
amdgpu_bo_gpu_offset(struct amdgpu_bo
*bo
)
1453 WARN_ON_ONCE(bo
->tbo
.mem
.mem_type
== TTM_PL_SYSTEM
);
1454 WARN_ON_ONCE(!dma_resv_is_locked(bo
->tbo
.base
.resv
) &&
1455 !bo
->tbo
.pin_count
&& bo
->tbo
.type
!= ttm_bo_type_kernel
);
1456 WARN_ON_ONCE(bo
->tbo
.mem
.start
== AMDGPU_BO_INVALID_OFFSET
);
1457 WARN_ON_ONCE(bo
->tbo
.mem
.mem_type
== TTM_PL_VRAM
&&
1458 !(bo
->flags
& AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
));
1460 return amdgpu_bo_gpu_offset_no_check(bo
);
1464 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo
1465 * @bo: amdgpu object for which we query the offset
1468 * current GPU offset of the object without raising warnings.
1470 u64
amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo
*bo
)
1472 struct amdgpu_device
*adev
= amdgpu_ttm_adev(bo
->tbo
.bdev
);
1475 offset
= (bo
->tbo
.mem
.start
<< PAGE_SHIFT
) +
1476 amdgpu_ttm_domain_start(adev
, bo
->tbo
.mem
.mem_type
);
1478 return amdgpu_gmc_sign_extend(offset
);
1482 * amdgpu_bo_get_preferred_pin_domain - get preferred domain for scanout
1483 * @adev: amdgpu device object
1484 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>`
1487 * Which of the allowed domains is preferred for pinning the BO for scanout.
1489 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device
*adev
,
1492 if (domain
== (AMDGPU_GEM_DOMAIN_VRAM
| AMDGPU_GEM_DOMAIN_GTT
)) {
1493 domain
= AMDGPU_GEM_DOMAIN_VRAM
;
1494 if (adev
->gmc
.real_vram_size
<= AMDGPU_SG_THRESHOLD
)
1495 domain
= AMDGPU_GEM_DOMAIN_GTT
;
1500 #if defined(CONFIG_DEBUG_FS)
1501 #define amdgpu_bo_print_flag(m, bo, flag) \
1503 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \
1504 seq_printf((m), " " #flag); \
1509 * amdgpu_bo_print_info - print BO info in debugfs file
1511 * @id: Index or Id of the BO
1512 * @bo: Requested BO for printing info
1515 * Print BO information in debugfs file
1518 * Size of the BO in bytes.
1520 u64
amdgpu_bo_print_info(int id
, struct amdgpu_bo
*bo
, struct seq_file
*m
)
1522 struct dma_buf_attachment
*attachment
;
1523 struct dma_buf
*dma_buf
;
1524 unsigned int domain
;
1525 const char *placement
;
1526 unsigned int pin_count
;
1529 domain
= amdgpu_mem_type_to_domain(bo
->tbo
.mem
.mem_type
);
1531 case AMDGPU_GEM_DOMAIN_VRAM
:
1534 case AMDGPU_GEM_DOMAIN_GTT
:
1537 case AMDGPU_GEM_DOMAIN_CPU
:
1543 size
= amdgpu_bo_size(bo
);
1544 seq_printf(m
, "\t\t0x%08x: %12lld byte %s",
1545 id
, size
, placement
);
1547 pin_count
= READ_ONCE(bo
->tbo
.pin_count
);
1549 seq_printf(m
, " pin count %d", pin_count
);
1551 dma_buf
= READ_ONCE(bo
->tbo
.base
.dma_buf
);
1552 attachment
= READ_ONCE(bo
->tbo
.base
.import_attach
);
1555 seq_printf(m
, " imported from %p", dma_buf
);
1557 seq_printf(m
, " exported as %p", dma_buf
);
1559 amdgpu_bo_print_flag(m
, bo
, CPU_ACCESS_REQUIRED
);
1560 amdgpu_bo_print_flag(m
, bo
, NO_CPU_ACCESS
);
1561 amdgpu_bo_print_flag(m
, bo
, CPU_GTT_USWC
);
1562 amdgpu_bo_print_flag(m
, bo
, VRAM_CLEARED
);
1563 amdgpu_bo_print_flag(m
, bo
, VRAM_CONTIGUOUS
);
1564 amdgpu_bo_print_flag(m
, bo
, VM_ALWAYS_VALID
);
1565 amdgpu_bo_print_flag(m
, bo
, EXPLICIT_SYNC
);