drivers/gpu/drm/amd/amdgpu/amdgpu_object.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __AMDGPU_OBJECT_H__
  29 #define __AMDGPU_OBJECT_H__
  30
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu.h"
  33
  34 #define AMDGPU_BO_INVALID_OFFSET        LONG_MAX
  35
  36 /**
  37  * amdgpu_mem_type_to_domain - return domain corresponding to mem_type
  38  * @mem_type:   ttm memory type
  39  *
  40  * Returns corresponding domain of the ttm mem_type
  41  */
  42 static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
  43 {
  44         switch (mem_type) {
  45         case TTM_PL_VRAM:
  46                 return AMDGPU_GEM_DOMAIN_VRAM;
  47         case TTM_PL_TT:
  48                 return AMDGPU_GEM_DOMAIN_GTT;
  49         case TTM_PL_SYSTEM:
  50                 return AMDGPU_GEM_DOMAIN_CPU;
  51         case AMDGPU_PL_GDS:
  52                 return AMDGPU_GEM_DOMAIN_GDS;
  53         case AMDGPU_PL_GWS:
  54                 return AMDGPU_GEM_DOMAIN_GWS;
  55         case AMDGPU_PL_OA:
  56                 return AMDGPU_GEM_DOMAIN_OA;
  57         default:
  58                 break;
  59         }
  60         return 0;
  61 }
  62
  63 /**
  64  * amdgpu_bo_reserve - reserve bo
  65  * @bo:         bo structure
  66  * @no_intr:    don't return -ERESTARTSYS on pending signal
  67  *
  68  * Returns:
  69  * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
  70  * a signal. Release all buffer reservations and return to user-space.
  71  */
  72 static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
  73 {
  74         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
  75         int r;
  76
  77         r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
  78         if (unlikely(r != 0)) {
  79                 if (r != -ERESTARTSYS)
  80                         dev_err(adev->dev, "%p reserve failed\n", bo);
  81                 return r;
  82         }
  83         return 0;
  84 }
  85
  86 static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
  87 {
  88         ttm_bo_unreserve(&bo->tbo);
  89 }
  90
  91 static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
  92 {
  93         return bo->tbo.num_pages << PAGE_SHIFT;
  94 }
  95
  96 static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
  97 {
  98         return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
  99 }
 100
 101 static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
 102 {
 103         return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
 104 }
 105
 106 /**
 107  * amdgpu_bo_mmap_offset - return mmap offset of bo
 108  * @bo: amdgpu object for which we query the offset
 109  *
 110  * Returns mmap offset of the object.
 111  */
 112 static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
 113 {
 114         return drm_vma_node_offset_addr(&bo->tbo.vma_node);
 115 }
 116
 117 /**
 118  * amdgpu_bo_gpu_accessible - return whether the bo is currently in memory that
 119  * is accessible to the GPU.
 120  */
 121 static inline bool amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo)
 122 {
 123         return bo->tbo.mem.mem_type != TTM_PL_SYSTEM;
 124 }
 125
 126 int amdgpu_bo_create(struct amdgpu_device *adev,
 127                             unsigned long size, int byte_align,
 128                             bool kernel, u32 domain, u64 flags,
 129                             struct sg_table *sg,
 130                             struct reservation_object *resv,
 131                             struct amdgpu_bo **bo_ptr);
 132 int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
 133                                 unsigned long size, int byte_align,
 134                                 bool kernel, u32 domain, u64 flags,
 135                                 struct sg_table *sg,
 136                                 struct ttm_placement *placement,
 137                                 struct reservation_object *resv,
 138                                 struct amdgpu_bo **bo_ptr);
 139 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
 140                             unsigned long size, int align,
 141                             u32 domain, struct amdgpu_bo **bo_ptr,
 142                             u64 *gpu_addr, void **cpu_addr);
 143 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
 144                            void **cpu_addr);
 145 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
 146 void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
 147 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
 148 void amdgpu_bo_unref(struct amdgpu_bo **bo);
 149 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr);
 150 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 151                              u64 min_offset, u64 max_offset,
 152                              u64 *gpu_addr);
 153 int amdgpu_bo_unpin(struct amdgpu_bo *bo);
 154 int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
 155 int amdgpu_bo_init(struct amdgpu_device *adev);
 156 void amdgpu_bo_fini(struct amdgpu_device *adev);
 157 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 158                                 struct vm_area_struct *vma);
 159 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
 160 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
 161 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
 162                             uint32_t metadata_size, uint64_t flags);
 163 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 164                            size_t buffer_size, uint32_t *metadata_size,
 165                            uint64_t *flags);
 166 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 167                            bool evict,
 168                            struct ttm_mem_reg *new_mem);
 169 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
 170 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
 171                      bool shared);
 172 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
 173 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
 174                                struct amdgpu_ring *ring,
 175                                struct amdgpu_bo *bo,
 176                                struct reservation_object *resv,
 177                                struct dma_fence **fence, bool direct);
 178 int amdgpu_bo_validate(struct amdgpu_bo *bo);
 179 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
 180                                   struct amdgpu_ring *ring,
 181                                   struct amdgpu_bo *bo,
 182                                   struct reservation_object *resv,
 183                                   struct dma_fence **fence,
 184                                   bool direct);
 185
 186
 187 /*
 188  * sub allocation
 189  */
 190
 191 static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo)
 192 {
 193         return sa_bo->manager->gpu_addr + sa_bo->soffset;
 194 }
 195
 196 static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo)
 197 {
 198         return sa_bo->manager->cpu_ptr + sa_bo->soffset;
 199 }
 200
 201 int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
 202                                      struct amdgpu_sa_manager *sa_manager,
 203                                      unsigned size, u32 align, u32 domain);
 204 void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
 205                                       struct amdgpu_sa_manager *sa_manager);
 206 int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
 207                                       struct amdgpu_sa_manager *sa_manager);
 208 int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev,
 209                                         struct amdgpu_sa_manager *sa_manager);
 210 int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
 211                      struct amdgpu_sa_bo **sa_bo,
 212                      unsigned size, unsigned align);
 213 void amdgpu_sa_bo_free(struct amdgpu_device *adev,
 214                               struct amdgpu_sa_bo **sa_bo,
 215                               struct dma_fence *fence);
 216 #if defined(CONFIG_DEBUG_FS)
 217 void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
 218                                          struct seq_file *m);
 219 #endif
 220
 221
 222 #endif