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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_pm.c
1 /*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
22 */
23 #include <drm/drmP.h>
24 #include "amdgpu.h"
25 #include "amdgpu_drv.h"
26 #include "amdgpu_pm.h"
27 #include "amdgpu_dpm.h"
28 #include "atom.h"
29 #include <linux/power_supply.h>
30 #include <linux/hwmon.h>
31 #include <linux/hwmon-sysfs.h>
32
33 #include "amd_powerplay.h"
34
35 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
36
37 static const struct cg_flag_name clocks[] = {
38 {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
39 {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
40 {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
41 {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
42 {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
43 {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
44 {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
45 {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
46 {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
47 {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
48 {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
49 {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
50 {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
51 {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
52 {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
53 {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
54 {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
55 {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
56 {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
57 {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
58 {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
59 {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
60 {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
61 {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
62 {0, NULL},
63 };
64
65 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
66 {
67 if (adev->pp_enabled)
68 /* TODO */
69 return;
70
71 if (adev->pm.dpm_enabled) {
72 mutex_lock(&adev->pm.mutex);
73 if (power_supply_is_system_supplied() > 0)
74 adev->pm.dpm.ac_power = true;
75 else
76 adev->pm.dpm.ac_power = false;
77 if (adev->powerplay.pp_funcs->enable_bapm)
78 amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
79 mutex_unlock(&adev->pm.mutex);
80 }
81 }
82
83 static ssize_t amdgpu_get_dpm_state(struct device *dev,
84 struct device_attribute *attr,
85 char *buf)
86 {
87 struct drm_device *ddev = dev_get_drvdata(dev);
88 struct amdgpu_device *adev = ddev->dev_private;
89 enum amd_pm_state_type pm;
90
91 if (adev->powerplay.pp_funcs->get_current_power_state)
92 pm = amdgpu_dpm_get_current_power_state(adev);
93 else
94 pm = adev->pm.dpm.user_state;
95
96 return snprintf(buf, PAGE_SIZE, "%s\n",
97 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
98 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
99 }
100
101 static ssize_t amdgpu_set_dpm_state(struct device *dev,
102 struct device_attribute *attr,
103 const char *buf,
104 size_t count)
105 {
106 struct drm_device *ddev = dev_get_drvdata(dev);
107 struct amdgpu_device *adev = ddev->dev_private;
108 enum amd_pm_state_type state;
109
110 if (strncmp("battery", buf, strlen("battery")) == 0)
111 state = POWER_STATE_TYPE_BATTERY;
112 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
113 state = POWER_STATE_TYPE_BALANCED;
114 else if (strncmp("performance", buf, strlen("performance")) == 0)
115 state = POWER_STATE_TYPE_PERFORMANCE;
116 else {
117 count = -EINVAL;
118 goto fail;
119 }
120
121 if (adev->pp_enabled) {
122 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state, NULL);
123 } else {
124 mutex_lock(&adev->pm.mutex);
125 adev->pm.dpm.user_state = state;
126 mutex_unlock(&adev->pm.mutex);
127
128 /* Can't set dpm state when the card is off */
129 if (!(adev->flags & AMD_IS_PX) ||
130 (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
131 amdgpu_pm_compute_clocks(adev);
132 }
133 fail:
134 return count;
135 }
136
137 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
138 struct device_attribute *attr,
139 char *buf)
140 {
141 struct drm_device *ddev = dev_get_drvdata(dev);
142 struct amdgpu_device *adev = ddev->dev_private;
143 enum amd_dpm_forced_level level = 0xff;
144
145 if ((adev->flags & AMD_IS_PX) &&
146 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
147 return snprintf(buf, PAGE_SIZE, "off\n");
148
149 if (adev->powerplay.pp_funcs->get_performance_level)
150 level = amdgpu_dpm_get_performance_level(adev);
151 else
152 level = adev->pm.dpm.forced_level;
153
154 return snprintf(buf, PAGE_SIZE, "%s\n",
155 (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
156 (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
157 (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
158 (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
159 (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
160 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
161 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
162 (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
163 "unknown");
164 }
165
166 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
167 struct device_attribute *attr,
168 const char *buf,
169 size_t count)
170 {
171 struct drm_device *ddev = dev_get_drvdata(dev);
172 struct amdgpu_device *adev = ddev->dev_private;
173 enum amd_dpm_forced_level level;
174 enum amd_dpm_forced_level current_level = 0xff;
175 int ret = 0;
176
177 /* Can't force performance level when the card is off */
178 if ((adev->flags & AMD_IS_PX) &&
179 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
180 return -EINVAL;
181
182 if (adev->powerplay.pp_funcs->get_performance_level)
183 current_level = amdgpu_dpm_get_performance_level(adev);
184
185 if (strncmp("low", buf, strlen("low")) == 0) {
186 level = AMD_DPM_FORCED_LEVEL_LOW;
187 } else if (strncmp("high", buf, strlen("high")) == 0) {
188 level = AMD_DPM_FORCED_LEVEL_HIGH;
189 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
190 level = AMD_DPM_FORCED_LEVEL_AUTO;
191 } else if (strncmp("manual", buf, strlen("manual")) == 0) {
192 level = AMD_DPM_FORCED_LEVEL_MANUAL;
193 } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
194 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
195 } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
196 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
197 } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
198 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
199 } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
200 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
201 } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
202 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
203 } else {
204 count = -EINVAL;
205 goto fail;
206 }
207
208 if (current_level == level)
209 return count;
210
211 if (adev->powerplay.pp_funcs->force_performance_level) {
212 mutex_lock(&adev->pm.mutex);
213 if (adev->pm.dpm.thermal_active) {
214 count = -EINVAL;
215 mutex_unlock(&adev->pm.mutex);
216 goto fail;
217 }
218 ret = amdgpu_dpm_force_performance_level(adev, level);
219 if (ret)
220 count = -EINVAL;
221 else
222 adev->pm.dpm.forced_level = level;
223 mutex_unlock(&adev->pm.mutex);
224 }
225
226 fail:
227 return count;
228 }
229
230 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
231 struct device_attribute *attr,
232 char *buf)
233 {
234 struct drm_device *ddev = dev_get_drvdata(dev);
235 struct amdgpu_device *adev = ddev->dev_private;
236 struct pp_states_info data;
237 int i, buf_len;
238
239 if (adev->powerplay.pp_funcs->get_pp_num_states)
240 amdgpu_dpm_get_pp_num_states(adev, &data);
241
242 buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
243 for (i = 0; i < data.nums; i++)
244 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
245 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
246 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
247 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
248 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
249
250 return buf_len;
251 }
252
253 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
254 struct device_attribute *attr,
255 char *buf)
256 {
257 struct drm_device *ddev = dev_get_drvdata(dev);
258 struct amdgpu_device *adev = ddev->dev_private;
259 struct pp_states_info data;
260 enum amd_pm_state_type pm = 0;
261 int i = 0;
262
263 if (adev->powerplay.pp_funcs->get_current_power_state
264 && adev->powerplay.pp_funcs->get_pp_num_states) {
265 pm = amdgpu_dpm_get_current_power_state(adev);
266 amdgpu_dpm_get_pp_num_states(adev, &data);
267
268 for (i = 0; i < data.nums; i++) {
269 if (pm == data.states[i])
270 break;
271 }
272
273 if (i == data.nums)
274 i = -EINVAL;
275 }
276
277 return snprintf(buf, PAGE_SIZE, "%d\n", i);
278 }
279
280 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
281 struct device_attribute *attr,
282 char *buf)
283 {
284 struct drm_device *ddev = dev_get_drvdata(dev);
285 struct amdgpu_device *adev = ddev->dev_private;
286
287 if (adev->pp_force_state_enabled)
288 return amdgpu_get_pp_cur_state(dev, attr, buf);
289 else
290 return snprintf(buf, PAGE_SIZE, "\n");
291 }
292
293 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
294 struct device_attribute *attr,
295 const char *buf,
296 size_t count)
297 {
298 struct drm_device *ddev = dev_get_drvdata(dev);
299 struct amdgpu_device *adev = ddev->dev_private;
300 enum amd_pm_state_type state = 0;
301 unsigned long idx;
302 int ret;
303
304 if (strlen(buf) == 1)
305 adev->pp_force_state_enabled = false;
306 else if (adev->pp_enabled) {
307 struct pp_states_info data;
308
309 ret = kstrtoul(buf, 0, &idx);
310 if (ret || idx >= ARRAY_SIZE(data.states)) {
311 count = -EINVAL;
312 goto fail;
313 }
314
315 amdgpu_dpm_get_pp_num_states(adev, &data);
316 state = data.states[idx];
317 /* only set user selected power states */
318 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
319 state != POWER_STATE_TYPE_DEFAULT) {
320 amdgpu_dpm_dispatch_task(adev,
321 AMD_PP_TASK_ENABLE_USER_STATE, &state, NULL);
322 adev->pp_force_state_enabled = true;
323 }
324 }
325 fail:
326 return count;
327 }
328
329 static ssize_t amdgpu_get_pp_table(struct device *dev,
330 struct device_attribute *attr,
331 char *buf)
332 {
333 struct drm_device *ddev = dev_get_drvdata(dev);
334 struct amdgpu_device *adev = ddev->dev_private;
335 char *table = NULL;
336 int size;
337
338 if (adev->powerplay.pp_funcs->get_pp_table)
339 size = amdgpu_dpm_get_pp_table(adev, &table);
340 else
341 return 0;
342
343 if (size >= PAGE_SIZE)
344 size = PAGE_SIZE - 1;
345
346 memcpy(buf, table, size);
347
348 return size;
349 }
350
351 static ssize_t amdgpu_set_pp_table(struct device *dev,
352 struct device_attribute *attr,
353 const char *buf,
354 size_t count)
355 {
356 struct drm_device *ddev = dev_get_drvdata(dev);
357 struct amdgpu_device *adev = ddev->dev_private;
358
359 if (adev->powerplay.pp_funcs->set_pp_table)
360 amdgpu_dpm_set_pp_table(adev, buf, count);
361
362 return count;
363 }
364
365 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
366 struct device_attribute *attr,
367 char *buf)
368 {
369 struct drm_device *ddev = dev_get_drvdata(dev);
370 struct amdgpu_device *adev = ddev->dev_private;
371
372 if (adev->powerplay.pp_funcs->print_clock_levels)
373 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
374 else
375 return snprintf(buf, PAGE_SIZE, "\n");
376 }
377
378 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
379 struct device_attribute *attr,
380 const char *buf,
381 size_t count)
382 {
383 struct drm_device *ddev = dev_get_drvdata(dev);
384 struct amdgpu_device *adev = ddev->dev_private;
385 int ret;
386 long level;
387 uint32_t i, mask = 0;
388 char sub_str[2];
389
390 for (i = 0; i < strlen(buf); i++) {
391 if (*(buf + i) == '\n')
392 continue;
393 sub_str[0] = *(buf + i);
394 sub_str[1] = '\0';
395 ret = kstrtol(sub_str, 0, &level);
396
397 if (ret) {
398 count = -EINVAL;
399 goto fail;
400 }
401 mask |= 1 << level;
402 }
403
404 if (adev->powerplay.pp_funcs->force_clock_level)
405 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
406
407 fail:
408 return count;
409 }
410
411 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
412 struct device_attribute *attr,
413 char *buf)
414 {
415 struct drm_device *ddev = dev_get_drvdata(dev);
416 struct amdgpu_device *adev = ddev->dev_private;
417
418 if (adev->powerplay.pp_funcs->print_clock_levels)
419 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
420 else
421 return snprintf(buf, PAGE_SIZE, "\n");
422 }
423
424 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
425 struct device_attribute *attr,
426 const char *buf,
427 size_t count)
428 {
429 struct drm_device *ddev = dev_get_drvdata(dev);
430 struct amdgpu_device *adev = ddev->dev_private;
431 int ret;
432 long level;
433 uint32_t i, mask = 0;
434 char sub_str[2];
435
436 for (i = 0; i < strlen(buf); i++) {
437 if (*(buf + i) == '\n')
438 continue;
439 sub_str[0] = *(buf + i);
440 sub_str[1] = '\0';
441 ret = kstrtol(sub_str, 0, &level);
442
443 if (ret) {
444 count = -EINVAL;
445 goto fail;
446 }
447 mask |= 1 << level;
448 }
449 if (adev->powerplay.pp_funcs->force_clock_level)
450 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
451
452 fail:
453 return count;
454 }
455
456 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
457 struct device_attribute *attr,
458 char *buf)
459 {
460 struct drm_device *ddev = dev_get_drvdata(dev);
461 struct amdgpu_device *adev = ddev->dev_private;
462
463 if (adev->powerplay.pp_funcs->print_clock_levels)
464 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
465 else
466 return snprintf(buf, PAGE_SIZE, "\n");
467 }
468
469 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
470 struct device_attribute *attr,
471 const char *buf,
472 size_t count)
473 {
474 struct drm_device *ddev = dev_get_drvdata(dev);
475 struct amdgpu_device *adev = ddev->dev_private;
476 int ret;
477 long level;
478 uint32_t i, mask = 0;
479 char sub_str[2];
480
481 for (i = 0; i < strlen(buf); i++) {
482 if (*(buf + i) == '\n')
483 continue;
484 sub_str[0] = *(buf + i);
485 sub_str[1] = '\0';
486 ret = kstrtol(sub_str, 0, &level);
487
488 if (ret) {
489 count = -EINVAL;
490 goto fail;
491 }
492 mask |= 1 << level;
493 }
494 if (adev->powerplay.pp_funcs->force_clock_level)
495 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
496
497 fail:
498 return count;
499 }
500
501 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
502 struct device_attribute *attr,
503 char *buf)
504 {
505 struct drm_device *ddev = dev_get_drvdata(dev);
506 struct amdgpu_device *adev = ddev->dev_private;
507 uint32_t value = 0;
508
509 if (adev->powerplay.pp_funcs->get_sclk_od)
510 value = amdgpu_dpm_get_sclk_od(adev);
511
512 return snprintf(buf, PAGE_SIZE, "%d\n", value);
513 }
514
515 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
516 struct device_attribute *attr,
517 const char *buf,
518 size_t count)
519 {
520 struct drm_device *ddev = dev_get_drvdata(dev);
521 struct amdgpu_device *adev = ddev->dev_private;
522 int ret;
523 long int value;
524
525 ret = kstrtol(buf, 0, &value);
526
527 if (ret) {
528 count = -EINVAL;
529 goto fail;
530 }
531 if (adev->powerplay.pp_funcs->set_sclk_od)
532 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
533
534 if (adev->pp_enabled) {
535 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL);
536 } else {
537 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
538 amdgpu_pm_compute_clocks(adev);
539 }
540
541 fail:
542 return count;
543 }
544
545 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
546 struct device_attribute *attr,
547 char *buf)
548 {
549 struct drm_device *ddev = dev_get_drvdata(dev);
550 struct amdgpu_device *adev = ddev->dev_private;
551 uint32_t value = 0;
552
553 if (adev->powerplay.pp_funcs->get_mclk_od)
554 value = amdgpu_dpm_get_mclk_od(adev);
555
556 return snprintf(buf, PAGE_SIZE, "%d\n", value);
557 }
558
559 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
560 struct device_attribute *attr,
561 const char *buf,
562 size_t count)
563 {
564 struct drm_device *ddev = dev_get_drvdata(dev);
565 struct amdgpu_device *adev = ddev->dev_private;
566 int ret;
567 long int value;
568
569 ret = kstrtol(buf, 0, &value);
570
571 if (ret) {
572 count = -EINVAL;
573 goto fail;
574 }
575 if (adev->powerplay.pp_funcs->set_mclk_od)
576 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
577
578 if (adev->pp_enabled) {
579 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL);
580 } else {
581 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
582 amdgpu_pm_compute_clocks(adev);
583 }
584
585 fail:
586 return count;
587 }
588
589 static ssize_t amdgpu_get_pp_power_profile(struct device *dev,
590 char *buf, struct amd_pp_profile *query)
591 {
592 struct drm_device *ddev = dev_get_drvdata(dev);
593 struct amdgpu_device *adev = ddev->dev_private;
594 int ret = 0xff;
595
596 if (adev->powerplay.pp_funcs->get_power_profile_state)
597 ret = amdgpu_dpm_get_power_profile_state(
598 adev, query);
599
600 if (ret)
601 return ret;
602
603 return snprintf(buf, PAGE_SIZE,
604 "%d %d %d %d %d\n",
605 query->min_sclk / 100,
606 query->min_mclk / 100,
607 query->activity_threshold,
608 query->up_hyst,
609 query->down_hyst);
610 }
611
612 static ssize_t amdgpu_get_pp_gfx_power_profile(struct device *dev,
613 struct device_attribute *attr,
614 char *buf)
615 {
616 struct amd_pp_profile query = {0};
617
618 query.type = AMD_PP_GFX_PROFILE;
619
620 return amdgpu_get_pp_power_profile(dev, buf, &query);
621 }
622
623 static ssize_t amdgpu_get_pp_compute_power_profile(struct device *dev,
624 struct device_attribute *attr,
625 char *buf)
626 {
627 struct amd_pp_profile query = {0};
628
629 query.type = AMD_PP_COMPUTE_PROFILE;
630
631 return amdgpu_get_pp_power_profile(dev, buf, &query);
632 }
633
634 static ssize_t amdgpu_set_pp_power_profile(struct device *dev,
635 const char *buf,
636 size_t count,
637 struct amd_pp_profile *request)
638 {
639 struct drm_device *ddev = dev_get_drvdata(dev);
640 struct amdgpu_device *adev = ddev->dev_private;
641 uint32_t loop = 0;
642 char *sub_str, buf_cpy[128], *tmp_str;
643 const char delimiter[3] = {' ', '\n', '\0'};
644 long int value;
645 int ret = 0xff;
646
647 if (strncmp("reset", buf, strlen("reset")) == 0) {
648 if (adev->powerplay.pp_funcs->reset_power_profile_state)
649 ret = amdgpu_dpm_reset_power_profile_state(
650 adev, request);
651 if (ret) {
652 count = -EINVAL;
653 goto fail;
654 }
655 return count;
656 }
657
658 if (strncmp("set", buf, strlen("set")) == 0) {
659 if (adev->powerplay.pp_funcs->set_power_profile_state)
660 ret = amdgpu_dpm_set_power_profile_state(
661 adev, request);
662
663 if (ret) {
664 count = -EINVAL;
665 goto fail;
666 }
667 return count;
668 }
669
670 if (count + 1 >= 128) {
671 count = -EINVAL;
672 goto fail;
673 }
674
675 memcpy(buf_cpy, buf, count + 1);
676 tmp_str = buf_cpy;
677
678 while (tmp_str[0]) {
679 sub_str = strsep(&tmp_str, delimiter);
680 ret = kstrtol(sub_str, 0, &value);
681 if (ret) {
682 count = -EINVAL;
683 goto fail;
684 }
685
686 switch (loop) {
687 case 0:
688 /* input unit MHz convert to dpm table unit 10KHz*/
689 request->min_sclk = (uint32_t)value * 100;
690 break;
691 case 1:
692 /* input unit MHz convert to dpm table unit 10KHz*/
693 request->min_mclk = (uint32_t)value * 100;
694 break;
695 case 2:
696 request->activity_threshold = (uint16_t)value;
697 break;
698 case 3:
699 request->up_hyst = (uint8_t)value;
700 break;
701 case 4:
702 request->down_hyst = (uint8_t)value;
703 break;
704 default:
705 break;
706 }
707
708 loop++;
709 }
710 if (adev->powerplay.pp_funcs->set_power_profile_state)
711 ret = amdgpu_dpm_set_power_profile_state(adev, request);
712
713 if (ret)
714 count = -EINVAL;
715
716 fail:
717 return count;
718 }
719
720 static ssize_t amdgpu_set_pp_gfx_power_profile(struct device *dev,
721 struct device_attribute *attr,
722 const char *buf,
723 size_t count)
724 {
725 struct amd_pp_profile request = {0};
726
727 request.type = AMD_PP_GFX_PROFILE;
728
729 return amdgpu_set_pp_power_profile(dev, buf, count, &request);
730 }
731
732 static ssize_t amdgpu_set_pp_compute_power_profile(struct device *dev,
733 struct device_attribute *attr,
734 const char *buf,
735 size_t count)
736 {
737 struct amd_pp_profile request = {0};
738
739 request.type = AMD_PP_COMPUTE_PROFILE;
740
741 return amdgpu_set_pp_power_profile(dev, buf, count, &request);
742 }
743
744 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
745 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
746 amdgpu_get_dpm_forced_performance_level,
747 amdgpu_set_dpm_forced_performance_level);
748 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
749 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
750 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
751 amdgpu_get_pp_force_state,
752 amdgpu_set_pp_force_state);
753 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
754 amdgpu_get_pp_table,
755 amdgpu_set_pp_table);
756 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
757 amdgpu_get_pp_dpm_sclk,
758 amdgpu_set_pp_dpm_sclk);
759 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
760 amdgpu_get_pp_dpm_mclk,
761 amdgpu_set_pp_dpm_mclk);
762 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
763 amdgpu_get_pp_dpm_pcie,
764 amdgpu_set_pp_dpm_pcie);
765 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
766 amdgpu_get_pp_sclk_od,
767 amdgpu_set_pp_sclk_od);
768 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
769 amdgpu_get_pp_mclk_od,
770 amdgpu_set_pp_mclk_od);
771 static DEVICE_ATTR(pp_gfx_power_profile, S_IRUGO | S_IWUSR,
772 amdgpu_get_pp_gfx_power_profile,
773 amdgpu_set_pp_gfx_power_profile);
774 static DEVICE_ATTR(pp_compute_power_profile, S_IRUGO | S_IWUSR,
775 amdgpu_get_pp_compute_power_profile,
776 amdgpu_set_pp_compute_power_profile);
777
778 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
779 struct device_attribute *attr,
780 char *buf)
781 {
782 struct amdgpu_device *adev = dev_get_drvdata(dev);
783 struct drm_device *ddev = adev->ddev;
784 int temp;
785
786 /* Can't get temperature when the card is off */
787 if ((adev->flags & AMD_IS_PX) &&
788 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
789 return -EINVAL;
790
791 if (!adev->powerplay.pp_funcs->get_temperature)
792 temp = 0;
793 else
794 temp = amdgpu_dpm_get_temperature(adev);
795
796 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
797 }
798
799 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
800 struct device_attribute *attr,
801 char *buf)
802 {
803 struct amdgpu_device *adev = dev_get_drvdata(dev);
804 int hyst = to_sensor_dev_attr(attr)->index;
805 int temp;
806
807 if (hyst)
808 temp = adev->pm.dpm.thermal.min_temp;
809 else
810 temp = adev->pm.dpm.thermal.max_temp;
811
812 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
813 }
814
815 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
816 struct device_attribute *attr,
817 char *buf)
818 {
819 struct amdgpu_device *adev = dev_get_drvdata(dev);
820 u32 pwm_mode = 0;
821
822 if (!adev->powerplay.pp_funcs->get_fan_control_mode)
823 return -EINVAL;
824
825 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
826
827 return sprintf(buf, "%i\n", pwm_mode);
828 }
829
830 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
831 struct device_attribute *attr,
832 const char *buf,
833 size_t count)
834 {
835 struct amdgpu_device *adev = dev_get_drvdata(dev);
836 int err;
837 int value;
838
839 if (!adev->powerplay.pp_funcs->set_fan_control_mode)
840 return -EINVAL;
841
842 err = kstrtoint(buf, 10, &value);
843 if (err)
844 return err;
845
846 amdgpu_dpm_set_fan_control_mode(adev, value);
847
848 return count;
849 }
850
851 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
852 struct device_attribute *attr,
853 char *buf)
854 {
855 return sprintf(buf, "%i\n", 0);
856 }
857
858 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
859 struct device_attribute *attr,
860 char *buf)
861 {
862 return sprintf(buf, "%i\n", 255);
863 }
864
865 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
866 struct device_attribute *attr,
867 const char *buf, size_t count)
868 {
869 struct amdgpu_device *adev = dev_get_drvdata(dev);
870 int err;
871 u32 value;
872
873 err = kstrtou32(buf, 10, &value);
874 if (err)
875 return err;
876
877 value = (value * 100) / 255;
878
879 if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
880 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
881 if (err)
882 return err;
883 }
884
885 return count;
886 }
887
888 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
889 struct device_attribute *attr,
890 char *buf)
891 {
892 struct amdgpu_device *adev = dev_get_drvdata(dev);
893 int err;
894 u32 speed = 0;
895
896 if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
897 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
898 if (err)
899 return err;
900 }
901
902 speed = (speed * 255) / 100;
903
904 return sprintf(buf, "%i\n", speed);
905 }
906
907 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
908 struct device_attribute *attr,
909 char *buf)
910 {
911 struct amdgpu_device *adev = dev_get_drvdata(dev);
912 int err;
913 u32 speed = 0;
914
915 if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
916 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
917 if (err)
918 return err;
919 }
920
921 return sprintf(buf, "%i\n", speed);
922 }
923
924 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
925 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
926 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
927 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
928 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
929 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
930 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
931 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
932
933 static struct attribute *hwmon_attributes[] = {
934 &sensor_dev_attr_temp1_input.dev_attr.attr,
935 &sensor_dev_attr_temp1_crit.dev_attr.attr,
936 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
937 &sensor_dev_attr_pwm1.dev_attr.attr,
938 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
939 &sensor_dev_attr_pwm1_min.dev_attr.attr,
940 &sensor_dev_attr_pwm1_max.dev_attr.attr,
941 &sensor_dev_attr_fan1_input.dev_attr.attr,
942 NULL
943 };
944
945 static umode_t hwmon_attributes_visible(struct kobject *kobj,
946 struct attribute *attr, int index)
947 {
948 struct device *dev = kobj_to_dev(kobj);
949 struct amdgpu_device *adev = dev_get_drvdata(dev);
950 umode_t effective_mode = attr->mode;
951
952 /* Skip limit attributes if DPM is not enabled */
953 if (!adev->pm.dpm_enabled &&
954 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
955 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
956 attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
957 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
958 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
959 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
960 return 0;
961
962 if (adev->pp_enabled)
963 return effective_mode;
964
965 /* Skip fan attributes if fan is not present */
966 if (adev->pm.no_fan &&
967 (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
968 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
969 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
970 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
971 return 0;
972
973 /* mask fan attributes if we have no bindings for this asic to expose */
974 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
975 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
976 (!adev->powerplay.pp_funcs->get_fan_control_mode &&
977 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
978 effective_mode &= ~S_IRUGO;
979
980 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
981 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
982 (!adev->powerplay.pp_funcs->set_fan_control_mode &&
983 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
984 effective_mode &= ~S_IWUSR;
985
986 /* hide max/min values if we can't both query and manage the fan */
987 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
988 !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
989 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
990 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
991 return 0;
992
993 /* requires powerplay */
994 if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr)
995 return 0;
996
997 return effective_mode;
998 }
999
1000 static const struct attribute_group hwmon_attrgroup = {
1001 .attrs = hwmon_attributes,
1002 .is_visible = hwmon_attributes_visible,
1003 };
1004
1005 static const struct attribute_group *hwmon_groups[] = {
1006 &hwmon_attrgroup,
1007 NULL
1008 };
1009
1010 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
1011 {
1012 struct amdgpu_device *adev =
1013 container_of(work, struct amdgpu_device,
1014 pm.dpm.thermal.work);
1015 /* switch to the thermal state */
1016 enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
1017
1018 if (!adev->pm.dpm_enabled)
1019 return;
1020
1021 if (adev->powerplay.pp_funcs->get_temperature) {
1022 int temp = amdgpu_dpm_get_temperature(adev);
1023
1024 if (temp < adev->pm.dpm.thermal.min_temp)
1025 /* switch back the user state */
1026 dpm_state = adev->pm.dpm.user_state;
1027 } else {
1028 if (adev->pm.dpm.thermal.high_to_low)
1029 /* switch back the user state */
1030 dpm_state = adev->pm.dpm.user_state;
1031 }
1032 mutex_lock(&adev->pm.mutex);
1033 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
1034 adev->pm.dpm.thermal_active = true;
1035 else
1036 adev->pm.dpm.thermal_active = false;
1037 adev->pm.dpm.state = dpm_state;
1038 mutex_unlock(&adev->pm.mutex);
1039
1040 amdgpu_pm_compute_clocks(adev);
1041 }
1042
1043 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
1044 enum amd_pm_state_type dpm_state)
1045 {
1046 int i;
1047 struct amdgpu_ps *ps;
1048 u32 ui_class;
1049 bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
1050 true : false;
1051
1052 /* check if the vblank period is too short to adjust the mclk */
1053 if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
1054 if (amdgpu_dpm_vblank_too_short(adev))
1055 single_display = false;
1056 }
1057
1058 /* certain older asics have a separare 3D performance state,
1059 * so try that first if the user selected performance
1060 */
1061 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
1062 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
1063 /* balanced states don't exist at the moment */
1064 if (dpm_state == POWER_STATE_TYPE_BALANCED)
1065 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1066
1067 restart_search:
1068 /* Pick the best power state based on current conditions */
1069 for (i = 0; i < adev->pm.dpm.num_ps; i++) {
1070 ps = &adev->pm.dpm.ps[i];
1071 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
1072 switch (dpm_state) {
1073 /* user states */
1074 case POWER_STATE_TYPE_BATTERY:
1075 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
1076 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1077 if (single_display)
1078 return ps;
1079 } else
1080 return ps;
1081 }
1082 break;
1083 case POWER_STATE_TYPE_BALANCED:
1084 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
1085 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1086 if (single_display)
1087 return ps;
1088 } else
1089 return ps;
1090 }
1091 break;
1092 case POWER_STATE_TYPE_PERFORMANCE:
1093 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
1094 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1095 if (single_display)
1096 return ps;
1097 } else
1098 return ps;
1099 }
1100 break;
1101 /* internal states */
1102 case POWER_STATE_TYPE_INTERNAL_UVD:
1103 if (adev->pm.dpm.uvd_ps)
1104 return adev->pm.dpm.uvd_ps;
1105 else
1106 break;
1107 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1108 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
1109 return ps;
1110 break;
1111 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1112 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
1113 return ps;
1114 break;
1115 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1116 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
1117 return ps;
1118 break;
1119 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1120 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
1121 return ps;
1122 break;
1123 case POWER_STATE_TYPE_INTERNAL_BOOT:
1124 return adev->pm.dpm.boot_ps;
1125 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1126 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1127 return ps;
1128 break;
1129 case POWER_STATE_TYPE_INTERNAL_ACPI:
1130 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
1131 return ps;
1132 break;
1133 case POWER_STATE_TYPE_INTERNAL_ULV:
1134 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
1135 return ps;
1136 break;
1137 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1138 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1139 return ps;
1140 break;
1141 default:
1142 break;
1143 }
1144 }
1145 /* use a fallback state if we didn't match */
1146 switch (dpm_state) {
1147 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1148 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1149 goto restart_search;
1150 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1151 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1152 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1153 if (adev->pm.dpm.uvd_ps) {
1154 return adev->pm.dpm.uvd_ps;
1155 } else {
1156 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1157 goto restart_search;
1158 }
1159 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1160 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1161 goto restart_search;
1162 case POWER_STATE_TYPE_INTERNAL_ACPI:
1163 dpm_state = POWER_STATE_TYPE_BATTERY;
1164 goto restart_search;
1165 case POWER_STATE_TYPE_BATTERY:
1166 case POWER_STATE_TYPE_BALANCED:
1167 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1168 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1169 goto restart_search;
1170 default:
1171 break;
1172 }
1173
1174 return NULL;
1175 }
1176
1177 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
1178 {
1179 struct amdgpu_ps *ps;
1180 enum amd_pm_state_type dpm_state;
1181 int ret;
1182 bool equal = false;
1183
1184 /* if dpm init failed */
1185 if (!adev->pm.dpm_enabled)
1186 return;
1187
1188 if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
1189 /* add other state override checks here */
1190 if ((!adev->pm.dpm.thermal_active) &&
1191 (!adev->pm.dpm.uvd_active))
1192 adev->pm.dpm.state = adev->pm.dpm.user_state;
1193 }
1194 dpm_state = adev->pm.dpm.state;
1195
1196 ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
1197 if (ps)
1198 adev->pm.dpm.requested_ps = ps;
1199 else
1200 return;
1201
1202 if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
1203 printk("switching from power state:\n");
1204 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
1205 printk("switching to power state:\n");
1206 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
1207 }
1208
1209 /* update whether vce is active */
1210 ps->vce_active = adev->pm.dpm.vce_active;
1211 if (adev->powerplay.pp_funcs->display_configuration_changed)
1212 amdgpu_dpm_display_configuration_changed(adev);
1213
1214 ret = amdgpu_dpm_pre_set_power_state(adev);
1215 if (ret)
1216 return;
1217
1218 if (adev->powerplay.pp_funcs->check_state_equal) {
1219 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
1220 equal = false;
1221 }
1222
1223 if (equal)
1224 return;
1225
1226 amdgpu_dpm_set_power_state(adev);
1227 amdgpu_dpm_post_set_power_state(adev);
1228
1229 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1230 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1231
1232 if (adev->powerplay.pp_funcs->force_performance_level) {
1233 if (adev->pm.dpm.thermal_active) {
1234 enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
1235 /* force low perf level for thermal */
1236 amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
1237 /* save the user's level */
1238 adev->pm.dpm.forced_level = level;
1239 } else {
1240 /* otherwise, user selected level */
1241 amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
1242 }
1243 }
1244 }
1245
1246 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1247 {
1248 if (adev->powerplay.pp_funcs->powergate_uvd) {
1249 /* enable/disable UVD */
1250 mutex_lock(&adev->pm.mutex);
1251 amdgpu_dpm_powergate_uvd(adev, !enable);
1252 mutex_unlock(&adev->pm.mutex);
1253 } else {
1254 if (enable) {
1255 mutex_lock(&adev->pm.mutex);
1256 adev->pm.dpm.uvd_active = true;
1257 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1258 mutex_unlock(&adev->pm.mutex);
1259 } else {
1260 mutex_lock(&adev->pm.mutex);
1261 adev->pm.dpm.uvd_active = false;
1262 mutex_unlock(&adev->pm.mutex);
1263 }
1264 amdgpu_pm_compute_clocks(adev);
1265 }
1266 }
1267
1268 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1269 {
1270 if (adev->powerplay.pp_funcs->powergate_vce) {
1271 /* enable/disable VCE */
1272 mutex_lock(&adev->pm.mutex);
1273 amdgpu_dpm_powergate_vce(adev, !enable);
1274 mutex_unlock(&adev->pm.mutex);
1275 } else {
1276 if (enable) {
1277 mutex_lock(&adev->pm.mutex);
1278 adev->pm.dpm.vce_active = true;
1279 /* XXX select vce level based on ring/task */
1280 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
1281 mutex_unlock(&adev->pm.mutex);
1282 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1283 AMD_CG_STATE_UNGATE);
1284 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1285 AMD_PG_STATE_UNGATE);
1286 amdgpu_pm_compute_clocks(adev);
1287 } else {
1288 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1289 AMD_PG_STATE_GATE);
1290 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1291 AMD_CG_STATE_GATE);
1292 mutex_lock(&adev->pm.mutex);
1293 adev->pm.dpm.vce_active = false;
1294 mutex_unlock(&adev->pm.mutex);
1295 amdgpu_pm_compute_clocks(adev);
1296 }
1297
1298 }
1299 }
1300
1301 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1302 {
1303 int i;
1304
1305 if (adev->powerplay.pp_funcs->print_power_state == NULL)
1306 return;
1307
1308 for (i = 0; i < adev->pm.dpm.num_ps; i++)
1309 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1310
1311 }
1312
1313 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1314 {
1315 int ret;
1316
1317 if (adev->pm.sysfs_initialized)
1318 return 0;
1319
1320 if (adev->powerplay.pp_funcs->get_temperature == NULL)
1321 return 0;
1322
1323 adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1324 DRIVER_NAME, adev,
1325 hwmon_groups);
1326 if (IS_ERR(adev->pm.int_hwmon_dev)) {
1327 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1328 dev_err(adev->dev,
1329 "Unable to register hwmon device: %d\n", ret);
1330 return ret;
1331 }
1332
1333 ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1334 if (ret) {
1335 DRM_ERROR("failed to create device file for dpm state\n");
1336 return ret;
1337 }
1338 ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1339 if (ret) {
1340 DRM_ERROR("failed to create device file for dpm state\n");
1341 return ret;
1342 }
1343
1344 if (adev->pp_enabled) {
1345 ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1346 if (ret) {
1347 DRM_ERROR("failed to create device file pp_num_states\n");
1348 return ret;
1349 }
1350 ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1351 if (ret) {
1352 DRM_ERROR("failed to create device file pp_cur_state\n");
1353 return ret;
1354 }
1355 ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1356 if (ret) {
1357 DRM_ERROR("failed to create device file pp_force_state\n");
1358 return ret;
1359 }
1360 ret = device_create_file(adev->dev, &dev_attr_pp_table);
1361 if (ret) {
1362 DRM_ERROR("failed to create device file pp_table\n");
1363 return ret;
1364 }
1365 }
1366
1367 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1368 if (ret) {
1369 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1370 return ret;
1371 }
1372 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1373 if (ret) {
1374 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1375 return ret;
1376 }
1377 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1378 if (ret) {
1379 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1380 return ret;
1381 }
1382 ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
1383 if (ret) {
1384 DRM_ERROR("failed to create device file pp_sclk_od\n");
1385 return ret;
1386 }
1387 ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
1388 if (ret) {
1389 DRM_ERROR("failed to create device file pp_mclk_od\n");
1390 return ret;
1391 }
1392 ret = device_create_file(adev->dev,
1393 &dev_attr_pp_gfx_power_profile);
1394 if (ret) {
1395 DRM_ERROR("failed to create device file "
1396 "pp_gfx_power_profile\n");
1397 return ret;
1398 }
1399 ret = device_create_file(adev->dev,
1400 &dev_attr_pp_compute_power_profile);
1401 if (ret) {
1402 DRM_ERROR("failed to create device file "
1403 "pp_compute_power_profile\n");
1404 return ret;
1405 }
1406
1407 ret = amdgpu_debugfs_pm_init(adev);
1408 if (ret) {
1409 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1410 return ret;
1411 }
1412
1413 adev->pm.sysfs_initialized = true;
1414
1415 return 0;
1416 }
1417
1418 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1419 {
1420 if (adev->pm.int_hwmon_dev)
1421 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1422 device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1423 device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1424 if (adev->pp_enabled) {
1425 device_remove_file(adev->dev, &dev_attr_pp_num_states);
1426 device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1427 device_remove_file(adev->dev, &dev_attr_pp_force_state);
1428 device_remove_file(adev->dev, &dev_attr_pp_table);
1429 }
1430 device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1431 device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1432 device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1433 device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
1434 device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
1435 device_remove_file(adev->dev,
1436 &dev_attr_pp_gfx_power_profile);
1437 device_remove_file(adev->dev,
1438 &dev_attr_pp_compute_power_profile);
1439 }
1440
1441 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1442 {
1443 struct drm_device *ddev = adev->ddev;
1444 struct drm_crtc *crtc;
1445 struct amdgpu_crtc *amdgpu_crtc;
1446 int i = 0;
1447
1448 if (!adev->pm.dpm_enabled)
1449 return;
1450
1451 if (adev->mode_info.num_crtc)
1452 amdgpu_display_bandwidth_update(adev);
1453
1454 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1455 struct amdgpu_ring *ring = adev->rings[i];
1456 if (ring && ring->ready)
1457 amdgpu_fence_wait_empty(ring);
1458 }
1459
1460 if (adev->pp_enabled) {
1461 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL, NULL);
1462 } else {
1463 mutex_lock(&adev->pm.mutex);
1464 adev->pm.dpm.new_active_crtcs = 0;
1465 adev->pm.dpm.new_active_crtc_count = 0;
1466 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
1467 list_for_each_entry(crtc,
1468 &ddev->mode_config.crtc_list, head) {
1469 amdgpu_crtc = to_amdgpu_crtc(crtc);
1470 if (amdgpu_crtc->enabled) {
1471 adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
1472 adev->pm.dpm.new_active_crtc_count++;
1473 }
1474 }
1475 }
1476 /* update battery/ac status */
1477 if (power_supply_is_system_supplied() > 0)
1478 adev->pm.dpm.ac_power = true;
1479 else
1480 adev->pm.dpm.ac_power = false;
1481
1482 amdgpu_dpm_change_power_state_locked(adev);
1483
1484 mutex_unlock(&adev->pm.mutex);
1485 }
1486 }
1487
1488 /*
1489 * Debugfs info
1490 */
1491 #if defined(CONFIG_DEBUG_FS)
1492
1493 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
1494 {
1495 uint32_t value;
1496 struct pp_gpu_power query = {0};
1497 int size;
1498
1499 /* sanity check PP is enabled */
1500 if (!(adev->powerplay.pp_funcs &&
1501 adev->powerplay.pp_funcs->read_sensor))
1502 return -EINVAL;
1503
1504 /* GPU Clocks */
1505 size = sizeof(value);
1506 seq_printf(m, "GFX Clocks and Power:\n");
1507 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
1508 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
1509 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
1510 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
1511 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
1512 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
1513 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
1514 seq_printf(m, "\t%u mV (VDDNB)\n", value);
1515 size = sizeof(query);
1516 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size)) {
1517 seq_printf(m, "\t%u.%u W (VDDC)\n", query.vddc_power >> 8,
1518 query.vddc_power & 0xff);
1519 seq_printf(m, "\t%u.%u W (VDDCI)\n", query.vddci_power >> 8,
1520 query.vddci_power & 0xff);
1521 seq_printf(m, "\t%u.%u W (max GPU)\n", query.max_gpu_power >> 8,
1522 query.max_gpu_power & 0xff);
1523 seq_printf(m, "\t%u.%u W (average GPU)\n", query.average_gpu_power >> 8,
1524 query.average_gpu_power & 0xff);
1525 }
1526 size = sizeof(value);
1527 seq_printf(m, "\n");
1528
1529 /* GPU Temp */
1530 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
1531 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
1532
1533 /* GPU Load */
1534 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
1535 seq_printf(m, "GPU Load: %u %%\n", value);
1536 seq_printf(m, "\n");
1537
1538 /* UVD clocks */
1539 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
1540 if (!value) {
1541 seq_printf(m, "UVD: Disabled\n");
1542 } else {
1543 seq_printf(m, "UVD: Enabled\n");
1544 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
1545 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
1546 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
1547 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
1548 }
1549 }
1550 seq_printf(m, "\n");
1551
1552 /* VCE clocks */
1553 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
1554 if (!value) {
1555 seq_printf(m, "VCE: Disabled\n");
1556 } else {
1557 seq_printf(m, "VCE: Enabled\n");
1558 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
1559 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
1560 }
1561 }
1562
1563 return 0;
1564 }
1565
1566 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
1567 {
1568 int i;
1569
1570 for (i = 0; clocks[i].flag; i++)
1571 seq_printf(m, "\t%s: %s\n", clocks[i].name,
1572 (flags & clocks[i].flag) ? "On" : "Off");
1573 }
1574
1575 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1576 {
1577 struct drm_info_node *node = (struct drm_info_node *) m->private;
1578 struct drm_device *dev = node->minor->dev;
1579 struct amdgpu_device *adev = dev->dev_private;
1580 struct drm_device *ddev = adev->ddev;
1581 u32 flags = 0;
1582
1583 amdgpu_get_clockgating_state(adev, &flags);
1584 seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
1585 amdgpu_parse_cg_state(m, flags);
1586 seq_printf(m, "\n");
1587
1588 if (!adev->pm.dpm_enabled) {
1589 seq_printf(m, "dpm not enabled\n");
1590 return 0;
1591 }
1592 if ((adev->flags & AMD_IS_PX) &&
1593 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1594 seq_printf(m, "PX asic powered off\n");
1595 } else if (adev->pp_enabled) {
1596 return amdgpu_debugfs_pm_info_pp(m, adev);
1597 } else {
1598 mutex_lock(&adev->pm.mutex);
1599 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
1600 adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
1601 else
1602 seq_printf(m, "Debugfs support not implemented for this asic\n");
1603 mutex_unlock(&adev->pm.mutex);
1604 }
1605
1606 return 0;
1607 }
1608
1609 static const struct drm_info_list amdgpu_pm_info_list[] = {
1610 {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
1611 };
1612 #endif
1613
1614 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
1615 {
1616 #if defined(CONFIG_DEBUG_FS)
1617 return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
1618 #else
1619 return 0;
1620 #endif
1621 }
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