2 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Rafał Miłecki <zajec5@gmail.com>
23 * Alex Deucher <alexdeucher@gmail.com>
27 #include "amdgpu_drv.h"
28 #include "amdgpu_pm.h"
29 #include "amdgpu_dpm.h"
30 #include "amdgpu_display.h"
32 #include <linux/power_supply.h>
33 #include <linux/hwmon.h>
34 #include <linux/hwmon-sysfs.h>
35 #include <linux/nospec.h>
37 static int amdgpu_debugfs_pm_init(struct amdgpu_device
*adev
);
39 static const struct cg_flag_name clocks
[] = {
40 {AMD_CG_SUPPORT_GFX_MGCG
, "Graphics Medium Grain Clock Gating"},
41 {AMD_CG_SUPPORT_GFX_MGLS
, "Graphics Medium Grain memory Light Sleep"},
42 {AMD_CG_SUPPORT_GFX_CGCG
, "Graphics Coarse Grain Clock Gating"},
43 {AMD_CG_SUPPORT_GFX_CGLS
, "Graphics Coarse Grain memory Light Sleep"},
44 {AMD_CG_SUPPORT_GFX_CGTS
, "Graphics Coarse Grain Tree Shader Clock Gating"},
45 {AMD_CG_SUPPORT_GFX_CGTS_LS
, "Graphics Coarse Grain Tree Shader Light Sleep"},
46 {AMD_CG_SUPPORT_GFX_CP_LS
, "Graphics Command Processor Light Sleep"},
47 {AMD_CG_SUPPORT_GFX_RLC_LS
, "Graphics Run List Controller Light Sleep"},
48 {AMD_CG_SUPPORT_GFX_3D_CGCG
, "Graphics 3D Coarse Grain Clock Gating"},
49 {AMD_CG_SUPPORT_GFX_3D_CGLS
, "Graphics 3D Coarse Grain memory Light Sleep"},
50 {AMD_CG_SUPPORT_MC_LS
, "Memory Controller Light Sleep"},
51 {AMD_CG_SUPPORT_MC_MGCG
, "Memory Controller Medium Grain Clock Gating"},
52 {AMD_CG_SUPPORT_SDMA_LS
, "System Direct Memory Access Light Sleep"},
53 {AMD_CG_SUPPORT_SDMA_MGCG
, "System Direct Memory Access Medium Grain Clock Gating"},
54 {AMD_CG_SUPPORT_BIF_MGCG
, "Bus Interface Medium Grain Clock Gating"},
55 {AMD_CG_SUPPORT_BIF_LS
, "Bus Interface Light Sleep"},
56 {AMD_CG_SUPPORT_UVD_MGCG
, "Unified Video Decoder Medium Grain Clock Gating"},
57 {AMD_CG_SUPPORT_VCE_MGCG
, "Video Compression Engine Medium Grain Clock Gating"},
58 {AMD_CG_SUPPORT_HDP_LS
, "Host Data Path Light Sleep"},
59 {AMD_CG_SUPPORT_HDP_MGCG
, "Host Data Path Medium Grain Clock Gating"},
60 {AMD_CG_SUPPORT_DRM_MGCG
, "Digital Right Management Medium Grain Clock Gating"},
61 {AMD_CG_SUPPORT_DRM_LS
, "Digital Right Management Light Sleep"},
62 {AMD_CG_SUPPORT_ROM_MGCG
, "Rom Medium Grain Clock Gating"},
63 {AMD_CG_SUPPORT_DF_MGCG
, "Data Fabric Medium Grain Clock Gating"},
67 void amdgpu_pm_acpi_event_handler(struct amdgpu_device
*adev
)
69 if (adev
->pm
.dpm_enabled
) {
70 mutex_lock(&adev
->pm
.mutex
);
71 if (power_supply_is_system_supplied() > 0)
72 adev
->pm
.ac_power
= true;
74 adev
->pm
.ac_power
= false;
75 if (adev
->powerplay
.pp_funcs
->enable_bapm
)
76 amdgpu_dpm_enable_bapm(adev
, adev
->pm
.ac_power
);
77 mutex_unlock(&adev
->pm
.mutex
);
82 * DOC: power_dpm_state
84 * The power_dpm_state file is a legacy interface and is only provided for
85 * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
86 * certain power related parameters. The file power_dpm_state is used for this.
87 * It accepts the following arguments:
97 * On older GPUs, the vbios provided a special power state for battery
98 * operation. Selecting battery switched to this state. This is no
99 * longer provided on newer GPUs so the option does nothing in that case.
103 * On older GPUs, the vbios provided a special power state for balanced
104 * operation. Selecting balanced switched to this state. This is no
105 * longer provided on newer GPUs so the option does nothing in that case.
109 * On older GPUs, the vbios provided a special power state for performance
110 * operation. Selecting performance switched to this state. This is no
111 * longer provided on newer GPUs so the option does nothing in that case.
115 static ssize_t
amdgpu_get_dpm_state(struct device
*dev
,
116 struct device_attribute
*attr
,
119 struct drm_device
*ddev
= dev_get_drvdata(dev
);
120 struct amdgpu_device
*adev
= ddev
->dev_private
;
121 enum amd_pm_state_type pm
;
123 if (adev
->powerplay
.pp_funcs
->get_current_power_state
)
124 pm
= amdgpu_dpm_get_current_power_state(adev
);
126 pm
= adev
->pm
.dpm
.user_state
;
128 return snprintf(buf
, PAGE_SIZE
, "%s\n",
129 (pm
== POWER_STATE_TYPE_BATTERY
) ? "battery" :
130 (pm
== POWER_STATE_TYPE_BALANCED
) ? "balanced" : "performance");
133 static ssize_t
amdgpu_set_dpm_state(struct device
*dev
,
134 struct device_attribute
*attr
,
138 struct drm_device
*ddev
= dev_get_drvdata(dev
);
139 struct amdgpu_device
*adev
= ddev
->dev_private
;
140 enum amd_pm_state_type state
;
142 if (strncmp("battery", buf
, strlen("battery")) == 0)
143 state
= POWER_STATE_TYPE_BATTERY
;
144 else if (strncmp("balanced", buf
, strlen("balanced")) == 0)
145 state
= POWER_STATE_TYPE_BALANCED
;
146 else if (strncmp("performance", buf
, strlen("performance")) == 0)
147 state
= POWER_STATE_TYPE_PERFORMANCE
;
153 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
154 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_ENABLE_USER_STATE
, &state
);
156 mutex_lock(&adev
->pm
.mutex
);
157 adev
->pm
.dpm
.user_state
= state
;
158 mutex_unlock(&adev
->pm
.mutex
);
160 /* Can't set dpm state when the card is off */
161 if (!(adev
->flags
& AMD_IS_PX
) ||
162 (ddev
->switch_power_state
== DRM_SWITCH_POWER_ON
))
163 amdgpu_pm_compute_clocks(adev
);
171 * DOC: power_dpm_force_performance_level
173 * The amdgpu driver provides a sysfs API for adjusting certain power
174 * related parameters. The file power_dpm_force_performance_level is
175 * used for this. It accepts the following arguments:
195 * When auto is selected, the driver will attempt to dynamically select
196 * the optimal power profile for current conditions in the driver.
200 * When low is selected, the clocks are forced to the lowest power state.
204 * When high is selected, the clocks are forced to the highest power state.
208 * When manual is selected, the user can manually adjust which power states
209 * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
210 * and pp_dpm_pcie files and adjust the power state transition heuristics
211 * via the pp_power_profile_mode sysfs file.
218 * When the profiling modes are selected, clock and power gating are
219 * disabled and the clocks are set for different profiling cases. This
220 * mode is recommended for profiling specific work loads where you do
221 * not want clock or power gating for clock fluctuation to interfere
222 * with your results. profile_standard sets the clocks to a fixed clock
223 * level which varies from asic to asic. profile_min_sclk forces the sclk
224 * to the lowest level. profile_min_mclk forces the mclk to the lowest level.
225 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
229 static ssize_t
amdgpu_get_dpm_forced_performance_level(struct device
*dev
,
230 struct device_attribute
*attr
,
233 struct drm_device
*ddev
= dev_get_drvdata(dev
);
234 struct amdgpu_device
*adev
= ddev
->dev_private
;
235 enum amd_dpm_forced_level level
= 0xff;
237 if ((adev
->flags
& AMD_IS_PX
) &&
238 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
239 return snprintf(buf
, PAGE_SIZE
, "off\n");
241 if (adev
->powerplay
.pp_funcs
->get_performance_level
)
242 level
= amdgpu_dpm_get_performance_level(adev
);
244 level
= adev
->pm
.dpm
.forced_level
;
246 return snprintf(buf
, PAGE_SIZE
, "%s\n",
247 (level
== AMD_DPM_FORCED_LEVEL_AUTO
) ? "auto" :
248 (level
== AMD_DPM_FORCED_LEVEL_LOW
) ? "low" :
249 (level
== AMD_DPM_FORCED_LEVEL_HIGH
) ? "high" :
250 (level
== AMD_DPM_FORCED_LEVEL_MANUAL
) ? "manual" :
251 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
) ? "profile_standard" :
252 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
) ? "profile_min_sclk" :
253 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
) ? "profile_min_mclk" :
254 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
) ? "profile_peak" :
258 static ssize_t
amdgpu_set_dpm_forced_performance_level(struct device
*dev
,
259 struct device_attribute
*attr
,
263 struct drm_device
*ddev
= dev_get_drvdata(dev
);
264 struct amdgpu_device
*adev
= ddev
->dev_private
;
265 enum amd_dpm_forced_level level
;
266 enum amd_dpm_forced_level current_level
= 0xff;
269 /* Can't force performance level when the card is off */
270 if ((adev
->flags
& AMD_IS_PX
) &&
271 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
274 if (adev
->powerplay
.pp_funcs
->get_performance_level
)
275 current_level
= amdgpu_dpm_get_performance_level(adev
);
277 if (strncmp("low", buf
, strlen("low")) == 0) {
278 level
= AMD_DPM_FORCED_LEVEL_LOW
;
279 } else if (strncmp("high", buf
, strlen("high")) == 0) {
280 level
= AMD_DPM_FORCED_LEVEL_HIGH
;
281 } else if (strncmp("auto", buf
, strlen("auto")) == 0) {
282 level
= AMD_DPM_FORCED_LEVEL_AUTO
;
283 } else if (strncmp("manual", buf
, strlen("manual")) == 0) {
284 level
= AMD_DPM_FORCED_LEVEL_MANUAL
;
285 } else if (strncmp("profile_exit", buf
, strlen("profile_exit")) == 0) {
286 level
= AMD_DPM_FORCED_LEVEL_PROFILE_EXIT
;
287 } else if (strncmp("profile_standard", buf
, strlen("profile_standard")) == 0) {
288 level
= AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
;
289 } else if (strncmp("profile_min_sclk", buf
, strlen("profile_min_sclk")) == 0) {
290 level
= AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
;
291 } else if (strncmp("profile_min_mclk", buf
, strlen("profile_min_mclk")) == 0) {
292 level
= AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
;
293 } else if (strncmp("profile_peak", buf
, strlen("profile_peak")) == 0) {
294 level
= AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
;
300 if (current_level
== level
)
303 if (adev
->powerplay
.pp_funcs
->force_performance_level
) {
304 mutex_lock(&adev
->pm
.mutex
);
305 if (adev
->pm
.dpm
.thermal_active
) {
307 mutex_unlock(&adev
->pm
.mutex
);
310 ret
= amdgpu_dpm_force_performance_level(adev
, level
);
314 adev
->pm
.dpm
.forced_level
= level
;
315 mutex_unlock(&adev
->pm
.mutex
);
322 static ssize_t
amdgpu_get_pp_num_states(struct device
*dev
,
323 struct device_attribute
*attr
,
326 struct drm_device
*ddev
= dev_get_drvdata(dev
);
327 struct amdgpu_device
*adev
= ddev
->dev_private
;
328 struct pp_states_info data
;
331 if (adev
->powerplay
.pp_funcs
->get_pp_num_states
)
332 amdgpu_dpm_get_pp_num_states(adev
, &data
);
334 buf_len
= snprintf(buf
, PAGE_SIZE
, "states: %d\n", data
.nums
);
335 for (i
= 0; i
< data
.nums
; i
++)
336 buf_len
+= snprintf(buf
+ buf_len
, PAGE_SIZE
, "%d %s\n", i
,
337 (data
.states
[i
] == POWER_STATE_TYPE_INTERNAL_BOOT
) ? "boot" :
338 (data
.states
[i
] == POWER_STATE_TYPE_BATTERY
) ? "battery" :
339 (data
.states
[i
] == POWER_STATE_TYPE_BALANCED
) ? "balanced" :
340 (data
.states
[i
] == POWER_STATE_TYPE_PERFORMANCE
) ? "performance" : "default");
345 static ssize_t
amdgpu_get_pp_cur_state(struct device
*dev
,
346 struct device_attribute
*attr
,
349 struct drm_device
*ddev
= dev_get_drvdata(dev
);
350 struct amdgpu_device
*adev
= ddev
->dev_private
;
351 struct pp_states_info data
;
352 enum amd_pm_state_type pm
= 0;
355 if (adev
->powerplay
.pp_funcs
->get_current_power_state
356 && adev
->powerplay
.pp_funcs
->get_pp_num_states
) {
357 pm
= amdgpu_dpm_get_current_power_state(adev
);
358 amdgpu_dpm_get_pp_num_states(adev
, &data
);
360 for (i
= 0; i
< data
.nums
; i
++) {
361 if (pm
== data
.states
[i
])
369 return snprintf(buf
, PAGE_SIZE
, "%d\n", i
);
372 static ssize_t
amdgpu_get_pp_force_state(struct device
*dev
,
373 struct device_attribute
*attr
,
376 struct drm_device
*ddev
= dev_get_drvdata(dev
);
377 struct amdgpu_device
*adev
= ddev
->dev_private
;
379 if (adev
->pp_force_state_enabled
)
380 return amdgpu_get_pp_cur_state(dev
, attr
, buf
);
382 return snprintf(buf
, PAGE_SIZE
, "\n");
385 static ssize_t
amdgpu_set_pp_force_state(struct device
*dev
,
386 struct device_attribute
*attr
,
390 struct drm_device
*ddev
= dev_get_drvdata(dev
);
391 struct amdgpu_device
*adev
= ddev
->dev_private
;
392 enum amd_pm_state_type state
= 0;
396 if (strlen(buf
) == 1)
397 adev
->pp_force_state_enabled
= false;
398 else if (adev
->powerplay
.pp_funcs
->dispatch_tasks
&&
399 adev
->powerplay
.pp_funcs
->get_pp_num_states
) {
400 struct pp_states_info data
;
402 ret
= kstrtoul(buf
, 0, &idx
);
403 if (ret
|| idx
>= ARRAY_SIZE(data
.states
)) {
407 idx
= array_index_nospec(idx
, ARRAY_SIZE(data
.states
));
409 amdgpu_dpm_get_pp_num_states(adev
, &data
);
410 state
= data
.states
[idx
];
411 /* only set user selected power states */
412 if (state
!= POWER_STATE_TYPE_INTERNAL_BOOT
&&
413 state
!= POWER_STATE_TYPE_DEFAULT
) {
414 amdgpu_dpm_dispatch_task(adev
,
415 AMD_PP_TASK_ENABLE_USER_STATE
, &state
);
416 adev
->pp_force_state_enabled
= true;
426 * The amdgpu driver provides a sysfs API for uploading new powerplay
427 * tables. The file pp_table is used for this. Reading the file
428 * will dump the current power play table. Writing to the file
429 * will attempt to upload a new powerplay table and re-initialize
430 * powerplay using that new table.
434 static ssize_t
amdgpu_get_pp_table(struct device
*dev
,
435 struct device_attribute
*attr
,
438 struct drm_device
*ddev
= dev_get_drvdata(dev
);
439 struct amdgpu_device
*adev
= ddev
->dev_private
;
443 if (adev
->powerplay
.pp_funcs
->get_pp_table
)
444 size
= amdgpu_dpm_get_pp_table(adev
, &table
);
448 if (size
>= PAGE_SIZE
)
449 size
= PAGE_SIZE
- 1;
451 memcpy(buf
, table
, size
);
456 static ssize_t
amdgpu_set_pp_table(struct device
*dev
,
457 struct device_attribute
*attr
,
461 struct drm_device
*ddev
= dev_get_drvdata(dev
);
462 struct amdgpu_device
*adev
= ddev
->dev_private
;
464 if (adev
->powerplay
.pp_funcs
->set_pp_table
)
465 amdgpu_dpm_set_pp_table(adev
, buf
, count
);
471 * DOC: pp_od_clk_voltage
473 * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
474 * in each power level within a power state. The pp_od_clk_voltage is used for
477 * < For Vega10 and previous ASICs >
479 * Reading the file will display:
481 * - a list of engine clock levels and voltages labeled OD_SCLK
483 * - a list of memory clock levels and voltages labeled OD_MCLK
485 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
487 * To manually adjust these settings, first select manual using
488 * power_dpm_force_performance_level. Enter a new value for each
489 * level by writing a string that contains "s/m level clock voltage" to
490 * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
491 * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
492 * 810 mV. When you have edited all of the states as needed, write
493 * "c" (commit) to the file to commit your changes. If you want to reset to the
494 * default power levels, write "r" (reset) to the file to reset them.
499 * Reading the file will display:
501 * - minimum and maximum engine clock labeled OD_SCLK
503 * - maximum memory clock labeled OD_MCLK
505 * - three <frequency, voltage offset> points labeled OD_VDDC_CURVE.
506 * They can be used to calibrate the sclk voltage curve.
508 * - a list of valid ranges for sclk, mclk, and voltage curve points
511 * To manually adjust these settings:
513 * - First select manual using power_dpm_force_performance_level
515 * - For clock frequency setting, enter a new value by writing a
516 * string that contains "s/m index clock" to the file. The index
517 * should be 0 if to set minimum clock. And 1 if to set maximum
518 * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
519 * "m 1 800" will update maximum mclk to be 800Mhz.
521 * For sclk voltage curve, enter the new values by writing a
522 * string that contains "vc point clock voff" to the file. The
523 * points are indexed by 0, 1 and 2. E.g., "vc 0 300 10" will
524 * update point1 with clock set as 300Mhz and voltage increased
525 * by 10mV. "vc 2 1000 -10" will update point3 with clock set
526 * as 1000Mhz and voltage drop by 10mV.
528 * - When you have edited all of the states as needed, write "c" (commit)
529 * to the file to commit your changes
531 * - If you want to reset to the default power levels, write "r" (reset)
532 * to the file to reset them
536 static ssize_t
amdgpu_set_pp_od_clk_voltage(struct device
*dev
,
537 struct device_attribute
*attr
,
541 struct drm_device
*ddev
= dev_get_drvdata(dev
);
542 struct amdgpu_device
*adev
= ddev
->dev_private
;
544 uint32_t parameter_size
= 0;
549 const char delimiter
[3] = {' ', '\n', '\0'};
556 type
= PP_OD_EDIT_SCLK_VDDC_TABLE
;
557 else if (*buf
== 'm')
558 type
= PP_OD_EDIT_MCLK_VDDC_TABLE
;
560 type
= PP_OD_RESTORE_DEFAULT_TABLE
;
561 else if (*buf
== 'c')
562 type
= PP_OD_COMMIT_DPM_TABLE
;
563 else if (!strncmp(buf
, "vc", 2))
564 type
= PP_OD_EDIT_VDDC_CURVE
;
568 memcpy(buf_cpy
, buf
, count
+1);
572 if (type
== PP_OD_EDIT_VDDC_CURVE
)
574 while (isspace(*++tmp_str
));
577 sub_str
= strsep(&tmp_str
, delimiter
);
578 ret
= kstrtol(sub_str
, 0, ¶meter
[parameter_size
]);
583 while (isspace(*tmp_str
))
587 if (adev
->powerplay
.pp_funcs
->odn_edit_dpm_table
)
588 ret
= amdgpu_dpm_odn_edit_dpm_table(adev
, type
,
589 parameter
, parameter_size
);
594 if (type
== PP_OD_COMMIT_DPM_TABLE
) {
595 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
596 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_READJUST_POWER_STATE
, NULL
);
606 static ssize_t
amdgpu_get_pp_od_clk_voltage(struct device
*dev
,
607 struct device_attribute
*attr
,
610 struct drm_device
*ddev
= dev_get_drvdata(dev
);
611 struct amdgpu_device
*adev
= ddev
->dev_private
;
614 if (adev
->powerplay
.pp_funcs
->print_clock_levels
) {
615 size
= amdgpu_dpm_print_clock_levels(adev
, OD_SCLK
, buf
);
616 size
+= amdgpu_dpm_print_clock_levels(adev
, OD_MCLK
, buf
+size
);
617 size
+= amdgpu_dpm_print_clock_levels(adev
, OD_VDDC_CURVE
, buf
+size
);
618 size
+= amdgpu_dpm_print_clock_levels(adev
, OD_RANGE
, buf
+size
);
621 return snprintf(buf
, PAGE_SIZE
, "\n");
627 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
629 * The amdgpu driver provides a sysfs API for adjusting what power levels
630 * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk,
631 * and pp_dpm_pcie are used for this.
633 * Reading back the files will show you the available power levels within
634 * the power state and the clock information for those levels.
636 * To manually adjust these states, first select manual using
637 * power_dpm_force_performance_level.
638 * Secondly,Enter a new value for each level by inputing a string that
639 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
640 * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
643 static ssize_t
amdgpu_get_pp_dpm_sclk(struct device
*dev
,
644 struct device_attribute
*attr
,
647 struct drm_device
*ddev
= dev_get_drvdata(dev
);
648 struct amdgpu_device
*adev
= ddev
->dev_private
;
650 if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
651 return amdgpu_dpm_print_clock_levels(adev
, PP_SCLK
, buf
);
653 return snprintf(buf
, PAGE_SIZE
, "\n");
657 * Worst case: 32 bits individually specified, in octal at 12 characters
658 * per line (+1 for \n).
660 #define AMDGPU_MASK_BUF_MAX (32 * 13)
662 static ssize_t
amdgpu_read_mask(const char *buf
, size_t count
, uint32_t *mask
)
666 char *sub_str
= NULL
;
668 char buf_cpy
[AMDGPU_MASK_BUF_MAX
+ 1];
669 const char delimiter
[3] = {' ', '\n', '\0'};
674 bytes
= min(count
, sizeof(buf_cpy
) - 1);
675 memcpy(buf_cpy
, buf
, bytes
);
676 buf_cpy
[bytes
] = '\0';
679 sub_str
= strsep(&tmp
, delimiter
);
680 if (strlen(sub_str
)) {
681 ret
= kstrtol(sub_str
, 0, &level
);
692 static ssize_t
amdgpu_set_pp_dpm_sclk(struct device
*dev
,
693 struct device_attribute
*attr
,
697 struct drm_device
*ddev
= dev_get_drvdata(dev
);
698 struct amdgpu_device
*adev
= ddev
->dev_private
;
702 ret
= amdgpu_read_mask(buf
, count
, &mask
);
706 if (adev
->powerplay
.pp_funcs
->force_clock_level
)
707 amdgpu_dpm_force_clock_level(adev
, PP_SCLK
, mask
);
712 static ssize_t
amdgpu_get_pp_dpm_mclk(struct device
*dev
,
713 struct device_attribute
*attr
,
716 struct drm_device
*ddev
= dev_get_drvdata(dev
);
717 struct amdgpu_device
*adev
= ddev
->dev_private
;
719 if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
720 return amdgpu_dpm_print_clock_levels(adev
, PP_MCLK
, buf
);
722 return snprintf(buf
, PAGE_SIZE
, "\n");
725 static ssize_t
amdgpu_set_pp_dpm_mclk(struct device
*dev
,
726 struct device_attribute
*attr
,
730 struct drm_device
*ddev
= dev_get_drvdata(dev
);
731 struct amdgpu_device
*adev
= ddev
->dev_private
;
735 ret
= amdgpu_read_mask(buf
, count
, &mask
);
739 if (adev
->powerplay
.pp_funcs
->force_clock_level
)
740 amdgpu_dpm_force_clock_level(adev
, PP_MCLK
, mask
);
745 static ssize_t
amdgpu_get_pp_dpm_pcie(struct device
*dev
,
746 struct device_attribute
*attr
,
749 struct drm_device
*ddev
= dev_get_drvdata(dev
);
750 struct amdgpu_device
*adev
= ddev
->dev_private
;
752 if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
753 return amdgpu_dpm_print_clock_levels(adev
, PP_PCIE
, buf
);
755 return snprintf(buf
, PAGE_SIZE
, "\n");
758 static ssize_t
amdgpu_set_pp_dpm_pcie(struct device
*dev
,
759 struct device_attribute
*attr
,
763 struct drm_device
*ddev
= dev_get_drvdata(dev
);
764 struct amdgpu_device
*adev
= ddev
->dev_private
;
768 ret
= amdgpu_read_mask(buf
, count
, &mask
);
772 if (adev
->powerplay
.pp_funcs
->force_clock_level
)
773 amdgpu_dpm_force_clock_level(adev
, PP_PCIE
, mask
);
778 static ssize_t
amdgpu_get_pp_sclk_od(struct device
*dev
,
779 struct device_attribute
*attr
,
782 struct drm_device
*ddev
= dev_get_drvdata(dev
);
783 struct amdgpu_device
*adev
= ddev
->dev_private
;
786 if (adev
->powerplay
.pp_funcs
->get_sclk_od
)
787 value
= amdgpu_dpm_get_sclk_od(adev
);
789 return snprintf(buf
, PAGE_SIZE
, "%d\n", value
);
792 static ssize_t
amdgpu_set_pp_sclk_od(struct device
*dev
,
793 struct device_attribute
*attr
,
797 struct drm_device
*ddev
= dev_get_drvdata(dev
);
798 struct amdgpu_device
*adev
= ddev
->dev_private
;
802 ret
= kstrtol(buf
, 0, &value
);
808 if (adev
->powerplay
.pp_funcs
->set_sclk_od
)
809 amdgpu_dpm_set_sclk_od(adev
, (uint32_t)value
);
811 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
812 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_READJUST_POWER_STATE
, NULL
);
814 adev
->pm
.dpm
.current_ps
= adev
->pm
.dpm
.boot_ps
;
815 amdgpu_pm_compute_clocks(adev
);
822 static ssize_t
amdgpu_get_pp_mclk_od(struct device
*dev
,
823 struct device_attribute
*attr
,
826 struct drm_device
*ddev
= dev_get_drvdata(dev
);
827 struct amdgpu_device
*adev
= ddev
->dev_private
;
830 if (adev
->powerplay
.pp_funcs
->get_mclk_od
)
831 value
= amdgpu_dpm_get_mclk_od(adev
);
833 return snprintf(buf
, PAGE_SIZE
, "%d\n", value
);
836 static ssize_t
amdgpu_set_pp_mclk_od(struct device
*dev
,
837 struct device_attribute
*attr
,
841 struct drm_device
*ddev
= dev_get_drvdata(dev
);
842 struct amdgpu_device
*adev
= ddev
->dev_private
;
846 ret
= kstrtol(buf
, 0, &value
);
852 if (adev
->powerplay
.pp_funcs
->set_mclk_od
)
853 amdgpu_dpm_set_mclk_od(adev
, (uint32_t)value
);
855 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
856 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_READJUST_POWER_STATE
, NULL
);
858 adev
->pm
.dpm
.current_ps
= adev
->pm
.dpm
.boot_ps
;
859 amdgpu_pm_compute_clocks(adev
);
867 * DOC: pp_power_profile_mode
869 * The amdgpu driver provides a sysfs API for adjusting the heuristics
870 * related to switching between power levels in a power state. The file
871 * pp_power_profile_mode is used for this.
873 * Reading this file outputs a list of all of the predefined power profiles
874 * and the relevant heuristics settings for that profile.
876 * To select a profile or create a custom profile, first select manual using
877 * power_dpm_force_performance_level. Writing the number of a predefined
878 * profile to pp_power_profile_mode will enable those heuristics. To
879 * create a custom set of heuristics, write a string of numbers to the file
880 * starting with the number of the custom profile along with a setting
881 * for each heuristic parameter. Due to differences across asic families
882 * the heuristic parameters vary from family to family.
886 static ssize_t
amdgpu_get_pp_power_profile_mode(struct device
*dev
,
887 struct device_attribute
*attr
,
890 struct drm_device
*ddev
= dev_get_drvdata(dev
);
891 struct amdgpu_device
*adev
= ddev
->dev_private
;
893 if (adev
->powerplay
.pp_funcs
->get_power_profile_mode
)
894 return amdgpu_dpm_get_power_profile_mode(adev
, buf
);
896 return snprintf(buf
, PAGE_SIZE
, "\n");
900 static ssize_t
amdgpu_set_pp_power_profile_mode(struct device
*dev
,
901 struct device_attribute
*attr
,
906 struct drm_device
*ddev
= dev_get_drvdata(dev
);
907 struct amdgpu_device
*adev
= ddev
->dev_private
;
908 uint32_t parameter_size
= 0;
910 char *sub_str
, buf_cpy
[128];
914 long int profile_mode
= 0;
915 const char delimiter
[3] = {' ', '\n', '\0'};
919 ret
= kstrtol(tmp
, 0, &profile_mode
);
923 if (profile_mode
== PP_SMC_POWER_PROFILE_CUSTOM
) {
924 if (count
< 2 || count
> 127)
926 while (isspace(*++buf
))
928 memcpy(buf_cpy
, buf
, count
-i
);
931 sub_str
= strsep(&tmp_str
, delimiter
);
932 ret
= kstrtol(sub_str
, 0, ¶meter
[parameter_size
]);
938 while (isspace(*tmp_str
))
942 parameter
[parameter_size
] = profile_mode
;
943 if (adev
->powerplay
.pp_funcs
->set_power_profile_mode
)
944 ret
= amdgpu_dpm_set_power_profile_mode(adev
, parameter
, parameter_size
);
955 * The amdgpu driver provides a sysfs API for reading how busy the GPU
956 * is as a percentage. The file gpu_busy_percent is used for this.
957 * The SMU firmware computes a percentage of load based on the
958 * aggregate activity level in the IP cores.
960 static ssize_t
amdgpu_get_busy_percent(struct device
*dev
,
961 struct device_attribute
*attr
,
964 struct drm_device
*ddev
= dev_get_drvdata(dev
);
965 struct amdgpu_device
*adev
= ddev
->dev_private
;
966 int r
, value
, size
= sizeof(value
);
968 /* sanity check PP is enabled */
969 if (!(adev
->powerplay
.pp_funcs
&&
970 adev
->powerplay
.pp_funcs
->read_sensor
))
973 /* read the IP busy sensor */
974 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_LOAD
,
975 (void *)&value
, &size
);
979 return snprintf(buf
, PAGE_SIZE
, "%d\n", value
);
982 static DEVICE_ATTR(power_dpm_state
, S_IRUGO
| S_IWUSR
, amdgpu_get_dpm_state
, amdgpu_set_dpm_state
);
983 static DEVICE_ATTR(power_dpm_force_performance_level
, S_IRUGO
| S_IWUSR
,
984 amdgpu_get_dpm_forced_performance_level
,
985 amdgpu_set_dpm_forced_performance_level
);
986 static DEVICE_ATTR(pp_num_states
, S_IRUGO
, amdgpu_get_pp_num_states
, NULL
);
987 static DEVICE_ATTR(pp_cur_state
, S_IRUGO
, amdgpu_get_pp_cur_state
, NULL
);
988 static DEVICE_ATTR(pp_force_state
, S_IRUGO
| S_IWUSR
,
989 amdgpu_get_pp_force_state
,
990 amdgpu_set_pp_force_state
);
991 static DEVICE_ATTR(pp_table
, S_IRUGO
| S_IWUSR
,
993 amdgpu_set_pp_table
);
994 static DEVICE_ATTR(pp_dpm_sclk
, S_IRUGO
| S_IWUSR
,
995 amdgpu_get_pp_dpm_sclk
,
996 amdgpu_set_pp_dpm_sclk
);
997 static DEVICE_ATTR(pp_dpm_mclk
, S_IRUGO
| S_IWUSR
,
998 amdgpu_get_pp_dpm_mclk
,
999 amdgpu_set_pp_dpm_mclk
);
1000 static DEVICE_ATTR(pp_dpm_pcie
, S_IRUGO
| S_IWUSR
,
1001 amdgpu_get_pp_dpm_pcie
,
1002 amdgpu_set_pp_dpm_pcie
);
1003 static DEVICE_ATTR(pp_sclk_od
, S_IRUGO
| S_IWUSR
,
1004 amdgpu_get_pp_sclk_od
,
1005 amdgpu_set_pp_sclk_od
);
1006 static DEVICE_ATTR(pp_mclk_od
, S_IRUGO
| S_IWUSR
,
1007 amdgpu_get_pp_mclk_od
,
1008 amdgpu_set_pp_mclk_od
);
1009 static DEVICE_ATTR(pp_power_profile_mode
, S_IRUGO
| S_IWUSR
,
1010 amdgpu_get_pp_power_profile_mode
,
1011 amdgpu_set_pp_power_profile_mode
);
1012 static DEVICE_ATTR(pp_od_clk_voltage
, S_IRUGO
| S_IWUSR
,
1013 amdgpu_get_pp_od_clk_voltage
,
1014 amdgpu_set_pp_od_clk_voltage
);
1015 static DEVICE_ATTR(gpu_busy_percent
, S_IRUGO
,
1016 amdgpu_get_busy_percent
, NULL
);
1018 static ssize_t
amdgpu_hwmon_show_temp(struct device
*dev
,
1019 struct device_attribute
*attr
,
1022 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1023 struct drm_device
*ddev
= adev
->ddev
;
1024 int r
, temp
, size
= sizeof(temp
);
1026 /* Can't get temperature when the card is off */
1027 if ((adev
->flags
& AMD_IS_PX
) &&
1028 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1031 /* sanity check PP is enabled */
1032 if (!(adev
->powerplay
.pp_funcs
&&
1033 adev
->powerplay
.pp_funcs
->read_sensor
))
1036 /* get the temperature */
1037 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_TEMP
,
1038 (void *)&temp
, &size
);
1042 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
1045 static ssize_t
amdgpu_hwmon_show_temp_thresh(struct device
*dev
,
1046 struct device_attribute
*attr
,
1049 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1050 int hyst
= to_sensor_dev_attr(attr
)->index
;
1054 temp
= adev
->pm
.dpm
.thermal
.min_temp
;
1056 temp
= adev
->pm
.dpm
.thermal
.max_temp
;
1058 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
1061 static ssize_t
amdgpu_hwmon_get_pwm1_enable(struct device
*dev
,
1062 struct device_attribute
*attr
,
1065 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1068 if (!adev
->powerplay
.pp_funcs
->get_fan_control_mode
)
1071 pwm_mode
= amdgpu_dpm_get_fan_control_mode(adev
);
1073 return sprintf(buf
, "%i\n", pwm_mode
);
1076 static ssize_t
amdgpu_hwmon_set_pwm1_enable(struct device
*dev
,
1077 struct device_attribute
*attr
,
1081 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1085 /* Can't adjust fan when the card is off */
1086 if ((adev
->flags
& AMD_IS_PX
) &&
1087 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1090 if (!adev
->powerplay
.pp_funcs
->set_fan_control_mode
)
1093 err
= kstrtoint(buf
, 10, &value
);
1097 amdgpu_dpm_set_fan_control_mode(adev
, value
);
1102 static ssize_t
amdgpu_hwmon_get_pwm1_min(struct device
*dev
,
1103 struct device_attribute
*attr
,
1106 return sprintf(buf
, "%i\n", 0);
1109 static ssize_t
amdgpu_hwmon_get_pwm1_max(struct device
*dev
,
1110 struct device_attribute
*attr
,
1113 return sprintf(buf
, "%i\n", 255);
1116 static ssize_t
amdgpu_hwmon_set_pwm1(struct device
*dev
,
1117 struct device_attribute
*attr
,
1118 const char *buf
, size_t count
)
1120 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1124 /* Can't adjust fan when the card is off */
1125 if ((adev
->flags
& AMD_IS_PX
) &&
1126 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1129 err
= kstrtou32(buf
, 10, &value
);
1133 value
= (value
* 100) / 255;
1135 if (adev
->powerplay
.pp_funcs
->set_fan_speed_percent
) {
1136 err
= amdgpu_dpm_set_fan_speed_percent(adev
, value
);
1144 static ssize_t
amdgpu_hwmon_get_pwm1(struct device
*dev
,
1145 struct device_attribute
*attr
,
1148 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1152 /* Can't adjust fan when the card is off */
1153 if ((adev
->flags
& AMD_IS_PX
) &&
1154 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1157 if (adev
->powerplay
.pp_funcs
->get_fan_speed_percent
) {
1158 err
= amdgpu_dpm_get_fan_speed_percent(adev
, &speed
);
1163 speed
= (speed
* 255) / 100;
1165 return sprintf(buf
, "%i\n", speed
);
1168 static ssize_t
amdgpu_hwmon_get_fan1_input(struct device
*dev
,
1169 struct device_attribute
*attr
,
1172 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1176 /* Can't adjust fan when the card is off */
1177 if ((adev
->flags
& AMD_IS_PX
) &&
1178 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1181 if (adev
->powerplay
.pp_funcs
->get_fan_speed_rpm
) {
1182 err
= amdgpu_dpm_get_fan_speed_rpm(adev
, &speed
);
1187 return sprintf(buf
, "%i\n", speed
);
1190 static ssize_t
amdgpu_hwmon_show_vddgfx(struct device
*dev
,
1191 struct device_attribute
*attr
,
1194 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1195 struct drm_device
*ddev
= adev
->ddev
;
1197 int r
, size
= sizeof(vddgfx
);
1199 /* Can't get voltage when the card is off */
1200 if ((adev
->flags
& AMD_IS_PX
) &&
1201 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1204 /* sanity check PP is enabled */
1205 if (!(adev
->powerplay
.pp_funcs
&&
1206 adev
->powerplay
.pp_funcs
->read_sensor
))
1209 /* get the voltage */
1210 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDGFX
,
1211 (void *)&vddgfx
, &size
);
1215 return snprintf(buf
, PAGE_SIZE
, "%d\n", vddgfx
);
1218 static ssize_t
amdgpu_hwmon_show_vddgfx_label(struct device
*dev
,
1219 struct device_attribute
*attr
,
1222 return snprintf(buf
, PAGE_SIZE
, "vddgfx\n");
1225 static ssize_t
amdgpu_hwmon_show_vddnb(struct device
*dev
,
1226 struct device_attribute
*attr
,
1229 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1230 struct drm_device
*ddev
= adev
->ddev
;
1232 int r
, size
= sizeof(vddnb
);
1234 /* only APUs have vddnb */
1235 if (!(adev
->flags
& AMD_IS_APU
))
1238 /* Can't get voltage when the card is off */
1239 if ((adev
->flags
& AMD_IS_PX
) &&
1240 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1243 /* sanity check PP is enabled */
1244 if (!(adev
->powerplay
.pp_funcs
&&
1245 adev
->powerplay
.pp_funcs
->read_sensor
))
1248 /* get the voltage */
1249 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDNB
,
1250 (void *)&vddnb
, &size
);
1254 return snprintf(buf
, PAGE_SIZE
, "%d\n", vddnb
);
1257 static ssize_t
amdgpu_hwmon_show_vddnb_label(struct device
*dev
,
1258 struct device_attribute
*attr
,
1261 return snprintf(buf
, PAGE_SIZE
, "vddnb\n");
1264 static ssize_t
amdgpu_hwmon_show_power_avg(struct device
*dev
,
1265 struct device_attribute
*attr
,
1268 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1269 struct drm_device
*ddev
= adev
->ddev
;
1271 int r
, size
= sizeof(u32
);
1274 /* Can't get power when the card is off */
1275 if ((adev
->flags
& AMD_IS_PX
) &&
1276 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1279 /* sanity check PP is enabled */
1280 if (!(adev
->powerplay
.pp_funcs
&&
1281 adev
->powerplay
.pp_funcs
->read_sensor
))
1284 /* get the voltage */
1285 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_POWER
,
1286 (void *)&query
, &size
);
1290 /* convert to microwatts */
1291 uw
= (query
>> 8) * 1000000 + (query
& 0xff) * 1000;
1293 return snprintf(buf
, PAGE_SIZE
, "%u\n", uw
);
1296 static ssize_t
amdgpu_hwmon_show_power_cap_min(struct device
*dev
,
1297 struct device_attribute
*attr
,
1300 return sprintf(buf
, "%i\n", 0);
1303 static ssize_t
amdgpu_hwmon_show_power_cap_max(struct device
*dev
,
1304 struct device_attribute
*attr
,
1307 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1310 if (adev
->powerplay
.pp_funcs
&& adev
->powerplay
.pp_funcs
->get_power_limit
) {
1311 adev
->powerplay
.pp_funcs
->get_power_limit(adev
->powerplay
.pp_handle
, &limit
, true);
1312 return snprintf(buf
, PAGE_SIZE
, "%u\n", limit
* 1000000);
1314 return snprintf(buf
, PAGE_SIZE
, "\n");
1318 static ssize_t
amdgpu_hwmon_show_power_cap(struct device
*dev
,
1319 struct device_attribute
*attr
,
1322 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1325 if (adev
->powerplay
.pp_funcs
&& adev
->powerplay
.pp_funcs
->get_power_limit
) {
1326 adev
->powerplay
.pp_funcs
->get_power_limit(adev
->powerplay
.pp_handle
, &limit
, false);
1327 return snprintf(buf
, PAGE_SIZE
, "%u\n", limit
* 1000000);
1329 return snprintf(buf
, PAGE_SIZE
, "\n");
1334 static ssize_t
amdgpu_hwmon_set_power_cap(struct device
*dev
,
1335 struct device_attribute
*attr
,
1339 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1343 err
= kstrtou32(buf
, 10, &value
);
1347 value
= value
/ 1000000; /* convert to Watt */
1348 if (adev
->powerplay
.pp_funcs
&& adev
->powerplay
.pp_funcs
->set_power_limit
) {
1349 err
= adev
->powerplay
.pp_funcs
->set_power_limit(adev
->powerplay
.pp_handle
, value
);
1363 * The amdgpu driver exposes the following sensor interfaces:
1365 * - GPU temperature (via the on-die sensor)
1369 * - Northbridge voltage (APUs only)
1375 * hwmon interfaces for GPU temperature:
1377 * - temp1_input: the on die GPU temperature in millidegrees Celsius
1379 * - temp1_crit: temperature critical max value in millidegrees Celsius
1381 * - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
1383 * hwmon interfaces for GPU voltage:
1385 * - in0_input: the voltage on the GPU in millivolts
1387 * - in1_input: the voltage on the Northbridge in millivolts
1389 * hwmon interfaces for GPU power:
1391 * - power1_average: average power used by the GPU in microWatts
1393 * - power1_cap_min: minimum cap supported in microWatts
1395 * - power1_cap_max: maximum cap supported in microWatts
1397 * - power1_cap: selected power cap in microWatts
1399 * hwmon interfaces for GPU fan:
1401 * - pwm1: pulse width modulation fan level (0-255)
1403 * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
1405 * - pwm1_min: pulse width modulation fan control minimum level (0)
1407 * - pwm1_max: pulse width modulation fan control maximum level (255)
1409 * - fan1_input: fan speed in RPM
1411 * You can use hwmon tools like sensors to view this information on your system.
1415 static SENSOR_DEVICE_ATTR(temp1_input
, S_IRUGO
, amdgpu_hwmon_show_temp
, NULL
, 0);
1416 static SENSOR_DEVICE_ATTR(temp1_crit
, S_IRUGO
, amdgpu_hwmon_show_temp_thresh
, NULL
, 0);
1417 static SENSOR_DEVICE_ATTR(temp1_crit_hyst
, S_IRUGO
, amdgpu_hwmon_show_temp_thresh
, NULL
, 1);
1418 static SENSOR_DEVICE_ATTR(pwm1
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_get_pwm1
, amdgpu_hwmon_set_pwm1
, 0);
1419 static SENSOR_DEVICE_ATTR(pwm1_enable
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_get_pwm1_enable
, amdgpu_hwmon_set_pwm1_enable
, 0);
1420 static SENSOR_DEVICE_ATTR(pwm1_min
, S_IRUGO
, amdgpu_hwmon_get_pwm1_min
, NULL
, 0);
1421 static SENSOR_DEVICE_ATTR(pwm1_max
, S_IRUGO
, amdgpu_hwmon_get_pwm1_max
, NULL
, 0);
1422 static SENSOR_DEVICE_ATTR(fan1_input
, S_IRUGO
, amdgpu_hwmon_get_fan1_input
, NULL
, 0);
1423 static SENSOR_DEVICE_ATTR(in0_input
, S_IRUGO
, amdgpu_hwmon_show_vddgfx
, NULL
, 0);
1424 static SENSOR_DEVICE_ATTR(in0_label
, S_IRUGO
, amdgpu_hwmon_show_vddgfx_label
, NULL
, 0);
1425 static SENSOR_DEVICE_ATTR(in1_input
, S_IRUGO
, amdgpu_hwmon_show_vddnb
, NULL
, 0);
1426 static SENSOR_DEVICE_ATTR(in1_label
, S_IRUGO
, amdgpu_hwmon_show_vddnb_label
, NULL
, 0);
1427 static SENSOR_DEVICE_ATTR(power1_average
, S_IRUGO
, amdgpu_hwmon_show_power_avg
, NULL
, 0);
1428 static SENSOR_DEVICE_ATTR(power1_cap_max
, S_IRUGO
, amdgpu_hwmon_show_power_cap_max
, NULL
, 0);
1429 static SENSOR_DEVICE_ATTR(power1_cap_min
, S_IRUGO
, amdgpu_hwmon_show_power_cap_min
, NULL
, 0);
1430 static SENSOR_DEVICE_ATTR(power1_cap
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_show_power_cap
, amdgpu_hwmon_set_power_cap
, 0);
1432 static struct attribute
*hwmon_attributes
[] = {
1433 &sensor_dev_attr_temp1_input
.dev_attr
.attr
,
1434 &sensor_dev_attr_temp1_crit
.dev_attr
.attr
,
1435 &sensor_dev_attr_temp1_crit_hyst
.dev_attr
.attr
,
1436 &sensor_dev_attr_pwm1
.dev_attr
.attr
,
1437 &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
,
1438 &sensor_dev_attr_pwm1_min
.dev_attr
.attr
,
1439 &sensor_dev_attr_pwm1_max
.dev_attr
.attr
,
1440 &sensor_dev_attr_fan1_input
.dev_attr
.attr
,
1441 &sensor_dev_attr_in0_input
.dev_attr
.attr
,
1442 &sensor_dev_attr_in0_label
.dev_attr
.attr
,
1443 &sensor_dev_attr_in1_input
.dev_attr
.attr
,
1444 &sensor_dev_attr_in1_label
.dev_attr
.attr
,
1445 &sensor_dev_attr_power1_average
.dev_attr
.attr
,
1446 &sensor_dev_attr_power1_cap_max
.dev_attr
.attr
,
1447 &sensor_dev_attr_power1_cap_min
.dev_attr
.attr
,
1448 &sensor_dev_attr_power1_cap
.dev_attr
.attr
,
1452 static umode_t
hwmon_attributes_visible(struct kobject
*kobj
,
1453 struct attribute
*attr
, int index
)
1455 struct device
*dev
= kobj_to_dev(kobj
);
1456 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1457 umode_t effective_mode
= attr
->mode
;
1460 /* Skip fan attributes if fan is not present */
1461 if (adev
->pm
.no_fan
&& (attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
||
1462 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
||
1463 attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
1464 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
||
1465 attr
== &sensor_dev_attr_fan1_input
.dev_attr
.attr
))
1468 /* Skip limit attributes if DPM is not enabled */
1469 if (!adev
->pm
.dpm_enabled
&&
1470 (attr
== &sensor_dev_attr_temp1_crit
.dev_attr
.attr
||
1471 attr
== &sensor_dev_attr_temp1_crit_hyst
.dev_attr
.attr
||
1472 attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
||
1473 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
||
1474 attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
1475 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
))
1478 /* mask fan attributes if we have no bindings for this asic to expose */
1479 if ((!adev
->powerplay
.pp_funcs
->get_fan_speed_percent
&&
1480 attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
) || /* can't query fan */
1481 (!adev
->powerplay
.pp_funcs
->get_fan_control_mode
&&
1482 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
)) /* can't query state */
1483 effective_mode
&= ~S_IRUGO
;
1485 if ((!adev
->powerplay
.pp_funcs
->set_fan_speed_percent
&&
1486 attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
) || /* can't manage fan */
1487 (!adev
->powerplay
.pp_funcs
->set_fan_control_mode
&&
1488 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
)) /* can't manage state */
1489 effective_mode
&= ~S_IWUSR
;
1491 if ((adev
->flags
& AMD_IS_APU
) &&
1492 (attr
== &sensor_dev_attr_power1_cap_max
.dev_attr
.attr
||
1493 attr
== &sensor_dev_attr_power1_cap_min
.dev_attr
.attr
||
1494 attr
== &sensor_dev_attr_power1_cap
.dev_attr
.attr
))
1497 /* hide max/min values if we can't both query and manage the fan */
1498 if ((!adev
->powerplay
.pp_funcs
->set_fan_speed_percent
&&
1499 !adev
->powerplay
.pp_funcs
->get_fan_speed_percent
) &&
1500 (attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
1501 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
))
1504 /* only APUs have vddnb */
1505 if (!(adev
->flags
& AMD_IS_APU
) &&
1506 (attr
== &sensor_dev_attr_in1_input
.dev_attr
.attr
||
1507 attr
== &sensor_dev_attr_in1_label
.dev_attr
.attr
))
1510 return effective_mode
;
1513 static const struct attribute_group hwmon_attrgroup
= {
1514 .attrs
= hwmon_attributes
,
1515 .is_visible
= hwmon_attributes_visible
,
1518 static const struct attribute_group
*hwmon_groups
[] = {
1523 void amdgpu_dpm_thermal_work_handler(struct work_struct
*work
)
1525 struct amdgpu_device
*adev
=
1526 container_of(work
, struct amdgpu_device
,
1527 pm
.dpm
.thermal
.work
);
1528 /* switch to the thermal state */
1529 enum amd_pm_state_type dpm_state
= POWER_STATE_TYPE_INTERNAL_THERMAL
;
1530 int temp
, size
= sizeof(temp
);
1532 if (!adev
->pm
.dpm_enabled
)
1535 if (adev
->powerplay
.pp_funcs
&&
1536 adev
->powerplay
.pp_funcs
->read_sensor
&&
1537 !amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_TEMP
,
1538 (void *)&temp
, &size
)) {
1539 if (temp
< adev
->pm
.dpm
.thermal
.min_temp
)
1540 /* switch back the user state */
1541 dpm_state
= adev
->pm
.dpm
.user_state
;
1543 if (adev
->pm
.dpm
.thermal
.high_to_low
)
1544 /* switch back the user state */
1545 dpm_state
= adev
->pm
.dpm
.user_state
;
1547 mutex_lock(&adev
->pm
.mutex
);
1548 if (dpm_state
== POWER_STATE_TYPE_INTERNAL_THERMAL
)
1549 adev
->pm
.dpm
.thermal_active
= true;
1551 adev
->pm
.dpm
.thermal_active
= false;
1552 adev
->pm
.dpm
.state
= dpm_state
;
1553 mutex_unlock(&adev
->pm
.mutex
);
1555 amdgpu_pm_compute_clocks(adev
);
1558 static struct amdgpu_ps
*amdgpu_dpm_pick_power_state(struct amdgpu_device
*adev
,
1559 enum amd_pm_state_type dpm_state
)
1562 struct amdgpu_ps
*ps
;
1564 bool single_display
= (adev
->pm
.dpm
.new_active_crtc_count
< 2) ?
1567 /* check if the vblank period is too short to adjust the mclk */
1568 if (single_display
&& adev
->powerplay
.pp_funcs
->vblank_too_short
) {
1569 if (amdgpu_dpm_vblank_too_short(adev
))
1570 single_display
= false;
1573 /* certain older asics have a separare 3D performance state,
1574 * so try that first if the user selected performance
1576 if (dpm_state
== POWER_STATE_TYPE_PERFORMANCE
)
1577 dpm_state
= POWER_STATE_TYPE_INTERNAL_3DPERF
;
1578 /* balanced states don't exist at the moment */
1579 if (dpm_state
== POWER_STATE_TYPE_BALANCED
)
1580 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
1583 /* Pick the best power state based on current conditions */
1584 for (i
= 0; i
< adev
->pm
.dpm
.num_ps
; i
++) {
1585 ps
= &adev
->pm
.dpm
.ps
[i
];
1586 ui_class
= ps
->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK
;
1587 switch (dpm_state
) {
1589 case POWER_STATE_TYPE_BATTERY
:
1590 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
) {
1591 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
1598 case POWER_STATE_TYPE_BALANCED
:
1599 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BALANCED
) {
1600 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
1607 case POWER_STATE_TYPE_PERFORMANCE
:
1608 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
) {
1609 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
1616 /* internal states */
1617 case POWER_STATE_TYPE_INTERNAL_UVD
:
1618 if (adev
->pm
.dpm
.uvd_ps
)
1619 return adev
->pm
.dpm
.uvd_ps
;
1622 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
1623 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE
)
1626 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
1627 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE
)
1630 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
1631 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE
)
1634 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
1635 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_MVC
)
1638 case POWER_STATE_TYPE_INTERNAL_BOOT
:
1639 return adev
->pm
.dpm
.boot_ps
;
1640 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
1641 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_THERMAL
)
1644 case POWER_STATE_TYPE_INTERNAL_ACPI
:
1645 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_ACPI
)
1648 case POWER_STATE_TYPE_INTERNAL_ULV
:
1649 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_ULV
)
1652 case POWER_STATE_TYPE_INTERNAL_3DPERF
:
1653 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE
)
1660 /* use a fallback state if we didn't match */
1661 switch (dpm_state
) {
1662 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
1663 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD_HD
;
1664 goto restart_search
;
1665 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
1666 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
1667 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
1668 if (adev
->pm
.dpm
.uvd_ps
) {
1669 return adev
->pm
.dpm
.uvd_ps
;
1671 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
1672 goto restart_search
;
1674 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
1675 dpm_state
= POWER_STATE_TYPE_INTERNAL_ACPI
;
1676 goto restart_search
;
1677 case POWER_STATE_TYPE_INTERNAL_ACPI
:
1678 dpm_state
= POWER_STATE_TYPE_BATTERY
;
1679 goto restart_search
;
1680 case POWER_STATE_TYPE_BATTERY
:
1681 case POWER_STATE_TYPE_BALANCED
:
1682 case POWER_STATE_TYPE_INTERNAL_3DPERF
:
1683 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
1684 goto restart_search
;
1692 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device
*adev
)
1694 struct amdgpu_ps
*ps
;
1695 enum amd_pm_state_type dpm_state
;
1699 /* if dpm init failed */
1700 if (!adev
->pm
.dpm_enabled
)
1703 if (adev
->pm
.dpm
.user_state
!= adev
->pm
.dpm
.state
) {
1704 /* add other state override checks here */
1705 if ((!adev
->pm
.dpm
.thermal_active
) &&
1706 (!adev
->pm
.dpm
.uvd_active
))
1707 adev
->pm
.dpm
.state
= adev
->pm
.dpm
.user_state
;
1709 dpm_state
= adev
->pm
.dpm
.state
;
1711 ps
= amdgpu_dpm_pick_power_state(adev
, dpm_state
);
1713 adev
->pm
.dpm
.requested_ps
= ps
;
1717 if (amdgpu_dpm
== 1 && adev
->powerplay
.pp_funcs
->print_power_state
) {
1718 printk("switching from power state:\n");
1719 amdgpu_dpm_print_power_state(adev
, adev
->pm
.dpm
.current_ps
);
1720 printk("switching to power state:\n");
1721 amdgpu_dpm_print_power_state(adev
, adev
->pm
.dpm
.requested_ps
);
1724 /* update whether vce is active */
1725 ps
->vce_active
= adev
->pm
.dpm
.vce_active
;
1726 if (adev
->powerplay
.pp_funcs
->display_configuration_changed
)
1727 amdgpu_dpm_display_configuration_changed(adev
);
1729 ret
= amdgpu_dpm_pre_set_power_state(adev
);
1733 if (adev
->powerplay
.pp_funcs
->check_state_equal
) {
1734 if (0 != amdgpu_dpm_check_state_equal(adev
, adev
->pm
.dpm
.current_ps
, adev
->pm
.dpm
.requested_ps
, &equal
))
1741 amdgpu_dpm_set_power_state(adev
);
1742 amdgpu_dpm_post_set_power_state(adev
);
1744 adev
->pm
.dpm
.current_active_crtcs
= adev
->pm
.dpm
.new_active_crtcs
;
1745 adev
->pm
.dpm
.current_active_crtc_count
= adev
->pm
.dpm
.new_active_crtc_count
;
1747 if (adev
->powerplay
.pp_funcs
->force_performance_level
) {
1748 if (adev
->pm
.dpm
.thermal_active
) {
1749 enum amd_dpm_forced_level level
= adev
->pm
.dpm
.forced_level
;
1750 /* force low perf level for thermal */
1751 amdgpu_dpm_force_performance_level(adev
, AMD_DPM_FORCED_LEVEL_LOW
);
1752 /* save the user's level */
1753 adev
->pm
.dpm
.forced_level
= level
;
1755 /* otherwise, user selected level */
1756 amdgpu_dpm_force_performance_level(adev
, adev
->pm
.dpm
.forced_level
);
1761 void amdgpu_dpm_enable_uvd(struct amdgpu_device
*adev
, bool enable
)
1763 if (adev
->powerplay
.pp_funcs
->set_powergating_by_smu
) {
1764 /* enable/disable UVD */
1765 mutex_lock(&adev
->pm
.mutex
);
1766 amdgpu_dpm_set_powergating_by_smu(adev
, AMD_IP_BLOCK_TYPE_UVD
, !enable
);
1767 mutex_unlock(&adev
->pm
.mutex
);
1771 void amdgpu_dpm_enable_vce(struct amdgpu_device
*adev
, bool enable
)
1773 if (adev
->powerplay
.pp_funcs
->set_powergating_by_smu
) {
1774 /* enable/disable VCE */
1775 mutex_lock(&adev
->pm
.mutex
);
1776 amdgpu_dpm_set_powergating_by_smu(adev
, AMD_IP_BLOCK_TYPE_VCE
, !enable
);
1777 mutex_unlock(&adev
->pm
.mutex
);
1781 void amdgpu_pm_print_power_states(struct amdgpu_device
*adev
)
1785 if (adev
->powerplay
.pp_funcs
->print_power_state
== NULL
)
1788 for (i
= 0; i
< adev
->pm
.dpm
.num_ps
; i
++)
1789 amdgpu_dpm_print_power_state(adev
, &adev
->pm
.dpm
.ps
[i
]);
1793 int amdgpu_pm_sysfs_init(struct amdgpu_device
*adev
)
1797 if (adev
->pm
.sysfs_initialized
)
1800 if (adev
->pm
.dpm_enabled
== 0)
1803 adev
->pm
.int_hwmon_dev
= hwmon_device_register_with_groups(adev
->dev
,
1806 if (IS_ERR(adev
->pm
.int_hwmon_dev
)) {
1807 ret
= PTR_ERR(adev
->pm
.int_hwmon_dev
);
1809 "Unable to register hwmon device: %d\n", ret
);
1813 ret
= device_create_file(adev
->dev
, &dev_attr_power_dpm_state
);
1815 DRM_ERROR("failed to create device file for dpm state\n");
1818 ret
= device_create_file(adev
->dev
, &dev_attr_power_dpm_force_performance_level
);
1820 DRM_ERROR("failed to create device file for dpm state\n");
1825 ret
= device_create_file(adev
->dev
, &dev_attr_pp_num_states
);
1827 DRM_ERROR("failed to create device file pp_num_states\n");
1830 ret
= device_create_file(adev
->dev
, &dev_attr_pp_cur_state
);
1832 DRM_ERROR("failed to create device file pp_cur_state\n");
1835 ret
= device_create_file(adev
->dev
, &dev_attr_pp_force_state
);
1837 DRM_ERROR("failed to create device file pp_force_state\n");
1840 ret
= device_create_file(adev
->dev
, &dev_attr_pp_table
);
1842 DRM_ERROR("failed to create device file pp_table\n");
1846 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_sclk
);
1848 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1851 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_mclk
);
1853 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1856 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_pcie
);
1858 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1861 ret
= device_create_file(adev
->dev
, &dev_attr_pp_sclk_od
);
1863 DRM_ERROR("failed to create device file pp_sclk_od\n");
1866 ret
= device_create_file(adev
->dev
, &dev_attr_pp_mclk_od
);
1868 DRM_ERROR("failed to create device file pp_mclk_od\n");
1871 ret
= device_create_file(adev
->dev
,
1872 &dev_attr_pp_power_profile_mode
);
1874 DRM_ERROR("failed to create device file "
1875 "pp_power_profile_mode\n");
1878 ret
= device_create_file(adev
->dev
,
1879 &dev_attr_pp_od_clk_voltage
);
1881 DRM_ERROR("failed to create device file "
1882 "pp_od_clk_voltage\n");
1885 ret
= device_create_file(adev
->dev
,
1886 &dev_attr_gpu_busy_percent
);
1888 DRM_ERROR("failed to create device file "
1889 "gpu_busy_level\n");
1892 ret
= amdgpu_debugfs_pm_init(adev
);
1894 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1898 adev
->pm
.sysfs_initialized
= true;
1903 void amdgpu_pm_sysfs_fini(struct amdgpu_device
*adev
)
1905 if (adev
->pm
.dpm_enabled
== 0)
1908 if (adev
->pm
.int_hwmon_dev
)
1909 hwmon_device_unregister(adev
->pm
.int_hwmon_dev
);
1910 device_remove_file(adev
->dev
, &dev_attr_power_dpm_state
);
1911 device_remove_file(adev
->dev
, &dev_attr_power_dpm_force_performance_level
);
1913 device_remove_file(adev
->dev
, &dev_attr_pp_num_states
);
1914 device_remove_file(adev
->dev
, &dev_attr_pp_cur_state
);
1915 device_remove_file(adev
->dev
, &dev_attr_pp_force_state
);
1916 device_remove_file(adev
->dev
, &dev_attr_pp_table
);
1918 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_sclk
);
1919 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_mclk
);
1920 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_pcie
);
1921 device_remove_file(adev
->dev
, &dev_attr_pp_sclk_od
);
1922 device_remove_file(adev
->dev
, &dev_attr_pp_mclk_od
);
1923 device_remove_file(adev
->dev
,
1924 &dev_attr_pp_power_profile_mode
);
1925 device_remove_file(adev
->dev
,
1926 &dev_attr_pp_od_clk_voltage
);
1927 device_remove_file(adev
->dev
, &dev_attr_gpu_busy_percent
);
1930 void amdgpu_pm_compute_clocks(struct amdgpu_device
*adev
)
1934 if (!adev
->pm
.dpm_enabled
)
1937 if (adev
->mode_info
.num_crtc
)
1938 amdgpu_display_bandwidth_update(adev
);
1940 for (i
= 0; i
< AMDGPU_MAX_RINGS
; i
++) {
1941 struct amdgpu_ring
*ring
= adev
->rings
[i
];
1942 if (ring
&& ring
->ready
)
1943 amdgpu_fence_wait_empty(ring
);
1946 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
1947 if (!amdgpu_device_has_dc_support(adev
)) {
1948 mutex_lock(&adev
->pm
.mutex
);
1949 amdgpu_dpm_get_active_displays(adev
);
1950 adev
->pm
.pm_display_cfg
.num_display
= adev
->pm
.dpm
.new_active_crtc_count
;
1951 adev
->pm
.pm_display_cfg
.vrefresh
= amdgpu_dpm_get_vrefresh(adev
);
1952 adev
->pm
.pm_display_cfg
.min_vblank_time
= amdgpu_dpm_get_vblank_time(adev
);
1953 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
1954 if (adev
->pm
.pm_display_cfg
.vrefresh
> 120)
1955 adev
->pm
.pm_display_cfg
.min_vblank_time
= 0;
1956 if (adev
->powerplay
.pp_funcs
->display_configuration_change
)
1957 adev
->powerplay
.pp_funcs
->display_configuration_change(
1958 adev
->powerplay
.pp_handle
,
1959 &adev
->pm
.pm_display_cfg
);
1960 mutex_unlock(&adev
->pm
.mutex
);
1962 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE
, NULL
);
1964 mutex_lock(&adev
->pm
.mutex
);
1965 amdgpu_dpm_get_active_displays(adev
);
1966 amdgpu_dpm_change_power_state_locked(adev
);
1967 mutex_unlock(&adev
->pm
.mutex
);
1974 #if defined(CONFIG_DEBUG_FS)
1976 static int amdgpu_debugfs_pm_info_pp(struct seq_file
*m
, struct amdgpu_device
*adev
)
1982 /* sanity check PP is enabled */
1983 if (!(adev
->powerplay
.pp_funcs
&&
1984 adev
->powerplay
.pp_funcs
->read_sensor
))
1988 size
= sizeof(value
);
1989 seq_printf(m
, "GFX Clocks and Power:\n");
1990 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GFX_MCLK
, (void *)&value
, &size
))
1991 seq_printf(m
, "\t%u MHz (MCLK)\n", value
/100);
1992 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GFX_SCLK
, (void *)&value
, &size
))
1993 seq_printf(m
, "\t%u MHz (SCLK)\n", value
/100);
1994 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK
, (void *)&value
, &size
))
1995 seq_printf(m
, "\t%u MHz (PSTATE_SCLK)\n", value
/100);
1996 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK
, (void *)&value
, &size
))
1997 seq_printf(m
, "\t%u MHz (PSTATE_MCLK)\n", value
/100);
1998 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDGFX
, (void *)&value
, &size
))
1999 seq_printf(m
, "\t%u mV (VDDGFX)\n", value
);
2000 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDNB
, (void *)&value
, &size
))
2001 seq_printf(m
, "\t%u mV (VDDNB)\n", value
);
2002 size
= sizeof(uint32_t);
2003 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_POWER
, (void *)&query
, &size
))
2004 seq_printf(m
, "\t%u.%u W (average GPU)\n", query
>> 8, query
& 0xff);
2005 size
= sizeof(value
);
2006 seq_printf(m
, "\n");
2009 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_TEMP
, (void *)&value
, &size
))
2010 seq_printf(m
, "GPU Temperature: %u C\n", value
/1000);
2013 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_LOAD
, (void *)&value
, &size
))
2014 seq_printf(m
, "GPU Load: %u %%\n", value
);
2015 seq_printf(m
, "\n");
2018 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_UVD_POWER
, (void *)&value
, &size
)) {
2020 seq_printf(m
, "UVD: Disabled\n");
2022 seq_printf(m
, "UVD: Enabled\n");
2023 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_UVD_DCLK
, (void *)&value
, &size
))
2024 seq_printf(m
, "\t%u MHz (DCLK)\n", value
/100);
2025 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_UVD_VCLK
, (void *)&value
, &size
))
2026 seq_printf(m
, "\t%u MHz (VCLK)\n", value
/100);
2029 seq_printf(m
, "\n");
2032 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VCE_POWER
, (void *)&value
, &size
)) {
2034 seq_printf(m
, "VCE: Disabled\n");
2036 seq_printf(m
, "VCE: Enabled\n");
2037 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VCE_ECCLK
, (void *)&value
, &size
))
2038 seq_printf(m
, "\t%u MHz (ECCLK)\n", value
/100);
2045 static void amdgpu_parse_cg_state(struct seq_file
*m
, u32 flags
)
2049 for (i
= 0; clocks
[i
].flag
; i
++)
2050 seq_printf(m
, "\t%s: %s\n", clocks
[i
].name
,
2051 (flags
& clocks
[i
].flag
) ? "On" : "Off");
2054 static int amdgpu_debugfs_pm_info(struct seq_file
*m
, void *data
)
2056 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2057 struct drm_device
*dev
= node
->minor
->dev
;
2058 struct amdgpu_device
*adev
= dev
->dev_private
;
2059 struct drm_device
*ddev
= adev
->ddev
;
2062 amdgpu_device_ip_get_clockgating_state(adev
, &flags
);
2063 seq_printf(m
, "Clock Gating Flags Mask: 0x%x\n", flags
);
2064 amdgpu_parse_cg_state(m
, flags
);
2065 seq_printf(m
, "\n");
2067 if (!adev
->pm
.dpm_enabled
) {
2068 seq_printf(m
, "dpm not enabled\n");
2071 if ((adev
->flags
& AMD_IS_PX
) &&
2072 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
)) {
2073 seq_printf(m
, "PX asic powered off\n");
2074 } else if (adev
->powerplay
.pp_funcs
->debugfs_print_current_performance_level
) {
2075 mutex_lock(&adev
->pm
.mutex
);
2076 if (adev
->powerplay
.pp_funcs
->debugfs_print_current_performance_level
)
2077 adev
->powerplay
.pp_funcs
->debugfs_print_current_performance_level(adev
, m
);
2079 seq_printf(m
, "Debugfs support not implemented for this asic\n");
2080 mutex_unlock(&adev
->pm
.mutex
);
2082 return amdgpu_debugfs_pm_info_pp(m
, adev
);
2088 static const struct drm_info_list amdgpu_pm_info_list
[] = {
2089 {"amdgpu_pm_info", amdgpu_debugfs_pm_info
, 0, NULL
},
2093 static int amdgpu_debugfs_pm_init(struct amdgpu_device
*adev
)
2095 #if defined(CONFIG_DEBUG_FS)
2096 return amdgpu_debugfs_add_files(adev
, amdgpu_pm_info_list
, ARRAY_SIZE(amdgpu_pm_info_list
));