2 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Rafał Miłecki <zajec5@gmail.com>
23 * Alex Deucher <alexdeucher@gmail.com>
27 #include "amdgpu_drv.h"
28 #include "amdgpu_pm.h"
29 #include "amdgpu_dpm.h"
30 #include "amdgpu_display.h"
31 #include "amdgpu_smu.h"
33 #include <linux/power_supply.h>
34 #include <linux/hwmon.h>
35 #include <linux/hwmon-sysfs.h>
36 #include <linux/nospec.h>
40 static int amdgpu_debugfs_pm_init(struct amdgpu_device
*adev
);
42 static const struct cg_flag_name clocks
[] = {
43 {AMD_CG_SUPPORT_GFX_MGCG
, "Graphics Medium Grain Clock Gating"},
44 {AMD_CG_SUPPORT_GFX_MGLS
, "Graphics Medium Grain memory Light Sleep"},
45 {AMD_CG_SUPPORT_GFX_CGCG
, "Graphics Coarse Grain Clock Gating"},
46 {AMD_CG_SUPPORT_GFX_CGLS
, "Graphics Coarse Grain memory Light Sleep"},
47 {AMD_CG_SUPPORT_GFX_CGTS
, "Graphics Coarse Grain Tree Shader Clock Gating"},
48 {AMD_CG_SUPPORT_GFX_CGTS_LS
, "Graphics Coarse Grain Tree Shader Light Sleep"},
49 {AMD_CG_SUPPORT_GFX_CP_LS
, "Graphics Command Processor Light Sleep"},
50 {AMD_CG_SUPPORT_GFX_RLC_LS
, "Graphics Run List Controller Light Sleep"},
51 {AMD_CG_SUPPORT_GFX_3D_CGCG
, "Graphics 3D Coarse Grain Clock Gating"},
52 {AMD_CG_SUPPORT_GFX_3D_CGLS
, "Graphics 3D Coarse Grain memory Light Sleep"},
53 {AMD_CG_SUPPORT_MC_LS
, "Memory Controller Light Sleep"},
54 {AMD_CG_SUPPORT_MC_MGCG
, "Memory Controller Medium Grain Clock Gating"},
55 {AMD_CG_SUPPORT_SDMA_LS
, "System Direct Memory Access Light Sleep"},
56 {AMD_CG_SUPPORT_SDMA_MGCG
, "System Direct Memory Access Medium Grain Clock Gating"},
57 {AMD_CG_SUPPORT_BIF_MGCG
, "Bus Interface Medium Grain Clock Gating"},
58 {AMD_CG_SUPPORT_BIF_LS
, "Bus Interface Light Sleep"},
59 {AMD_CG_SUPPORT_UVD_MGCG
, "Unified Video Decoder Medium Grain Clock Gating"},
60 {AMD_CG_SUPPORT_VCE_MGCG
, "Video Compression Engine Medium Grain Clock Gating"},
61 {AMD_CG_SUPPORT_HDP_LS
, "Host Data Path Light Sleep"},
62 {AMD_CG_SUPPORT_HDP_MGCG
, "Host Data Path Medium Grain Clock Gating"},
63 {AMD_CG_SUPPORT_DRM_MGCG
, "Digital Right Management Medium Grain Clock Gating"},
64 {AMD_CG_SUPPORT_DRM_LS
, "Digital Right Management Light Sleep"},
65 {AMD_CG_SUPPORT_ROM_MGCG
, "Rom Medium Grain Clock Gating"},
66 {AMD_CG_SUPPORT_DF_MGCG
, "Data Fabric Medium Grain Clock Gating"},
70 void amdgpu_pm_acpi_event_handler(struct amdgpu_device
*adev
)
72 if (adev
->pm
.dpm_enabled
) {
73 mutex_lock(&adev
->pm
.mutex
);
74 if (power_supply_is_system_supplied() > 0)
75 adev
->pm
.ac_power
= true;
77 adev
->pm
.ac_power
= false;
78 if (adev
->powerplay
.pp_funcs
->enable_bapm
)
79 amdgpu_dpm_enable_bapm(adev
, adev
->pm
.ac_power
);
80 mutex_unlock(&adev
->pm
.mutex
);
84 int amdgpu_dpm_read_sensor(struct amdgpu_device
*adev
, enum amd_pp_sensors sensor
,
85 void *data
, uint32_t *size
)
92 if (is_support_sw_smu(adev
))
93 ret
= smu_read_sensor(&adev
->smu
, sensor
, data
, size
);
95 if (adev
->powerplay
.pp_funcs
&& adev
->powerplay
.pp_funcs
->read_sensor
)
96 ret
= adev
->powerplay
.pp_funcs
->read_sensor((adev
)->powerplay
.pp_handle
,
106 * DOC: power_dpm_state
108 * The power_dpm_state file is a legacy interface and is only provided for
109 * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
110 * certain power related parameters. The file power_dpm_state is used for this.
111 * It accepts the following arguments:
121 * On older GPUs, the vbios provided a special power state for battery
122 * operation. Selecting battery switched to this state. This is no
123 * longer provided on newer GPUs so the option does nothing in that case.
127 * On older GPUs, the vbios provided a special power state for balanced
128 * operation. Selecting balanced switched to this state. This is no
129 * longer provided on newer GPUs so the option does nothing in that case.
133 * On older GPUs, the vbios provided a special power state for performance
134 * operation. Selecting performance switched to this state. This is no
135 * longer provided on newer GPUs so the option does nothing in that case.
139 static ssize_t
amdgpu_get_dpm_state(struct device
*dev
,
140 struct device_attribute
*attr
,
143 struct drm_device
*ddev
= dev_get_drvdata(dev
);
144 struct amdgpu_device
*adev
= ddev
->dev_private
;
145 enum amd_pm_state_type pm
;
147 if (is_support_sw_smu(adev
) && adev
->smu
.ppt_funcs
->get_current_power_state
)
148 pm
= amdgpu_smu_get_current_power_state(adev
);
149 else if (adev
->powerplay
.pp_funcs
->get_current_power_state
)
150 pm
= amdgpu_dpm_get_current_power_state(adev
);
152 pm
= adev
->pm
.dpm
.user_state
;
154 return snprintf(buf
, PAGE_SIZE
, "%s\n",
155 (pm
== POWER_STATE_TYPE_BATTERY
) ? "battery" :
156 (pm
== POWER_STATE_TYPE_BALANCED
) ? "balanced" : "performance");
159 static ssize_t
amdgpu_set_dpm_state(struct device
*dev
,
160 struct device_attribute
*attr
,
164 struct drm_device
*ddev
= dev_get_drvdata(dev
);
165 struct amdgpu_device
*adev
= ddev
->dev_private
;
166 enum amd_pm_state_type state
;
168 if (strncmp("battery", buf
, strlen("battery")) == 0)
169 state
= POWER_STATE_TYPE_BATTERY
;
170 else if (strncmp("balanced", buf
, strlen("balanced")) == 0)
171 state
= POWER_STATE_TYPE_BALANCED
;
172 else if (strncmp("performance", buf
, strlen("performance")) == 0)
173 state
= POWER_STATE_TYPE_PERFORMANCE
;
179 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
180 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_ENABLE_USER_STATE
, &state
);
182 mutex_lock(&adev
->pm
.mutex
);
183 adev
->pm
.dpm
.user_state
= state
;
184 mutex_unlock(&adev
->pm
.mutex
);
186 /* Can't set dpm state when the card is off */
187 if (!(adev
->flags
& AMD_IS_PX
) ||
188 (ddev
->switch_power_state
== DRM_SWITCH_POWER_ON
))
189 amdgpu_pm_compute_clocks(adev
);
197 * DOC: power_dpm_force_performance_level
199 * The amdgpu driver provides a sysfs API for adjusting certain power
200 * related parameters. The file power_dpm_force_performance_level is
201 * used for this. It accepts the following arguments:
221 * When auto is selected, the driver will attempt to dynamically select
222 * the optimal power profile for current conditions in the driver.
226 * When low is selected, the clocks are forced to the lowest power state.
230 * When high is selected, the clocks are forced to the highest power state.
234 * When manual is selected, the user can manually adjust which power states
235 * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
236 * and pp_dpm_pcie files and adjust the power state transition heuristics
237 * via the pp_power_profile_mode sysfs file.
244 * When the profiling modes are selected, clock and power gating are
245 * disabled and the clocks are set for different profiling cases. This
246 * mode is recommended for profiling specific work loads where you do
247 * not want clock or power gating for clock fluctuation to interfere
248 * with your results. profile_standard sets the clocks to a fixed clock
249 * level which varies from asic to asic. profile_min_sclk forces the sclk
250 * to the lowest level. profile_min_mclk forces the mclk to the lowest level.
251 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
255 static ssize_t
amdgpu_get_dpm_forced_performance_level(struct device
*dev
,
256 struct device_attribute
*attr
,
259 struct drm_device
*ddev
= dev_get_drvdata(dev
);
260 struct amdgpu_device
*adev
= ddev
->dev_private
;
261 enum amd_dpm_forced_level level
= 0xff;
263 if ((adev
->flags
& AMD_IS_PX
) &&
264 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
265 return snprintf(buf
, PAGE_SIZE
, "off\n");
267 if (is_support_sw_smu(adev
))
268 level
= smu_get_performance_level(&adev
->smu
);
269 else if (adev
->powerplay
.pp_funcs
->get_performance_level
)
270 level
= amdgpu_dpm_get_performance_level(adev
);
272 level
= adev
->pm
.dpm
.forced_level
;
274 return snprintf(buf
, PAGE_SIZE
, "%s\n",
275 (level
== AMD_DPM_FORCED_LEVEL_AUTO
) ? "auto" :
276 (level
== AMD_DPM_FORCED_LEVEL_LOW
) ? "low" :
277 (level
== AMD_DPM_FORCED_LEVEL_HIGH
) ? "high" :
278 (level
== AMD_DPM_FORCED_LEVEL_MANUAL
) ? "manual" :
279 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
) ? "profile_standard" :
280 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
) ? "profile_min_sclk" :
281 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
) ? "profile_min_mclk" :
282 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
) ? "profile_peak" :
286 static ssize_t
amdgpu_set_dpm_forced_performance_level(struct device
*dev
,
287 struct device_attribute
*attr
,
291 struct drm_device
*ddev
= dev_get_drvdata(dev
);
292 struct amdgpu_device
*adev
= ddev
->dev_private
;
293 enum amd_dpm_forced_level level
;
294 enum amd_dpm_forced_level current_level
= 0xff;
297 /* Can't force performance level when the card is off */
298 if ((adev
->flags
& AMD_IS_PX
) &&
299 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
302 if (is_support_sw_smu(adev
))
303 current_level
= smu_get_performance_level(&adev
->smu
);
304 else if (adev
->powerplay
.pp_funcs
->get_performance_level
)
305 current_level
= amdgpu_dpm_get_performance_level(adev
);
307 if (strncmp("low", buf
, strlen("low")) == 0) {
308 level
= AMD_DPM_FORCED_LEVEL_LOW
;
309 } else if (strncmp("high", buf
, strlen("high")) == 0) {
310 level
= AMD_DPM_FORCED_LEVEL_HIGH
;
311 } else if (strncmp("auto", buf
, strlen("auto")) == 0) {
312 level
= AMD_DPM_FORCED_LEVEL_AUTO
;
313 } else if (strncmp("manual", buf
, strlen("manual")) == 0) {
314 level
= AMD_DPM_FORCED_LEVEL_MANUAL
;
315 } else if (strncmp("profile_exit", buf
, strlen("profile_exit")) == 0) {
316 level
= AMD_DPM_FORCED_LEVEL_PROFILE_EXIT
;
317 } else if (strncmp("profile_standard", buf
, strlen("profile_standard")) == 0) {
318 level
= AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
;
319 } else if (strncmp("profile_min_sclk", buf
, strlen("profile_min_sclk")) == 0) {
320 level
= AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
;
321 } else if (strncmp("profile_min_mclk", buf
, strlen("profile_min_mclk")) == 0) {
322 level
= AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
;
323 } else if (strncmp("profile_peak", buf
, strlen("profile_peak")) == 0) {
324 level
= AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
;
330 if (amdgpu_sriov_vf(adev
)) {
331 if (amdgim_is_hwperf(adev
) &&
332 adev
->virt
.ops
->force_dpm_level
) {
333 mutex_lock(&adev
->pm
.mutex
);
334 adev
->virt
.ops
->force_dpm_level(adev
, level
);
335 mutex_unlock(&adev
->pm
.mutex
);
342 if (current_level
== level
)
345 /* profile_exit setting is valid only when current mode is in profile mode */
346 if (!(current_level
& (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
|
347 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
|
348 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
|
349 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
)) &&
350 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_EXIT
)) {
351 pr_err("Currently not in any profile mode!\n");
355 if (is_support_sw_smu(adev
)) {
356 mutex_lock(&adev
->pm
.mutex
);
357 if (adev
->pm
.dpm
.thermal_active
) {
359 mutex_unlock(&adev
->pm
.mutex
);
362 ret
= smu_force_performance_level(&adev
->smu
, level
);
366 adev
->pm
.dpm
.forced_level
= level
;
367 mutex_unlock(&adev
->pm
.mutex
);
368 } else if (adev
->powerplay
.pp_funcs
->force_performance_level
) {
369 mutex_lock(&adev
->pm
.mutex
);
370 if (adev
->pm
.dpm
.thermal_active
) {
372 mutex_unlock(&adev
->pm
.mutex
);
375 ret
= amdgpu_dpm_force_performance_level(adev
, level
);
379 adev
->pm
.dpm
.forced_level
= level
;
380 mutex_unlock(&adev
->pm
.mutex
);
387 static ssize_t
amdgpu_get_pp_num_states(struct device
*dev
,
388 struct device_attribute
*attr
,
391 struct drm_device
*ddev
= dev_get_drvdata(dev
);
392 struct amdgpu_device
*adev
= ddev
->dev_private
;
393 struct pp_states_info data
;
396 if (is_support_sw_smu(adev
)) {
397 ret
= smu_get_power_num_states(&adev
->smu
, &data
);
400 } else if (adev
->powerplay
.pp_funcs
->get_pp_num_states
)
401 amdgpu_dpm_get_pp_num_states(adev
, &data
);
403 buf_len
= snprintf(buf
, PAGE_SIZE
, "states: %d\n", data
.nums
);
404 for (i
= 0; i
< data
.nums
; i
++)
405 buf_len
+= snprintf(buf
+ buf_len
, PAGE_SIZE
, "%d %s\n", i
,
406 (data
.states
[i
] == POWER_STATE_TYPE_INTERNAL_BOOT
) ? "boot" :
407 (data
.states
[i
] == POWER_STATE_TYPE_BATTERY
) ? "battery" :
408 (data
.states
[i
] == POWER_STATE_TYPE_BALANCED
) ? "balanced" :
409 (data
.states
[i
] == POWER_STATE_TYPE_PERFORMANCE
) ? "performance" : "default");
414 static ssize_t
amdgpu_get_pp_cur_state(struct device
*dev
,
415 struct device_attribute
*attr
,
418 struct drm_device
*ddev
= dev_get_drvdata(dev
);
419 struct amdgpu_device
*adev
= ddev
->dev_private
;
420 struct pp_states_info data
;
421 struct smu_context
*smu
= &adev
->smu
;
422 enum amd_pm_state_type pm
= 0;
425 if (is_support_sw_smu(adev
)) {
426 pm
= smu_get_current_power_state(smu
);
427 ret
= smu_get_power_num_states(smu
, &data
);
430 } else if (adev
->powerplay
.pp_funcs
->get_current_power_state
431 && adev
->powerplay
.pp_funcs
->get_pp_num_states
) {
432 pm
= amdgpu_dpm_get_current_power_state(adev
);
433 amdgpu_dpm_get_pp_num_states(adev
, &data
);
436 for (i
= 0; i
< data
.nums
; i
++) {
437 if (pm
== data
.states
[i
])
444 return snprintf(buf
, PAGE_SIZE
, "%d\n", i
);
447 static ssize_t
amdgpu_get_pp_force_state(struct device
*dev
,
448 struct device_attribute
*attr
,
451 struct drm_device
*ddev
= dev_get_drvdata(dev
);
452 struct amdgpu_device
*adev
= ddev
->dev_private
;
454 if (adev
->pp_force_state_enabled
)
455 return amdgpu_get_pp_cur_state(dev
, attr
, buf
);
457 return snprintf(buf
, PAGE_SIZE
, "\n");
460 static ssize_t
amdgpu_set_pp_force_state(struct device
*dev
,
461 struct device_attribute
*attr
,
465 struct drm_device
*ddev
= dev_get_drvdata(dev
);
466 struct amdgpu_device
*adev
= ddev
->dev_private
;
467 enum amd_pm_state_type state
= 0;
471 if (strlen(buf
) == 1)
472 adev
->pp_force_state_enabled
= false;
473 else if (is_support_sw_smu(adev
))
474 adev
->pp_force_state_enabled
= false;
475 else if (adev
->powerplay
.pp_funcs
->dispatch_tasks
&&
476 adev
->powerplay
.pp_funcs
->get_pp_num_states
) {
477 struct pp_states_info data
;
479 ret
= kstrtoul(buf
, 0, &idx
);
480 if (ret
|| idx
>= ARRAY_SIZE(data
.states
)) {
484 idx
= array_index_nospec(idx
, ARRAY_SIZE(data
.states
));
486 amdgpu_dpm_get_pp_num_states(adev
, &data
);
487 state
= data
.states
[idx
];
488 /* only set user selected power states */
489 if (state
!= POWER_STATE_TYPE_INTERNAL_BOOT
&&
490 state
!= POWER_STATE_TYPE_DEFAULT
) {
491 amdgpu_dpm_dispatch_task(adev
,
492 AMD_PP_TASK_ENABLE_USER_STATE
, &state
);
493 adev
->pp_force_state_enabled
= true;
503 * The amdgpu driver provides a sysfs API for uploading new powerplay
504 * tables. The file pp_table is used for this. Reading the file
505 * will dump the current power play table. Writing to the file
506 * will attempt to upload a new powerplay table and re-initialize
507 * powerplay using that new table.
511 static ssize_t
amdgpu_get_pp_table(struct device
*dev
,
512 struct device_attribute
*attr
,
515 struct drm_device
*ddev
= dev_get_drvdata(dev
);
516 struct amdgpu_device
*adev
= ddev
->dev_private
;
520 if (is_support_sw_smu(adev
)) {
521 size
= smu_sys_get_pp_table(&adev
->smu
, (void **)&table
);
525 else if (adev
->powerplay
.pp_funcs
->get_pp_table
)
526 size
= amdgpu_dpm_get_pp_table(adev
, &table
);
530 if (size
>= PAGE_SIZE
)
531 size
= PAGE_SIZE
- 1;
533 memcpy(buf
, table
, size
);
538 static ssize_t
amdgpu_set_pp_table(struct device
*dev
,
539 struct device_attribute
*attr
,
543 struct drm_device
*ddev
= dev_get_drvdata(dev
);
544 struct amdgpu_device
*adev
= ddev
->dev_private
;
547 if (is_support_sw_smu(adev
)) {
548 ret
= smu_sys_set_pp_table(&adev
->smu
, (void *)buf
, count
);
551 } else if (adev
->powerplay
.pp_funcs
->set_pp_table
)
552 amdgpu_dpm_set_pp_table(adev
, buf
, count
);
558 * DOC: pp_od_clk_voltage
560 * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
561 * in each power level within a power state. The pp_od_clk_voltage is used for
564 * < For Vega10 and previous ASICs >
566 * Reading the file will display:
568 * - a list of engine clock levels and voltages labeled OD_SCLK
570 * - a list of memory clock levels and voltages labeled OD_MCLK
572 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
574 * To manually adjust these settings, first select manual using
575 * power_dpm_force_performance_level. Enter a new value for each
576 * level by writing a string that contains "s/m level clock voltage" to
577 * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
578 * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
579 * 810 mV. When you have edited all of the states as needed, write
580 * "c" (commit) to the file to commit your changes. If you want to reset to the
581 * default power levels, write "r" (reset) to the file to reset them.
586 * Reading the file will display:
588 * - minimum and maximum engine clock labeled OD_SCLK
590 * - maximum memory clock labeled OD_MCLK
592 * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
593 * They can be used to calibrate the sclk voltage curve.
595 * - a list of valid ranges for sclk, mclk, and voltage curve points
598 * To manually adjust these settings:
600 * - First select manual using power_dpm_force_performance_level
602 * - For clock frequency setting, enter a new value by writing a
603 * string that contains "s/m index clock" to the file. The index
604 * should be 0 if to set minimum clock. And 1 if to set maximum
605 * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
606 * "m 1 800" will update maximum mclk to be 800Mhz.
608 * For sclk voltage curve, enter the new values by writing a
609 * string that contains "vc point clock voltage" to the file. The
610 * points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
611 * update point1 with clock set as 300Mhz and voltage as
612 * 600mV. "vc 2 1000 1000" will update point3 with clock set
613 * as 1000Mhz and voltage 1000mV.
615 * - When you have edited all of the states as needed, write "c" (commit)
616 * to the file to commit your changes
618 * - If you want to reset to the default power levels, write "r" (reset)
619 * to the file to reset them
623 static ssize_t
amdgpu_set_pp_od_clk_voltage(struct device
*dev
,
624 struct device_attribute
*attr
,
628 struct drm_device
*ddev
= dev_get_drvdata(dev
);
629 struct amdgpu_device
*adev
= ddev
->dev_private
;
631 uint32_t parameter_size
= 0;
636 const char delimiter
[3] = {' ', '\n', '\0'};
643 type
= PP_OD_EDIT_SCLK_VDDC_TABLE
;
644 else if (*buf
== 'm')
645 type
= PP_OD_EDIT_MCLK_VDDC_TABLE
;
647 type
= PP_OD_RESTORE_DEFAULT_TABLE
;
648 else if (*buf
== 'c')
649 type
= PP_OD_COMMIT_DPM_TABLE
;
650 else if (!strncmp(buf
, "vc", 2))
651 type
= PP_OD_EDIT_VDDC_CURVE
;
655 memcpy(buf_cpy
, buf
, count
+1);
659 if (type
== PP_OD_EDIT_VDDC_CURVE
)
661 while (isspace(*++tmp_str
));
664 sub_str
= strsep(&tmp_str
, delimiter
);
665 ret
= kstrtol(sub_str
, 0, ¶meter
[parameter_size
]);
670 while (isspace(*tmp_str
))
674 if (is_support_sw_smu(adev
)) {
675 ret
= smu_od_edit_dpm_table(&adev
->smu
, type
,
676 parameter
, parameter_size
);
681 if (adev
->powerplay
.pp_funcs
->odn_edit_dpm_table
)
682 ret
= amdgpu_dpm_odn_edit_dpm_table(adev
, type
,
683 parameter
, parameter_size
);
688 if (type
== PP_OD_COMMIT_DPM_TABLE
) {
689 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
690 amdgpu_dpm_dispatch_task(adev
,
691 AMD_PP_TASK_READJUST_POWER_STATE
,
703 static ssize_t
amdgpu_get_pp_od_clk_voltage(struct device
*dev
,
704 struct device_attribute
*attr
,
707 struct drm_device
*ddev
= dev_get_drvdata(dev
);
708 struct amdgpu_device
*adev
= ddev
->dev_private
;
711 if (is_support_sw_smu(adev
)) {
712 size
= smu_print_clk_levels(&adev
->smu
, OD_SCLK
, buf
);
713 size
+= smu_print_clk_levels(&adev
->smu
, OD_MCLK
, buf
+size
);
714 size
+= smu_print_clk_levels(&adev
->smu
, OD_VDDC_CURVE
, buf
+size
);
715 size
+= smu_print_clk_levels(&adev
->smu
, OD_RANGE
, buf
+size
);
717 } else if (adev
->powerplay
.pp_funcs
->print_clock_levels
) {
718 size
= amdgpu_dpm_print_clock_levels(adev
, OD_SCLK
, buf
);
719 size
+= amdgpu_dpm_print_clock_levels(adev
, OD_MCLK
, buf
+size
);
720 size
+= amdgpu_dpm_print_clock_levels(adev
, OD_VDDC_CURVE
, buf
+size
);
721 size
+= amdgpu_dpm_print_clock_levels(adev
, OD_RANGE
, buf
+size
);
724 return snprintf(buf
, PAGE_SIZE
, "\n");
732 * The amdgpu driver provides a sysfs API for adjusting what powerplay
733 * features to be enabled. The file ppfeatures is used for this. And
734 * this is only available for Vega10 and later dGPUs.
736 * Reading back the file will show you the followings:
737 * - Current ppfeature masks
738 * - List of the all supported powerplay features with their naming,
739 * bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
741 * To manually enable or disable a specific feature, just set or clear
742 * the corresponding bit from original ppfeature masks and input the
743 * new ppfeature masks.
745 static ssize_t
amdgpu_set_ppfeature_status(struct device
*dev
,
746 struct device_attribute
*attr
,
750 struct drm_device
*ddev
= dev_get_drvdata(dev
);
751 struct amdgpu_device
*adev
= ddev
->dev_private
;
752 uint64_t featuremask
;
755 ret
= kstrtou64(buf
, 0, &featuremask
);
759 pr_debug("featuremask = 0x%llx\n", featuremask
);
761 if (adev
->powerplay
.pp_funcs
->set_ppfeature_status
) {
762 ret
= amdgpu_dpm_set_ppfeature_status(adev
, featuremask
);
770 static ssize_t
amdgpu_get_ppfeature_status(struct device
*dev
,
771 struct device_attribute
*attr
,
774 struct drm_device
*ddev
= dev_get_drvdata(dev
);
775 struct amdgpu_device
*adev
= ddev
->dev_private
;
777 if (adev
->powerplay
.pp_funcs
->get_ppfeature_status
)
778 return amdgpu_dpm_get_ppfeature_status(adev
, buf
);
780 return snprintf(buf
, PAGE_SIZE
, "\n");
784 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk
787 * The amdgpu driver provides a sysfs API for adjusting what power levels
788 * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk,
789 * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
792 * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
793 * Vega10 and later ASICs.
794 * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
796 * Reading back the files will show you the available power levels within
797 * the power state and the clock information for those levels.
799 * To manually adjust these states, first select manual using
800 * power_dpm_force_performance_level.
801 * Secondly,Enter a new value for each level by inputing a string that
802 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
803 * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
805 * NOTE: change to the dcefclk max dpm level is not supported now
808 static ssize_t
amdgpu_get_pp_dpm_sclk(struct device
*dev
,
809 struct device_attribute
*attr
,
812 struct drm_device
*ddev
= dev_get_drvdata(dev
);
813 struct amdgpu_device
*adev
= ddev
->dev_private
;
815 if (amdgpu_sriov_vf(adev
) && amdgim_is_hwperf(adev
) &&
816 adev
->virt
.ops
->get_pp_clk
)
817 return adev
->virt
.ops
->get_pp_clk(adev
, PP_SCLK
, buf
);
819 if (is_support_sw_smu(adev
))
820 return smu_print_clk_levels(&adev
->smu
, PP_SCLK
, buf
);
821 else if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
822 return amdgpu_dpm_print_clock_levels(adev
, PP_SCLK
, buf
);
824 return snprintf(buf
, PAGE_SIZE
, "\n");
828 * Worst case: 32 bits individually specified, in octal at 12 characters
829 * per line (+1 for \n).
831 #define AMDGPU_MASK_BUF_MAX (32 * 13)
833 static ssize_t
amdgpu_read_mask(const char *buf
, size_t count
, uint32_t *mask
)
837 char *sub_str
= NULL
;
839 char buf_cpy
[AMDGPU_MASK_BUF_MAX
+ 1];
840 const char delimiter
[3] = {' ', '\n', '\0'};
845 bytes
= min(count
, sizeof(buf_cpy
) - 1);
846 memcpy(buf_cpy
, buf
, bytes
);
847 buf_cpy
[bytes
] = '\0';
850 sub_str
= strsep(&tmp
, delimiter
);
851 if (strlen(sub_str
)) {
852 ret
= kstrtol(sub_str
, 0, &level
);
863 static ssize_t
amdgpu_set_pp_dpm_sclk(struct device
*dev
,
864 struct device_attribute
*attr
,
868 struct drm_device
*ddev
= dev_get_drvdata(dev
);
869 struct amdgpu_device
*adev
= ddev
->dev_private
;
873 ret
= amdgpu_read_mask(buf
, count
, &mask
);
877 if (is_support_sw_smu(adev
))
878 ret
= smu_force_clk_levels(&adev
->smu
, PP_SCLK
, mask
);
879 else if (adev
->powerplay
.pp_funcs
->force_clock_level
)
880 ret
= amdgpu_dpm_force_clock_level(adev
, PP_SCLK
, mask
);
888 static ssize_t
amdgpu_get_pp_dpm_mclk(struct device
*dev
,
889 struct device_attribute
*attr
,
892 struct drm_device
*ddev
= dev_get_drvdata(dev
);
893 struct amdgpu_device
*adev
= ddev
->dev_private
;
895 if (is_support_sw_smu(adev
))
896 return smu_print_clk_levels(&adev
->smu
, PP_MCLK
, buf
);
897 else if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
898 return amdgpu_dpm_print_clock_levels(adev
, PP_MCLK
, buf
);
900 return snprintf(buf
, PAGE_SIZE
, "\n");
903 static ssize_t
amdgpu_set_pp_dpm_mclk(struct device
*dev
,
904 struct device_attribute
*attr
,
908 struct drm_device
*ddev
= dev_get_drvdata(dev
);
909 struct amdgpu_device
*adev
= ddev
->dev_private
;
913 ret
= amdgpu_read_mask(buf
, count
, &mask
);
917 if (is_support_sw_smu(adev
))
918 ret
= smu_force_clk_levels(&adev
->smu
, PP_MCLK
, mask
);
919 else if (adev
->powerplay
.pp_funcs
->force_clock_level
)
920 ret
= amdgpu_dpm_force_clock_level(adev
, PP_MCLK
, mask
);
928 static ssize_t
amdgpu_get_pp_dpm_socclk(struct device
*dev
,
929 struct device_attribute
*attr
,
932 struct drm_device
*ddev
= dev_get_drvdata(dev
);
933 struct amdgpu_device
*adev
= ddev
->dev_private
;
935 if (is_support_sw_smu(adev
))
936 return smu_print_clk_levels(&adev
->smu
, PP_SOCCLK
, buf
);
937 else if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
938 return amdgpu_dpm_print_clock_levels(adev
, PP_SOCCLK
, buf
);
940 return snprintf(buf
, PAGE_SIZE
, "\n");
943 static ssize_t
amdgpu_set_pp_dpm_socclk(struct device
*dev
,
944 struct device_attribute
*attr
,
948 struct drm_device
*ddev
= dev_get_drvdata(dev
);
949 struct amdgpu_device
*adev
= ddev
->dev_private
;
953 ret
= amdgpu_read_mask(buf
, count
, &mask
);
957 if (is_support_sw_smu(adev
))
958 ret
= smu_force_clk_levels(&adev
->smu
, PP_SOCCLK
, mask
);
959 else if (adev
->powerplay
.pp_funcs
->force_clock_level
)
960 ret
= amdgpu_dpm_force_clock_level(adev
, PP_SOCCLK
, mask
);
968 static ssize_t
amdgpu_get_pp_dpm_fclk(struct device
*dev
,
969 struct device_attribute
*attr
,
972 struct drm_device
*ddev
= dev_get_drvdata(dev
);
973 struct amdgpu_device
*adev
= ddev
->dev_private
;
975 if (is_support_sw_smu(adev
))
976 return smu_print_clk_levels(&adev
->smu
, PP_FCLK
, buf
);
977 else if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
978 return amdgpu_dpm_print_clock_levels(adev
, PP_FCLK
, buf
);
980 return snprintf(buf
, PAGE_SIZE
, "\n");
983 static ssize_t
amdgpu_set_pp_dpm_fclk(struct device
*dev
,
984 struct device_attribute
*attr
,
988 struct drm_device
*ddev
= dev_get_drvdata(dev
);
989 struct amdgpu_device
*adev
= ddev
->dev_private
;
993 ret
= amdgpu_read_mask(buf
, count
, &mask
);
997 if (is_support_sw_smu(adev
))
998 ret
= smu_force_clk_levels(&adev
->smu
, PP_FCLK
, mask
);
999 else if (adev
->powerplay
.pp_funcs
->force_clock_level
)
1000 ret
= amdgpu_dpm_force_clock_level(adev
, PP_FCLK
, mask
);
1008 static ssize_t
amdgpu_get_pp_dpm_dcefclk(struct device
*dev
,
1009 struct device_attribute
*attr
,
1012 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1013 struct amdgpu_device
*adev
= ddev
->dev_private
;
1015 if (is_support_sw_smu(adev
))
1016 return smu_print_clk_levels(&adev
->smu
, PP_DCEFCLK
, buf
);
1017 else if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
1018 return amdgpu_dpm_print_clock_levels(adev
, PP_DCEFCLK
, buf
);
1020 return snprintf(buf
, PAGE_SIZE
, "\n");
1023 static ssize_t
amdgpu_set_pp_dpm_dcefclk(struct device
*dev
,
1024 struct device_attribute
*attr
,
1028 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1029 struct amdgpu_device
*adev
= ddev
->dev_private
;
1033 ret
= amdgpu_read_mask(buf
, count
, &mask
);
1037 if (is_support_sw_smu(adev
))
1038 ret
= smu_force_clk_levels(&adev
->smu
, PP_DCEFCLK
, mask
);
1039 else if (adev
->powerplay
.pp_funcs
->force_clock_level
)
1040 ret
= amdgpu_dpm_force_clock_level(adev
, PP_DCEFCLK
, mask
);
1048 static ssize_t
amdgpu_get_pp_dpm_pcie(struct device
*dev
,
1049 struct device_attribute
*attr
,
1052 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1053 struct amdgpu_device
*adev
= ddev
->dev_private
;
1055 if (is_support_sw_smu(adev
))
1056 return smu_print_clk_levels(&adev
->smu
, PP_PCIE
, buf
);
1057 else if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
1058 return amdgpu_dpm_print_clock_levels(adev
, PP_PCIE
, buf
);
1060 return snprintf(buf
, PAGE_SIZE
, "\n");
1063 static ssize_t
amdgpu_set_pp_dpm_pcie(struct device
*dev
,
1064 struct device_attribute
*attr
,
1068 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1069 struct amdgpu_device
*adev
= ddev
->dev_private
;
1073 ret
= amdgpu_read_mask(buf
, count
, &mask
);
1077 if (is_support_sw_smu(adev
))
1078 ret
= smu_force_clk_levels(&adev
->smu
, PP_PCIE
, mask
);
1079 else if (adev
->powerplay
.pp_funcs
->force_clock_level
)
1080 ret
= amdgpu_dpm_force_clock_level(adev
, PP_PCIE
, mask
);
1088 static ssize_t
amdgpu_get_pp_sclk_od(struct device
*dev
,
1089 struct device_attribute
*attr
,
1092 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1093 struct amdgpu_device
*adev
= ddev
->dev_private
;
1096 if (is_support_sw_smu(adev
))
1097 value
= smu_get_od_percentage(&(adev
->smu
), OD_SCLK
);
1098 else if (adev
->powerplay
.pp_funcs
->get_sclk_od
)
1099 value
= amdgpu_dpm_get_sclk_od(adev
);
1101 return snprintf(buf
, PAGE_SIZE
, "%d\n", value
);
1104 static ssize_t
amdgpu_set_pp_sclk_od(struct device
*dev
,
1105 struct device_attribute
*attr
,
1109 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1110 struct amdgpu_device
*adev
= ddev
->dev_private
;
1114 ret
= kstrtol(buf
, 0, &value
);
1121 if (is_support_sw_smu(adev
)) {
1122 value
= smu_set_od_percentage(&(adev
->smu
), OD_SCLK
, (uint32_t)value
);
1124 if (adev
->powerplay
.pp_funcs
->set_sclk_od
)
1125 amdgpu_dpm_set_sclk_od(adev
, (uint32_t)value
);
1127 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
1128 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_READJUST_POWER_STATE
, NULL
);
1130 adev
->pm
.dpm
.current_ps
= adev
->pm
.dpm
.boot_ps
;
1131 amdgpu_pm_compute_clocks(adev
);
1139 static ssize_t
amdgpu_get_pp_mclk_od(struct device
*dev
,
1140 struct device_attribute
*attr
,
1143 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1144 struct amdgpu_device
*adev
= ddev
->dev_private
;
1147 if (is_support_sw_smu(adev
))
1148 value
= smu_get_od_percentage(&(adev
->smu
), OD_MCLK
);
1149 else if (adev
->powerplay
.pp_funcs
->get_mclk_od
)
1150 value
= amdgpu_dpm_get_mclk_od(adev
);
1152 return snprintf(buf
, PAGE_SIZE
, "%d\n", value
);
1155 static ssize_t
amdgpu_set_pp_mclk_od(struct device
*dev
,
1156 struct device_attribute
*attr
,
1160 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1161 struct amdgpu_device
*adev
= ddev
->dev_private
;
1165 ret
= kstrtol(buf
, 0, &value
);
1172 if (is_support_sw_smu(adev
)) {
1173 value
= smu_set_od_percentage(&(adev
->smu
), OD_MCLK
, (uint32_t)value
);
1175 if (adev
->powerplay
.pp_funcs
->set_mclk_od
)
1176 amdgpu_dpm_set_mclk_od(adev
, (uint32_t)value
);
1178 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
1179 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_READJUST_POWER_STATE
, NULL
);
1181 adev
->pm
.dpm
.current_ps
= adev
->pm
.dpm
.boot_ps
;
1182 amdgpu_pm_compute_clocks(adev
);
1191 * DOC: pp_power_profile_mode
1193 * The amdgpu driver provides a sysfs API for adjusting the heuristics
1194 * related to switching between power levels in a power state. The file
1195 * pp_power_profile_mode is used for this.
1197 * Reading this file outputs a list of all of the predefined power profiles
1198 * and the relevant heuristics settings for that profile.
1200 * To select a profile or create a custom profile, first select manual using
1201 * power_dpm_force_performance_level. Writing the number of a predefined
1202 * profile to pp_power_profile_mode will enable those heuristics. To
1203 * create a custom set of heuristics, write a string of numbers to the file
1204 * starting with the number of the custom profile along with a setting
1205 * for each heuristic parameter. Due to differences across asic families
1206 * the heuristic parameters vary from family to family.
1210 static ssize_t
amdgpu_get_pp_power_profile_mode(struct device
*dev
,
1211 struct device_attribute
*attr
,
1214 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1215 struct amdgpu_device
*adev
= ddev
->dev_private
;
1217 if (is_support_sw_smu(adev
))
1218 return smu_get_power_profile_mode(&adev
->smu
, buf
);
1219 else if (adev
->powerplay
.pp_funcs
->get_power_profile_mode
)
1220 return amdgpu_dpm_get_power_profile_mode(adev
, buf
);
1222 return snprintf(buf
, PAGE_SIZE
, "\n");
1226 static ssize_t
amdgpu_set_pp_power_profile_mode(struct device
*dev
,
1227 struct device_attribute
*attr
,
1232 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1233 struct amdgpu_device
*adev
= ddev
->dev_private
;
1234 uint32_t parameter_size
= 0;
1236 char *sub_str
, buf_cpy
[128];
1240 long int profile_mode
= 0;
1241 const char delimiter
[3] = {' ', '\n', '\0'};
1245 ret
= kstrtol(tmp
, 0, &profile_mode
);
1249 if (profile_mode
== PP_SMC_POWER_PROFILE_CUSTOM
) {
1250 if (count
< 2 || count
> 127)
1252 while (isspace(*++buf
))
1254 memcpy(buf_cpy
, buf
, count
-i
);
1256 while (tmp_str
[0]) {
1257 sub_str
= strsep(&tmp_str
, delimiter
);
1258 ret
= kstrtol(sub_str
, 0, ¶meter
[parameter_size
]);
1264 while (isspace(*tmp_str
))
1268 parameter
[parameter_size
] = profile_mode
;
1269 if (is_support_sw_smu(adev
))
1270 ret
= smu_set_power_profile_mode(&adev
->smu
, parameter
, parameter_size
);
1271 else if (adev
->powerplay
.pp_funcs
->set_power_profile_mode
)
1272 ret
= amdgpu_dpm_set_power_profile_mode(adev
, parameter
, parameter_size
);
1282 * The amdgpu driver provides a sysfs API for reading how busy the GPU
1283 * is as a percentage. The file gpu_busy_percent is used for this.
1284 * The SMU firmware computes a percentage of load based on the
1285 * aggregate activity level in the IP cores.
1287 static ssize_t
amdgpu_get_busy_percent(struct device
*dev
,
1288 struct device_attribute
*attr
,
1291 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1292 struct amdgpu_device
*adev
= ddev
->dev_private
;
1293 int r
, value
, size
= sizeof(value
);
1295 /* read the IP busy sensor */
1296 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_LOAD
,
1297 (void *)&value
, &size
);
1302 return snprintf(buf
, PAGE_SIZE
, "%d\n", value
);
1308 * The amdgpu driver provides a sysfs API for estimating how much data
1309 * has been received and sent by the GPU in the last second through PCIe.
1310 * The file pcie_bw is used for this.
1311 * The Perf counters count the number of received and sent messages and return
1312 * those values, as well as the maximum payload size of a PCIe packet (mps).
1313 * Note that it is not possible to easily and quickly obtain the size of each
1314 * packet transmitted, so we output the max payload size (mps) to allow for
1315 * quick estimation of the PCIe bandwidth usage
1317 static ssize_t
amdgpu_get_pcie_bw(struct device
*dev
,
1318 struct device_attribute
*attr
,
1321 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1322 struct amdgpu_device
*adev
= ddev
->dev_private
;
1323 uint64_t count0
, count1
;
1325 amdgpu_asic_get_pcie_usage(adev
, &count0
, &count1
);
1326 return snprintf(buf
, PAGE_SIZE
, "%llu %llu %i\n",
1327 count0
, count1
, pcie_get_mps(adev
->pdev
));
1330 static DEVICE_ATTR(power_dpm_state
, S_IRUGO
| S_IWUSR
, amdgpu_get_dpm_state
, amdgpu_set_dpm_state
);
1331 static DEVICE_ATTR(power_dpm_force_performance_level
, S_IRUGO
| S_IWUSR
,
1332 amdgpu_get_dpm_forced_performance_level
,
1333 amdgpu_set_dpm_forced_performance_level
);
1334 static DEVICE_ATTR(pp_num_states
, S_IRUGO
, amdgpu_get_pp_num_states
, NULL
);
1335 static DEVICE_ATTR(pp_cur_state
, S_IRUGO
, amdgpu_get_pp_cur_state
, NULL
);
1336 static DEVICE_ATTR(pp_force_state
, S_IRUGO
| S_IWUSR
,
1337 amdgpu_get_pp_force_state
,
1338 amdgpu_set_pp_force_state
);
1339 static DEVICE_ATTR(pp_table
, S_IRUGO
| S_IWUSR
,
1340 amdgpu_get_pp_table
,
1341 amdgpu_set_pp_table
);
1342 static DEVICE_ATTR(pp_dpm_sclk
, S_IRUGO
| S_IWUSR
,
1343 amdgpu_get_pp_dpm_sclk
,
1344 amdgpu_set_pp_dpm_sclk
);
1345 static DEVICE_ATTR(pp_dpm_mclk
, S_IRUGO
| S_IWUSR
,
1346 amdgpu_get_pp_dpm_mclk
,
1347 amdgpu_set_pp_dpm_mclk
);
1348 static DEVICE_ATTR(pp_dpm_socclk
, S_IRUGO
| S_IWUSR
,
1349 amdgpu_get_pp_dpm_socclk
,
1350 amdgpu_set_pp_dpm_socclk
);
1351 static DEVICE_ATTR(pp_dpm_fclk
, S_IRUGO
| S_IWUSR
,
1352 amdgpu_get_pp_dpm_fclk
,
1353 amdgpu_set_pp_dpm_fclk
);
1354 static DEVICE_ATTR(pp_dpm_dcefclk
, S_IRUGO
| S_IWUSR
,
1355 amdgpu_get_pp_dpm_dcefclk
,
1356 amdgpu_set_pp_dpm_dcefclk
);
1357 static DEVICE_ATTR(pp_dpm_pcie
, S_IRUGO
| S_IWUSR
,
1358 amdgpu_get_pp_dpm_pcie
,
1359 amdgpu_set_pp_dpm_pcie
);
1360 static DEVICE_ATTR(pp_sclk_od
, S_IRUGO
| S_IWUSR
,
1361 amdgpu_get_pp_sclk_od
,
1362 amdgpu_set_pp_sclk_od
);
1363 static DEVICE_ATTR(pp_mclk_od
, S_IRUGO
| S_IWUSR
,
1364 amdgpu_get_pp_mclk_od
,
1365 amdgpu_set_pp_mclk_od
);
1366 static DEVICE_ATTR(pp_power_profile_mode
, S_IRUGO
| S_IWUSR
,
1367 amdgpu_get_pp_power_profile_mode
,
1368 amdgpu_set_pp_power_profile_mode
);
1369 static DEVICE_ATTR(pp_od_clk_voltage
, S_IRUGO
| S_IWUSR
,
1370 amdgpu_get_pp_od_clk_voltage
,
1371 amdgpu_set_pp_od_clk_voltage
);
1372 static DEVICE_ATTR(gpu_busy_percent
, S_IRUGO
,
1373 amdgpu_get_busy_percent
, NULL
);
1374 static DEVICE_ATTR(pcie_bw
, S_IRUGO
, amdgpu_get_pcie_bw
, NULL
);
1375 static DEVICE_ATTR(ppfeatures
, S_IRUGO
| S_IWUSR
,
1376 amdgpu_get_ppfeature_status
,
1377 amdgpu_set_ppfeature_status
);
1379 static ssize_t
amdgpu_hwmon_show_temp(struct device
*dev
,
1380 struct device_attribute
*attr
,
1383 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1384 struct drm_device
*ddev
= adev
->ddev
;
1385 int r
, temp
, size
= sizeof(temp
);
1387 /* Can't get temperature when the card is off */
1388 if ((adev
->flags
& AMD_IS_PX
) &&
1389 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1392 /* get the temperature */
1393 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_TEMP
,
1394 (void *)&temp
, &size
);
1398 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
1401 static ssize_t
amdgpu_hwmon_show_temp_thresh(struct device
*dev
,
1402 struct device_attribute
*attr
,
1405 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1406 int hyst
= to_sensor_dev_attr(attr
)->index
;
1410 temp
= adev
->pm
.dpm
.thermal
.min_temp
;
1412 temp
= adev
->pm
.dpm
.thermal
.max_temp
;
1414 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
1417 static ssize_t
amdgpu_hwmon_get_pwm1_enable(struct device
*dev
,
1418 struct device_attribute
*attr
,
1421 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1423 if (is_support_sw_smu(adev
)) {
1424 pwm_mode
= smu_get_fan_control_mode(&adev
->smu
);
1426 if (!adev
->powerplay
.pp_funcs
->get_fan_control_mode
)
1429 pwm_mode
= amdgpu_dpm_get_fan_control_mode(adev
);
1432 return sprintf(buf
, "%i\n", pwm_mode
);
1435 static ssize_t
amdgpu_hwmon_set_pwm1_enable(struct device
*dev
,
1436 struct device_attribute
*attr
,
1440 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1444 /* Can't adjust fan when the card is off */
1445 if ((adev
->flags
& AMD_IS_PX
) &&
1446 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1449 if (is_support_sw_smu(adev
)) {
1450 err
= kstrtoint(buf
, 10, &value
);
1454 smu_set_fan_control_mode(&adev
->smu
, value
);
1456 if (!adev
->powerplay
.pp_funcs
->set_fan_control_mode
)
1459 err
= kstrtoint(buf
, 10, &value
);
1463 amdgpu_dpm_set_fan_control_mode(adev
, value
);
1469 static ssize_t
amdgpu_hwmon_get_pwm1_min(struct device
*dev
,
1470 struct device_attribute
*attr
,
1473 return sprintf(buf
, "%i\n", 0);
1476 static ssize_t
amdgpu_hwmon_get_pwm1_max(struct device
*dev
,
1477 struct device_attribute
*attr
,
1480 return sprintf(buf
, "%i\n", 255);
1483 static ssize_t
amdgpu_hwmon_set_pwm1(struct device
*dev
,
1484 struct device_attribute
*attr
,
1485 const char *buf
, size_t count
)
1487 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1492 /* Can't adjust fan when the card is off */
1493 if ((adev
->flags
& AMD_IS_PX
) &&
1494 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1496 if (is_support_sw_smu(adev
))
1497 pwm_mode
= smu_get_fan_control_mode(&adev
->smu
);
1499 pwm_mode
= amdgpu_dpm_get_fan_control_mode(adev
);
1500 if (pwm_mode
!= AMD_FAN_CTRL_MANUAL
) {
1501 pr_info("manual fan speed control should be enabled first\n");
1505 err
= kstrtou32(buf
, 10, &value
);
1509 value
= (value
* 100) / 255;
1511 if (is_support_sw_smu(adev
)) {
1512 err
= smu_set_fan_speed_percent(&adev
->smu
, value
);
1515 } else if (adev
->powerplay
.pp_funcs
->set_fan_speed_percent
) {
1516 err
= amdgpu_dpm_set_fan_speed_percent(adev
, value
);
1524 static ssize_t
amdgpu_hwmon_get_pwm1(struct device
*dev
,
1525 struct device_attribute
*attr
,
1528 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1532 /* Can't adjust fan when the card is off */
1533 if ((adev
->flags
& AMD_IS_PX
) &&
1534 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1537 if (is_support_sw_smu(adev
)) {
1538 err
= smu_get_fan_speed_percent(&adev
->smu
, &speed
);
1541 } else if (adev
->powerplay
.pp_funcs
->get_fan_speed_percent
) {
1542 err
= amdgpu_dpm_get_fan_speed_percent(adev
, &speed
);
1547 speed
= (speed
* 255) / 100;
1549 return sprintf(buf
, "%i\n", speed
);
1552 static ssize_t
amdgpu_hwmon_get_fan1_input(struct device
*dev
,
1553 struct device_attribute
*attr
,
1556 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1560 /* Can't adjust fan when the card is off */
1561 if ((adev
->flags
& AMD_IS_PX
) &&
1562 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1565 if (is_support_sw_smu(adev
)) {
1566 err
= smu_get_current_rpm(&adev
->smu
, &speed
);
1569 } else if (adev
->powerplay
.pp_funcs
->get_fan_speed_rpm
) {
1570 err
= amdgpu_dpm_get_fan_speed_rpm(adev
, &speed
);
1575 return sprintf(buf
, "%i\n", speed
);
1578 static ssize_t
amdgpu_hwmon_get_fan1_min(struct device
*dev
,
1579 struct device_attribute
*attr
,
1582 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1584 u32 size
= sizeof(min_rpm
);
1587 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_MIN_FAN_RPM
,
1588 (void *)&min_rpm
, &size
);
1592 return snprintf(buf
, PAGE_SIZE
, "%d\n", min_rpm
);
1595 static ssize_t
amdgpu_hwmon_get_fan1_max(struct device
*dev
,
1596 struct device_attribute
*attr
,
1599 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1601 u32 size
= sizeof(max_rpm
);
1604 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_MAX_FAN_RPM
,
1605 (void *)&max_rpm
, &size
);
1609 return snprintf(buf
, PAGE_SIZE
, "%d\n", max_rpm
);
1612 static ssize_t
amdgpu_hwmon_get_fan1_target(struct device
*dev
,
1613 struct device_attribute
*attr
,
1616 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1620 /* Can't adjust fan when the card is off */
1621 if ((adev
->flags
& AMD_IS_PX
) &&
1622 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1625 if (is_support_sw_smu(adev
)) {
1626 err
= smu_get_current_rpm(&adev
->smu
, &rpm
);
1629 } else if (adev
->powerplay
.pp_funcs
->get_fan_speed_rpm
) {
1630 err
= amdgpu_dpm_get_fan_speed_rpm(adev
, &rpm
);
1635 return sprintf(buf
, "%i\n", rpm
);
1638 static ssize_t
amdgpu_hwmon_set_fan1_target(struct device
*dev
,
1639 struct device_attribute
*attr
,
1640 const char *buf
, size_t count
)
1642 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1647 if (is_support_sw_smu(adev
))
1648 pwm_mode
= smu_get_fan_control_mode(&adev
->smu
);
1650 pwm_mode
= amdgpu_dpm_get_fan_control_mode(adev
);
1652 if (pwm_mode
!= AMD_FAN_CTRL_MANUAL
)
1655 /* Can't adjust fan when the card is off */
1656 if ((adev
->flags
& AMD_IS_PX
) &&
1657 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1660 err
= kstrtou32(buf
, 10, &value
);
1664 if (is_support_sw_smu(adev
)) {
1665 err
= smu_set_fan_speed_rpm(&adev
->smu
, value
);
1668 } else if (adev
->powerplay
.pp_funcs
->set_fan_speed_rpm
) {
1669 err
= amdgpu_dpm_set_fan_speed_rpm(adev
, value
);
1677 static ssize_t
amdgpu_hwmon_get_fan1_enable(struct device
*dev
,
1678 struct device_attribute
*attr
,
1681 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1684 if (is_support_sw_smu(adev
)) {
1685 pwm_mode
= smu_get_fan_control_mode(&adev
->smu
);
1687 if (!adev
->powerplay
.pp_funcs
->get_fan_control_mode
)
1690 pwm_mode
= amdgpu_dpm_get_fan_control_mode(adev
);
1692 return sprintf(buf
, "%i\n", pwm_mode
== AMD_FAN_CTRL_AUTO
? 0 : 1);
1695 static ssize_t
amdgpu_hwmon_set_fan1_enable(struct device
*dev
,
1696 struct device_attribute
*attr
,
1700 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1705 /* Can't adjust fan when the card is off */
1706 if ((adev
->flags
& AMD_IS_PX
) &&
1707 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1711 err
= kstrtoint(buf
, 10, &value
);
1716 pwm_mode
= AMD_FAN_CTRL_AUTO
;
1717 else if (value
== 1)
1718 pwm_mode
= AMD_FAN_CTRL_MANUAL
;
1722 if (is_support_sw_smu(adev
)) {
1723 smu_set_fan_control_mode(&adev
->smu
, pwm_mode
);
1725 if (!adev
->powerplay
.pp_funcs
->set_fan_control_mode
)
1727 amdgpu_dpm_set_fan_control_mode(adev
, pwm_mode
);
1733 static ssize_t
amdgpu_hwmon_show_vddgfx(struct device
*dev
,
1734 struct device_attribute
*attr
,
1737 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1738 struct drm_device
*ddev
= adev
->ddev
;
1740 int r
, size
= sizeof(vddgfx
);
1742 /* Can't get voltage when the card is off */
1743 if ((adev
->flags
& AMD_IS_PX
) &&
1744 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1747 /* get the voltage */
1748 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDGFX
,
1749 (void *)&vddgfx
, &size
);
1753 return snprintf(buf
, PAGE_SIZE
, "%d\n", vddgfx
);
1756 static ssize_t
amdgpu_hwmon_show_vddgfx_label(struct device
*dev
,
1757 struct device_attribute
*attr
,
1760 return snprintf(buf
, PAGE_SIZE
, "vddgfx\n");
1763 static ssize_t
amdgpu_hwmon_show_vddnb(struct device
*dev
,
1764 struct device_attribute
*attr
,
1767 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1768 struct drm_device
*ddev
= adev
->ddev
;
1770 int r
, size
= sizeof(vddnb
);
1772 /* only APUs have vddnb */
1773 if (!(adev
->flags
& AMD_IS_APU
))
1776 /* Can't get voltage when the card is off */
1777 if ((adev
->flags
& AMD_IS_PX
) &&
1778 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1781 /* get the voltage */
1782 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDNB
,
1783 (void *)&vddnb
, &size
);
1787 return snprintf(buf
, PAGE_SIZE
, "%d\n", vddnb
);
1790 static ssize_t
amdgpu_hwmon_show_vddnb_label(struct device
*dev
,
1791 struct device_attribute
*attr
,
1794 return snprintf(buf
, PAGE_SIZE
, "vddnb\n");
1797 static ssize_t
amdgpu_hwmon_show_power_avg(struct device
*dev
,
1798 struct device_attribute
*attr
,
1801 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1802 struct drm_device
*ddev
= adev
->ddev
;
1804 int r
, size
= sizeof(u32
);
1807 /* Can't get power when the card is off */
1808 if ((adev
->flags
& AMD_IS_PX
) &&
1809 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1812 /* get the voltage */
1813 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_POWER
,
1814 (void *)&query
, &size
);
1818 /* convert to microwatts */
1819 uw
= (query
>> 8) * 1000000 + (query
& 0xff) * 1000;
1821 return snprintf(buf
, PAGE_SIZE
, "%u\n", uw
);
1824 static ssize_t
amdgpu_hwmon_show_power_cap_min(struct device
*dev
,
1825 struct device_attribute
*attr
,
1828 return sprintf(buf
, "%i\n", 0);
1831 static ssize_t
amdgpu_hwmon_show_power_cap_max(struct device
*dev
,
1832 struct device_attribute
*attr
,
1835 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1838 if (is_support_sw_smu(adev
)) {
1839 smu_get_power_limit(&adev
->smu
, &limit
, true);
1840 return snprintf(buf
, PAGE_SIZE
, "%u\n", limit
* 1000000);
1841 } else if (adev
->powerplay
.pp_funcs
&& adev
->powerplay
.pp_funcs
->get_power_limit
) {
1842 adev
->powerplay
.pp_funcs
->get_power_limit(adev
->powerplay
.pp_handle
, &limit
, true);
1843 return snprintf(buf
, PAGE_SIZE
, "%u\n", limit
* 1000000);
1845 return snprintf(buf
, PAGE_SIZE
, "\n");
1849 static ssize_t
amdgpu_hwmon_show_power_cap(struct device
*dev
,
1850 struct device_attribute
*attr
,
1853 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1856 if (is_support_sw_smu(adev
)) {
1857 smu_get_power_limit(&adev
->smu
, &limit
, false);
1858 return snprintf(buf
, PAGE_SIZE
, "%u\n", limit
* 1000000);
1859 } else if (adev
->powerplay
.pp_funcs
&& adev
->powerplay
.pp_funcs
->get_power_limit
) {
1860 adev
->powerplay
.pp_funcs
->get_power_limit(adev
->powerplay
.pp_handle
, &limit
, false);
1861 return snprintf(buf
, PAGE_SIZE
, "%u\n", limit
* 1000000);
1863 return snprintf(buf
, PAGE_SIZE
, "\n");
1868 static ssize_t
amdgpu_hwmon_set_power_cap(struct device
*dev
,
1869 struct device_attribute
*attr
,
1873 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1877 err
= kstrtou32(buf
, 10, &value
);
1881 value
= value
/ 1000000; /* convert to Watt */
1882 if (is_support_sw_smu(adev
)) {
1883 adev
->smu
.funcs
->set_power_limit(&adev
->smu
, value
);
1884 } else if (adev
->powerplay
.pp_funcs
&& adev
->powerplay
.pp_funcs
->set_power_limit
) {
1885 err
= adev
->powerplay
.pp_funcs
->set_power_limit(adev
->powerplay
.pp_handle
, value
);
1895 static ssize_t
amdgpu_hwmon_show_sclk(struct device
*dev
,
1896 struct device_attribute
*attr
,
1899 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1900 struct drm_device
*ddev
= adev
->ddev
;
1902 int r
, size
= sizeof(sclk
);
1904 /* Can't get voltage when the card is off */
1905 if ((adev
->flags
& AMD_IS_PX
) &&
1906 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1909 /* sanity check PP is enabled */
1910 if (!(adev
->powerplay
.pp_funcs
&&
1911 adev
->powerplay
.pp_funcs
->read_sensor
))
1915 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GFX_SCLK
,
1916 (void *)&sclk
, &size
);
1920 return snprintf(buf
, PAGE_SIZE
, "%d\n", sclk
* 10 * 1000);
1923 static ssize_t
amdgpu_hwmon_show_sclk_label(struct device
*dev
,
1924 struct device_attribute
*attr
,
1927 return snprintf(buf
, PAGE_SIZE
, "sclk\n");
1930 static ssize_t
amdgpu_hwmon_show_mclk(struct device
*dev
,
1931 struct device_attribute
*attr
,
1934 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1935 struct drm_device
*ddev
= adev
->ddev
;
1937 int r
, size
= sizeof(mclk
);
1939 /* Can't get voltage when the card is off */
1940 if ((adev
->flags
& AMD_IS_PX
) &&
1941 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1944 /* sanity check PP is enabled */
1945 if (!(adev
->powerplay
.pp_funcs
&&
1946 adev
->powerplay
.pp_funcs
->read_sensor
))
1950 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GFX_MCLK
,
1951 (void *)&mclk
, &size
);
1955 return snprintf(buf
, PAGE_SIZE
, "%d\n", mclk
* 10 * 1000);
1958 static ssize_t
amdgpu_hwmon_show_mclk_label(struct device
*dev
,
1959 struct device_attribute
*attr
,
1962 return snprintf(buf
, PAGE_SIZE
, "mclk\n");
1968 * The amdgpu driver exposes the following sensor interfaces:
1970 * - GPU temperature (via the on-die sensor)
1974 * - Northbridge voltage (APUs only)
1980 * - GPU gfx/compute engine clock
1982 * - GPU memory clock (dGPU only)
1984 * hwmon interfaces for GPU temperature:
1986 * - temp1_input: the on die GPU temperature in millidegrees Celsius
1988 * - temp1_crit: temperature critical max value in millidegrees Celsius
1990 * - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
1992 * hwmon interfaces for GPU voltage:
1994 * - in0_input: the voltage on the GPU in millivolts
1996 * - in1_input: the voltage on the Northbridge in millivolts
1998 * hwmon interfaces for GPU power:
2000 * - power1_average: average power used by the GPU in microWatts
2002 * - power1_cap_min: minimum cap supported in microWatts
2004 * - power1_cap_max: maximum cap supported in microWatts
2006 * - power1_cap: selected power cap in microWatts
2008 * hwmon interfaces for GPU fan:
2010 * - pwm1: pulse width modulation fan level (0-255)
2012 * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
2014 * - pwm1_min: pulse width modulation fan control minimum level (0)
2016 * - pwm1_max: pulse width modulation fan control maximum level (255)
2018 * - fan1_min: an minimum value Unit: revolution/min (RPM)
2020 * - fan1_max: an maxmum value Unit: revolution/max (RPM)
2022 * - fan1_input: fan speed in RPM
2024 * - fan[1-*]_target: Desired fan speed Unit: revolution/min (RPM)
2026 * - fan[1-*]_enable: Enable or disable the sensors.1: Enable 0: Disable
2028 * hwmon interfaces for GPU clocks:
2030 * - freq1_input: the gfx/compute clock in hertz
2032 * - freq2_input: the memory clock in hertz
2034 * You can use hwmon tools like sensors to view this information on your system.
2038 static SENSOR_DEVICE_ATTR(temp1_input
, S_IRUGO
, amdgpu_hwmon_show_temp
, NULL
, 0);
2039 static SENSOR_DEVICE_ATTR(temp1_crit
, S_IRUGO
, amdgpu_hwmon_show_temp_thresh
, NULL
, 0);
2040 static SENSOR_DEVICE_ATTR(temp1_crit_hyst
, S_IRUGO
, amdgpu_hwmon_show_temp_thresh
, NULL
, 1);
2041 static SENSOR_DEVICE_ATTR(pwm1
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_get_pwm1
, amdgpu_hwmon_set_pwm1
, 0);
2042 static SENSOR_DEVICE_ATTR(pwm1_enable
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_get_pwm1_enable
, amdgpu_hwmon_set_pwm1_enable
, 0);
2043 static SENSOR_DEVICE_ATTR(pwm1_min
, S_IRUGO
, amdgpu_hwmon_get_pwm1_min
, NULL
, 0);
2044 static SENSOR_DEVICE_ATTR(pwm1_max
, S_IRUGO
, amdgpu_hwmon_get_pwm1_max
, NULL
, 0);
2045 static SENSOR_DEVICE_ATTR(fan1_input
, S_IRUGO
, amdgpu_hwmon_get_fan1_input
, NULL
, 0);
2046 static SENSOR_DEVICE_ATTR(fan1_min
, S_IRUGO
, amdgpu_hwmon_get_fan1_min
, NULL
, 0);
2047 static SENSOR_DEVICE_ATTR(fan1_max
, S_IRUGO
, amdgpu_hwmon_get_fan1_max
, NULL
, 0);
2048 static SENSOR_DEVICE_ATTR(fan1_target
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_get_fan1_target
, amdgpu_hwmon_set_fan1_target
, 0);
2049 static SENSOR_DEVICE_ATTR(fan1_enable
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_get_fan1_enable
, amdgpu_hwmon_set_fan1_enable
, 0);
2050 static SENSOR_DEVICE_ATTR(in0_input
, S_IRUGO
, amdgpu_hwmon_show_vddgfx
, NULL
, 0);
2051 static SENSOR_DEVICE_ATTR(in0_label
, S_IRUGO
, amdgpu_hwmon_show_vddgfx_label
, NULL
, 0);
2052 static SENSOR_DEVICE_ATTR(in1_input
, S_IRUGO
, amdgpu_hwmon_show_vddnb
, NULL
, 0);
2053 static SENSOR_DEVICE_ATTR(in1_label
, S_IRUGO
, amdgpu_hwmon_show_vddnb_label
, NULL
, 0);
2054 static SENSOR_DEVICE_ATTR(power1_average
, S_IRUGO
, amdgpu_hwmon_show_power_avg
, NULL
, 0);
2055 static SENSOR_DEVICE_ATTR(power1_cap_max
, S_IRUGO
, amdgpu_hwmon_show_power_cap_max
, NULL
, 0);
2056 static SENSOR_DEVICE_ATTR(power1_cap_min
, S_IRUGO
, amdgpu_hwmon_show_power_cap_min
, NULL
, 0);
2057 static SENSOR_DEVICE_ATTR(power1_cap
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_show_power_cap
, amdgpu_hwmon_set_power_cap
, 0);
2058 static SENSOR_DEVICE_ATTR(freq1_input
, S_IRUGO
, amdgpu_hwmon_show_sclk
, NULL
, 0);
2059 static SENSOR_DEVICE_ATTR(freq1_label
, S_IRUGO
, amdgpu_hwmon_show_sclk_label
, NULL
, 0);
2060 static SENSOR_DEVICE_ATTR(freq2_input
, S_IRUGO
, amdgpu_hwmon_show_mclk
, NULL
, 0);
2061 static SENSOR_DEVICE_ATTR(freq2_label
, S_IRUGO
, amdgpu_hwmon_show_mclk_label
, NULL
, 0);
2063 static struct attribute
*hwmon_attributes
[] = {
2064 &sensor_dev_attr_temp1_input
.dev_attr
.attr
,
2065 &sensor_dev_attr_temp1_crit
.dev_attr
.attr
,
2066 &sensor_dev_attr_temp1_crit_hyst
.dev_attr
.attr
,
2067 &sensor_dev_attr_pwm1
.dev_attr
.attr
,
2068 &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
,
2069 &sensor_dev_attr_pwm1_min
.dev_attr
.attr
,
2070 &sensor_dev_attr_pwm1_max
.dev_attr
.attr
,
2071 &sensor_dev_attr_fan1_input
.dev_attr
.attr
,
2072 &sensor_dev_attr_fan1_min
.dev_attr
.attr
,
2073 &sensor_dev_attr_fan1_max
.dev_attr
.attr
,
2074 &sensor_dev_attr_fan1_target
.dev_attr
.attr
,
2075 &sensor_dev_attr_fan1_enable
.dev_attr
.attr
,
2076 &sensor_dev_attr_in0_input
.dev_attr
.attr
,
2077 &sensor_dev_attr_in0_label
.dev_attr
.attr
,
2078 &sensor_dev_attr_in1_input
.dev_attr
.attr
,
2079 &sensor_dev_attr_in1_label
.dev_attr
.attr
,
2080 &sensor_dev_attr_power1_average
.dev_attr
.attr
,
2081 &sensor_dev_attr_power1_cap_max
.dev_attr
.attr
,
2082 &sensor_dev_attr_power1_cap_min
.dev_attr
.attr
,
2083 &sensor_dev_attr_power1_cap
.dev_attr
.attr
,
2084 &sensor_dev_attr_freq1_input
.dev_attr
.attr
,
2085 &sensor_dev_attr_freq1_label
.dev_attr
.attr
,
2086 &sensor_dev_attr_freq2_input
.dev_attr
.attr
,
2087 &sensor_dev_attr_freq2_label
.dev_attr
.attr
,
2091 static umode_t
hwmon_attributes_visible(struct kobject
*kobj
,
2092 struct attribute
*attr
, int index
)
2094 struct device
*dev
= kobj_to_dev(kobj
);
2095 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
2096 umode_t effective_mode
= attr
->mode
;
2098 /* Skip fan attributes if fan is not present */
2099 if (adev
->pm
.no_fan
&& (attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
||
2100 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
||
2101 attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
2102 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
||
2103 attr
== &sensor_dev_attr_fan1_input
.dev_attr
.attr
||
2104 attr
== &sensor_dev_attr_fan1_min
.dev_attr
.attr
||
2105 attr
== &sensor_dev_attr_fan1_max
.dev_attr
.attr
||
2106 attr
== &sensor_dev_attr_fan1_target
.dev_attr
.attr
||
2107 attr
== &sensor_dev_attr_fan1_enable
.dev_attr
.attr
))
2110 /* Skip fan attributes on APU */
2111 if ((adev
->flags
& AMD_IS_APU
) &&
2112 (attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
||
2113 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
||
2114 attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
2115 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
||
2116 attr
== &sensor_dev_attr_fan1_input
.dev_attr
.attr
||
2117 attr
== &sensor_dev_attr_fan1_min
.dev_attr
.attr
||
2118 attr
== &sensor_dev_attr_fan1_max
.dev_attr
.attr
||
2119 attr
== &sensor_dev_attr_fan1_target
.dev_attr
.attr
||
2120 attr
== &sensor_dev_attr_fan1_enable
.dev_attr
.attr
))
2123 /* Skip limit attributes if DPM is not enabled */
2124 if (!adev
->pm
.dpm_enabled
&&
2125 (attr
== &sensor_dev_attr_temp1_crit
.dev_attr
.attr
||
2126 attr
== &sensor_dev_attr_temp1_crit_hyst
.dev_attr
.attr
||
2127 attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
||
2128 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
||
2129 attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
2130 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
||
2131 attr
== &sensor_dev_attr_fan1_input
.dev_attr
.attr
||
2132 attr
== &sensor_dev_attr_fan1_min
.dev_attr
.attr
||
2133 attr
== &sensor_dev_attr_fan1_max
.dev_attr
.attr
||
2134 attr
== &sensor_dev_attr_fan1_target
.dev_attr
.attr
||
2135 attr
== &sensor_dev_attr_fan1_enable
.dev_attr
.attr
))
2138 if (!is_support_sw_smu(adev
)) {
2139 /* mask fan attributes if we have no bindings for this asic to expose */
2140 if ((!adev
->powerplay
.pp_funcs
->get_fan_speed_percent
&&
2141 attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
) || /* can't query fan */
2142 (!adev
->powerplay
.pp_funcs
->get_fan_control_mode
&&
2143 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
)) /* can't query state */
2144 effective_mode
&= ~S_IRUGO
;
2146 if ((!adev
->powerplay
.pp_funcs
->set_fan_speed_percent
&&
2147 attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
) || /* can't manage fan */
2148 (!adev
->powerplay
.pp_funcs
->set_fan_control_mode
&&
2149 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
)) /* can't manage state */
2150 effective_mode
&= ~S_IWUSR
;
2153 if ((adev
->flags
& AMD_IS_APU
) &&
2154 (attr
== &sensor_dev_attr_power1_average
.dev_attr
.attr
||
2155 attr
== &sensor_dev_attr_power1_cap_max
.dev_attr
.attr
||
2156 attr
== &sensor_dev_attr_power1_cap_min
.dev_attr
.attr
||
2157 attr
== &sensor_dev_attr_power1_cap
.dev_attr
.attr
))
2160 if (!is_support_sw_smu(adev
)) {
2161 /* hide max/min values if we can't both query and manage the fan */
2162 if ((!adev
->powerplay
.pp_funcs
->set_fan_speed_percent
&&
2163 !adev
->powerplay
.pp_funcs
->get_fan_speed_percent
) &&
2164 (!adev
->powerplay
.pp_funcs
->set_fan_speed_rpm
&&
2165 !adev
->powerplay
.pp_funcs
->get_fan_speed_rpm
) &&
2166 (attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
2167 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
))
2170 if ((!adev
->powerplay
.pp_funcs
->set_fan_speed_rpm
&&
2171 !adev
->powerplay
.pp_funcs
->get_fan_speed_rpm
) &&
2172 (attr
== &sensor_dev_attr_fan1_max
.dev_attr
.attr
||
2173 attr
== &sensor_dev_attr_fan1_min
.dev_attr
.attr
))
2177 /* only APUs have vddnb */
2178 if (!(adev
->flags
& AMD_IS_APU
) &&
2179 (attr
== &sensor_dev_attr_in1_input
.dev_attr
.attr
||
2180 attr
== &sensor_dev_attr_in1_label
.dev_attr
.attr
))
2183 /* no mclk on APUs */
2184 if ((adev
->flags
& AMD_IS_APU
) &&
2185 (attr
== &sensor_dev_attr_freq2_input
.dev_attr
.attr
||
2186 attr
== &sensor_dev_attr_freq2_label
.dev_attr
.attr
))
2189 return effective_mode
;
2192 static const struct attribute_group hwmon_attrgroup
= {
2193 .attrs
= hwmon_attributes
,
2194 .is_visible
= hwmon_attributes_visible
,
2197 static const struct attribute_group
*hwmon_groups
[] = {
2202 void amdgpu_dpm_thermal_work_handler(struct work_struct
*work
)
2204 struct amdgpu_device
*adev
=
2205 container_of(work
, struct amdgpu_device
,
2206 pm
.dpm
.thermal
.work
);
2207 /* switch to the thermal state */
2208 enum amd_pm_state_type dpm_state
= POWER_STATE_TYPE_INTERNAL_THERMAL
;
2209 int temp
, size
= sizeof(temp
);
2211 if (!adev
->pm
.dpm_enabled
)
2214 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_TEMP
,
2215 (void *)&temp
, &size
)) {
2216 if (temp
< adev
->pm
.dpm
.thermal
.min_temp
)
2217 /* switch back the user state */
2218 dpm_state
= adev
->pm
.dpm
.user_state
;
2220 if (adev
->pm
.dpm
.thermal
.high_to_low
)
2221 /* switch back the user state */
2222 dpm_state
= adev
->pm
.dpm
.user_state
;
2224 mutex_lock(&adev
->pm
.mutex
);
2225 if (dpm_state
== POWER_STATE_TYPE_INTERNAL_THERMAL
)
2226 adev
->pm
.dpm
.thermal_active
= true;
2228 adev
->pm
.dpm
.thermal_active
= false;
2229 adev
->pm
.dpm
.state
= dpm_state
;
2230 mutex_unlock(&adev
->pm
.mutex
);
2232 amdgpu_pm_compute_clocks(adev
);
2235 static struct amdgpu_ps
*amdgpu_dpm_pick_power_state(struct amdgpu_device
*adev
,
2236 enum amd_pm_state_type dpm_state
)
2239 struct amdgpu_ps
*ps
;
2241 bool single_display
= (adev
->pm
.dpm
.new_active_crtc_count
< 2) ?
2244 /* check if the vblank period is too short to adjust the mclk */
2245 if (single_display
&& adev
->powerplay
.pp_funcs
->vblank_too_short
) {
2246 if (amdgpu_dpm_vblank_too_short(adev
))
2247 single_display
= false;
2250 /* certain older asics have a separare 3D performance state,
2251 * so try that first if the user selected performance
2253 if (dpm_state
== POWER_STATE_TYPE_PERFORMANCE
)
2254 dpm_state
= POWER_STATE_TYPE_INTERNAL_3DPERF
;
2255 /* balanced states don't exist at the moment */
2256 if (dpm_state
== POWER_STATE_TYPE_BALANCED
)
2257 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
2260 /* Pick the best power state based on current conditions */
2261 for (i
= 0; i
< adev
->pm
.dpm
.num_ps
; i
++) {
2262 ps
= &adev
->pm
.dpm
.ps
[i
];
2263 ui_class
= ps
->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK
;
2264 switch (dpm_state
) {
2266 case POWER_STATE_TYPE_BATTERY
:
2267 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
) {
2268 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
2275 case POWER_STATE_TYPE_BALANCED
:
2276 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BALANCED
) {
2277 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
2284 case POWER_STATE_TYPE_PERFORMANCE
:
2285 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
) {
2286 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
2293 /* internal states */
2294 case POWER_STATE_TYPE_INTERNAL_UVD
:
2295 if (adev
->pm
.dpm
.uvd_ps
)
2296 return adev
->pm
.dpm
.uvd_ps
;
2299 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
2300 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE
)
2303 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
2304 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE
)
2307 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
2308 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE
)
2311 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
2312 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_MVC
)
2315 case POWER_STATE_TYPE_INTERNAL_BOOT
:
2316 return adev
->pm
.dpm
.boot_ps
;
2317 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
2318 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_THERMAL
)
2321 case POWER_STATE_TYPE_INTERNAL_ACPI
:
2322 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_ACPI
)
2325 case POWER_STATE_TYPE_INTERNAL_ULV
:
2326 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_ULV
)
2329 case POWER_STATE_TYPE_INTERNAL_3DPERF
:
2330 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE
)
2337 /* use a fallback state if we didn't match */
2338 switch (dpm_state
) {
2339 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
2340 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD_HD
;
2341 goto restart_search
;
2342 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
2343 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
2344 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
2345 if (adev
->pm
.dpm
.uvd_ps
) {
2346 return adev
->pm
.dpm
.uvd_ps
;
2348 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
2349 goto restart_search
;
2351 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
2352 dpm_state
= POWER_STATE_TYPE_INTERNAL_ACPI
;
2353 goto restart_search
;
2354 case POWER_STATE_TYPE_INTERNAL_ACPI
:
2355 dpm_state
= POWER_STATE_TYPE_BATTERY
;
2356 goto restart_search
;
2357 case POWER_STATE_TYPE_BATTERY
:
2358 case POWER_STATE_TYPE_BALANCED
:
2359 case POWER_STATE_TYPE_INTERNAL_3DPERF
:
2360 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
2361 goto restart_search
;
2369 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device
*adev
)
2371 struct amdgpu_ps
*ps
;
2372 enum amd_pm_state_type dpm_state
;
2376 /* if dpm init failed */
2377 if (!adev
->pm
.dpm_enabled
)
2380 if (adev
->pm
.dpm
.user_state
!= adev
->pm
.dpm
.state
) {
2381 /* add other state override checks here */
2382 if ((!adev
->pm
.dpm
.thermal_active
) &&
2383 (!adev
->pm
.dpm
.uvd_active
))
2384 adev
->pm
.dpm
.state
= adev
->pm
.dpm
.user_state
;
2386 dpm_state
= adev
->pm
.dpm
.state
;
2388 ps
= amdgpu_dpm_pick_power_state(adev
, dpm_state
);
2390 adev
->pm
.dpm
.requested_ps
= ps
;
2394 if (amdgpu_dpm
== 1 && adev
->powerplay
.pp_funcs
->print_power_state
) {
2395 printk("switching from power state:\n");
2396 amdgpu_dpm_print_power_state(adev
, adev
->pm
.dpm
.current_ps
);
2397 printk("switching to power state:\n");
2398 amdgpu_dpm_print_power_state(adev
, adev
->pm
.dpm
.requested_ps
);
2401 /* update whether vce is active */
2402 ps
->vce_active
= adev
->pm
.dpm
.vce_active
;
2403 if (adev
->powerplay
.pp_funcs
->display_configuration_changed
)
2404 amdgpu_dpm_display_configuration_changed(adev
);
2406 ret
= amdgpu_dpm_pre_set_power_state(adev
);
2410 if (adev
->powerplay
.pp_funcs
->check_state_equal
) {
2411 if (0 != amdgpu_dpm_check_state_equal(adev
, adev
->pm
.dpm
.current_ps
, adev
->pm
.dpm
.requested_ps
, &equal
))
2418 amdgpu_dpm_set_power_state(adev
);
2419 amdgpu_dpm_post_set_power_state(adev
);
2421 adev
->pm
.dpm
.current_active_crtcs
= adev
->pm
.dpm
.new_active_crtcs
;
2422 adev
->pm
.dpm
.current_active_crtc_count
= adev
->pm
.dpm
.new_active_crtc_count
;
2424 if (adev
->powerplay
.pp_funcs
->force_performance_level
) {
2425 if (adev
->pm
.dpm
.thermal_active
) {
2426 enum amd_dpm_forced_level level
= adev
->pm
.dpm
.forced_level
;
2427 /* force low perf level for thermal */
2428 amdgpu_dpm_force_performance_level(adev
, AMD_DPM_FORCED_LEVEL_LOW
);
2429 /* save the user's level */
2430 adev
->pm
.dpm
.forced_level
= level
;
2432 /* otherwise, user selected level */
2433 amdgpu_dpm_force_performance_level(adev
, adev
->pm
.dpm
.forced_level
);
2438 void amdgpu_dpm_enable_uvd(struct amdgpu_device
*adev
, bool enable
)
2441 if (is_support_sw_smu(adev
)) {
2442 ret
= smu_dpm_set_power_gate(&adev
->smu
, AMD_IP_BLOCK_TYPE_UVD
, enable
);
2444 DRM_ERROR("[SW SMU]: dpm enable uvd failed, state = %s, ret = %d. \n",
2445 enable
? "true" : "false", ret
);
2446 } else if (adev
->powerplay
.pp_funcs
->set_powergating_by_smu
) {
2447 /* enable/disable UVD */
2448 mutex_lock(&adev
->pm
.mutex
);
2449 amdgpu_dpm_set_powergating_by_smu(adev
, AMD_IP_BLOCK_TYPE_UVD
, !enable
);
2450 mutex_unlock(&adev
->pm
.mutex
);
2452 /* enable/disable Low Memory PState for UVD (4k videos) */
2453 if (adev
->asic_type
== CHIP_STONEY
&&
2454 adev
->uvd
.decode_image_width
>= WIDTH_4K
) {
2455 struct pp_hwmgr
*hwmgr
= adev
->powerplay
.pp_handle
;
2457 if (hwmgr
&& hwmgr
->hwmgr_func
&&
2458 hwmgr
->hwmgr_func
->update_nbdpm_pstate
)
2459 hwmgr
->hwmgr_func
->update_nbdpm_pstate(hwmgr
,
2465 void amdgpu_dpm_enable_vce(struct amdgpu_device
*adev
, bool enable
)
2468 if (is_support_sw_smu(adev
)) {
2469 ret
= smu_dpm_set_power_gate(&adev
->smu
, AMD_IP_BLOCK_TYPE_VCE
, enable
);
2471 DRM_ERROR("[SW SMU]: dpm enable vce failed, state = %s, ret = %d. \n",
2472 enable
? "true" : "false", ret
);
2473 } else if (adev
->powerplay
.pp_funcs
->set_powergating_by_smu
) {
2474 /* enable/disable VCE */
2475 mutex_lock(&adev
->pm
.mutex
);
2476 amdgpu_dpm_set_powergating_by_smu(adev
, AMD_IP_BLOCK_TYPE_VCE
, !enable
);
2477 mutex_unlock(&adev
->pm
.mutex
);
2481 void amdgpu_pm_print_power_states(struct amdgpu_device
*adev
)
2485 if (adev
->powerplay
.pp_funcs
->print_power_state
== NULL
)
2488 for (i
= 0; i
< adev
->pm
.dpm
.num_ps
; i
++)
2489 amdgpu_dpm_print_power_state(adev
, &adev
->pm
.dpm
.ps
[i
]);
2493 int amdgpu_pm_sysfs_init(struct amdgpu_device
*adev
)
2495 struct pp_hwmgr
*hwmgr
= adev
->powerplay
.pp_handle
;
2498 if (adev
->pm
.sysfs_initialized
)
2501 if (adev
->pm
.dpm_enabled
== 0)
2504 adev
->pm
.int_hwmon_dev
= hwmon_device_register_with_groups(adev
->dev
,
2507 if (IS_ERR(adev
->pm
.int_hwmon_dev
)) {
2508 ret
= PTR_ERR(adev
->pm
.int_hwmon_dev
);
2510 "Unable to register hwmon device: %d\n", ret
);
2514 ret
= device_create_file(adev
->dev
, &dev_attr_power_dpm_state
);
2516 DRM_ERROR("failed to create device file for dpm state\n");
2519 ret
= device_create_file(adev
->dev
, &dev_attr_power_dpm_force_performance_level
);
2521 DRM_ERROR("failed to create device file for dpm state\n");
2526 ret
= device_create_file(adev
->dev
, &dev_attr_pp_num_states
);
2528 DRM_ERROR("failed to create device file pp_num_states\n");
2531 ret
= device_create_file(adev
->dev
, &dev_attr_pp_cur_state
);
2533 DRM_ERROR("failed to create device file pp_cur_state\n");
2536 ret
= device_create_file(adev
->dev
, &dev_attr_pp_force_state
);
2538 DRM_ERROR("failed to create device file pp_force_state\n");
2541 ret
= device_create_file(adev
->dev
, &dev_attr_pp_table
);
2543 DRM_ERROR("failed to create device file pp_table\n");
2547 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_sclk
);
2549 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
2552 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_mclk
);
2554 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2557 if (adev
->asic_type
>= CHIP_VEGA10
) {
2558 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_socclk
);
2560 DRM_ERROR("failed to create device file pp_dpm_socclk\n");
2563 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_dcefclk
);
2565 DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
2569 if (adev
->asic_type
>= CHIP_VEGA20
) {
2570 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_fclk
);
2572 DRM_ERROR("failed to create device file pp_dpm_fclk\n");
2576 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_pcie
);
2578 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
2581 ret
= device_create_file(adev
->dev
, &dev_attr_pp_sclk_od
);
2583 DRM_ERROR("failed to create device file pp_sclk_od\n");
2586 ret
= device_create_file(adev
->dev
, &dev_attr_pp_mclk_od
);
2588 DRM_ERROR("failed to create device file pp_mclk_od\n");
2591 ret
= device_create_file(adev
->dev
,
2592 &dev_attr_pp_power_profile_mode
);
2594 DRM_ERROR("failed to create device file "
2595 "pp_power_profile_mode\n");
2598 if ((is_support_sw_smu(adev
) && adev
->smu
.od_enabled
) ||
2599 (!is_support_sw_smu(adev
) && hwmgr
->od_enabled
)) {
2600 ret
= device_create_file(adev
->dev
,
2601 &dev_attr_pp_od_clk_voltage
);
2603 DRM_ERROR("failed to create device file "
2604 "pp_od_clk_voltage\n");
2608 ret
= device_create_file(adev
->dev
,
2609 &dev_attr_gpu_busy_percent
);
2611 DRM_ERROR("failed to create device file "
2612 "gpu_busy_level\n");
2615 /* PCIe Perf counters won't work on APU nodes */
2616 if (!(adev
->flags
& AMD_IS_APU
)) {
2617 ret
= device_create_file(adev
->dev
, &dev_attr_pcie_bw
);
2619 DRM_ERROR("failed to create device file pcie_bw\n");
2623 ret
= amdgpu_debugfs_pm_init(adev
);
2625 DRM_ERROR("Failed to register debugfs file for dpm!\n");
2629 if ((adev
->asic_type
>= CHIP_VEGA10
) &&
2630 !(adev
->flags
& AMD_IS_APU
)) {
2631 ret
= device_create_file(adev
->dev
,
2632 &dev_attr_ppfeatures
);
2634 DRM_ERROR("failed to create device file "
2640 adev
->pm
.sysfs_initialized
= true;
2645 void amdgpu_pm_sysfs_fini(struct amdgpu_device
*adev
)
2647 struct pp_hwmgr
*hwmgr
= adev
->powerplay
.pp_handle
;
2649 if (adev
->pm
.dpm_enabled
== 0)
2652 if (adev
->pm
.int_hwmon_dev
)
2653 hwmon_device_unregister(adev
->pm
.int_hwmon_dev
);
2654 device_remove_file(adev
->dev
, &dev_attr_power_dpm_state
);
2655 device_remove_file(adev
->dev
, &dev_attr_power_dpm_force_performance_level
);
2657 device_remove_file(adev
->dev
, &dev_attr_pp_num_states
);
2658 device_remove_file(adev
->dev
, &dev_attr_pp_cur_state
);
2659 device_remove_file(adev
->dev
, &dev_attr_pp_force_state
);
2660 device_remove_file(adev
->dev
, &dev_attr_pp_table
);
2662 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_sclk
);
2663 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_mclk
);
2664 if (adev
->asic_type
>= CHIP_VEGA10
) {
2665 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_socclk
);
2666 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_dcefclk
);
2668 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_pcie
);
2669 if (adev
->asic_type
>= CHIP_VEGA20
)
2670 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_fclk
);
2671 device_remove_file(adev
->dev
, &dev_attr_pp_sclk_od
);
2672 device_remove_file(adev
->dev
, &dev_attr_pp_mclk_od
);
2673 device_remove_file(adev
->dev
,
2674 &dev_attr_pp_power_profile_mode
);
2675 if ((is_support_sw_smu(adev
) && adev
->smu
.od_enabled
) ||
2676 (!is_support_sw_smu(adev
) && hwmgr
->od_enabled
))
2677 device_remove_file(adev
->dev
,
2678 &dev_attr_pp_od_clk_voltage
);
2679 device_remove_file(adev
->dev
, &dev_attr_gpu_busy_percent
);
2680 if (!(adev
->flags
& AMD_IS_APU
))
2681 device_remove_file(adev
->dev
, &dev_attr_pcie_bw
);
2682 if ((adev
->asic_type
>= CHIP_VEGA10
) &&
2683 !(adev
->flags
& AMD_IS_APU
))
2684 device_remove_file(adev
->dev
, &dev_attr_ppfeatures
);
2687 void amdgpu_pm_compute_clocks(struct amdgpu_device
*adev
)
2691 if (!adev
->pm
.dpm_enabled
)
2694 if (adev
->mode_info
.num_crtc
)
2695 amdgpu_display_bandwidth_update(adev
);
2697 for (i
= 0; i
< AMDGPU_MAX_RINGS
; i
++) {
2698 struct amdgpu_ring
*ring
= adev
->rings
[i
];
2699 if (ring
&& ring
->sched
.ready
)
2700 amdgpu_fence_wait_empty(ring
);
2703 if (is_support_sw_smu(adev
)) {
2704 struct smu_context
*smu
= &adev
->smu
;
2705 struct smu_dpm_context
*smu_dpm
= &adev
->smu
.smu_dpm
;
2706 mutex_lock(&(smu
->mutex
));
2707 smu_handle_task(&adev
->smu
,
2709 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE
);
2710 mutex_unlock(&(smu
->mutex
));
2712 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
2713 if (!amdgpu_device_has_dc_support(adev
)) {
2714 mutex_lock(&adev
->pm
.mutex
);
2715 amdgpu_dpm_get_active_displays(adev
);
2716 adev
->pm
.pm_display_cfg
.num_display
= adev
->pm
.dpm
.new_active_crtc_count
;
2717 adev
->pm
.pm_display_cfg
.vrefresh
= amdgpu_dpm_get_vrefresh(adev
);
2718 adev
->pm
.pm_display_cfg
.min_vblank_time
= amdgpu_dpm_get_vblank_time(adev
);
2719 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
2720 if (adev
->pm
.pm_display_cfg
.vrefresh
> 120)
2721 adev
->pm
.pm_display_cfg
.min_vblank_time
= 0;
2722 if (adev
->powerplay
.pp_funcs
->display_configuration_change
)
2723 adev
->powerplay
.pp_funcs
->display_configuration_change(
2724 adev
->powerplay
.pp_handle
,
2725 &adev
->pm
.pm_display_cfg
);
2726 mutex_unlock(&adev
->pm
.mutex
);
2728 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE
, NULL
);
2730 mutex_lock(&adev
->pm
.mutex
);
2731 amdgpu_dpm_get_active_displays(adev
);
2732 amdgpu_dpm_change_power_state_locked(adev
);
2733 mutex_unlock(&adev
->pm
.mutex
);
2741 #if defined(CONFIG_DEBUG_FS)
2743 static int amdgpu_debugfs_pm_info_pp(struct seq_file
*m
, struct amdgpu_device
*adev
)
2751 size
= sizeof(value
);
2752 seq_printf(m
, "GFX Clocks and Power:\n");
2753 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GFX_MCLK
, (void *)&value
, &size
))
2754 seq_printf(m
, "\t%u MHz (MCLK)\n", value
/100);
2755 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GFX_SCLK
, (void *)&value
, &size
))
2756 seq_printf(m
, "\t%u MHz (SCLK)\n", value
/100);
2757 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK
, (void *)&value
, &size
))
2758 seq_printf(m
, "\t%u MHz (PSTATE_SCLK)\n", value
/100);
2759 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK
, (void *)&value
, &size
))
2760 seq_printf(m
, "\t%u MHz (PSTATE_MCLK)\n", value
/100);
2761 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDGFX
, (void *)&value
, &size
))
2762 seq_printf(m
, "\t%u mV (VDDGFX)\n", value
);
2763 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDNB
, (void *)&value
, &size
))
2764 seq_printf(m
, "\t%u mV (VDDNB)\n", value
);
2765 size
= sizeof(uint32_t);
2766 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_POWER
, (void *)&query
, &size
))
2767 seq_printf(m
, "\t%u.%u W (average GPU)\n", query
>> 8, query
& 0xff);
2768 size
= sizeof(value
);
2769 seq_printf(m
, "\n");
2772 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_TEMP
, (void *)&value
, &size
))
2773 seq_printf(m
, "GPU Temperature: %u C\n", value
/1000);
2776 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_LOAD
, (void *)&value
, &size
))
2777 seq_printf(m
, "GPU Load: %u %%\n", value
);
2778 seq_printf(m
, "\n");
2780 /* SMC feature mask */
2781 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK
, (void *)&value64
, &size
))
2782 seq_printf(m
, "SMC Feature Mask: 0x%016llx\n", value64
);
2785 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_UVD_POWER
, (void *)&value
, &size
)) {
2787 seq_printf(m
, "UVD: Disabled\n");
2789 seq_printf(m
, "UVD: Enabled\n");
2790 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_UVD_DCLK
, (void *)&value
, &size
))
2791 seq_printf(m
, "\t%u MHz (DCLK)\n", value
/100);
2792 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_UVD_VCLK
, (void *)&value
, &size
))
2793 seq_printf(m
, "\t%u MHz (VCLK)\n", value
/100);
2796 seq_printf(m
, "\n");
2799 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VCE_POWER
, (void *)&value
, &size
)) {
2801 seq_printf(m
, "VCE: Disabled\n");
2803 seq_printf(m
, "VCE: Enabled\n");
2804 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VCE_ECCLK
, (void *)&value
, &size
))
2805 seq_printf(m
, "\t%u MHz (ECCLK)\n", value
/100);
2812 static void amdgpu_parse_cg_state(struct seq_file
*m
, u32 flags
)
2816 for (i
= 0; clocks
[i
].flag
; i
++)
2817 seq_printf(m
, "\t%s: %s\n", clocks
[i
].name
,
2818 (flags
& clocks
[i
].flag
) ? "On" : "Off");
2821 static int amdgpu_debugfs_pm_info(struct seq_file
*m
, void *data
)
2823 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2824 struct drm_device
*dev
= node
->minor
->dev
;
2825 struct amdgpu_device
*adev
= dev
->dev_private
;
2826 struct drm_device
*ddev
= adev
->ddev
;
2829 amdgpu_device_ip_get_clockgating_state(adev
, &flags
);
2830 seq_printf(m
, "Clock Gating Flags Mask: 0x%x\n", flags
);
2831 amdgpu_parse_cg_state(m
, flags
);
2832 seq_printf(m
, "\n");
2834 if (!adev
->pm
.dpm_enabled
) {
2835 seq_printf(m
, "dpm not enabled\n");
2838 if ((adev
->flags
& AMD_IS_PX
) &&
2839 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
)) {
2840 seq_printf(m
, "PX asic powered off\n");
2841 } else if (!is_support_sw_smu(adev
) && adev
->powerplay
.pp_funcs
->debugfs_print_current_performance_level
) {
2842 mutex_lock(&adev
->pm
.mutex
);
2843 if (adev
->powerplay
.pp_funcs
->debugfs_print_current_performance_level
)
2844 adev
->powerplay
.pp_funcs
->debugfs_print_current_performance_level(adev
, m
);
2846 seq_printf(m
, "Debugfs support not implemented for this asic\n");
2847 mutex_unlock(&adev
->pm
.mutex
);
2849 return amdgpu_debugfs_pm_info_pp(m
, adev
);
2855 static const struct drm_info_list amdgpu_pm_info_list
[] = {
2856 {"amdgpu_pm_info", amdgpu_debugfs_pm_info
, 0, NULL
},
2860 static int amdgpu_debugfs_pm_init(struct amdgpu_device
*adev
)
2862 #if defined(CONFIG_DEBUG_FS)
2863 return amdgpu_debugfs_add_files(adev
, amdgpu_pm_info_list
, ARRAY_SIZE(amdgpu_pm_info_list
));