2 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Rafał Miłecki <zajec5@gmail.com>
23 * Alex Deucher <alexdeucher@gmail.com>
26 #include <drm/drm_debugfs.h>
29 #include "amdgpu_drv.h"
30 #include "amdgpu_pm.h"
31 #include "amdgpu_dpm.h"
32 #include "amdgpu_display.h"
33 #include "amdgpu_smu.h"
35 #include <linux/power_supply.h>
36 #include <linux/pci.h>
37 #include <linux/hwmon.h>
38 #include <linux/hwmon-sysfs.h>
39 #include <linux/nospec.h>
43 static int amdgpu_debugfs_pm_init(struct amdgpu_device
*adev
);
45 static const struct cg_flag_name clocks
[] = {
46 {AMD_CG_SUPPORT_GFX_MGCG
, "Graphics Medium Grain Clock Gating"},
47 {AMD_CG_SUPPORT_GFX_MGLS
, "Graphics Medium Grain memory Light Sleep"},
48 {AMD_CG_SUPPORT_GFX_CGCG
, "Graphics Coarse Grain Clock Gating"},
49 {AMD_CG_SUPPORT_GFX_CGLS
, "Graphics Coarse Grain memory Light Sleep"},
50 {AMD_CG_SUPPORT_GFX_CGTS
, "Graphics Coarse Grain Tree Shader Clock Gating"},
51 {AMD_CG_SUPPORT_GFX_CGTS_LS
, "Graphics Coarse Grain Tree Shader Light Sleep"},
52 {AMD_CG_SUPPORT_GFX_CP_LS
, "Graphics Command Processor Light Sleep"},
53 {AMD_CG_SUPPORT_GFX_RLC_LS
, "Graphics Run List Controller Light Sleep"},
54 {AMD_CG_SUPPORT_GFX_3D_CGCG
, "Graphics 3D Coarse Grain Clock Gating"},
55 {AMD_CG_SUPPORT_GFX_3D_CGLS
, "Graphics 3D Coarse Grain memory Light Sleep"},
56 {AMD_CG_SUPPORT_MC_LS
, "Memory Controller Light Sleep"},
57 {AMD_CG_SUPPORT_MC_MGCG
, "Memory Controller Medium Grain Clock Gating"},
58 {AMD_CG_SUPPORT_SDMA_LS
, "System Direct Memory Access Light Sleep"},
59 {AMD_CG_SUPPORT_SDMA_MGCG
, "System Direct Memory Access Medium Grain Clock Gating"},
60 {AMD_CG_SUPPORT_BIF_MGCG
, "Bus Interface Medium Grain Clock Gating"},
61 {AMD_CG_SUPPORT_BIF_LS
, "Bus Interface Light Sleep"},
62 {AMD_CG_SUPPORT_UVD_MGCG
, "Unified Video Decoder Medium Grain Clock Gating"},
63 {AMD_CG_SUPPORT_VCE_MGCG
, "Video Compression Engine Medium Grain Clock Gating"},
64 {AMD_CG_SUPPORT_HDP_LS
, "Host Data Path Light Sleep"},
65 {AMD_CG_SUPPORT_HDP_MGCG
, "Host Data Path Medium Grain Clock Gating"},
66 {AMD_CG_SUPPORT_DRM_MGCG
, "Digital Right Management Medium Grain Clock Gating"},
67 {AMD_CG_SUPPORT_DRM_LS
, "Digital Right Management Light Sleep"},
68 {AMD_CG_SUPPORT_ROM_MGCG
, "Rom Medium Grain Clock Gating"},
69 {AMD_CG_SUPPORT_DF_MGCG
, "Data Fabric Medium Grain Clock Gating"},
71 {AMD_CG_SUPPORT_ATHUB_MGCG
, "Address Translation Hub Medium Grain Clock Gating"},
72 {AMD_CG_SUPPORT_ATHUB_LS
, "Address Translation Hub Light Sleep"},
76 static const struct hwmon_temp_label
{
77 enum PP_HWMON_TEMP channel
;
80 {PP_TEMP_EDGE
, "edge"},
81 {PP_TEMP_JUNCTION
, "junction"},
85 void amdgpu_pm_acpi_event_handler(struct amdgpu_device
*adev
)
87 if (adev
->pm
.dpm_enabled
) {
88 mutex_lock(&adev
->pm
.mutex
);
89 if (power_supply_is_system_supplied() > 0)
90 adev
->pm
.ac_power
= true;
92 adev
->pm
.ac_power
= false;
93 if (adev
->powerplay
.pp_funcs
->enable_bapm
)
94 amdgpu_dpm_enable_bapm(adev
, adev
->pm
.ac_power
);
95 mutex_unlock(&adev
->pm
.mutex
);
99 int amdgpu_dpm_read_sensor(struct amdgpu_device
*adev
, enum amd_pp_sensors sensor
,
100 void *data
, uint32_t *size
)
107 if (is_support_sw_smu(adev
))
108 ret
= smu_read_sensor(&adev
->smu
, sensor
, data
, size
);
110 if (adev
->powerplay
.pp_funcs
&& adev
->powerplay
.pp_funcs
->read_sensor
)
111 ret
= adev
->powerplay
.pp_funcs
->read_sensor((adev
)->powerplay
.pp_handle
,
121 * DOC: power_dpm_state
123 * The power_dpm_state file is a legacy interface and is only provided for
124 * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
125 * certain power related parameters. The file power_dpm_state is used for this.
126 * It accepts the following arguments:
136 * On older GPUs, the vbios provided a special power state for battery
137 * operation. Selecting battery switched to this state. This is no
138 * longer provided on newer GPUs so the option does nothing in that case.
142 * On older GPUs, the vbios provided a special power state for balanced
143 * operation. Selecting balanced switched to this state. This is no
144 * longer provided on newer GPUs so the option does nothing in that case.
148 * On older GPUs, the vbios provided a special power state for performance
149 * operation. Selecting performance switched to this state. This is no
150 * longer provided on newer GPUs so the option does nothing in that case.
154 static ssize_t
amdgpu_get_dpm_state(struct device
*dev
,
155 struct device_attribute
*attr
,
158 struct drm_device
*ddev
= dev_get_drvdata(dev
);
159 struct amdgpu_device
*adev
= ddev
->dev_private
;
160 enum amd_pm_state_type pm
;
162 if (is_support_sw_smu(adev
)) {
163 if (adev
->smu
.ppt_funcs
->get_current_power_state
)
164 pm
= amdgpu_smu_get_current_power_state(adev
);
166 pm
= adev
->pm
.dpm
.user_state
;
167 } else if (adev
->powerplay
.pp_funcs
->get_current_power_state
) {
168 pm
= amdgpu_dpm_get_current_power_state(adev
);
170 pm
= adev
->pm
.dpm
.user_state
;
173 return snprintf(buf
, PAGE_SIZE
, "%s\n",
174 (pm
== POWER_STATE_TYPE_BATTERY
) ? "battery" :
175 (pm
== POWER_STATE_TYPE_BALANCED
) ? "balanced" : "performance");
178 static ssize_t
amdgpu_set_dpm_state(struct device
*dev
,
179 struct device_attribute
*attr
,
183 struct drm_device
*ddev
= dev_get_drvdata(dev
);
184 struct amdgpu_device
*adev
= ddev
->dev_private
;
185 enum amd_pm_state_type state
;
187 if (strncmp("battery", buf
, strlen("battery")) == 0)
188 state
= POWER_STATE_TYPE_BATTERY
;
189 else if (strncmp("balanced", buf
, strlen("balanced")) == 0)
190 state
= POWER_STATE_TYPE_BALANCED
;
191 else if (strncmp("performance", buf
, strlen("performance")) == 0)
192 state
= POWER_STATE_TYPE_PERFORMANCE
;
198 if (is_support_sw_smu(adev
)) {
199 mutex_lock(&adev
->pm
.mutex
);
200 adev
->pm
.dpm
.user_state
= state
;
201 mutex_unlock(&adev
->pm
.mutex
);
202 } else if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
203 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_ENABLE_USER_STATE
, &state
);
205 mutex_lock(&adev
->pm
.mutex
);
206 adev
->pm
.dpm
.user_state
= state
;
207 mutex_unlock(&adev
->pm
.mutex
);
209 /* Can't set dpm state when the card is off */
210 if (!(adev
->flags
& AMD_IS_PX
) ||
211 (ddev
->switch_power_state
== DRM_SWITCH_POWER_ON
))
212 amdgpu_pm_compute_clocks(adev
);
220 * DOC: power_dpm_force_performance_level
222 * The amdgpu driver provides a sysfs API for adjusting certain power
223 * related parameters. The file power_dpm_force_performance_level is
224 * used for this. It accepts the following arguments:
244 * When auto is selected, the driver will attempt to dynamically select
245 * the optimal power profile for current conditions in the driver.
249 * When low is selected, the clocks are forced to the lowest power state.
253 * When high is selected, the clocks are forced to the highest power state.
257 * When manual is selected, the user can manually adjust which power states
258 * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
259 * and pp_dpm_pcie files and adjust the power state transition heuristics
260 * via the pp_power_profile_mode sysfs file.
267 * When the profiling modes are selected, clock and power gating are
268 * disabled and the clocks are set for different profiling cases. This
269 * mode is recommended for profiling specific work loads where you do
270 * not want clock or power gating for clock fluctuation to interfere
271 * with your results. profile_standard sets the clocks to a fixed clock
272 * level which varies from asic to asic. profile_min_sclk forces the sclk
273 * to the lowest level. profile_min_mclk forces the mclk to the lowest level.
274 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
278 static ssize_t
amdgpu_get_dpm_forced_performance_level(struct device
*dev
,
279 struct device_attribute
*attr
,
282 struct drm_device
*ddev
= dev_get_drvdata(dev
);
283 struct amdgpu_device
*adev
= ddev
->dev_private
;
284 enum amd_dpm_forced_level level
= 0xff;
286 if (amdgpu_sriov_vf(adev
))
289 if ((adev
->flags
& AMD_IS_PX
) &&
290 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
291 return snprintf(buf
, PAGE_SIZE
, "off\n");
293 if (is_support_sw_smu(adev
))
294 level
= smu_get_performance_level(&adev
->smu
);
295 else if (adev
->powerplay
.pp_funcs
->get_performance_level
)
296 level
= amdgpu_dpm_get_performance_level(adev
);
298 level
= adev
->pm
.dpm
.forced_level
;
300 return snprintf(buf
, PAGE_SIZE
, "%s\n",
301 (level
== AMD_DPM_FORCED_LEVEL_AUTO
) ? "auto" :
302 (level
== AMD_DPM_FORCED_LEVEL_LOW
) ? "low" :
303 (level
== AMD_DPM_FORCED_LEVEL_HIGH
) ? "high" :
304 (level
== AMD_DPM_FORCED_LEVEL_MANUAL
) ? "manual" :
305 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
) ? "profile_standard" :
306 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
) ? "profile_min_sclk" :
307 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
) ? "profile_min_mclk" :
308 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
) ? "profile_peak" :
312 static ssize_t
amdgpu_set_dpm_forced_performance_level(struct device
*dev
,
313 struct device_attribute
*attr
,
317 struct drm_device
*ddev
= dev_get_drvdata(dev
);
318 struct amdgpu_device
*adev
= ddev
->dev_private
;
319 enum amd_dpm_forced_level level
;
320 enum amd_dpm_forced_level current_level
= 0xff;
323 /* Can't force performance level when the card is off */
324 if ((adev
->flags
& AMD_IS_PX
) &&
325 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
328 if (!amdgpu_sriov_vf(adev
)) {
329 if (is_support_sw_smu(adev
))
330 current_level
= smu_get_performance_level(&adev
->smu
);
331 else if (adev
->powerplay
.pp_funcs
->get_performance_level
)
332 current_level
= amdgpu_dpm_get_performance_level(adev
);
335 if (strncmp("low", buf
, strlen("low")) == 0) {
336 level
= AMD_DPM_FORCED_LEVEL_LOW
;
337 } else if (strncmp("high", buf
, strlen("high")) == 0) {
338 level
= AMD_DPM_FORCED_LEVEL_HIGH
;
339 } else if (strncmp("auto", buf
, strlen("auto")) == 0) {
340 level
= AMD_DPM_FORCED_LEVEL_AUTO
;
341 } else if (strncmp("manual", buf
, strlen("manual")) == 0) {
342 level
= AMD_DPM_FORCED_LEVEL_MANUAL
;
343 } else if (strncmp("profile_exit", buf
, strlen("profile_exit")) == 0) {
344 level
= AMD_DPM_FORCED_LEVEL_PROFILE_EXIT
;
345 } else if (strncmp("profile_standard", buf
, strlen("profile_standard")) == 0) {
346 level
= AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
;
347 } else if (strncmp("profile_min_sclk", buf
, strlen("profile_min_sclk")) == 0) {
348 level
= AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
;
349 } else if (strncmp("profile_min_mclk", buf
, strlen("profile_min_mclk")) == 0) {
350 level
= AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
;
351 } else if (strncmp("profile_peak", buf
, strlen("profile_peak")) == 0) {
352 level
= AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
;
358 if (amdgpu_sriov_vf(adev
)) {
359 if (amdgim_is_hwperf(adev
) &&
360 adev
->virt
.ops
->force_dpm_level
) {
361 mutex_lock(&adev
->pm
.mutex
);
362 adev
->virt
.ops
->force_dpm_level(adev
, level
);
363 mutex_unlock(&adev
->pm
.mutex
);
370 if (current_level
== level
)
373 /* profile_exit setting is valid only when current mode is in profile mode */
374 if (!(current_level
& (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
|
375 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
|
376 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
|
377 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
)) &&
378 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_EXIT
)) {
379 pr_err("Currently not in any profile mode!\n");
383 if (is_support_sw_smu(adev
)) {
384 ret
= smu_force_performance_level(&adev
->smu
, level
);
387 } else if (adev
->powerplay
.pp_funcs
->force_performance_level
) {
388 mutex_lock(&adev
->pm
.mutex
);
389 if (adev
->pm
.dpm
.thermal_active
) {
391 mutex_unlock(&adev
->pm
.mutex
);
394 ret
= amdgpu_dpm_force_performance_level(adev
, level
);
398 adev
->pm
.dpm
.forced_level
= level
;
399 mutex_unlock(&adev
->pm
.mutex
);
406 static ssize_t
amdgpu_get_pp_num_states(struct device
*dev
,
407 struct device_attribute
*attr
,
410 struct drm_device
*ddev
= dev_get_drvdata(dev
);
411 struct amdgpu_device
*adev
= ddev
->dev_private
;
412 struct pp_states_info data
;
415 if (is_support_sw_smu(adev
)) {
416 ret
= smu_get_power_num_states(&adev
->smu
, &data
);
419 } else if (adev
->powerplay
.pp_funcs
->get_pp_num_states
)
420 amdgpu_dpm_get_pp_num_states(adev
, &data
);
422 buf_len
= snprintf(buf
, PAGE_SIZE
, "states: %d\n", data
.nums
);
423 for (i
= 0; i
< data
.nums
; i
++)
424 buf_len
+= snprintf(buf
+ buf_len
, PAGE_SIZE
, "%d %s\n", i
,
425 (data
.states
[i
] == POWER_STATE_TYPE_INTERNAL_BOOT
) ? "boot" :
426 (data
.states
[i
] == POWER_STATE_TYPE_BATTERY
) ? "battery" :
427 (data
.states
[i
] == POWER_STATE_TYPE_BALANCED
) ? "balanced" :
428 (data
.states
[i
] == POWER_STATE_TYPE_PERFORMANCE
) ? "performance" : "default");
433 static ssize_t
amdgpu_get_pp_cur_state(struct device
*dev
,
434 struct device_attribute
*attr
,
437 struct drm_device
*ddev
= dev_get_drvdata(dev
);
438 struct amdgpu_device
*adev
= ddev
->dev_private
;
439 struct pp_states_info data
;
440 struct smu_context
*smu
= &adev
->smu
;
441 enum amd_pm_state_type pm
= 0;
444 if (is_support_sw_smu(adev
)) {
445 pm
= smu_get_current_power_state(smu
);
446 ret
= smu_get_power_num_states(smu
, &data
);
449 } else if (adev
->powerplay
.pp_funcs
->get_current_power_state
450 && adev
->powerplay
.pp_funcs
->get_pp_num_states
) {
451 pm
= amdgpu_dpm_get_current_power_state(adev
);
452 amdgpu_dpm_get_pp_num_states(adev
, &data
);
455 for (i
= 0; i
< data
.nums
; i
++) {
456 if (pm
== data
.states
[i
])
463 return snprintf(buf
, PAGE_SIZE
, "%d\n", i
);
466 static ssize_t
amdgpu_get_pp_force_state(struct device
*dev
,
467 struct device_attribute
*attr
,
470 struct drm_device
*ddev
= dev_get_drvdata(dev
);
471 struct amdgpu_device
*adev
= ddev
->dev_private
;
473 if (adev
->pp_force_state_enabled
)
474 return amdgpu_get_pp_cur_state(dev
, attr
, buf
);
476 return snprintf(buf
, PAGE_SIZE
, "\n");
479 static ssize_t
amdgpu_set_pp_force_state(struct device
*dev
,
480 struct device_attribute
*attr
,
484 struct drm_device
*ddev
= dev_get_drvdata(dev
);
485 struct amdgpu_device
*adev
= ddev
->dev_private
;
486 enum amd_pm_state_type state
= 0;
490 if (strlen(buf
) == 1)
491 adev
->pp_force_state_enabled
= false;
492 else if (is_support_sw_smu(adev
))
493 adev
->pp_force_state_enabled
= false;
494 else if (adev
->powerplay
.pp_funcs
->dispatch_tasks
&&
495 adev
->powerplay
.pp_funcs
->get_pp_num_states
) {
496 struct pp_states_info data
;
498 ret
= kstrtoul(buf
, 0, &idx
);
499 if (ret
|| idx
>= ARRAY_SIZE(data
.states
)) {
503 idx
= array_index_nospec(idx
, ARRAY_SIZE(data
.states
));
505 amdgpu_dpm_get_pp_num_states(adev
, &data
);
506 state
= data
.states
[idx
];
507 /* only set user selected power states */
508 if (state
!= POWER_STATE_TYPE_INTERNAL_BOOT
&&
509 state
!= POWER_STATE_TYPE_DEFAULT
) {
510 amdgpu_dpm_dispatch_task(adev
,
511 AMD_PP_TASK_ENABLE_USER_STATE
, &state
);
512 adev
->pp_force_state_enabled
= true;
522 * The amdgpu driver provides a sysfs API for uploading new powerplay
523 * tables. The file pp_table is used for this. Reading the file
524 * will dump the current power play table. Writing to the file
525 * will attempt to upload a new powerplay table and re-initialize
526 * powerplay using that new table.
530 static ssize_t
amdgpu_get_pp_table(struct device
*dev
,
531 struct device_attribute
*attr
,
534 struct drm_device
*ddev
= dev_get_drvdata(dev
);
535 struct amdgpu_device
*adev
= ddev
->dev_private
;
539 if (is_support_sw_smu(adev
)) {
540 size
= smu_sys_get_pp_table(&adev
->smu
, (void **)&table
);
544 else if (adev
->powerplay
.pp_funcs
->get_pp_table
)
545 size
= amdgpu_dpm_get_pp_table(adev
, &table
);
549 if (size
>= PAGE_SIZE
)
550 size
= PAGE_SIZE
- 1;
552 memcpy(buf
, table
, size
);
557 static ssize_t
amdgpu_set_pp_table(struct device
*dev
,
558 struct device_attribute
*attr
,
562 struct drm_device
*ddev
= dev_get_drvdata(dev
);
563 struct amdgpu_device
*adev
= ddev
->dev_private
;
566 if (is_support_sw_smu(adev
)) {
567 ret
= smu_sys_set_pp_table(&adev
->smu
, (void *)buf
, count
);
570 } else if (adev
->powerplay
.pp_funcs
->set_pp_table
)
571 amdgpu_dpm_set_pp_table(adev
, buf
, count
);
577 * DOC: pp_od_clk_voltage
579 * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
580 * in each power level within a power state. The pp_od_clk_voltage is used for
583 * < For Vega10 and previous ASICs >
585 * Reading the file will display:
587 * - a list of engine clock levels and voltages labeled OD_SCLK
589 * - a list of memory clock levels and voltages labeled OD_MCLK
591 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
593 * To manually adjust these settings, first select manual using
594 * power_dpm_force_performance_level. Enter a new value for each
595 * level by writing a string that contains "s/m level clock voltage" to
596 * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
597 * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
598 * 810 mV. When you have edited all of the states as needed, write
599 * "c" (commit) to the file to commit your changes. If you want to reset to the
600 * default power levels, write "r" (reset) to the file to reset them.
605 * Reading the file will display:
607 * - minimum and maximum engine clock labeled OD_SCLK
609 * - maximum memory clock labeled OD_MCLK
611 * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
612 * They can be used to calibrate the sclk voltage curve.
614 * - a list of valid ranges for sclk, mclk, and voltage curve points
617 * To manually adjust these settings:
619 * - First select manual using power_dpm_force_performance_level
621 * - For clock frequency setting, enter a new value by writing a
622 * string that contains "s/m index clock" to the file. The index
623 * should be 0 if to set minimum clock. And 1 if to set maximum
624 * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
625 * "m 1 800" will update maximum mclk to be 800Mhz.
627 * For sclk voltage curve, enter the new values by writing a
628 * string that contains "vc point clock voltage" to the file. The
629 * points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
630 * update point1 with clock set as 300Mhz and voltage as
631 * 600mV. "vc 2 1000 1000" will update point3 with clock set
632 * as 1000Mhz and voltage 1000mV.
634 * - When you have edited all of the states as needed, write "c" (commit)
635 * to the file to commit your changes
637 * - If you want to reset to the default power levels, write "r" (reset)
638 * to the file to reset them
642 static ssize_t
amdgpu_set_pp_od_clk_voltage(struct device
*dev
,
643 struct device_attribute
*attr
,
647 struct drm_device
*ddev
= dev_get_drvdata(dev
);
648 struct amdgpu_device
*adev
= ddev
->dev_private
;
650 uint32_t parameter_size
= 0;
655 const char delimiter
[3] = {' ', '\n', '\0'};
662 type
= PP_OD_EDIT_SCLK_VDDC_TABLE
;
663 else if (*buf
== 'm')
664 type
= PP_OD_EDIT_MCLK_VDDC_TABLE
;
666 type
= PP_OD_RESTORE_DEFAULT_TABLE
;
667 else if (*buf
== 'c')
668 type
= PP_OD_COMMIT_DPM_TABLE
;
669 else if (!strncmp(buf
, "vc", 2))
670 type
= PP_OD_EDIT_VDDC_CURVE
;
674 memcpy(buf_cpy
, buf
, count
+1);
678 if (type
== PP_OD_EDIT_VDDC_CURVE
)
680 while (isspace(*++tmp_str
));
683 sub_str
= strsep(&tmp_str
, delimiter
);
684 ret
= kstrtol(sub_str
, 0, ¶meter
[parameter_size
]);
689 while (isspace(*tmp_str
))
693 if (is_support_sw_smu(adev
)) {
694 ret
= smu_od_edit_dpm_table(&adev
->smu
, type
,
695 parameter
, parameter_size
);
700 if (adev
->powerplay
.pp_funcs
->odn_edit_dpm_table
) {
701 ret
= amdgpu_dpm_odn_edit_dpm_table(adev
, type
,
702 parameter
, parameter_size
);
707 if (type
== PP_OD_COMMIT_DPM_TABLE
) {
708 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
709 amdgpu_dpm_dispatch_task(adev
,
710 AMD_PP_TASK_READJUST_POWER_STATE
,
722 static ssize_t
amdgpu_get_pp_od_clk_voltage(struct device
*dev
,
723 struct device_attribute
*attr
,
726 struct drm_device
*ddev
= dev_get_drvdata(dev
);
727 struct amdgpu_device
*adev
= ddev
->dev_private
;
730 if (is_support_sw_smu(adev
)) {
731 size
= smu_print_clk_levels(&adev
->smu
, SMU_OD_SCLK
, buf
);
732 size
+= smu_print_clk_levels(&adev
->smu
, SMU_OD_MCLK
, buf
+size
);
733 size
+= smu_print_clk_levels(&adev
->smu
, SMU_OD_VDDC_CURVE
, buf
+size
);
734 size
+= smu_print_clk_levels(&adev
->smu
, SMU_OD_RANGE
, buf
+size
);
736 } else if (adev
->powerplay
.pp_funcs
->print_clock_levels
) {
737 size
= amdgpu_dpm_print_clock_levels(adev
, OD_SCLK
, buf
);
738 size
+= amdgpu_dpm_print_clock_levels(adev
, OD_MCLK
, buf
+size
);
739 size
+= amdgpu_dpm_print_clock_levels(adev
, OD_VDDC_CURVE
, buf
+size
);
740 size
+= amdgpu_dpm_print_clock_levels(adev
, OD_RANGE
, buf
+size
);
743 return snprintf(buf
, PAGE_SIZE
, "\n");
751 * The amdgpu driver provides a sysfs API for adjusting what powerplay
752 * features to be enabled. The file ppfeatures is used for this. And
753 * this is only available for Vega10 and later dGPUs.
755 * Reading back the file will show you the followings:
756 * - Current ppfeature masks
757 * - List of the all supported powerplay features with their naming,
758 * bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
760 * To manually enable or disable a specific feature, just set or clear
761 * the corresponding bit from original ppfeature masks and input the
762 * new ppfeature masks.
764 static ssize_t
amdgpu_set_ppfeature_status(struct device
*dev
,
765 struct device_attribute
*attr
,
769 struct drm_device
*ddev
= dev_get_drvdata(dev
);
770 struct amdgpu_device
*adev
= ddev
->dev_private
;
771 uint64_t featuremask
;
774 ret
= kstrtou64(buf
, 0, &featuremask
);
778 pr_debug("featuremask = 0x%llx\n", featuremask
);
780 if (is_support_sw_smu(adev
)) {
781 ret
= smu_set_ppfeature_status(&adev
->smu
, featuremask
);
784 } else if (adev
->powerplay
.pp_funcs
->set_ppfeature_status
) {
785 ret
= amdgpu_dpm_set_ppfeature_status(adev
, featuremask
);
793 static ssize_t
amdgpu_get_ppfeature_status(struct device
*dev
,
794 struct device_attribute
*attr
,
797 struct drm_device
*ddev
= dev_get_drvdata(dev
);
798 struct amdgpu_device
*adev
= ddev
->dev_private
;
800 if (is_support_sw_smu(adev
)) {
801 return smu_get_ppfeature_status(&adev
->smu
, buf
);
802 } else if (adev
->powerplay
.pp_funcs
->get_ppfeature_status
)
803 return amdgpu_dpm_get_ppfeature_status(adev
, buf
);
805 return snprintf(buf
, PAGE_SIZE
, "\n");
809 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk
812 * The amdgpu driver provides a sysfs API for adjusting what power levels
813 * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk,
814 * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
817 * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
818 * Vega10 and later ASICs.
819 * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
821 * Reading back the files will show you the available power levels within
822 * the power state and the clock information for those levels.
824 * To manually adjust these states, first select manual using
825 * power_dpm_force_performance_level.
826 * Secondly,Enter a new value for each level by inputing a string that
827 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
828 * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
830 * NOTE: change to the dcefclk max dpm level is not supported now
833 static ssize_t
amdgpu_get_pp_dpm_sclk(struct device
*dev
,
834 struct device_attribute
*attr
,
837 struct drm_device
*ddev
= dev_get_drvdata(dev
);
838 struct amdgpu_device
*adev
= ddev
->dev_private
;
840 if (amdgpu_sriov_vf(adev
) && amdgim_is_hwperf(adev
) &&
841 adev
->virt
.ops
->get_pp_clk
)
842 return adev
->virt
.ops
->get_pp_clk(adev
, PP_SCLK
, buf
);
844 if (is_support_sw_smu(adev
))
845 return smu_print_clk_levels(&adev
->smu
, SMU_SCLK
, buf
);
846 else if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
847 return amdgpu_dpm_print_clock_levels(adev
, PP_SCLK
, buf
);
849 return snprintf(buf
, PAGE_SIZE
, "\n");
853 * Worst case: 32 bits individually specified, in octal at 12 characters
854 * per line (+1 for \n).
856 #define AMDGPU_MASK_BUF_MAX (32 * 13)
858 static ssize_t
amdgpu_read_mask(const char *buf
, size_t count
, uint32_t *mask
)
862 char *sub_str
= NULL
;
864 char buf_cpy
[AMDGPU_MASK_BUF_MAX
+ 1];
865 const char delimiter
[3] = {' ', '\n', '\0'};
870 bytes
= min(count
, sizeof(buf_cpy
) - 1);
871 memcpy(buf_cpy
, buf
, bytes
);
872 buf_cpy
[bytes
] = '\0';
875 sub_str
= strsep(&tmp
, delimiter
);
876 if (strlen(sub_str
)) {
877 ret
= kstrtol(sub_str
, 0, &level
);
888 static ssize_t
amdgpu_set_pp_dpm_sclk(struct device
*dev
,
889 struct device_attribute
*attr
,
893 struct drm_device
*ddev
= dev_get_drvdata(dev
);
894 struct amdgpu_device
*adev
= ddev
->dev_private
;
898 if (amdgpu_sriov_vf(adev
))
901 ret
= amdgpu_read_mask(buf
, count
, &mask
);
905 if (is_support_sw_smu(adev
))
906 ret
= smu_force_clk_levels(&adev
->smu
, SMU_SCLK
, mask
);
907 else if (adev
->powerplay
.pp_funcs
->force_clock_level
)
908 ret
= amdgpu_dpm_force_clock_level(adev
, PP_SCLK
, mask
);
916 static ssize_t
amdgpu_get_pp_dpm_mclk(struct device
*dev
,
917 struct device_attribute
*attr
,
920 struct drm_device
*ddev
= dev_get_drvdata(dev
);
921 struct amdgpu_device
*adev
= ddev
->dev_private
;
923 if (amdgpu_sriov_vf(adev
) && amdgim_is_hwperf(adev
) &&
924 adev
->virt
.ops
->get_pp_clk
)
925 return adev
->virt
.ops
->get_pp_clk(adev
, PP_MCLK
, buf
);
927 if (is_support_sw_smu(adev
))
928 return smu_print_clk_levels(&adev
->smu
, SMU_MCLK
, buf
);
929 else if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
930 return amdgpu_dpm_print_clock_levels(adev
, PP_MCLK
, buf
);
932 return snprintf(buf
, PAGE_SIZE
, "\n");
935 static ssize_t
amdgpu_set_pp_dpm_mclk(struct device
*dev
,
936 struct device_attribute
*attr
,
940 struct drm_device
*ddev
= dev_get_drvdata(dev
);
941 struct amdgpu_device
*adev
= ddev
->dev_private
;
945 if (amdgpu_sriov_vf(adev
))
948 ret
= amdgpu_read_mask(buf
, count
, &mask
);
952 if (is_support_sw_smu(adev
))
953 ret
= smu_force_clk_levels(&adev
->smu
, SMU_MCLK
, mask
);
954 else if (adev
->powerplay
.pp_funcs
->force_clock_level
)
955 ret
= amdgpu_dpm_force_clock_level(adev
, PP_MCLK
, mask
);
963 static ssize_t
amdgpu_get_pp_dpm_socclk(struct device
*dev
,
964 struct device_attribute
*attr
,
967 struct drm_device
*ddev
= dev_get_drvdata(dev
);
968 struct amdgpu_device
*adev
= ddev
->dev_private
;
970 if (is_support_sw_smu(adev
))
971 return smu_print_clk_levels(&adev
->smu
, SMU_SOCCLK
, buf
);
972 else if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
973 return amdgpu_dpm_print_clock_levels(adev
, PP_SOCCLK
, buf
);
975 return snprintf(buf
, PAGE_SIZE
, "\n");
978 static ssize_t
amdgpu_set_pp_dpm_socclk(struct device
*dev
,
979 struct device_attribute
*attr
,
983 struct drm_device
*ddev
= dev_get_drvdata(dev
);
984 struct amdgpu_device
*adev
= ddev
->dev_private
;
988 ret
= amdgpu_read_mask(buf
, count
, &mask
);
992 if (is_support_sw_smu(adev
))
993 ret
= smu_force_clk_levels(&adev
->smu
, SMU_SOCCLK
, mask
);
994 else if (adev
->powerplay
.pp_funcs
->force_clock_level
)
995 ret
= amdgpu_dpm_force_clock_level(adev
, PP_SOCCLK
, mask
);
1003 static ssize_t
amdgpu_get_pp_dpm_fclk(struct device
*dev
,
1004 struct device_attribute
*attr
,
1007 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1008 struct amdgpu_device
*adev
= ddev
->dev_private
;
1010 if (is_support_sw_smu(adev
))
1011 return smu_print_clk_levels(&adev
->smu
, SMU_FCLK
, buf
);
1012 else if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
1013 return amdgpu_dpm_print_clock_levels(adev
, PP_FCLK
, buf
);
1015 return snprintf(buf
, PAGE_SIZE
, "\n");
1018 static ssize_t
amdgpu_set_pp_dpm_fclk(struct device
*dev
,
1019 struct device_attribute
*attr
,
1023 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1024 struct amdgpu_device
*adev
= ddev
->dev_private
;
1028 ret
= amdgpu_read_mask(buf
, count
, &mask
);
1032 if (is_support_sw_smu(adev
))
1033 ret
= smu_force_clk_levels(&adev
->smu
, SMU_FCLK
, mask
);
1034 else if (adev
->powerplay
.pp_funcs
->force_clock_level
)
1035 ret
= amdgpu_dpm_force_clock_level(adev
, PP_FCLK
, mask
);
1043 static ssize_t
amdgpu_get_pp_dpm_dcefclk(struct device
*dev
,
1044 struct device_attribute
*attr
,
1047 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1048 struct amdgpu_device
*adev
= ddev
->dev_private
;
1050 if (is_support_sw_smu(adev
))
1051 return smu_print_clk_levels(&adev
->smu
, SMU_DCEFCLK
, buf
);
1052 else if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
1053 return amdgpu_dpm_print_clock_levels(adev
, PP_DCEFCLK
, buf
);
1055 return snprintf(buf
, PAGE_SIZE
, "\n");
1058 static ssize_t
amdgpu_set_pp_dpm_dcefclk(struct device
*dev
,
1059 struct device_attribute
*attr
,
1063 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1064 struct amdgpu_device
*adev
= ddev
->dev_private
;
1068 ret
= amdgpu_read_mask(buf
, count
, &mask
);
1072 if (is_support_sw_smu(adev
))
1073 ret
= smu_force_clk_levels(&adev
->smu
, SMU_DCEFCLK
, mask
);
1074 else if (adev
->powerplay
.pp_funcs
->force_clock_level
)
1075 ret
= amdgpu_dpm_force_clock_level(adev
, PP_DCEFCLK
, mask
);
1083 static ssize_t
amdgpu_get_pp_dpm_pcie(struct device
*dev
,
1084 struct device_attribute
*attr
,
1087 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1088 struct amdgpu_device
*adev
= ddev
->dev_private
;
1090 if (is_support_sw_smu(adev
))
1091 return smu_print_clk_levels(&adev
->smu
, SMU_PCIE
, buf
);
1092 else if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
1093 return amdgpu_dpm_print_clock_levels(adev
, PP_PCIE
, buf
);
1095 return snprintf(buf
, PAGE_SIZE
, "\n");
1098 static ssize_t
amdgpu_set_pp_dpm_pcie(struct device
*dev
,
1099 struct device_attribute
*attr
,
1103 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1104 struct amdgpu_device
*adev
= ddev
->dev_private
;
1108 ret
= amdgpu_read_mask(buf
, count
, &mask
);
1112 if (is_support_sw_smu(adev
))
1113 ret
= smu_force_clk_levels(&adev
->smu
, SMU_PCIE
, mask
);
1114 else if (adev
->powerplay
.pp_funcs
->force_clock_level
)
1115 ret
= amdgpu_dpm_force_clock_level(adev
, PP_PCIE
, mask
);
1123 static ssize_t
amdgpu_get_pp_sclk_od(struct device
*dev
,
1124 struct device_attribute
*attr
,
1127 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1128 struct amdgpu_device
*adev
= ddev
->dev_private
;
1131 if (is_support_sw_smu(adev
))
1132 value
= smu_get_od_percentage(&(adev
->smu
), SMU_OD_SCLK
);
1133 else if (adev
->powerplay
.pp_funcs
->get_sclk_od
)
1134 value
= amdgpu_dpm_get_sclk_od(adev
);
1136 return snprintf(buf
, PAGE_SIZE
, "%d\n", value
);
1139 static ssize_t
amdgpu_set_pp_sclk_od(struct device
*dev
,
1140 struct device_attribute
*attr
,
1144 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1145 struct amdgpu_device
*adev
= ddev
->dev_private
;
1149 ret
= kstrtol(buf
, 0, &value
);
1156 if (is_support_sw_smu(adev
)) {
1157 value
= smu_set_od_percentage(&(adev
->smu
), SMU_OD_SCLK
, (uint32_t)value
);
1159 if (adev
->powerplay
.pp_funcs
->set_sclk_od
)
1160 amdgpu_dpm_set_sclk_od(adev
, (uint32_t)value
);
1162 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
1163 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_READJUST_POWER_STATE
, NULL
);
1165 adev
->pm
.dpm
.current_ps
= adev
->pm
.dpm
.boot_ps
;
1166 amdgpu_pm_compute_clocks(adev
);
1174 static ssize_t
amdgpu_get_pp_mclk_od(struct device
*dev
,
1175 struct device_attribute
*attr
,
1178 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1179 struct amdgpu_device
*adev
= ddev
->dev_private
;
1182 if (is_support_sw_smu(adev
))
1183 value
= smu_get_od_percentage(&(adev
->smu
), SMU_OD_MCLK
);
1184 else if (adev
->powerplay
.pp_funcs
->get_mclk_od
)
1185 value
= amdgpu_dpm_get_mclk_od(adev
);
1187 return snprintf(buf
, PAGE_SIZE
, "%d\n", value
);
1190 static ssize_t
amdgpu_set_pp_mclk_od(struct device
*dev
,
1191 struct device_attribute
*attr
,
1195 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1196 struct amdgpu_device
*adev
= ddev
->dev_private
;
1200 ret
= kstrtol(buf
, 0, &value
);
1207 if (is_support_sw_smu(adev
)) {
1208 value
= smu_set_od_percentage(&(adev
->smu
), SMU_OD_MCLK
, (uint32_t)value
);
1210 if (adev
->powerplay
.pp_funcs
->set_mclk_od
)
1211 amdgpu_dpm_set_mclk_od(adev
, (uint32_t)value
);
1213 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
1214 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_READJUST_POWER_STATE
, NULL
);
1216 adev
->pm
.dpm
.current_ps
= adev
->pm
.dpm
.boot_ps
;
1217 amdgpu_pm_compute_clocks(adev
);
1226 * DOC: pp_power_profile_mode
1228 * The amdgpu driver provides a sysfs API for adjusting the heuristics
1229 * related to switching between power levels in a power state. The file
1230 * pp_power_profile_mode is used for this.
1232 * Reading this file outputs a list of all of the predefined power profiles
1233 * and the relevant heuristics settings for that profile.
1235 * To select a profile or create a custom profile, first select manual using
1236 * power_dpm_force_performance_level. Writing the number of a predefined
1237 * profile to pp_power_profile_mode will enable those heuristics. To
1238 * create a custom set of heuristics, write a string of numbers to the file
1239 * starting with the number of the custom profile along with a setting
1240 * for each heuristic parameter. Due to differences across asic families
1241 * the heuristic parameters vary from family to family.
1245 static ssize_t
amdgpu_get_pp_power_profile_mode(struct device
*dev
,
1246 struct device_attribute
*attr
,
1249 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1250 struct amdgpu_device
*adev
= ddev
->dev_private
;
1252 if (is_support_sw_smu(adev
))
1253 return smu_get_power_profile_mode(&adev
->smu
, buf
);
1254 else if (adev
->powerplay
.pp_funcs
->get_power_profile_mode
)
1255 return amdgpu_dpm_get_power_profile_mode(adev
, buf
);
1257 return snprintf(buf
, PAGE_SIZE
, "\n");
1261 static ssize_t
amdgpu_set_pp_power_profile_mode(struct device
*dev
,
1262 struct device_attribute
*attr
,
1267 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1268 struct amdgpu_device
*adev
= ddev
->dev_private
;
1269 uint32_t parameter_size
= 0;
1271 char *sub_str
, buf_cpy
[128];
1275 long int profile_mode
= 0;
1276 const char delimiter
[3] = {' ', '\n', '\0'};
1280 ret
= kstrtol(tmp
, 0, &profile_mode
);
1284 if (profile_mode
== PP_SMC_POWER_PROFILE_CUSTOM
) {
1285 if (count
< 2 || count
> 127)
1287 while (isspace(*++buf
))
1289 memcpy(buf_cpy
, buf
, count
-i
);
1291 while (tmp_str
[0]) {
1292 sub_str
= strsep(&tmp_str
, delimiter
);
1293 ret
= kstrtol(sub_str
, 0, ¶meter
[parameter_size
]);
1299 while (isspace(*tmp_str
))
1303 parameter
[parameter_size
] = profile_mode
;
1304 if (is_support_sw_smu(adev
))
1305 ret
= smu_set_power_profile_mode(&adev
->smu
, parameter
, parameter_size
);
1306 else if (adev
->powerplay
.pp_funcs
->set_power_profile_mode
)
1307 ret
= amdgpu_dpm_set_power_profile_mode(adev
, parameter
, parameter_size
);
1317 * The amdgpu driver provides a sysfs API for reading how busy the GPU
1318 * is as a percentage. The file gpu_busy_percent is used for this.
1319 * The SMU firmware computes a percentage of load based on the
1320 * aggregate activity level in the IP cores.
1322 static ssize_t
amdgpu_get_busy_percent(struct device
*dev
,
1323 struct device_attribute
*attr
,
1326 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1327 struct amdgpu_device
*adev
= ddev
->dev_private
;
1328 int r
, value
, size
= sizeof(value
);
1330 /* read the IP busy sensor */
1331 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_LOAD
,
1332 (void *)&value
, &size
);
1337 return snprintf(buf
, PAGE_SIZE
, "%d\n", value
);
1341 * DOC: mem_busy_percent
1343 * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1344 * is as a percentage. The file mem_busy_percent is used for this.
1345 * The SMU firmware computes a percentage of load based on the
1346 * aggregate activity level in the IP cores.
1348 static ssize_t
amdgpu_get_memory_busy_percent(struct device
*dev
,
1349 struct device_attribute
*attr
,
1352 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1353 struct amdgpu_device
*adev
= ddev
->dev_private
;
1354 int r
, value
, size
= sizeof(value
);
1356 /* read the IP busy sensor */
1357 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_MEM_LOAD
,
1358 (void *)&value
, &size
);
1363 return snprintf(buf
, PAGE_SIZE
, "%d\n", value
);
1369 * The amdgpu driver provides a sysfs API for estimating how much data
1370 * has been received and sent by the GPU in the last second through PCIe.
1371 * The file pcie_bw is used for this.
1372 * The Perf counters count the number of received and sent messages and return
1373 * those values, as well as the maximum payload size of a PCIe packet (mps).
1374 * Note that it is not possible to easily and quickly obtain the size of each
1375 * packet transmitted, so we output the max payload size (mps) to allow for
1376 * quick estimation of the PCIe bandwidth usage
1378 static ssize_t
amdgpu_get_pcie_bw(struct device
*dev
,
1379 struct device_attribute
*attr
,
1382 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1383 struct amdgpu_device
*adev
= ddev
->dev_private
;
1384 uint64_t count0
, count1
;
1386 amdgpu_asic_get_pcie_usage(adev
, &count0
, &count1
);
1387 return snprintf(buf
, PAGE_SIZE
, "%llu %llu %i\n",
1388 count0
, count1
, pcie_get_mps(adev
->pdev
));
1394 * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1395 * The file unique_id is used for this.
1396 * This will provide a Unique ID that will persist from machine to machine
1398 * NOTE: This will only work for GFX9 and newer. This file will be absent
1399 * on unsupported ASICs (GFX8 and older)
1401 static ssize_t
amdgpu_get_unique_id(struct device
*dev
,
1402 struct device_attribute
*attr
,
1405 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1406 struct amdgpu_device
*adev
= ddev
->dev_private
;
1408 if (adev
->unique_id
)
1409 return snprintf(buf
, PAGE_SIZE
, "%016llx\n", adev
->unique_id
);
1414 static DEVICE_ATTR(power_dpm_state
, S_IRUGO
| S_IWUSR
, amdgpu_get_dpm_state
, amdgpu_set_dpm_state
);
1415 static DEVICE_ATTR(power_dpm_force_performance_level
, S_IRUGO
| S_IWUSR
,
1416 amdgpu_get_dpm_forced_performance_level
,
1417 amdgpu_set_dpm_forced_performance_level
);
1418 static DEVICE_ATTR(pp_num_states
, S_IRUGO
, amdgpu_get_pp_num_states
, NULL
);
1419 static DEVICE_ATTR(pp_cur_state
, S_IRUGO
, amdgpu_get_pp_cur_state
, NULL
);
1420 static DEVICE_ATTR(pp_force_state
, S_IRUGO
| S_IWUSR
,
1421 amdgpu_get_pp_force_state
,
1422 amdgpu_set_pp_force_state
);
1423 static DEVICE_ATTR(pp_table
, S_IRUGO
| S_IWUSR
,
1424 amdgpu_get_pp_table
,
1425 amdgpu_set_pp_table
);
1426 static DEVICE_ATTR(pp_dpm_sclk
, S_IRUGO
| S_IWUSR
,
1427 amdgpu_get_pp_dpm_sclk
,
1428 amdgpu_set_pp_dpm_sclk
);
1429 static DEVICE_ATTR(pp_dpm_mclk
, S_IRUGO
| S_IWUSR
,
1430 amdgpu_get_pp_dpm_mclk
,
1431 amdgpu_set_pp_dpm_mclk
);
1432 static DEVICE_ATTR(pp_dpm_socclk
, S_IRUGO
| S_IWUSR
,
1433 amdgpu_get_pp_dpm_socclk
,
1434 amdgpu_set_pp_dpm_socclk
);
1435 static DEVICE_ATTR(pp_dpm_fclk
, S_IRUGO
| S_IWUSR
,
1436 amdgpu_get_pp_dpm_fclk
,
1437 amdgpu_set_pp_dpm_fclk
);
1438 static DEVICE_ATTR(pp_dpm_dcefclk
, S_IRUGO
| S_IWUSR
,
1439 amdgpu_get_pp_dpm_dcefclk
,
1440 amdgpu_set_pp_dpm_dcefclk
);
1441 static DEVICE_ATTR(pp_dpm_pcie
, S_IRUGO
| S_IWUSR
,
1442 amdgpu_get_pp_dpm_pcie
,
1443 amdgpu_set_pp_dpm_pcie
);
1444 static DEVICE_ATTR(pp_sclk_od
, S_IRUGO
| S_IWUSR
,
1445 amdgpu_get_pp_sclk_od
,
1446 amdgpu_set_pp_sclk_od
);
1447 static DEVICE_ATTR(pp_mclk_od
, S_IRUGO
| S_IWUSR
,
1448 amdgpu_get_pp_mclk_od
,
1449 amdgpu_set_pp_mclk_od
);
1450 static DEVICE_ATTR(pp_power_profile_mode
, S_IRUGO
| S_IWUSR
,
1451 amdgpu_get_pp_power_profile_mode
,
1452 amdgpu_set_pp_power_profile_mode
);
1453 static DEVICE_ATTR(pp_od_clk_voltage
, S_IRUGO
| S_IWUSR
,
1454 amdgpu_get_pp_od_clk_voltage
,
1455 amdgpu_set_pp_od_clk_voltage
);
1456 static DEVICE_ATTR(gpu_busy_percent
, S_IRUGO
,
1457 amdgpu_get_busy_percent
, NULL
);
1458 static DEVICE_ATTR(mem_busy_percent
, S_IRUGO
,
1459 amdgpu_get_memory_busy_percent
, NULL
);
1460 static DEVICE_ATTR(pcie_bw
, S_IRUGO
, amdgpu_get_pcie_bw
, NULL
);
1461 static DEVICE_ATTR(ppfeatures
, S_IRUGO
| S_IWUSR
,
1462 amdgpu_get_ppfeature_status
,
1463 amdgpu_set_ppfeature_status
);
1464 static DEVICE_ATTR(unique_id
, S_IRUGO
, amdgpu_get_unique_id
, NULL
);
1466 static ssize_t
amdgpu_hwmon_show_temp(struct device
*dev
,
1467 struct device_attribute
*attr
,
1470 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1471 struct drm_device
*ddev
= adev
->ddev
;
1472 int channel
= to_sensor_dev_attr(attr
)->index
;
1473 int r
, temp
= 0, size
= sizeof(temp
);
1475 /* Can't get temperature when the card is off */
1476 if ((adev
->flags
& AMD_IS_PX
) &&
1477 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1480 if (channel
>= PP_TEMP_MAX
)
1484 case PP_TEMP_JUNCTION
:
1485 /* get current junction temperature */
1486 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_HOTSPOT_TEMP
,
1487 (void *)&temp
, &size
);
1492 /* get current edge temperature */
1493 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_EDGE_TEMP
,
1494 (void *)&temp
, &size
);
1499 /* get current memory temperature */
1500 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_MEM_TEMP
,
1501 (void *)&temp
, &size
);
1507 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
1510 static ssize_t
amdgpu_hwmon_show_temp_thresh(struct device
*dev
,
1511 struct device_attribute
*attr
,
1514 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1515 int hyst
= to_sensor_dev_attr(attr
)->index
;
1519 temp
= adev
->pm
.dpm
.thermal
.min_temp
;
1521 temp
= adev
->pm
.dpm
.thermal
.max_temp
;
1523 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
1526 static ssize_t
amdgpu_hwmon_show_hotspot_temp_thresh(struct device
*dev
,
1527 struct device_attribute
*attr
,
1530 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1531 int hyst
= to_sensor_dev_attr(attr
)->index
;
1535 temp
= adev
->pm
.dpm
.thermal
.min_hotspot_temp
;
1537 temp
= adev
->pm
.dpm
.thermal
.max_hotspot_crit_temp
;
1539 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
1542 static ssize_t
amdgpu_hwmon_show_mem_temp_thresh(struct device
*dev
,
1543 struct device_attribute
*attr
,
1546 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1547 int hyst
= to_sensor_dev_attr(attr
)->index
;
1551 temp
= adev
->pm
.dpm
.thermal
.min_mem_temp
;
1553 temp
= adev
->pm
.dpm
.thermal
.max_mem_crit_temp
;
1555 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
1558 static ssize_t
amdgpu_hwmon_show_temp_label(struct device
*dev
,
1559 struct device_attribute
*attr
,
1562 int channel
= to_sensor_dev_attr(attr
)->index
;
1564 if (channel
>= PP_TEMP_MAX
)
1567 return snprintf(buf
, PAGE_SIZE
, "%s\n", temp_label
[channel
].label
);
1570 static ssize_t
amdgpu_hwmon_show_temp_emergency(struct device
*dev
,
1571 struct device_attribute
*attr
,
1574 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1575 int channel
= to_sensor_dev_attr(attr
)->index
;
1578 if (channel
>= PP_TEMP_MAX
)
1582 case PP_TEMP_JUNCTION
:
1583 temp
= adev
->pm
.dpm
.thermal
.max_hotspot_emergency_temp
;
1586 temp
= adev
->pm
.dpm
.thermal
.max_edge_emergency_temp
;
1589 temp
= adev
->pm
.dpm
.thermal
.max_mem_emergency_temp
;
1593 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
1596 static ssize_t
amdgpu_hwmon_get_pwm1_enable(struct device
*dev
,
1597 struct device_attribute
*attr
,
1600 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1602 if (is_support_sw_smu(adev
)) {
1603 pwm_mode
= smu_get_fan_control_mode(&adev
->smu
);
1605 if (!adev
->powerplay
.pp_funcs
->get_fan_control_mode
)
1608 pwm_mode
= amdgpu_dpm_get_fan_control_mode(adev
);
1611 return sprintf(buf
, "%i\n", pwm_mode
);
1614 static ssize_t
amdgpu_hwmon_set_pwm1_enable(struct device
*dev
,
1615 struct device_attribute
*attr
,
1619 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1623 /* Can't adjust fan when the card is off */
1624 if ((adev
->flags
& AMD_IS_PX
) &&
1625 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1628 if (is_support_sw_smu(adev
)) {
1629 err
= kstrtoint(buf
, 10, &value
);
1633 smu_set_fan_control_mode(&adev
->smu
, value
);
1635 if (!adev
->powerplay
.pp_funcs
->set_fan_control_mode
)
1638 err
= kstrtoint(buf
, 10, &value
);
1642 amdgpu_dpm_set_fan_control_mode(adev
, value
);
1648 static ssize_t
amdgpu_hwmon_get_pwm1_min(struct device
*dev
,
1649 struct device_attribute
*attr
,
1652 return sprintf(buf
, "%i\n", 0);
1655 static ssize_t
amdgpu_hwmon_get_pwm1_max(struct device
*dev
,
1656 struct device_attribute
*attr
,
1659 return sprintf(buf
, "%i\n", 255);
1662 static ssize_t
amdgpu_hwmon_set_pwm1(struct device
*dev
,
1663 struct device_attribute
*attr
,
1664 const char *buf
, size_t count
)
1666 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1671 /* Can't adjust fan when the card is off */
1672 if ((adev
->flags
& AMD_IS_PX
) &&
1673 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1675 if (is_support_sw_smu(adev
))
1676 pwm_mode
= smu_get_fan_control_mode(&adev
->smu
);
1678 pwm_mode
= amdgpu_dpm_get_fan_control_mode(adev
);
1679 if (pwm_mode
!= AMD_FAN_CTRL_MANUAL
) {
1680 pr_info("manual fan speed control should be enabled first\n");
1684 err
= kstrtou32(buf
, 10, &value
);
1688 value
= (value
* 100) / 255;
1690 if (is_support_sw_smu(adev
)) {
1691 err
= smu_set_fan_speed_percent(&adev
->smu
, value
);
1694 } else if (adev
->powerplay
.pp_funcs
->set_fan_speed_percent
) {
1695 err
= amdgpu_dpm_set_fan_speed_percent(adev
, value
);
1703 static ssize_t
amdgpu_hwmon_get_pwm1(struct device
*dev
,
1704 struct device_attribute
*attr
,
1707 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1711 /* Can't adjust fan when the card is off */
1712 if ((adev
->flags
& AMD_IS_PX
) &&
1713 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1716 if (is_support_sw_smu(adev
)) {
1717 err
= smu_get_fan_speed_percent(&adev
->smu
, &speed
);
1720 } else if (adev
->powerplay
.pp_funcs
->get_fan_speed_percent
) {
1721 err
= amdgpu_dpm_get_fan_speed_percent(adev
, &speed
);
1726 speed
= (speed
* 255) / 100;
1728 return sprintf(buf
, "%i\n", speed
);
1731 static ssize_t
amdgpu_hwmon_get_fan1_input(struct device
*dev
,
1732 struct device_attribute
*attr
,
1735 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1739 /* Can't adjust fan when the card is off */
1740 if ((adev
->flags
& AMD_IS_PX
) &&
1741 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1744 if (is_support_sw_smu(adev
)) {
1745 err
= smu_get_fan_speed_rpm(&adev
->smu
, &speed
);
1748 } else if (adev
->powerplay
.pp_funcs
->get_fan_speed_rpm
) {
1749 err
= amdgpu_dpm_get_fan_speed_rpm(adev
, &speed
);
1754 return sprintf(buf
, "%i\n", speed
);
1757 static ssize_t
amdgpu_hwmon_get_fan1_min(struct device
*dev
,
1758 struct device_attribute
*attr
,
1761 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1763 u32 size
= sizeof(min_rpm
);
1766 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_MIN_FAN_RPM
,
1767 (void *)&min_rpm
, &size
);
1771 return snprintf(buf
, PAGE_SIZE
, "%d\n", min_rpm
);
1774 static ssize_t
amdgpu_hwmon_get_fan1_max(struct device
*dev
,
1775 struct device_attribute
*attr
,
1778 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1780 u32 size
= sizeof(max_rpm
);
1783 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_MAX_FAN_RPM
,
1784 (void *)&max_rpm
, &size
);
1788 return snprintf(buf
, PAGE_SIZE
, "%d\n", max_rpm
);
1791 static ssize_t
amdgpu_hwmon_get_fan1_target(struct device
*dev
,
1792 struct device_attribute
*attr
,
1795 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1799 /* Can't adjust fan when the card is off */
1800 if ((adev
->flags
& AMD_IS_PX
) &&
1801 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1804 if (is_support_sw_smu(adev
)) {
1805 err
= smu_get_fan_speed_rpm(&adev
->smu
, &rpm
);
1808 } else if (adev
->powerplay
.pp_funcs
->get_fan_speed_rpm
) {
1809 err
= amdgpu_dpm_get_fan_speed_rpm(adev
, &rpm
);
1814 return sprintf(buf
, "%i\n", rpm
);
1817 static ssize_t
amdgpu_hwmon_set_fan1_target(struct device
*dev
,
1818 struct device_attribute
*attr
,
1819 const char *buf
, size_t count
)
1821 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1826 if (is_support_sw_smu(adev
))
1827 pwm_mode
= smu_get_fan_control_mode(&adev
->smu
);
1829 pwm_mode
= amdgpu_dpm_get_fan_control_mode(adev
);
1831 if (pwm_mode
!= AMD_FAN_CTRL_MANUAL
)
1834 /* Can't adjust fan when the card is off */
1835 if ((adev
->flags
& AMD_IS_PX
) &&
1836 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1839 err
= kstrtou32(buf
, 10, &value
);
1843 if (is_support_sw_smu(adev
)) {
1844 err
= smu_set_fan_speed_rpm(&adev
->smu
, value
);
1847 } else if (adev
->powerplay
.pp_funcs
->set_fan_speed_rpm
) {
1848 err
= amdgpu_dpm_set_fan_speed_rpm(adev
, value
);
1856 static ssize_t
amdgpu_hwmon_get_fan1_enable(struct device
*dev
,
1857 struct device_attribute
*attr
,
1860 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1863 if (is_support_sw_smu(adev
)) {
1864 pwm_mode
= smu_get_fan_control_mode(&adev
->smu
);
1866 if (!adev
->powerplay
.pp_funcs
->get_fan_control_mode
)
1869 pwm_mode
= amdgpu_dpm_get_fan_control_mode(adev
);
1871 return sprintf(buf
, "%i\n", pwm_mode
== AMD_FAN_CTRL_AUTO
? 0 : 1);
1874 static ssize_t
amdgpu_hwmon_set_fan1_enable(struct device
*dev
,
1875 struct device_attribute
*attr
,
1879 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1884 /* Can't adjust fan when the card is off */
1885 if ((adev
->flags
& AMD_IS_PX
) &&
1886 (adev
->ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1890 err
= kstrtoint(buf
, 10, &value
);
1895 pwm_mode
= AMD_FAN_CTRL_AUTO
;
1896 else if (value
== 1)
1897 pwm_mode
= AMD_FAN_CTRL_MANUAL
;
1901 if (is_support_sw_smu(adev
)) {
1902 smu_set_fan_control_mode(&adev
->smu
, pwm_mode
);
1904 if (!adev
->powerplay
.pp_funcs
->set_fan_control_mode
)
1906 amdgpu_dpm_set_fan_control_mode(adev
, pwm_mode
);
1912 static ssize_t
amdgpu_hwmon_show_vddgfx(struct device
*dev
,
1913 struct device_attribute
*attr
,
1916 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1917 struct drm_device
*ddev
= adev
->ddev
;
1919 int r
, size
= sizeof(vddgfx
);
1921 /* Can't get voltage when the card is off */
1922 if ((adev
->flags
& AMD_IS_PX
) &&
1923 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1926 /* get the voltage */
1927 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDGFX
,
1928 (void *)&vddgfx
, &size
);
1932 return snprintf(buf
, PAGE_SIZE
, "%d\n", vddgfx
);
1935 static ssize_t
amdgpu_hwmon_show_vddgfx_label(struct device
*dev
,
1936 struct device_attribute
*attr
,
1939 return snprintf(buf
, PAGE_SIZE
, "vddgfx\n");
1942 static ssize_t
amdgpu_hwmon_show_vddnb(struct device
*dev
,
1943 struct device_attribute
*attr
,
1946 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1947 struct drm_device
*ddev
= adev
->ddev
;
1949 int r
, size
= sizeof(vddnb
);
1951 /* only APUs have vddnb */
1952 if (!(adev
->flags
& AMD_IS_APU
))
1955 /* Can't get voltage when the card is off */
1956 if ((adev
->flags
& AMD_IS_PX
) &&
1957 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1960 /* get the voltage */
1961 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDNB
,
1962 (void *)&vddnb
, &size
);
1966 return snprintf(buf
, PAGE_SIZE
, "%d\n", vddnb
);
1969 static ssize_t
amdgpu_hwmon_show_vddnb_label(struct device
*dev
,
1970 struct device_attribute
*attr
,
1973 return snprintf(buf
, PAGE_SIZE
, "vddnb\n");
1976 static ssize_t
amdgpu_hwmon_show_power_avg(struct device
*dev
,
1977 struct device_attribute
*attr
,
1980 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
1981 struct drm_device
*ddev
= adev
->ddev
;
1983 int r
, size
= sizeof(u32
);
1986 /* Can't get power when the card is off */
1987 if ((adev
->flags
& AMD_IS_PX
) &&
1988 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
1991 /* get the voltage */
1992 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_POWER
,
1993 (void *)&query
, &size
);
1997 /* convert to microwatts */
1998 uw
= (query
>> 8) * 1000000 + (query
& 0xff) * 1000;
2000 return snprintf(buf
, PAGE_SIZE
, "%u\n", uw
);
2003 static ssize_t
amdgpu_hwmon_show_power_cap_min(struct device
*dev
,
2004 struct device_attribute
*attr
,
2007 return sprintf(buf
, "%i\n", 0);
2010 static ssize_t
amdgpu_hwmon_show_power_cap_max(struct device
*dev
,
2011 struct device_attribute
*attr
,
2014 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
2017 if (is_support_sw_smu(adev
)) {
2018 smu_get_power_limit(&adev
->smu
, &limit
, true);
2019 return snprintf(buf
, PAGE_SIZE
, "%u\n", limit
* 1000000);
2020 } else if (adev
->powerplay
.pp_funcs
&& adev
->powerplay
.pp_funcs
->get_power_limit
) {
2021 adev
->powerplay
.pp_funcs
->get_power_limit(adev
->powerplay
.pp_handle
, &limit
, true);
2022 return snprintf(buf
, PAGE_SIZE
, "%u\n", limit
* 1000000);
2024 return snprintf(buf
, PAGE_SIZE
, "\n");
2028 static ssize_t
amdgpu_hwmon_show_power_cap(struct device
*dev
,
2029 struct device_attribute
*attr
,
2032 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
2035 if (is_support_sw_smu(adev
)) {
2036 smu_get_power_limit(&adev
->smu
, &limit
, false);
2037 return snprintf(buf
, PAGE_SIZE
, "%u\n", limit
* 1000000);
2038 } else if (adev
->powerplay
.pp_funcs
&& adev
->powerplay
.pp_funcs
->get_power_limit
) {
2039 adev
->powerplay
.pp_funcs
->get_power_limit(adev
->powerplay
.pp_handle
, &limit
, false);
2040 return snprintf(buf
, PAGE_SIZE
, "%u\n", limit
* 1000000);
2042 return snprintf(buf
, PAGE_SIZE
, "\n");
2047 static ssize_t
amdgpu_hwmon_set_power_cap(struct device
*dev
,
2048 struct device_attribute
*attr
,
2052 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
2056 err
= kstrtou32(buf
, 10, &value
);
2060 value
= value
/ 1000000; /* convert to Watt */
2061 if (is_support_sw_smu(adev
)) {
2062 adev
->smu
.funcs
->set_power_limit(&adev
->smu
, value
);
2063 } else if (adev
->powerplay
.pp_funcs
&& adev
->powerplay
.pp_funcs
->set_power_limit
) {
2064 err
= adev
->powerplay
.pp_funcs
->set_power_limit(adev
->powerplay
.pp_handle
, value
);
2074 static ssize_t
amdgpu_hwmon_show_sclk(struct device
*dev
,
2075 struct device_attribute
*attr
,
2078 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
2079 struct drm_device
*ddev
= adev
->ddev
;
2081 int r
, size
= sizeof(sclk
);
2083 /* Can't get voltage when the card is off */
2084 if ((adev
->flags
& AMD_IS_PX
) &&
2085 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
2089 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GFX_SCLK
,
2090 (void *)&sclk
, &size
);
2094 return snprintf(buf
, PAGE_SIZE
, "%d\n", sclk
* 10 * 1000);
2097 static ssize_t
amdgpu_hwmon_show_sclk_label(struct device
*dev
,
2098 struct device_attribute
*attr
,
2101 return snprintf(buf
, PAGE_SIZE
, "sclk\n");
2104 static ssize_t
amdgpu_hwmon_show_mclk(struct device
*dev
,
2105 struct device_attribute
*attr
,
2108 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
2109 struct drm_device
*ddev
= adev
->ddev
;
2111 int r
, size
= sizeof(mclk
);
2113 /* Can't get voltage when the card is off */
2114 if ((adev
->flags
& AMD_IS_PX
) &&
2115 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
2119 r
= amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GFX_MCLK
,
2120 (void *)&mclk
, &size
);
2124 return snprintf(buf
, PAGE_SIZE
, "%d\n", mclk
* 10 * 1000);
2127 static ssize_t
amdgpu_hwmon_show_mclk_label(struct device
*dev
,
2128 struct device_attribute
*attr
,
2131 return snprintf(buf
, PAGE_SIZE
, "mclk\n");
2137 * The amdgpu driver exposes the following sensor interfaces:
2139 * - GPU temperature (via the on-die sensor)
2143 * - Northbridge voltage (APUs only)
2149 * - GPU gfx/compute engine clock
2151 * - GPU memory clock (dGPU only)
2153 * hwmon interfaces for GPU temperature:
2155 * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
2156 * - temp2_input and temp3_input are supported on SOC15 dGPUs only
2158 * - temp[1-3]_label: temperature channel label
2159 * - temp2_label and temp3_label are supported on SOC15 dGPUs only
2161 * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
2162 * - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
2164 * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
2165 * - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
2167 * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
2168 * - these are supported on SOC15 dGPUs only
2170 * hwmon interfaces for GPU voltage:
2172 * - in0_input: the voltage on the GPU in millivolts
2174 * - in1_input: the voltage on the Northbridge in millivolts
2176 * hwmon interfaces for GPU power:
2178 * - power1_average: average power used by the GPU in microWatts
2180 * - power1_cap_min: minimum cap supported in microWatts
2182 * - power1_cap_max: maximum cap supported in microWatts
2184 * - power1_cap: selected power cap in microWatts
2186 * hwmon interfaces for GPU fan:
2188 * - pwm1: pulse width modulation fan level (0-255)
2190 * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
2192 * - pwm1_min: pulse width modulation fan control minimum level (0)
2194 * - pwm1_max: pulse width modulation fan control maximum level (255)
2196 * - fan1_min: an minimum value Unit: revolution/min (RPM)
2198 * - fan1_max: an maxmum value Unit: revolution/max (RPM)
2200 * - fan1_input: fan speed in RPM
2202 * - fan[1-*]_target: Desired fan speed Unit: revolution/min (RPM)
2204 * - fan[1-*]_enable: Enable or disable the sensors.1: Enable 0: Disable
2206 * hwmon interfaces for GPU clocks:
2208 * - freq1_input: the gfx/compute clock in hertz
2210 * - freq2_input: the memory clock in hertz
2212 * You can use hwmon tools like sensors to view this information on your system.
2216 static SENSOR_DEVICE_ATTR(temp1_input
, S_IRUGO
, amdgpu_hwmon_show_temp
, NULL
, PP_TEMP_EDGE
);
2217 static SENSOR_DEVICE_ATTR(temp1_crit
, S_IRUGO
, amdgpu_hwmon_show_temp_thresh
, NULL
, 0);
2218 static SENSOR_DEVICE_ATTR(temp1_crit_hyst
, S_IRUGO
, amdgpu_hwmon_show_temp_thresh
, NULL
, 1);
2219 static SENSOR_DEVICE_ATTR(temp1_emergency
, S_IRUGO
, amdgpu_hwmon_show_temp_emergency
, NULL
, PP_TEMP_EDGE
);
2220 static SENSOR_DEVICE_ATTR(temp2_input
, S_IRUGO
, amdgpu_hwmon_show_temp
, NULL
, PP_TEMP_JUNCTION
);
2221 static SENSOR_DEVICE_ATTR(temp2_crit
, S_IRUGO
, amdgpu_hwmon_show_hotspot_temp_thresh
, NULL
, 0);
2222 static SENSOR_DEVICE_ATTR(temp2_crit_hyst
, S_IRUGO
, amdgpu_hwmon_show_hotspot_temp_thresh
, NULL
, 1);
2223 static SENSOR_DEVICE_ATTR(temp2_emergency
, S_IRUGO
, amdgpu_hwmon_show_temp_emergency
, NULL
, PP_TEMP_JUNCTION
);
2224 static SENSOR_DEVICE_ATTR(temp3_input
, S_IRUGO
, amdgpu_hwmon_show_temp
, NULL
, PP_TEMP_MEM
);
2225 static SENSOR_DEVICE_ATTR(temp3_crit
, S_IRUGO
, amdgpu_hwmon_show_mem_temp_thresh
, NULL
, 0);
2226 static SENSOR_DEVICE_ATTR(temp3_crit_hyst
, S_IRUGO
, amdgpu_hwmon_show_mem_temp_thresh
, NULL
, 1);
2227 static SENSOR_DEVICE_ATTR(temp3_emergency
, S_IRUGO
, amdgpu_hwmon_show_temp_emergency
, NULL
, PP_TEMP_MEM
);
2228 static SENSOR_DEVICE_ATTR(temp1_label
, S_IRUGO
, amdgpu_hwmon_show_temp_label
, NULL
, PP_TEMP_EDGE
);
2229 static SENSOR_DEVICE_ATTR(temp2_label
, S_IRUGO
, amdgpu_hwmon_show_temp_label
, NULL
, PP_TEMP_JUNCTION
);
2230 static SENSOR_DEVICE_ATTR(temp3_label
, S_IRUGO
, amdgpu_hwmon_show_temp_label
, NULL
, PP_TEMP_MEM
);
2231 static SENSOR_DEVICE_ATTR(pwm1
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_get_pwm1
, amdgpu_hwmon_set_pwm1
, 0);
2232 static SENSOR_DEVICE_ATTR(pwm1_enable
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_get_pwm1_enable
, amdgpu_hwmon_set_pwm1_enable
, 0);
2233 static SENSOR_DEVICE_ATTR(pwm1_min
, S_IRUGO
, amdgpu_hwmon_get_pwm1_min
, NULL
, 0);
2234 static SENSOR_DEVICE_ATTR(pwm1_max
, S_IRUGO
, amdgpu_hwmon_get_pwm1_max
, NULL
, 0);
2235 static SENSOR_DEVICE_ATTR(fan1_input
, S_IRUGO
, amdgpu_hwmon_get_fan1_input
, NULL
, 0);
2236 static SENSOR_DEVICE_ATTR(fan1_min
, S_IRUGO
, amdgpu_hwmon_get_fan1_min
, NULL
, 0);
2237 static SENSOR_DEVICE_ATTR(fan1_max
, S_IRUGO
, amdgpu_hwmon_get_fan1_max
, NULL
, 0);
2238 static SENSOR_DEVICE_ATTR(fan1_target
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_get_fan1_target
, amdgpu_hwmon_set_fan1_target
, 0);
2239 static SENSOR_DEVICE_ATTR(fan1_enable
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_get_fan1_enable
, amdgpu_hwmon_set_fan1_enable
, 0);
2240 static SENSOR_DEVICE_ATTR(in0_input
, S_IRUGO
, amdgpu_hwmon_show_vddgfx
, NULL
, 0);
2241 static SENSOR_DEVICE_ATTR(in0_label
, S_IRUGO
, amdgpu_hwmon_show_vddgfx_label
, NULL
, 0);
2242 static SENSOR_DEVICE_ATTR(in1_input
, S_IRUGO
, amdgpu_hwmon_show_vddnb
, NULL
, 0);
2243 static SENSOR_DEVICE_ATTR(in1_label
, S_IRUGO
, amdgpu_hwmon_show_vddnb_label
, NULL
, 0);
2244 static SENSOR_DEVICE_ATTR(power1_average
, S_IRUGO
, amdgpu_hwmon_show_power_avg
, NULL
, 0);
2245 static SENSOR_DEVICE_ATTR(power1_cap_max
, S_IRUGO
, amdgpu_hwmon_show_power_cap_max
, NULL
, 0);
2246 static SENSOR_DEVICE_ATTR(power1_cap_min
, S_IRUGO
, amdgpu_hwmon_show_power_cap_min
, NULL
, 0);
2247 static SENSOR_DEVICE_ATTR(power1_cap
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_show_power_cap
, amdgpu_hwmon_set_power_cap
, 0);
2248 static SENSOR_DEVICE_ATTR(freq1_input
, S_IRUGO
, amdgpu_hwmon_show_sclk
, NULL
, 0);
2249 static SENSOR_DEVICE_ATTR(freq1_label
, S_IRUGO
, amdgpu_hwmon_show_sclk_label
, NULL
, 0);
2250 static SENSOR_DEVICE_ATTR(freq2_input
, S_IRUGO
, amdgpu_hwmon_show_mclk
, NULL
, 0);
2251 static SENSOR_DEVICE_ATTR(freq2_label
, S_IRUGO
, amdgpu_hwmon_show_mclk_label
, NULL
, 0);
2253 static struct attribute
*hwmon_attributes
[] = {
2254 &sensor_dev_attr_temp1_input
.dev_attr
.attr
,
2255 &sensor_dev_attr_temp1_crit
.dev_attr
.attr
,
2256 &sensor_dev_attr_temp1_crit_hyst
.dev_attr
.attr
,
2257 &sensor_dev_attr_temp2_input
.dev_attr
.attr
,
2258 &sensor_dev_attr_temp2_crit
.dev_attr
.attr
,
2259 &sensor_dev_attr_temp2_crit_hyst
.dev_attr
.attr
,
2260 &sensor_dev_attr_temp3_input
.dev_attr
.attr
,
2261 &sensor_dev_attr_temp3_crit
.dev_attr
.attr
,
2262 &sensor_dev_attr_temp3_crit_hyst
.dev_attr
.attr
,
2263 &sensor_dev_attr_temp1_emergency
.dev_attr
.attr
,
2264 &sensor_dev_attr_temp2_emergency
.dev_attr
.attr
,
2265 &sensor_dev_attr_temp3_emergency
.dev_attr
.attr
,
2266 &sensor_dev_attr_temp1_label
.dev_attr
.attr
,
2267 &sensor_dev_attr_temp2_label
.dev_attr
.attr
,
2268 &sensor_dev_attr_temp3_label
.dev_attr
.attr
,
2269 &sensor_dev_attr_pwm1
.dev_attr
.attr
,
2270 &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
,
2271 &sensor_dev_attr_pwm1_min
.dev_attr
.attr
,
2272 &sensor_dev_attr_pwm1_max
.dev_attr
.attr
,
2273 &sensor_dev_attr_fan1_input
.dev_attr
.attr
,
2274 &sensor_dev_attr_fan1_min
.dev_attr
.attr
,
2275 &sensor_dev_attr_fan1_max
.dev_attr
.attr
,
2276 &sensor_dev_attr_fan1_target
.dev_attr
.attr
,
2277 &sensor_dev_attr_fan1_enable
.dev_attr
.attr
,
2278 &sensor_dev_attr_in0_input
.dev_attr
.attr
,
2279 &sensor_dev_attr_in0_label
.dev_attr
.attr
,
2280 &sensor_dev_attr_in1_input
.dev_attr
.attr
,
2281 &sensor_dev_attr_in1_label
.dev_attr
.attr
,
2282 &sensor_dev_attr_power1_average
.dev_attr
.attr
,
2283 &sensor_dev_attr_power1_cap_max
.dev_attr
.attr
,
2284 &sensor_dev_attr_power1_cap_min
.dev_attr
.attr
,
2285 &sensor_dev_attr_power1_cap
.dev_attr
.attr
,
2286 &sensor_dev_attr_freq1_input
.dev_attr
.attr
,
2287 &sensor_dev_attr_freq1_label
.dev_attr
.attr
,
2288 &sensor_dev_attr_freq2_input
.dev_attr
.attr
,
2289 &sensor_dev_attr_freq2_label
.dev_attr
.attr
,
2293 static umode_t
hwmon_attributes_visible(struct kobject
*kobj
,
2294 struct attribute
*attr
, int index
)
2296 struct device
*dev
= kobj_to_dev(kobj
);
2297 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
2298 umode_t effective_mode
= attr
->mode
;
2300 /* Skip fan attributes if fan is not present */
2301 if (adev
->pm
.no_fan
&& (attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
||
2302 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
||
2303 attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
2304 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
||
2305 attr
== &sensor_dev_attr_fan1_input
.dev_attr
.attr
||
2306 attr
== &sensor_dev_attr_fan1_min
.dev_attr
.attr
||
2307 attr
== &sensor_dev_attr_fan1_max
.dev_attr
.attr
||
2308 attr
== &sensor_dev_attr_fan1_target
.dev_attr
.attr
||
2309 attr
== &sensor_dev_attr_fan1_enable
.dev_attr
.attr
))
2312 /* Skip fan attributes on APU */
2313 if ((adev
->flags
& AMD_IS_APU
) &&
2314 (attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
||
2315 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
||
2316 attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
2317 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
||
2318 attr
== &sensor_dev_attr_fan1_input
.dev_attr
.attr
||
2319 attr
== &sensor_dev_attr_fan1_min
.dev_attr
.attr
||
2320 attr
== &sensor_dev_attr_fan1_max
.dev_attr
.attr
||
2321 attr
== &sensor_dev_attr_fan1_target
.dev_attr
.attr
||
2322 attr
== &sensor_dev_attr_fan1_enable
.dev_attr
.attr
))
2325 /* Skip limit attributes if DPM is not enabled */
2326 if (!adev
->pm
.dpm_enabled
&&
2327 (attr
== &sensor_dev_attr_temp1_crit
.dev_attr
.attr
||
2328 attr
== &sensor_dev_attr_temp1_crit_hyst
.dev_attr
.attr
||
2329 attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
||
2330 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
||
2331 attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
2332 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
||
2333 attr
== &sensor_dev_attr_fan1_input
.dev_attr
.attr
||
2334 attr
== &sensor_dev_attr_fan1_min
.dev_attr
.attr
||
2335 attr
== &sensor_dev_attr_fan1_max
.dev_attr
.attr
||
2336 attr
== &sensor_dev_attr_fan1_target
.dev_attr
.attr
||
2337 attr
== &sensor_dev_attr_fan1_enable
.dev_attr
.attr
))
2340 if (!is_support_sw_smu(adev
)) {
2341 /* mask fan attributes if we have no bindings for this asic to expose */
2342 if ((!adev
->powerplay
.pp_funcs
->get_fan_speed_percent
&&
2343 attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
) || /* can't query fan */
2344 (!adev
->powerplay
.pp_funcs
->get_fan_control_mode
&&
2345 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
)) /* can't query state */
2346 effective_mode
&= ~S_IRUGO
;
2348 if ((!adev
->powerplay
.pp_funcs
->set_fan_speed_percent
&&
2349 attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
) || /* can't manage fan */
2350 (!adev
->powerplay
.pp_funcs
->set_fan_control_mode
&&
2351 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
)) /* can't manage state */
2352 effective_mode
&= ~S_IWUSR
;
2355 if ((adev
->flags
& AMD_IS_APU
) &&
2356 (attr
== &sensor_dev_attr_power1_average
.dev_attr
.attr
||
2357 attr
== &sensor_dev_attr_power1_cap_max
.dev_attr
.attr
||
2358 attr
== &sensor_dev_attr_power1_cap_min
.dev_attr
.attr
||
2359 attr
== &sensor_dev_attr_power1_cap
.dev_attr
.attr
))
2362 if (!is_support_sw_smu(adev
)) {
2363 /* hide max/min values if we can't both query and manage the fan */
2364 if ((!adev
->powerplay
.pp_funcs
->set_fan_speed_percent
&&
2365 !adev
->powerplay
.pp_funcs
->get_fan_speed_percent
) &&
2366 (!adev
->powerplay
.pp_funcs
->set_fan_speed_rpm
&&
2367 !adev
->powerplay
.pp_funcs
->get_fan_speed_rpm
) &&
2368 (attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
2369 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
))
2372 if ((!adev
->powerplay
.pp_funcs
->set_fan_speed_rpm
&&
2373 !adev
->powerplay
.pp_funcs
->get_fan_speed_rpm
) &&
2374 (attr
== &sensor_dev_attr_fan1_max
.dev_attr
.attr
||
2375 attr
== &sensor_dev_attr_fan1_min
.dev_attr
.attr
))
2379 /* only APUs have vddnb */
2380 if (!(adev
->flags
& AMD_IS_APU
) &&
2381 (attr
== &sensor_dev_attr_in1_input
.dev_attr
.attr
||
2382 attr
== &sensor_dev_attr_in1_label
.dev_attr
.attr
))
2385 /* no mclk on APUs */
2386 if ((adev
->flags
& AMD_IS_APU
) &&
2387 (attr
== &sensor_dev_attr_freq2_input
.dev_attr
.attr
||
2388 attr
== &sensor_dev_attr_freq2_label
.dev_attr
.attr
))
2391 /* only SOC15 dGPUs support hotspot and mem temperatures */
2392 if (((adev
->flags
& AMD_IS_APU
) ||
2393 adev
->asic_type
< CHIP_VEGA10
) &&
2394 (attr
== &sensor_dev_attr_temp2_crit
.dev_attr
.attr
||
2395 attr
== &sensor_dev_attr_temp2_crit_hyst
.dev_attr
.attr
||
2396 attr
== &sensor_dev_attr_temp3_crit
.dev_attr
.attr
||
2397 attr
== &sensor_dev_attr_temp3_crit_hyst
.dev_attr
.attr
||
2398 attr
== &sensor_dev_attr_temp1_emergency
.dev_attr
.attr
||
2399 attr
== &sensor_dev_attr_temp2_emergency
.dev_attr
.attr
||
2400 attr
== &sensor_dev_attr_temp3_emergency
.dev_attr
.attr
||
2401 attr
== &sensor_dev_attr_temp2_input
.dev_attr
.attr
||
2402 attr
== &sensor_dev_attr_temp3_input
.dev_attr
.attr
||
2403 attr
== &sensor_dev_attr_temp2_label
.dev_attr
.attr
||
2404 attr
== &sensor_dev_attr_temp3_label
.dev_attr
.attr
))
2407 return effective_mode
;
2410 static const struct attribute_group hwmon_attrgroup
= {
2411 .attrs
= hwmon_attributes
,
2412 .is_visible
= hwmon_attributes_visible
,
2415 static const struct attribute_group
*hwmon_groups
[] = {
2420 void amdgpu_dpm_thermal_work_handler(struct work_struct
*work
)
2422 struct amdgpu_device
*adev
=
2423 container_of(work
, struct amdgpu_device
,
2424 pm
.dpm
.thermal
.work
);
2425 /* switch to the thermal state */
2426 enum amd_pm_state_type dpm_state
= POWER_STATE_TYPE_INTERNAL_THERMAL
;
2427 int temp
, size
= sizeof(temp
);
2429 if (!adev
->pm
.dpm_enabled
)
2432 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_TEMP
,
2433 (void *)&temp
, &size
)) {
2434 if (temp
< adev
->pm
.dpm
.thermal
.min_temp
)
2435 /* switch back the user state */
2436 dpm_state
= adev
->pm
.dpm
.user_state
;
2438 if (adev
->pm
.dpm
.thermal
.high_to_low
)
2439 /* switch back the user state */
2440 dpm_state
= adev
->pm
.dpm
.user_state
;
2442 mutex_lock(&adev
->pm
.mutex
);
2443 if (dpm_state
== POWER_STATE_TYPE_INTERNAL_THERMAL
)
2444 adev
->pm
.dpm
.thermal_active
= true;
2446 adev
->pm
.dpm
.thermal_active
= false;
2447 adev
->pm
.dpm
.state
= dpm_state
;
2448 mutex_unlock(&adev
->pm
.mutex
);
2450 amdgpu_pm_compute_clocks(adev
);
2453 static struct amdgpu_ps
*amdgpu_dpm_pick_power_state(struct amdgpu_device
*adev
,
2454 enum amd_pm_state_type dpm_state
)
2457 struct amdgpu_ps
*ps
;
2459 bool single_display
= (adev
->pm
.dpm
.new_active_crtc_count
< 2) ?
2462 /* check if the vblank period is too short to adjust the mclk */
2463 if (single_display
&& adev
->powerplay
.pp_funcs
->vblank_too_short
) {
2464 if (amdgpu_dpm_vblank_too_short(adev
))
2465 single_display
= false;
2468 /* certain older asics have a separare 3D performance state,
2469 * so try that first if the user selected performance
2471 if (dpm_state
== POWER_STATE_TYPE_PERFORMANCE
)
2472 dpm_state
= POWER_STATE_TYPE_INTERNAL_3DPERF
;
2473 /* balanced states don't exist at the moment */
2474 if (dpm_state
== POWER_STATE_TYPE_BALANCED
)
2475 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
2478 /* Pick the best power state based on current conditions */
2479 for (i
= 0; i
< adev
->pm
.dpm
.num_ps
; i
++) {
2480 ps
= &adev
->pm
.dpm
.ps
[i
];
2481 ui_class
= ps
->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK
;
2482 switch (dpm_state
) {
2484 case POWER_STATE_TYPE_BATTERY
:
2485 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
) {
2486 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
2493 case POWER_STATE_TYPE_BALANCED
:
2494 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BALANCED
) {
2495 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
2502 case POWER_STATE_TYPE_PERFORMANCE
:
2503 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
) {
2504 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
2511 /* internal states */
2512 case POWER_STATE_TYPE_INTERNAL_UVD
:
2513 if (adev
->pm
.dpm
.uvd_ps
)
2514 return adev
->pm
.dpm
.uvd_ps
;
2517 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
2518 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE
)
2521 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
2522 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE
)
2525 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
2526 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE
)
2529 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
2530 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_MVC
)
2533 case POWER_STATE_TYPE_INTERNAL_BOOT
:
2534 return adev
->pm
.dpm
.boot_ps
;
2535 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
2536 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_THERMAL
)
2539 case POWER_STATE_TYPE_INTERNAL_ACPI
:
2540 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_ACPI
)
2543 case POWER_STATE_TYPE_INTERNAL_ULV
:
2544 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_ULV
)
2547 case POWER_STATE_TYPE_INTERNAL_3DPERF
:
2548 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE
)
2555 /* use a fallback state if we didn't match */
2556 switch (dpm_state
) {
2557 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
2558 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD_HD
;
2559 goto restart_search
;
2560 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
2561 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
2562 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
2563 if (adev
->pm
.dpm
.uvd_ps
) {
2564 return adev
->pm
.dpm
.uvd_ps
;
2566 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
2567 goto restart_search
;
2569 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
2570 dpm_state
= POWER_STATE_TYPE_INTERNAL_ACPI
;
2571 goto restart_search
;
2572 case POWER_STATE_TYPE_INTERNAL_ACPI
:
2573 dpm_state
= POWER_STATE_TYPE_BATTERY
;
2574 goto restart_search
;
2575 case POWER_STATE_TYPE_BATTERY
:
2576 case POWER_STATE_TYPE_BALANCED
:
2577 case POWER_STATE_TYPE_INTERNAL_3DPERF
:
2578 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
2579 goto restart_search
;
2587 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device
*adev
)
2589 struct amdgpu_ps
*ps
;
2590 enum amd_pm_state_type dpm_state
;
2594 /* if dpm init failed */
2595 if (!adev
->pm
.dpm_enabled
)
2598 if (adev
->pm
.dpm
.user_state
!= adev
->pm
.dpm
.state
) {
2599 /* add other state override checks here */
2600 if ((!adev
->pm
.dpm
.thermal_active
) &&
2601 (!adev
->pm
.dpm
.uvd_active
))
2602 adev
->pm
.dpm
.state
= adev
->pm
.dpm
.user_state
;
2604 dpm_state
= adev
->pm
.dpm
.state
;
2606 ps
= amdgpu_dpm_pick_power_state(adev
, dpm_state
);
2608 adev
->pm
.dpm
.requested_ps
= ps
;
2612 if (amdgpu_dpm
== 1 && adev
->powerplay
.pp_funcs
->print_power_state
) {
2613 printk("switching from power state:\n");
2614 amdgpu_dpm_print_power_state(adev
, adev
->pm
.dpm
.current_ps
);
2615 printk("switching to power state:\n");
2616 amdgpu_dpm_print_power_state(adev
, adev
->pm
.dpm
.requested_ps
);
2619 /* update whether vce is active */
2620 ps
->vce_active
= adev
->pm
.dpm
.vce_active
;
2621 if (adev
->powerplay
.pp_funcs
->display_configuration_changed
)
2622 amdgpu_dpm_display_configuration_changed(adev
);
2624 ret
= amdgpu_dpm_pre_set_power_state(adev
);
2628 if (adev
->powerplay
.pp_funcs
->check_state_equal
) {
2629 if (0 != amdgpu_dpm_check_state_equal(adev
, adev
->pm
.dpm
.current_ps
, adev
->pm
.dpm
.requested_ps
, &equal
))
2636 amdgpu_dpm_set_power_state(adev
);
2637 amdgpu_dpm_post_set_power_state(adev
);
2639 adev
->pm
.dpm
.current_active_crtcs
= adev
->pm
.dpm
.new_active_crtcs
;
2640 adev
->pm
.dpm
.current_active_crtc_count
= adev
->pm
.dpm
.new_active_crtc_count
;
2642 if (adev
->powerplay
.pp_funcs
->force_performance_level
) {
2643 if (adev
->pm
.dpm
.thermal_active
) {
2644 enum amd_dpm_forced_level level
= adev
->pm
.dpm
.forced_level
;
2645 /* force low perf level for thermal */
2646 amdgpu_dpm_force_performance_level(adev
, AMD_DPM_FORCED_LEVEL_LOW
);
2647 /* save the user's level */
2648 adev
->pm
.dpm
.forced_level
= level
;
2650 /* otherwise, user selected level */
2651 amdgpu_dpm_force_performance_level(adev
, adev
->pm
.dpm
.forced_level
);
2656 void amdgpu_dpm_enable_uvd(struct amdgpu_device
*adev
, bool enable
)
2659 if (is_support_sw_smu(adev
)) {
2660 ret
= smu_dpm_set_power_gate(&adev
->smu
, AMD_IP_BLOCK_TYPE_UVD
, enable
);
2662 DRM_ERROR("[SW SMU]: dpm enable uvd failed, state = %s, ret = %d. \n",
2663 enable
? "true" : "false", ret
);
2664 } else if (adev
->powerplay
.pp_funcs
->set_powergating_by_smu
) {
2665 /* enable/disable UVD */
2666 mutex_lock(&adev
->pm
.mutex
);
2667 amdgpu_dpm_set_powergating_by_smu(adev
, AMD_IP_BLOCK_TYPE_UVD
, !enable
);
2668 mutex_unlock(&adev
->pm
.mutex
);
2670 /* enable/disable Low Memory PState for UVD (4k videos) */
2671 if (adev
->asic_type
== CHIP_STONEY
&&
2672 adev
->uvd
.decode_image_width
>= WIDTH_4K
) {
2673 struct pp_hwmgr
*hwmgr
= adev
->powerplay
.pp_handle
;
2675 if (hwmgr
&& hwmgr
->hwmgr_func
&&
2676 hwmgr
->hwmgr_func
->update_nbdpm_pstate
)
2677 hwmgr
->hwmgr_func
->update_nbdpm_pstate(hwmgr
,
2683 void amdgpu_dpm_enable_vce(struct amdgpu_device
*adev
, bool enable
)
2686 if (is_support_sw_smu(adev
)) {
2687 ret
= smu_dpm_set_power_gate(&adev
->smu
, AMD_IP_BLOCK_TYPE_VCE
, enable
);
2689 DRM_ERROR("[SW SMU]: dpm enable vce failed, state = %s, ret = %d. \n",
2690 enable
? "true" : "false", ret
);
2691 } else if (adev
->powerplay
.pp_funcs
->set_powergating_by_smu
) {
2692 /* enable/disable VCE */
2693 mutex_lock(&adev
->pm
.mutex
);
2694 amdgpu_dpm_set_powergating_by_smu(adev
, AMD_IP_BLOCK_TYPE_VCE
, !enable
);
2695 mutex_unlock(&adev
->pm
.mutex
);
2699 void amdgpu_pm_print_power_states(struct amdgpu_device
*adev
)
2703 if (adev
->powerplay
.pp_funcs
->print_power_state
== NULL
)
2706 for (i
= 0; i
< adev
->pm
.dpm
.num_ps
; i
++)
2707 amdgpu_dpm_print_power_state(adev
, &adev
->pm
.dpm
.ps
[i
]);
2711 int amdgpu_pm_virt_sysfs_init(struct amdgpu_device
*adev
)
2715 if (!(amdgpu_sriov_vf(adev
) && amdgim_is_hwperf(adev
)))
2718 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_sclk
);
2720 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
2724 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_mclk
);
2726 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2730 ret
= device_create_file(adev
->dev
, &dev_attr_power_dpm_force_performance_level
);
2732 DRM_ERROR("failed to create device file for dpm state\n");
2739 void amdgpu_pm_virt_sysfs_fini(struct amdgpu_device
*adev
)
2741 if (!(amdgpu_sriov_vf(adev
) && amdgim_is_hwperf(adev
)))
2744 device_remove_file(adev
->dev
, &dev_attr_power_dpm_force_performance_level
);
2745 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_sclk
);
2746 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_mclk
);
2749 int amdgpu_pm_load_smu_firmware(struct amdgpu_device
*adev
, uint32_t *smu_version
)
2753 if (adev
->powerplay
.pp_funcs
&& adev
->powerplay
.pp_funcs
->load_firmware
) {
2754 r
= adev
->powerplay
.pp_funcs
->load_firmware(adev
->powerplay
.pp_handle
);
2756 pr_err("smu firmware loading failed\n");
2759 *smu_version
= adev
->pm
.fw_version
;
2764 int amdgpu_pm_sysfs_init(struct amdgpu_device
*adev
)
2766 struct pp_hwmgr
*hwmgr
= adev
->powerplay
.pp_handle
;
2769 if (adev
->pm
.sysfs_initialized
)
2772 if (adev
->pm
.dpm_enabled
== 0)
2775 adev
->pm
.int_hwmon_dev
= hwmon_device_register_with_groups(adev
->dev
,
2778 if (IS_ERR(adev
->pm
.int_hwmon_dev
)) {
2779 ret
= PTR_ERR(adev
->pm
.int_hwmon_dev
);
2781 "Unable to register hwmon device: %d\n", ret
);
2785 ret
= device_create_file(adev
->dev
, &dev_attr_power_dpm_state
);
2787 DRM_ERROR("failed to create device file for dpm state\n");
2790 ret
= device_create_file(adev
->dev
, &dev_attr_power_dpm_force_performance_level
);
2792 DRM_ERROR("failed to create device file for dpm state\n");
2797 ret
= device_create_file(adev
->dev
, &dev_attr_pp_num_states
);
2799 DRM_ERROR("failed to create device file pp_num_states\n");
2802 ret
= device_create_file(adev
->dev
, &dev_attr_pp_cur_state
);
2804 DRM_ERROR("failed to create device file pp_cur_state\n");
2807 ret
= device_create_file(adev
->dev
, &dev_attr_pp_force_state
);
2809 DRM_ERROR("failed to create device file pp_force_state\n");
2812 ret
= device_create_file(adev
->dev
, &dev_attr_pp_table
);
2814 DRM_ERROR("failed to create device file pp_table\n");
2818 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_sclk
);
2820 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
2823 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_mclk
);
2825 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2828 if (adev
->asic_type
>= CHIP_VEGA10
) {
2829 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_socclk
);
2831 DRM_ERROR("failed to create device file pp_dpm_socclk\n");
2834 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_dcefclk
);
2836 DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
2840 if (adev
->asic_type
>= CHIP_VEGA20
) {
2841 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_fclk
);
2843 DRM_ERROR("failed to create device file pp_dpm_fclk\n");
2847 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_pcie
);
2849 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
2852 ret
= device_create_file(adev
->dev
, &dev_attr_pp_sclk_od
);
2854 DRM_ERROR("failed to create device file pp_sclk_od\n");
2857 ret
= device_create_file(adev
->dev
, &dev_attr_pp_mclk_od
);
2859 DRM_ERROR("failed to create device file pp_mclk_od\n");
2862 ret
= device_create_file(adev
->dev
,
2863 &dev_attr_pp_power_profile_mode
);
2865 DRM_ERROR("failed to create device file "
2866 "pp_power_profile_mode\n");
2869 if ((is_support_sw_smu(adev
) && adev
->smu
.od_enabled
) ||
2870 (!is_support_sw_smu(adev
) && hwmgr
->od_enabled
)) {
2871 ret
= device_create_file(adev
->dev
,
2872 &dev_attr_pp_od_clk_voltage
);
2874 DRM_ERROR("failed to create device file "
2875 "pp_od_clk_voltage\n");
2879 ret
= device_create_file(adev
->dev
,
2880 &dev_attr_gpu_busy_percent
);
2882 DRM_ERROR("failed to create device file "
2883 "gpu_busy_level\n");
2886 /* APU does not have its own dedicated memory */
2887 if (!(adev
->flags
& AMD_IS_APU
) &&
2888 (adev
->asic_type
!= CHIP_VEGA10
)) {
2889 ret
= device_create_file(adev
->dev
,
2890 &dev_attr_mem_busy_percent
);
2892 DRM_ERROR("failed to create device file "
2893 "mem_busy_percent\n");
2897 /* PCIe Perf counters won't work on APU nodes */
2898 if (!(adev
->flags
& AMD_IS_APU
)) {
2899 ret
= device_create_file(adev
->dev
, &dev_attr_pcie_bw
);
2901 DRM_ERROR("failed to create device file pcie_bw\n");
2905 if (adev
->unique_id
)
2906 ret
= device_create_file(adev
->dev
, &dev_attr_unique_id
);
2908 DRM_ERROR("failed to create device file unique_id\n");
2911 ret
= amdgpu_debugfs_pm_init(adev
);
2913 DRM_ERROR("Failed to register debugfs file for dpm!\n");
2917 if ((adev
->asic_type
>= CHIP_VEGA10
) &&
2918 !(adev
->flags
& AMD_IS_APU
)) {
2919 ret
= device_create_file(adev
->dev
,
2920 &dev_attr_ppfeatures
);
2922 DRM_ERROR("failed to create device file "
2928 adev
->pm
.sysfs_initialized
= true;
2933 void amdgpu_pm_sysfs_fini(struct amdgpu_device
*adev
)
2935 struct pp_hwmgr
*hwmgr
= adev
->powerplay
.pp_handle
;
2937 if (adev
->pm
.dpm_enabled
== 0)
2940 if (adev
->pm
.int_hwmon_dev
)
2941 hwmon_device_unregister(adev
->pm
.int_hwmon_dev
);
2942 device_remove_file(adev
->dev
, &dev_attr_power_dpm_state
);
2943 device_remove_file(adev
->dev
, &dev_attr_power_dpm_force_performance_level
);
2945 device_remove_file(adev
->dev
, &dev_attr_pp_num_states
);
2946 device_remove_file(adev
->dev
, &dev_attr_pp_cur_state
);
2947 device_remove_file(adev
->dev
, &dev_attr_pp_force_state
);
2948 device_remove_file(adev
->dev
, &dev_attr_pp_table
);
2950 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_sclk
);
2951 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_mclk
);
2952 if (adev
->asic_type
>= CHIP_VEGA10
) {
2953 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_socclk
);
2954 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_dcefclk
);
2956 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_pcie
);
2957 if (adev
->asic_type
>= CHIP_VEGA20
)
2958 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_fclk
);
2959 device_remove_file(adev
->dev
, &dev_attr_pp_sclk_od
);
2960 device_remove_file(adev
->dev
, &dev_attr_pp_mclk_od
);
2961 device_remove_file(adev
->dev
,
2962 &dev_attr_pp_power_profile_mode
);
2963 if ((is_support_sw_smu(adev
) && adev
->smu
.od_enabled
) ||
2964 (!is_support_sw_smu(adev
) && hwmgr
->od_enabled
))
2965 device_remove_file(adev
->dev
,
2966 &dev_attr_pp_od_clk_voltage
);
2967 device_remove_file(adev
->dev
, &dev_attr_gpu_busy_percent
);
2968 if (!(adev
->flags
& AMD_IS_APU
) &&
2969 (adev
->asic_type
!= CHIP_VEGA10
))
2970 device_remove_file(adev
->dev
, &dev_attr_mem_busy_percent
);
2971 if (!(adev
->flags
& AMD_IS_APU
))
2972 device_remove_file(adev
->dev
, &dev_attr_pcie_bw
);
2973 if (adev
->unique_id
)
2974 device_remove_file(adev
->dev
, &dev_attr_unique_id
);
2975 if ((adev
->asic_type
>= CHIP_VEGA10
) &&
2976 !(adev
->flags
& AMD_IS_APU
))
2977 device_remove_file(adev
->dev
, &dev_attr_ppfeatures
);
2980 void amdgpu_pm_compute_clocks(struct amdgpu_device
*adev
)
2984 if (!adev
->pm
.dpm_enabled
)
2987 if (adev
->mode_info
.num_crtc
)
2988 amdgpu_display_bandwidth_update(adev
);
2990 for (i
= 0; i
< AMDGPU_MAX_RINGS
; i
++) {
2991 struct amdgpu_ring
*ring
= adev
->rings
[i
];
2992 if (ring
&& ring
->sched
.ready
)
2993 amdgpu_fence_wait_empty(ring
);
2996 if (is_support_sw_smu(adev
)) {
2997 struct smu_dpm_context
*smu_dpm
= &adev
->smu
.smu_dpm
;
2998 smu_handle_task(&adev
->smu
,
3000 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE
);
3002 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
3003 if (!amdgpu_device_has_dc_support(adev
)) {
3004 mutex_lock(&adev
->pm
.mutex
);
3005 amdgpu_dpm_get_active_displays(adev
);
3006 adev
->pm
.pm_display_cfg
.num_display
= adev
->pm
.dpm
.new_active_crtc_count
;
3007 adev
->pm
.pm_display_cfg
.vrefresh
= amdgpu_dpm_get_vrefresh(adev
);
3008 adev
->pm
.pm_display_cfg
.min_vblank_time
= amdgpu_dpm_get_vblank_time(adev
);
3009 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
3010 if (adev
->pm
.pm_display_cfg
.vrefresh
> 120)
3011 adev
->pm
.pm_display_cfg
.min_vblank_time
= 0;
3012 if (adev
->powerplay
.pp_funcs
->display_configuration_change
)
3013 adev
->powerplay
.pp_funcs
->display_configuration_change(
3014 adev
->powerplay
.pp_handle
,
3015 &adev
->pm
.pm_display_cfg
);
3016 mutex_unlock(&adev
->pm
.mutex
);
3018 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE
, NULL
);
3020 mutex_lock(&adev
->pm
.mutex
);
3021 amdgpu_dpm_get_active_displays(adev
);
3022 amdgpu_dpm_change_power_state_locked(adev
);
3023 mutex_unlock(&adev
->pm
.mutex
);
3031 #if defined(CONFIG_DEBUG_FS)
3033 static int amdgpu_debugfs_pm_info_pp(struct seq_file
*m
, struct amdgpu_device
*adev
)
3041 size
= sizeof(value
);
3042 seq_printf(m
, "GFX Clocks and Power:\n");
3043 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GFX_MCLK
, (void *)&value
, &size
))
3044 seq_printf(m
, "\t%u MHz (MCLK)\n", value
/100);
3045 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GFX_SCLK
, (void *)&value
, &size
))
3046 seq_printf(m
, "\t%u MHz (SCLK)\n", value
/100);
3047 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK
, (void *)&value
, &size
))
3048 seq_printf(m
, "\t%u MHz (PSTATE_SCLK)\n", value
/100);
3049 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK
, (void *)&value
, &size
))
3050 seq_printf(m
, "\t%u MHz (PSTATE_MCLK)\n", value
/100);
3051 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDGFX
, (void *)&value
, &size
))
3052 seq_printf(m
, "\t%u mV (VDDGFX)\n", value
);
3053 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDNB
, (void *)&value
, &size
))
3054 seq_printf(m
, "\t%u mV (VDDNB)\n", value
);
3055 size
= sizeof(uint32_t);
3056 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_POWER
, (void *)&query
, &size
))
3057 seq_printf(m
, "\t%u.%u W (average GPU)\n", query
>> 8, query
& 0xff);
3058 size
= sizeof(value
);
3059 seq_printf(m
, "\n");
3062 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_TEMP
, (void *)&value
, &size
))
3063 seq_printf(m
, "GPU Temperature: %u C\n", value
/1000);
3066 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_LOAD
, (void *)&value
, &size
))
3067 seq_printf(m
, "GPU Load: %u %%\n", value
);
3069 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_MEM_LOAD
, (void *)&value
, &size
))
3070 seq_printf(m
, "MEM Load: %u %%\n", value
);
3072 seq_printf(m
, "\n");
3074 /* SMC feature mask */
3075 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK
, (void *)&value64
, &size
))
3076 seq_printf(m
, "SMC Feature Mask: 0x%016llx\n", value64
);
3078 if (adev
->asic_type
> CHIP_VEGA20
) {
3080 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VCN_POWER_STATE
, (void *)&value
, &size
)) {
3082 seq_printf(m
, "VCN: Disabled\n");
3084 seq_printf(m
, "VCN: Enabled\n");
3085 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_UVD_DCLK
, (void *)&value
, &size
))
3086 seq_printf(m
, "\t%u MHz (DCLK)\n", value
/100);
3087 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_UVD_VCLK
, (void *)&value
, &size
))
3088 seq_printf(m
, "\t%u MHz (VCLK)\n", value
/100);
3091 seq_printf(m
, "\n");
3094 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_UVD_POWER
, (void *)&value
, &size
)) {
3096 seq_printf(m
, "UVD: Disabled\n");
3098 seq_printf(m
, "UVD: Enabled\n");
3099 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_UVD_DCLK
, (void *)&value
, &size
))
3100 seq_printf(m
, "\t%u MHz (DCLK)\n", value
/100);
3101 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_UVD_VCLK
, (void *)&value
, &size
))
3102 seq_printf(m
, "\t%u MHz (VCLK)\n", value
/100);
3105 seq_printf(m
, "\n");
3108 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VCE_POWER
, (void *)&value
, &size
)) {
3110 seq_printf(m
, "VCE: Disabled\n");
3112 seq_printf(m
, "VCE: Enabled\n");
3113 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VCE_ECCLK
, (void *)&value
, &size
))
3114 seq_printf(m
, "\t%u MHz (ECCLK)\n", value
/100);
3122 static void amdgpu_parse_cg_state(struct seq_file
*m
, u32 flags
)
3126 for (i
= 0; clocks
[i
].flag
; i
++)
3127 seq_printf(m
, "\t%s: %s\n", clocks
[i
].name
,
3128 (flags
& clocks
[i
].flag
) ? "On" : "Off");
3131 static int amdgpu_debugfs_pm_info(struct seq_file
*m
, void *data
)
3133 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3134 struct drm_device
*dev
= node
->minor
->dev
;
3135 struct amdgpu_device
*adev
= dev
->dev_private
;
3136 struct drm_device
*ddev
= adev
->ddev
;
3139 amdgpu_device_ip_get_clockgating_state(adev
, &flags
);
3140 seq_printf(m
, "Clock Gating Flags Mask: 0x%x\n", flags
);
3141 amdgpu_parse_cg_state(m
, flags
);
3142 seq_printf(m
, "\n");
3144 if (!adev
->pm
.dpm_enabled
) {
3145 seq_printf(m
, "dpm not enabled\n");
3148 if ((adev
->flags
& AMD_IS_PX
) &&
3149 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
)) {
3150 seq_printf(m
, "PX asic powered off\n");
3151 } else if (!is_support_sw_smu(adev
) && adev
->powerplay
.pp_funcs
->debugfs_print_current_performance_level
) {
3152 mutex_lock(&adev
->pm
.mutex
);
3153 if (adev
->powerplay
.pp_funcs
->debugfs_print_current_performance_level
)
3154 adev
->powerplay
.pp_funcs
->debugfs_print_current_performance_level(adev
, m
);
3156 seq_printf(m
, "Debugfs support not implemented for this asic\n");
3157 mutex_unlock(&adev
->pm
.mutex
);
3159 return amdgpu_debugfs_pm_info_pp(m
, adev
);
3165 static const struct drm_info_list amdgpu_pm_info_list
[] = {
3166 {"amdgpu_pm_info", amdgpu_debugfs_pm_info
, 0, NULL
},
3170 static int amdgpu_debugfs_pm_init(struct amdgpu_device
*adev
)
3172 #if defined(CONFIG_DEBUG_FS)
3173 return amdgpu_debugfs_add_files(adev
, amdgpu_pm_info_list
, ARRAY_SIZE(amdgpu_pm_info_list
));