2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
25 #include "amdgpu_drv.h"
26 #include "amdgpu_pm.h"
27 #include "amdgpu_dpm.h"
29 #include <linux/power_supply.h>
30 #include <linux/hwmon.h>
31 #include <linux/hwmon-sysfs.h>
33 #include "amd_powerplay.h"
35 static int amdgpu_debugfs_pm_init(struct amdgpu_device
*adev
);
37 static const struct cg_flag_name clocks
[] = {
38 {AMD_CG_SUPPORT_GFX_MGCG
, "Graphics Medium Grain Clock Gating"},
39 {AMD_CG_SUPPORT_GFX_MGLS
, "Graphics Medium Grain memory Light Sleep"},
40 {AMD_CG_SUPPORT_GFX_CGCG
, "Graphics Coarse Grain Clock Gating"},
41 {AMD_CG_SUPPORT_GFX_CGLS
, "Graphics Coarse Grain memory Light Sleep"},
42 {AMD_CG_SUPPORT_GFX_CGTS
, "Graphics Coarse Grain Tree Shader Clock Gating"},
43 {AMD_CG_SUPPORT_GFX_CGTS_LS
, "Graphics Coarse Grain Tree Shader Light Sleep"},
44 {AMD_CG_SUPPORT_GFX_CP_LS
, "Graphics Command Processor Light Sleep"},
45 {AMD_CG_SUPPORT_GFX_RLC_LS
, "Graphics Run List Controller Light Sleep"},
46 {AMD_CG_SUPPORT_GFX_3D_CGCG
, "Graphics 3D Coarse Grain Clock Gating"},
47 {AMD_CG_SUPPORT_GFX_3D_CGLS
, "Graphics 3D Coarse Grain memory Light Sleep"},
48 {AMD_CG_SUPPORT_MC_LS
, "Memory Controller Light Sleep"},
49 {AMD_CG_SUPPORT_MC_MGCG
, "Memory Controller Medium Grain Clock Gating"},
50 {AMD_CG_SUPPORT_SDMA_LS
, "System Direct Memory Access Light Sleep"},
51 {AMD_CG_SUPPORT_SDMA_MGCG
, "System Direct Memory Access Medium Grain Clock Gating"},
52 {AMD_CG_SUPPORT_BIF_MGCG
, "Bus Interface Medium Grain Clock Gating"},
53 {AMD_CG_SUPPORT_BIF_LS
, "Bus Interface Light Sleep"},
54 {AMD_CG_SUPPORT_UVD_MGCG
, "Unified Video Decoder Medium Grain Clock Gating"},
55 {AMD_CG_SUPPORT_VCE_MGCG
, "Video Compression Engine Medium Grain Clock Gating"},
56 {AMD_CG_SUPPORT_HDP_LS
, "Host Data Path Light Sleep"},
57 {AMD_CG_SUPPORT_HDP_MGCG
, "Host Data Path Medium Grain Clock Gating"},
58 {AMD_CG_SUPPORT_DRM_MGCG
, "Digital Right Management Medium Grain Clock Gating"},
59 {AMD_CG_SUPPORT_DRM_LS
, "Digital Right Management Light Sleep"},
60 {AMD_CG_SUPPORT_ROM_MGCG
, "Rom Medium Grain Clock Gating"},
61 {AMD_CG_SUPPORT_DF_MGCG
, "Data Fabric Medium Grain Clock Gating"},
65 void amdgpu_pm_acpi_event_handler(struct amdgpu_device
*adev
)
67 if (adev
->pm
.dpm_enabled
) {
68 mutex_lock(&adev
->pm
.mutex
);
69 if (power_supply_is_system_supplied() > 0)
70 adev
->pm
.dpm
.ac_power
= true;
72 adev
->pm
.dpm
.ac_power
= false;
73 if (adev
->powerplay
.pp_funcs
->enable_bapm
)
74 amdgpu_dpm_enable_bapm(adev
, adev
->pm
.dpm
.ac_power
);
75 mutex_unlock(&adev
->pm
.mutex
);
79 static ssize_t
amdgpu_get_dpm_state(struct device
*dev
,
80 struct device_attribute
*attr
,
83 struct drm_device
*ddev
= dev_get_drvdata(dev
);
84 struct amdgpu_device
*adev
= ddev
->dev_private
;
85 enum amd_pm_state_type pm
;
87 if (adev
->powerplay
.pp_funcs
->get_current_power_state
)
88 pm
= amdgpu_dpm_get_current_power_state(adev
);
90 pm
= adev
->pm
.dpm
.user_state
;
92 return snprintf(buf
, PAGE_SIZE
, "%s\n",
93 (pm
== POWER_STATE_TYPE_BATTERY
) ? "battery" :
94 (pm
== POWER_STATE_TYPE_BALANCED
) ? "balanced" : "performance");
97 static ssize_t
amdgpu_set_dpm_state(struct device
*dev
,
98 struct device_attribute
*attr
,
102 struct drm_device
*ddev
= dev_get_drvdata(dev
);
103 struct amdgpu_device
*adev
= ddev
->dev_private
;
104 enum amd_pm_state_type state
;
106 if (strncmp("battery", buf
, strlen("battery")) == 0)
107 state
= POWER_STATE_TYPE_BATTERY
;
108 else if (strncmp("balanced", buf
, strlen("balanced")) == 0)
109 state
= POWER_STATE_TYPE_BALANCED
;
110 else if (strncmp("performance", buf
, strlen("performance")) == 0)
111 state
= POWER_STATE_TYPE_PERFORMANCE
;
117 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
118 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_ENABLE_USER_STATE
, &state
, NULL
);
120 mutex_lock(&adev
->pm
.mutex
);
121 adev
->pm
.dpm
.user_state
= state
;
122 mutex_unlock(&adev
->pm
.mutex
);
124 /* Can't set dpm state when the card is off */
125 if (!(adev
->flags
& AMD_IS_PX
) ||
126 (ddev
->switch_power_state
== DRM_SWITCH_POWER_ON
))
127 amdgpu_pm_compute_clocks(adev
);
133 static ssize_t
amdgpu_get_dpm_forced_performance_level(struct device
*dev
,
134 struct device_attribute
*attr
,
137 struct drm_device
*ddev
= dev_get_drvdata(dev
);
138 struct amdgpu_device
*adev
= ddev
->dev_private
;
139 enum amd_dpm_forced_level level
= 0xff;
141 if ((adev
->flags
& AMD_IS_PX
) &&
142 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
143 return snprintf(buf
, PAGE_SIZE
, "off\n");
145 if (adev
->powerplay
.pp_funcs
->get_performance_level
)
146 level
= amdgpu_dpm_get_performance_level(adev
);
148 level
= adev
->pm
.dpm
.forced_level
;
150 return snprintf(buf
, PAGE_SIZE
, "%s\n",
151 (level
== AMD_DPM_FORCED_LEVEL_AUTO
) ? "auto" :
152 (level
== AMD_DPM_FORCED_LEVEL_LOW
) ? "low" :
153 (level
== AMD_DPM_FORCED_LEVEL_HIGH
) ? "high" :
154 (level
== AMD_DPM_FORCED_LEVEL_MANUAL
) ? "manual" :
155 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
) ? "profile_standard" :
156 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
) ? "profile_min_sclk" :
157 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
) ? "profile_min_mclk" :
158 (level
== AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
) ? "profile_peak" :
162 static ssize_t
amdgpu_set_dpm_forced_performance_level(struct device
*dev
,
163 struct device_attribute
*attr
,
167 struct drm_device
*ddev
= dev_get_drvdata(dev
);
168 struct amdgpu_device
*adev
= ddev
->dev_private
;
169 enum amd_dpm_forced_level level
;
170 enum amd_dpm_forced_level current_level
= 0xff;
173 /* Can't force performance level when the card is off */
174 if ((adev
->flags
& AMD_IS_PX
) &&
175 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
178 if (adev
->powerplay
.pp_funcs
->get_performance_level
)
179 current_level
= amdgpu_dpm_get_performance_level(adev
);
181 if (strncmp("low", buf
, strlen("low")) == 0) {
182 level
= AMD_DPM_FORCED_LEVEL_LOW
;
183 } else if (strncmp("high", buf
, strlen("high")) == 0) {
184 level
= AMD_DPM_FORCED_LEVEL_HIGH
;
185 } else if (strncmp("auto", buf
, strlen("auto")) == 0) {
186 level
= AMD_DPM_FORCED_LEVEL_AUTO
;
187 } else if (strncmp("manual", buf
, strlen("manual")) == 0) {
188 level
= AMD_DPM_FORCED_LEVEL_MANUAL
;
189 } else if (strncmp("profile_exit", buf
, strlen("profile_exit")) == 0) {
190 level
= AMD_DPM_FORCED_LEVEL_PROFILE_EXIT
;
191 } else if (strncmp("profile_standard", buf
, strlen("profile_standard")) == 0) {
192 level
= AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
;
193 } else if (strncmp("profile_min_sclk", buf
, strlen("profile_min_sclk")) == 0) {
194 level
= AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
;
195 } else if (strncmp("profile_min_mclk", buf
, strlen("profile_min_mclk")) == 0) {
196 level
= AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
;
197 } else if (strncmp("profile_peak", buf
, strlen("profile_peak")) == 0) {
198 level
= AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
;
204 if (current_level
== level
)
207 if (adev
->powerplay
.pp_funcs
->force_performance_level
) {
208 mutex_lock(&adev
->pm
.mutex
);
209 if (adev
->pm
.dpm
.thermal_active
) {
211 mutex_unlock(&adev
->pm
.mutex
);
214 ret
= amdgpu_dpm_force_performance_level(adev
, level
);
218 adev
->pm
.dpm
.forced_level
= level
;
219 mutex_unlock(&adev
->pm
.mutex
);
226 static ssize_t
amdgpu_get_pp_num_states(struct device
*dev
,
227 struct device_attribute
*attr
,
230 struct drm_device
*ddev
= dev_get_drvdata(dev
);
231 struct amdgpu_device
*adev
= ddev
->dev_private
;
232 struct pp_states_info data
;
235 if (adev
->powerplay
.pp_funcs
->get_pp_num_states
)
236 amdgpu_dpm_get_pp_num_states(adev
, &data
);
238 buf_len
= snprintf(buf
, PAGE_SIZE
, "states: %d\n", data
.nums
);
239 for (i
= 0; i
< data
.nums
; i
++)
240 buf_len
+= snprintf(buf
+ buf_len
, PAGE_SIZE
, "%d %s\n", i
,
241 (data
.states
[i
] == POWER_STATE_TYPE_INTERNAL_BOOT
) ? "boot" :
242 (data
.states
[i
] == POWER_STATE_TYPE_BATTERY
) ? "battery" :
243 (data
.states
[i
] == POWER_STATE_TYPE_BALANCED
) ? "balanced" :
244 (data
.states
[i
] == POWER_STATE_TYPE_PERFORMANCE
) ? "performance" : "default");
249 static ssize_t
amdgpu_get_pp_cur_state(struct device
*dev
,
250 struct device_attribute
*attr
,
253 struct drm_device
*ddev
= dev_get_drvdata(dev
);
254 struct amdgpu_device
*adev
= ddev
->dev_private
;
255 struct pp_states_info data
;
256 enum amd_pm_state_type pm
= 0;
259 if (adev
->powerplay
.pp_funcs
->get_current_power_state
260 && adev
->powerplay
.pp_funcs
->get_pp_num_states
) {
261 pm
= amdgpu_dpm_get_current_power_state(adev
);
262 amdgpu_dpm_get_pp_num_states(adev
, &data
);
264 for (i
= 0; i
< data
.nums
; i
++) {
265 if (pm
== data
.states
[i
])
273 return snprintf(buf
, PAGE_SIZE
, "%d\n", i
);
276 static ssize_t
amdgpu_get_pp_force_state(struct device
*dev
,
277 struct device_attribute
*attr
,
280 struct drm_device
*ddev
= dev_get_drvdata(dev
);
281 struct amdgpu_device
*adev
= ddev
->dev_private
;
283 if (adev
->pp_force_state_enabled
)
284 return amdgpu_get_pp_cur_state(dev
, attr
, buf
);
286 return snprintf(buf
, PAGE_SIZE
, "\n");
289 static ssize_t
amdgpu_set_pp_force_state(struct device
*dev
,
290 struct device_attribute
*attr
,
294 struct drm_device
*ddev
= dev_get_drvdata(dev
);
295 struct amdgpu_device
*adev
= ddev
->dev_private
;
296 enum amd_pm_state_type state
= 0;
300 if (strlen(buf
) == 1)
301 adev
->pp_force_state_enabled
= false;
302 else if (adev
->powerplay
.pp_funcs
->dispatch_tasks
&&
303 adev
->powerplay
.pp_funcs
->get_pp_num_states
) {
304 struct pp_states_info data
;
306 ret
= kstrtoul(buf
, 0, &idx
);
307 if (ret
|| idx
>= ARRAY_SIZE(data
.states
)) {
312 amdgpu_dpm_get_pp_num_states(adev
, &data
);
313 state
= data
.states
[idx
];
314 /* only set user selected power states */
315 if (state
!= POWER_STATE_TYPE_INTERNAL_BOOT
&&
316 state
!= POWER_STATE_TYPE_DEFAULT
) {
317 amdgpu_dpm_dispatch_task(adev
,
318 AMD_PP_TASK_ENABLE_USER_STATE
, &state
, NULL
);
319 adev
->pp_force_state_enabled
= true;
326 static ssize_t
amdgpu_get_pp_table(struct device
*dev
,
327 struct device_attribute
*attr
,
330 struct drm_device
*ddev
= dev_get_drvdata(dev
);
331 struct amdgpu_device
*adev
= ddev
->dev_private
;
335 if (adev
->powerplay
.pp_funcs
->get_pp_table
)
336 size
= amdgpu_dpm_get_pp_table(adev
, &table
);
340 if (size
>= PAGE_SIZE
)
341 size
= PAGE_SIZE
- 1;
343 memcpy(buf
, table
, size
);
348 static ssize_t
amdgpu_set_pp_table(struct device
*dev
,
349 struct device_attribute
*attr
,
353 struct drm_device
*ddev
= dev_get_drvdata(dev
);
354 struct amdgpu_device
*adev
= ddev
->dev_private
;
356 if (adev
->powerplay
.pp_funcs
->set_pp_table
)
357 amdgpu_dpm_set_pp_table(adev
, buf
, count
);
362 static ssize_t
amdgpu_get_pp_dpm_sclk(struct device
*dev
,
363 struct device_attribute
*attr
,
366 struct drm_device
*ddev
= dev_get_drvdata(dev
);
367 struct amdgpu_device
*adev
= ddev
->dev_private
;
369 if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
370 return amdgpu_dpm_print_clock_levels(adev
, PP_SCLK
, buf
);
372 return snprintf(buf
, PAGE_SIZE
, "\n");
375 static ssize_t
amdgpu_set_pp_dpm_sclk(struct device
*dev
,
376 struct device_attribute
*attr
,
380 struct drm_device
*ddev
= dev_get_drvdata(dev
);
381 struct amdgpu_device
*adev
= ddev
->dev_private
;
384 uint32_t i
, mask
= 0;
387 for (i
= 0; i
< strlen(buf
); i
++) {
388 if (*(buf
+ i
) == '\n')
390 sub_str
[0] = *(buf
+ i
);
392 ret
= kstrtol(sub_str
, 0, &level
);
401 if (adev
->powerplay
.pp_funcs
->force_clock_level
)
402 amdgpu_dpm_force_clock_level(adev
, PP_SCLK
, mask
);
408 static ssize_t
amdgpu_get_pp_dpm_mclk(struct device
*dev
,
409 struct device_attribute
*attr
,
412 struct drm_device
*ddev
= dev_get_drvdata(dev
);
413 struct amdgpu_device
*adev
= ddev
->dev_private
;
415 if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
416 return amdgpu_dpm_print_clock_levels(adev
, PP_MCLK
, buf
);
418 return snprintf(buf
, PAGE_SIZE
, "\n");
421 static ssize_t
amdgpu_set_pp_dpm_mclk(struct device
*dev
,
422 struct device_attribute
*attr
,
426 struct drm_device
*ddev
= dev_get_drvdata(dev
);
427 struct amdgpu_device
*adev
= ddev
->dev_private
;
430 uint32_t i
, mask
= 0;
433 for (i
= 0; i
< strlen(buf
); i
++) {
434 if (*(buf
+ i
) == '\n')
436 sub_str
[0] = *(buf
+ i
);
438 ret
= kstrtol(sub_str
, 0, &level
);
446 if (adev
->powerplay
.pp_funcs
->force_clock_level
)
447 amdgpu_dpm_force_clock_level(adev
, PP_MCLK
, mask
);
453 static ssize_t
amdgpu_get_pp_dpm_pcie(struct device
*dev
,
454 struct device_attribute
*attr
,
457 struct drm_device
*ddev
= dev_get_drvdata(dev
);
458 struct amdgpu_device
*adev
= ddev
->dev_private
;
460 if (adev
->powerplay
.pp_funcs
->print_clock_levels
)
461 return amdgpu_dpm_print_clock_levels(adev
, PP_PCIE
, buf
);
463 return snprintf(buf
, PAGE_SIZE
, "\n");
466 static ssize_t
amdgpu_set_pp_dpm_pcie(struct device
*dev
,
467 struct device_attribute
*attr
,
471 struct drm_device
*ddev
= dev_get_drvdata(dev
);
472 struct amdgpu_device
*adev
= ddev
->dev_private
;
475 uint32_t i
, mask
= 0;
478 for (i
= 0; i
< strlen(buf
); i
++) {
479 if (*(buf
+ i
) == '\n')
481 sub_str
[0] = *(buf
+ i
);
483 ret
= kstrtol(sub_str
, 0, &level
);
491 if (adev
->powerplay
.pp_funcs
->force_clock_level
)
492 amdgpu_dpm_force_clock_level(adev
, PP_PCIE
, mask
);
498 static ssize_t
amdgpu_get_pp_sclk_od(struct device
*dev
,
499 struct device_attribute
*attr
,
502 struct drm_device
*ddev
= dev_get_drvdata(dev
);
503 struct amdgpu_device
*adev
= ddev
->dev_private
;
506 if (adev
->powerplay
.pp_funcs
->get_sclk_od
)
507 value
= amdgpu_dpm_get_sclk_od(adev
);
509 return snprintf(buf
, PAGE_SIZE
, "%d\n", value
);
512 static ssize_t
amdgpu_set_pp_sclk_od(struct device
*dev
,
513 struct device_attribute
*attr
,
517 struct drm_device
*ddev
= dev_get_drvdata(dev
);
518 struct amdgpu_device
*adev
= ddev
->dev_private
;
522 ret
= kstrtol(buf
, 0, &value
);
528 if (adev
->powerplay
.pp_funcs
->set_sclk_od
)
529 amdgpu_dpm_set_sclk_od(adev
, (uint32_t)value
);
531 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
532 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_READJUST_POWER_STATE
, NULL
, NULL
);
534 adev
->pm
.dpm
.current_ps
= adev
->pm
.dpm
.boot_ps
;
535 amdgpu_pm_compute_clocks(adev
);
542 static ssize_t
amdgpu_get_pp_mclk_od(struct device
*dev
,
543 struct device_attribute
*attr
,
546 struct drm_device
*ddev
= dev_get_drvdata(dev
);
547 struct amdgpu_device
*adev
= ddev
->dev_private
;
550 if (adev
->powerplay
.pp_funcs
->get_mclk_od
)
551 value
= amdgpu_dpm_get_mclk_od(adev
);
553 return snprintf(buf
, PAGE_SIZE
, "%d\n", value
);
556 static ssize_t
amdgpu_set_pp_mclk_od(struct device
*dev
,
557 struct device_attribute
*attr
,
561 struct drm_device
*ddev
= dev_get_drvdata(dev
);
562 struct amdgpu_device
*adev
= ddev
->dev_private
;
566 ret
= kstrtol(buf
, 0, &value
);
572 if (adev
->powerplay
.pp_funcs
->set_mclk_od
)
573 amdgpu_dpm_set_mclk_od(adev
, (uint32_t)value
);
575 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
576 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_READJUST_POWER_STATE
, NULL
, NULL
);
578 adev
->pm
.dpm
.current_ps
= adev
->pm
.dpm
.boot_ps
;
579 amdgpu_pm_compute_clocks(adev
);
586 static ssize_t
amdgpu_get_pp_power_profile(struct device
*dev
,
587 char *buf
, struct amd_pp_profile
*query
)
589 struct drm_device
*ddev
= dev_get_drvdata(dev
);
590 struct amdgpu_device
*adev
= ddev
->dev_private
;
593 if (adev
->powerplay
.pp_funcs
->get_power_profile_state
)
594 ret
= amdgpu_dpm_get_power_profile_state(
600 return snprintf(buf
, PAGE_SIZE
,
602 query
->min_sclk
/ 100,
603 query
->min_mclk
/ 100,
604 query
->activity_threshold
,
609 static ssize_t
amdgpu_get_pp_gfx_power_profile(struct device
*dev
,
610 struct device_attribute
*attr
,
613 struct amd_pp_profile query
= {0};
615 query
.type
= AMD_PP_GFX_PROFILE
;
617 return amdgpu_get_pp_power_profile(dev
, buf
, &query
);
620 static ssize_t
amdgpu_get_pp_compute_power_profile(struct device
*dev
,
621 struct device_attribute
*attr
,
624 struct amd_pp_profile query
= {0};
626 query
.type
= AMD_PP_COMPUTE_PROFILE
;
628 return amdgpu_get_pp_power_profile(dev
, buf
, &query
);
631 static ssize_t
amdgpu_set_pp_power_profile(struct device
*dev
,
634 struct amd_pp_profile
*request
)
636 struct drm_device
*ddev
= dev_get_drvdata(dev
);
637 struct amdgpu_device
*adev
= ddev
->dev_private
;
639 char *sub_str
, buf_cpy
[128], *tmp_str
;
640 const char delimiter
[3] = {' ', '\n', '\0'};
644 if (strncmp("reset", buf
, strlen("reset")) == 0) {
645 if (adev
->powerplay
.pp_funcs
->reset_power_profile_state
)
646 ret
= amdgpu_dpm_reset_power_profile_state(
655 if (strncmp("set", buf
, strlen("set")) == 0) {
656 if (adev
->powerplay
.pp_funcs
->set_power_profile_state
)
657 ret
= amdgpu_dpm_set_power_profile_state(
667 if (count
+ 1 >= 128) {
672 memcpy(buf_cpy
, buf
, count
+ 1);
676 sub_str
= strsep(&tmp_str
, delimiter
);
677 ret
= kstrtol(sub_str
, 0, &value
);
685 /* input unit MHz convert to dpm table unit 10KHz*/
686 request
->min_sclk
= (uint32_t)value
* 100;
689 /* input unit MHz convert to dpm table unit 10KHz*/
690 request
->min_mclk
= (uint32_t)value
* 100;
693 request
->activity_threshold
= (uint16_t)value
;
696 request
->up_hyst
= (uint8_t)value
;
699 request
->down_hyst
= (uint8_t)value
;
707 if (adev
->powerplay
.pp_funcs
->set_power_profile_state
)
708 ret
= amdgpu_dpm_set_power_profile_state(adev
, request
);
717 static ssize_t
amdgpu_set_pp_gfx_power_profile(struct device
*dev
,
718 struct device_attribute
*attr
,
722 struct amd_pp_profile request
= {0};
724 request
.type
= AMD_PP_GFX_PROFILE
;
726 return amdgpu_set_pp_power_profile(dev
, buf
, count
, &request
);
729 static ssize_t
amdgpu_set_pp_compute_power_profile(struct device
*dev
,
730 struct device_attribute
*attr
,
734 struct amd_pp_profile request
= {0};
736 request
.type
= AMD_PP_COMPUTE_PROFILE
;
738 return amdgpu_set_pp_power_profile(dev
, buf
, count
, &request
);
741 static DEVICE_ATTR(power_dpm_state
, S_IRUGO
| S_IWUSR
, amdgpu_get_dpm_state
, amdgpu_set_dpm_state
);
742 static DEVICE_ATTR(power_dpm_force_performance_level
, S_IRUGO
| S_IWUSR
,
743 amdgpu_get_dpm_forced_performance_level
,
744 amdgpu_set_dpm_forced_performance_level
);
745 static DEVICE_ATTR(pp_num_states
, S_IRUGO
, amdgpu_get_pp_num_states
, NULL
);
746 static DEVICE_ATTR(pp_cur_state
, S_IRUGO
, amdgpu_get_pp_cur_state
, NULL
);
747 static DEVICE_ATTR(pp_force_state
, S_IRUGO
| S_IWUSR
,
748 amdgpu_get_pp_force_state
,
749 amdgpu_set_pp_force_state
);
750 static DEVICE_ATTR(pp_table
, S_IRUGO
| S_IWUSR
,
752 amdgpu_set_pp_table
);
753 static DEVICE_ATTR(pp_dpm_sclk
, S_IRUGO
| S_IWUSR
,
754 amdgpu_get_pp_dpm_sclk
,
755 amdgpu_set_pp_dpm_sclk
);
756 static DEVICE_ATTR(pp_dpm_mclk
, S_IRUGO
| S_IWUSR
,
757 amdgpu_get_pp_dpm_mclk
,
758 amdgpu_set_pp_dpm_mclk
);
759 static DEVICE_ATTR(pp_dpm_pcie
, S_IRUGO
| S_IWUSR
,
760 amdgpu_get_pp_dpm_pcie
,
761 amdgpu_set_pp_dpm_pcie
);
762 static DEVICE_ATTR(pp_sclk_od
, S_IRUGO
| S_IWUSR
,
763 amdgpu_get_pp_sclk_od
,
764 amdgpu_set_pp_sclk_od
);
765 static DEVICE_ATTR(pp_mclk_od
, S_IRUGO
| S_IWUSR
,
766 amdgpu_get_pp_mclk_od
,
767 amdgpu_set_pp_mclk_od
);
768 static DEVICE_ATTR(pp_gfx_power_profile
, S_IRUGO
| S_IWUSR
,
769 amdgpu_get_pp_gfx_power_profile
,
770 amdgpu_set_pp_gfx_power_profile
);
771 static DEVICE_ATTR(pp_compute_power_profile
, S_IRUGO
| S_IWUSR
,
772 amdgpu_get_pp_compute_power_profile
,
773 amdgpu_set_pp_compute_power_profile
);
775 static ssize_t
amdgpu_hwmon_show_temp(struct device
*dev
,
776 struct device_attribute
*attr
,
779 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
780 struct drm_device
*ddev
= adev
->ddev
;
783 /* Can't get temperature when the card is off */
784 if ((adev
->flags
& AMD_IS_PX
) &&
785 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
788 if (!adev
->powerplay
.pp_funcs
->get_temperature
)
791 temp
= amdgpu_dpm_get_temperature(adev
);
793 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
796 static ssize_t
amdgpu_hwmon_show_temp_thresh(struct device
*dev
,
797 struct device_attribute
*attr
,
800 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
801 int hyst
= to_sensor_dev_attr(attr
)->index
;
805 temp
= adev
->pm
.dpm
.thermal
.min_temp
;
807 temp
= adev
->pm
.dpm
.thermal
.max_temp
;
809 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
812 static ssize_t
amdgpu_hwmon_get_pwm1_enable(struct device
*dev
,
813 struct device_attribute
*attr
,
816 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
819 if (!adev
->powerplay
.pp_funcs
->get_fan_control_mode
)
822 pwm_mode
= amdgpu_dpm_get_fan_control_mode(adev
);
824 return sprintf(buf
, "%i\n", pwm_mode
);
827 static ssize_t
amdgpu_hwmon_set_pwm1_enable(struct device
*dev
,
828 struct device_attribute
*attr
,
832 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
836 if (!adev
->powerplay
.pp_funcs
->set_fan_control_mode
)
839 err
= kstrtoint(buf
, 10, &value
);
843 amdgpu_dpm_set_fan_control_mode(adev
, value
);
848 static ssize_t
amdgpu_hwmon_get_pwm1_min(struct device
*dev
,
849 struct device_attribute
*attr
,
852 return sprintf(buf
, "%i\n", 0);
855 static ssize_t
amdgpu_hwmon_get_pwm1_max(struct device
*dev
,
856 struct device_attribute
*attr
,
859 return sprintf(buf
, "%i\n", 255);
862 static ssize_t
amdgpu_hwmon_set_pwm1(struct device
*dev
,
863 struct device_attribute
*attr
,
864 const char *buf
, size_t count
)
866 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
870 err
= kstrtou32(buf
, 10, &value
);
874 value
= (value
* 100) / 255;
876 if (adev
->powerplay
.pp_funcs
->set_fan_speed_percent
) {
877 err
= amdgpu_dpm_set_fan_speed_percent(adev
, value
);
885 static ssize_t
amdgpu_hwmon_get_pwm1(struct device
*dev
,
886 struct device_attribute
*attr
,
889 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
893 if (adev
->powerplay
.pp_funcs
->get_fan_speed_percent
) {
894 err
= amdgpu_dpm_get_fan_speed_percent(adev
, &speed
);
899 speed
= (speed
* 255) / 100;
901 return sprintf(buf
, "%i\n", speed
);
904 static ssize_t
amdgpu_hwmon_get_fan1_input(struct device
*dev
,
905 struct device_attribute
*attr
,
908 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
912 if (adev
->powerplay
.pp_funcs
->get_fan_speed_rpm
) {
913 err
= amdgpu_dpm_get_fan_speed_rpm(adev
, &speed
);
918 return sprintf(buf
, "%i\n", speed
);
921 static SENSOR_DEVICE_ATTR(temp1_input
, S_IRUGO
, amdgpu_hwmon_show_temp
, NULL
, 0);
922 static SENSOR_DEVICE_ATTR(temp1_crit
, S_IRUGO
, amdgpu_hwmon_show_temp_thresh
, NULL
, 0);
923 static SENSOR_DEVICE_ATTR(temp1_crit_hyst
, S_IRUGO
, amdgpu_hwmon_show_temp_thresh
, NULL
, 1);
924 static SENSOR_DEVICE_ATTR(pwm1
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_get_pwm1
, amdgpu_hwmon_set_pwm1
, 0);
925 static SENSOR_DEVICE_ATTR(pwm1_enable
, S_IRUGO
| S_IWUSR
, amdgpu_hwmon_get_pwm1_enable
, amdgpu_hwmon_set_pwm1_enable
, 0);
926 static SENSOR_DEVICE_ATTR(pwm1_min
, S_IRUGO
, amdgpu_hwmon_get_pwm1_min
, NULL
, 0);
927 static SENSOR_DEVICE_ATTR(pwm1_max
, S_IRUGO
, amdgpu_hwmon_get_pwm1_max
, NULL
, 0);
928 static SENSOR_DEVICE_ATTR(fan1_input
, S_IRUGO
, amdgpu_hwmon_get_fan1_input
, NULL
, 0);
930 static struct attribute
*hwmon_attributes
[] = {
931 &sensor_dev_attr_temp1_input
.dev_attr
.attr
,
932 &sensor_dev_attr_temp1_crit
.dev_attr
.attr
,
933 &sensor_dev_attr_temp1_crit_hyst
.dev_attr
.attr
,
934 &sensor_dev_attr_pwm1
.dev_attr
.attr
,
935 &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
,
936 &sensor_dev_attr_pwm1_min
.dev_attr
.attr
,
937 &sensor_dev_attr_pwm1_max
.dev_attr
.attr
,
938 &sensor_dev_attr_fan1_input
.dev_attr
.attr
,
942 static umode_t
hwmon_attributes_visible(struct kobject
*kobj
,
943 struct attribute
*attr
, int index
)
945 struct device
*dev
= kobj_to_dev(kobj
);
946 struct amdgpu_device
*adev
= dev_get_drvdata(dev
);
947 umode_t effective_mode
= attr
->mode
;
949 /* Skip limit attributes if DPM is not enabled */
950 if (!adev
->pm
.dpm_enabled
&&
951 (attr
== &sensor_dev_attr_temp1_crit
.dev_attr
.attr
||
952 attr
== &sensor_dev_attr_temp1_crit_hyst
.dev_attr
.attr
||
953 attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
||
954 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
||
955 attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
956 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
))
959 /* Skip fan attributes if fan is not present */
960 if (adev
->pm
.no_fan
&&
961 (attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
||
962 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
||
963 attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
964 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
))
967 /* mask fan attributes if we have no bindings for this asic to expose */
968 if ((!adev
->powerplay
.pp_funcs
->get_fan_speed_percent
&&
969 attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
) || /* can't query fan */
970 (!adev
->powerplay
.pp_funcs
->get_fan_control_mode
&&
971 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
)) /* can't query state */
972 effective_mode
&= ~S_IRUGO
;
974 if ((!adev
->powerplay
.pp_funcs
->set_fan_speed_percent
&&
975 attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
) || /* can't manage fan */
976 (!adev
->powerplay
.pp_funcs
->set_fan_control_mode
&&
977 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
)) /* can't manage state */
978 effective_mode
&= ~S_IWUSR
;
980 /* hide max/min values if we can't both query and manage the fan */
981 if ((!adev
->powerplay
.pp_funcs
->set_fan_speed_percent
&&
982 !adev
->powerplay
.pp_funcs
->get_fan_speed_percent
) &&
983 (attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
984 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
))
987 /* requires powerplay */
988 if (attr
== &sensor_dev_attr_fan1_input
.dev_attr
.attr
)
991 return effective_mode
;
994 static const struct attribute_group hwmon_attrgroup
= {
995 .attrs
= hwmon_attributes
,
996 .is_visible
= hwmon_attributes_visible
,
999 static const struct attribute_group
*hwmon_groups
[] = {
1004 void amdgpu_dpm_thermal_work_handler(struct work_struct
*work
)
1006 struct amdgpu_device
*adev
=
1007 container_of(work
, struct amdgpu_device
,
1008 pm
.dpm
.thermal
.work
);
1009 /* switch to the thermal state */
1010 enum amd_pm_state_type dpm_state
= POWER_STATE_TYPE_INTERNAL_THERMAL
;
1012 if (!adev
->pm
.dpm_enabled
)
1015 if (adev
->powerplay
.pp_funcs
->get_temperature
) {
1016 int temp
= amdgpu_dpm_get_temperature(adev
);
1018 if (temp
< adev
->pm
.dpm
.thermal
.min_temp
)
1019 /* switch back the user state */
1020 dpm_state
= adev
->pm
.dpm
.user_state
;
1022 if (adev
->pm
.dpm
.thermal
.high_to_low
)
1023 /* switch back the user state */
1024 dpm_state
= adev
->pm
.dpm
.user_state
;
1026 mutex_lock(&adev
->pm
.mutex
);
1027 if (dpm_state
== POWER_STATE_TYPE_INTERNAL_THERMAL
)
1028 adev
->pm
.dpm
.thermal_active
= true;
1030 adev
->pm
.dpm
.thermal_active
= false;
1031 adev
->pm
.dpm
.state
= dpm_state
;
1032 mutex_unlock(&adev
->pm
.mutex
);
1034 amdgpu_pm_compute_clocks(adev
);
1037 static struct amdgpu_ps
*amdgpu_dpm_pick_power_state(struct amdgpu_device
*adev
,
1038 enum amd_pm_state_type dpm_state
)
1041 struct amdgpu_ps
*ps
;
1043 bool single_display
= (adev
->pm
.dpm
.new_active_crtc_count
< 2) ?
1046 /* check if the vblank period is too short to adjust the mclk */
1047 if (single_display
&& adev
->powerplay
.pp_funcs
->vblank_too_short
) {
1048 if (amdgpu_dpm_vblank_too_short(adev
))
1049 single_display
= false;
1052 /* certain older asics have a separare 3D performance state,
1053 * so try that first if the user selected performance
1055 if (dpm_state
== POWER_STATE_TYPE_PERFORMANCE
)
1056 dpm_state
= POWER_STATE_TYPE_INTERNAL_3DPERF
;
1057 /* balanced states don't exist at the moment */
1058 if (dpm_state
== POWER_STATE_TYPE_BALANCED
)
1059 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
1062 /* Pick the best power state based on current conditions */
1063 for (i
= 0; i
< adev
->pm
.dpm
.num_ps
; i
++) {
1064 ps
= &adev
->pm
.dpm
.ps
[i
];
1065 ui_class
= ps
->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK
;
1066 switch (dpm_state
) {
1068 case POWER_STATE_TYPE_BATTERY
:
1069 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
) {
1070 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
1077 case POWER_STATE_TYPE_BALANCED
:
1078 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BALANCED
) {
1079 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
1086 case POWER_STATE_TYPE_PERFORMANCE
:
1087 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
) {
1088 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
1095 /* internal states */
1096 case POWER_STATE_TYPE_INTERNAL_UVD
:
1097 if (adev
->pm
.dpm
.uvd_ps
)
1098 return adev
->pm
.dpm
.uvd_ps
;
1101 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
1102 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE
)
1105 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
1106 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE
)
1109 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
1110 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE
)
1113 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
1114 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_MVC
)
1117 case POWER_STATE_TYPE_INTERNAL_BOOT
:
1118 return adev
->pm
.dpm
.boot_ps
;
1119 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
1120 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_THERMAL
)
1123 case POWER_STATE_TYPE_INTERNAL_ACPI
:
1124 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_ACPI
)
1127 case POWER_STATE_TYPE_INTERNAL_ULV
:
1128 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_ULV
)
1131 case POWER_STATE_TYPE_INTERNAL_3DPERF
:
1132 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE
)
1139 /* use a fallback state if we didn't match */
1140 switch (dpm_state
) {
1141 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
1142 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD_HD
;
1143 goto restart_search
;
1144 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
1145 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
1146 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
1147 if (adev
->pm
.dpm
.uvd_ps
) {
1148 return adev
->pm
.dpm
.uvd_ps
;
1150 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
1151 goto restart_search
;
1153 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
1154 dpm_state
= POWER_STATE_TYPE_INTERNAL_ACPI
;
1155 goto restart_search
;
1156 case POWER_STATE_TYPE_INTERNAL_ACPI
:
1157 dpm_state
= POWER_STATE_TYPE_BATTERY
;
1158 goto restart_search
;
1159 case POWER_STATE_TYPE_BATTERY
:
1160 case POWER_STATE_TYPE_BALANCED
:
1161 case POWER_STATE_TYPE_INTERNAL_3DPERF
:
1162 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
1163 goto restart_search
;
1171 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device
*adev
)
1173 struct amdgpu_ps
*ps
;
1174 enum amd_pm_state_type dpm_state
;
1178 /* if dpm init failed */
1179 if (!adev
->pm
.dpm_enabled
)
1182 if (adev
->pm
.dpm
.user_state
!= adev
->pm
.dpm
.state
) {
1183 /* add other state override checks here */
1184 if ((!adev
->pm
.dpm
.thermal_active
) &&
1185 (!adev
->pm
.dpm
.uvd_active
))
1186 adev
->pm
.dpm
.state
= adev
->pm
.dpm
.user_state
;
1188 dpm_state
= adev
->pm
.dpm
.state
;
1190 ps
= amdgpu_dpm_pick_power_state(adev
, dpm_state
);
1192 adev
->pm
.dpm
.requested_ps
= ps
;
1196 if (amdgpu_dpm
== 1 && adev
->powerplay
.pp_funcs
->print_power_state
) {
1197 printk("switching from power state:\n");
1198 amdgpu_dpm_print_power_state(adev
, adev
->pm
.dpm
.current_ps
);
1199 printk("switching to power state:\n");
1200 amdgpu_dpm_print_power_state(adev
, adev
->pm
.dpm
.requested_ps
);
1203 /* update whether vce is active */
1204 ps
->vce_active
= adev
->pm
.dpm
.vce_active
;
1205 if (adev
->powerplay
.pp_funcs
->display_configuration_changed
)
1206 amdgpu_dpm_display_configuration_changed(adev
);
1208 ret
= amdgpu_dpm_pre_set_power_state(adev
);
1212 if (adev
->powerplay
.pp_funcs
->check_state_equal
) {
1213 if (0 != amdgpu_dpm_check_state_equal(adev
, adev
->pm
.dpm
.current_ps
, adev
->pm
.dpm
.requested_ps
, &equal
))
1220 amdgpu_dpm_set_power_state(adev
);
1221 amdgpu_dpm_post_set_power_state(adev
);
1223 adev
->pm
.dpm
.current_active_crtcs
= adev
->pm
.dpm
.new_active_crtcs
;
1224 adev
->pm
.dpm
.current_active_crtc_count
= adev
->pm
.dpm
.new_active_crtc_count
;
1226 if (adev
->powerplay
.pp_funcs
->force_performance_level
) {
1227 if (adev
->pm
.dpm
.thermal_active
) {
1228 enum amd_dpm_forced_level level
= adev
->pm
.dpm
.forced_level
;
1229 /* force low perf level for thermal */
1230 amdgpu_dpm_force_performance_level(adev
, AMD_DPM_FORCED_LEVEL_LOW
);
1231 /* save the user's level */
1232 adev
->pm
.dpm
.forced_level
= level
;
1234 /* otherwise, user selected level */
1235 amdgpu_dpm_force_performance_level(adev
, adev
->pm
.dpm
.forced_level
);
1240 void amdgpu_dpm_enable_uvd(struct amdgpu_device
*adev
, bool enable
)
1242 if (adev
->powerplay
.pp_funcs
->powergate_uvd
) {
1243 /* enable/disable UVD */
1244 mutex_lock(&adev
->pm
.mutex
);
1245 amdgpu_dpm_powergate_uvd(adev
, !enable
);
1246 mutex_unlock(&adev
->pm
.mutex
);
1249 mutex_lock(&adev
->pm
.mutex
);
1250 adev
->pm
.dpm
.uvd_active
= true;
1251 adev
->pm
.dpm
.state
= POWER_STATE_TYPE_INTERNAL_UVD
;
1252 mutex_unlock(&adev
->pm
.mutex
);
1254 mutex_lock(&adev
->pm
.mutex
);
1255 adev
->pm
.dpm
.uvd_active
= false;
1256 mutex_unlock(&adev
->pm
.mutex
);
1258 amdgpu_pm_compute_clocks(adev
);
1262 void amdgpu_dpm_enable_vce(struct amdgpu_device
*adev
, bool enable
)
1264 if (adev
->powerplay
.pp_funcs
->powergate_vce
) {
1265 /* enable/disable VCE */
1266 mutex_lock(&adev
->pm
.mutex
);
1267 amdgpu_dpm_powergate_vce(adev
, !enable
);
1268 mutex_unlock(&adev
->pm
.mutex
);
1271 mutex_lock(&adev
->pm
.mutex
);
1272 adev
->pm
.dpm
.vce_active
= true;
1273 /* XXX select vce level based on ring/task */
1274 adev
->pm
.dpm
.vce_level
= AMD_VCE_LEVEL_AC_ALL
;
1275 mutex_unlock(&adev
->pm
.mutex
);
1276 amdgpu_set_clockgating_state(adev
, AMD_IP_BLOCK_TYPE_VCE
,
1277 AMD_CG_STATE_UNGATE
);
1278 amdgpu_set_powergating_state(adev
, AMD_IP_BLOCK_TYPE_VCE
,
1279 AMD_PG_STATE_UNGATE
);
1280 amdgpu_pm_compute_clocks(adev
);
1282 amdgpu_set_powergating_state(adev
, AMD_IP_BLOCK_TYPE_VCE
,
1284 amdgpu_set_clockgating_state(adev
, AMD_IP_BLOCK_TYPE_VCE
,
1286 mutex_lock(&adev
->pm
.mutex
);
1287 adev
->pm
.dpm
.vce_active
= false;
1288 mutex_unlock(&adev
->pm
.mutex
);
1289 amdgpu_pm_compute_clocks(adev
);
1295 void amdgpu_pm_print_power_states(struct amdgpu_device
*adev
)
1299 if (adev
->powerplay
.pp_funcs
->print_power_state
== NULL
)
1302 for (i
= 0; i
< adev
->pm
.dpm
.num_ps
; i
++)
1303 amdgpu_dpm_print_power_state(adev
, &adev
->pm
.dpm
.ps
[i
]);
1307 int amdgpu_pm_sysfs_init(struct amdgpu_device
*adev
)
1311 if (adev
->pm
.sysfs_initialized
)
1314 if (adev
->pm
.dpm_enabled
== 0)
1317 if (adev
->powerplay
.pp_funcs
->get_temperature
== NULL
)
1320 adev
->pm
.int_hwmon_dev
= hwmon_device_register_with_groups(adev
->dev
,
1323 if (IS_ERR(adev
->pm
.int_hwmon_dev
)) {
1324 ret
= PTR_ERR(adev
->pm
.int_hwmon_dev
);
1326 "Unable to register hwmon device: %d\n", ret
);
1330 ret
= device_create_file(adev
->dev
, &dev_attr_power_dpm_state
);
1332 DRM_ERROR("failed to create device file for dpm state\n");
1335 ret
= device_create_file(adev
->dev
, &dev_attr_power_dpm_force_performance_level
);
1337 DRM_ERROR("failed to create device file for dpm state\n");
1342 ret
= device_create_file(adev
->dev
, &dev_attr_pp_num_states
);
1344 DRM_ERROR("failed to create device file pp_num_states\n");
1347 ret
= device_create_file(adev
->dev
, &dev_attr_pp_cur_state
);
1349 DRM_ERROR("failed to create device file pp_cur_state\n");
1352 ret
= device_create_file(adev
->dev
, &dev_attr_pp_force_state
);
1354 DRM_ERROR("failed to create device file pp_force_state\n");
1357 ret
= device_create_file(adev
->dev
, &dev_attr_pp_table
);
1359 DRM_ERROR("failed to create device file pp_table\n");
1363 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_sclk
);
1365 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1368 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_mclk
);
1370 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1373 ret
= device_create_file(adev
->dev
, &dev_attr_pp_dpm_pcie
);
1375 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1378 ret
= device_create_file(adev
->dev
, &dev_attr_pp_sclk_od
);
1380 DRM_ERROR("failed to create device file pp_sclk_od\n");
1383 ret
= device_create_file(adev
->dev
, &dev_attr_pp_mclk_od
);
1385 DRM_ERROR("failed to create device file pp_mclk_od\n");
1388 ret
= device_create_file(adev
->dev
,
1389 &dev_attr_pp_gfx_power_profile
);
1391 DRM_ERROR("failed to create device file "
1392 "pp_gfx_power_profile\n");
1395 ret
= device_create_file(adev
->dev
,
1396 &dev_attr_pp_compute_power_profile
);
1398 DRM_ERROR("failed to create device file "
1399 "pp_compute_power_profile\n");
1403 ret
= amdgpu_debugfs_pm_init(adev
);
1405 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1409 adev
->pm
.sysfs_initialized
= true;
1414 void amdgpu_pm_sysfs_fini(struct amdgpu_device
*adev
)
1416 if (adev
->pm
.dpm_enabled
== 0)
1419 if (adev
->pm
.int_hwmon_dev
)
1420 hwmon_device_unregister(adev
->pm
.int_hwmon_dev
);
1421 device_remove_file(adev
->dev
, &dev_attr_power_dpm_state
);
1422 device_remove_file(adev
->dev
, &dev_attr_power_dpm_force_performance_level
);
1424 device_remove_file(adev
->dev
, &dev_attr_pp_num_states
);
1425 device_remove_file(adev
->dev
, &dev_attr_pp_cur_state
);
1426 device_remove_file(adev
->dev
, &dev_attr_pp_force_state
);
1427 device_remove_file(adev
->dev
, &dev_attr_pp_table
);
1429 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_sclk
);
1430 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_mclk
);
1431 device_remove_file(adev
->dev
, &dev_attr_pp_dpm_pcie
);
1432 device_remove_file(adev
->dev
, &dev_attr_pp_sclk_od
);
1433 device_remove_file(adev
->dev
, &dev_attr_pp_mclk_od
);
1434 device_remove_file(adev
->dev
,
1435 &dev_attr_pp_gfx_power_profile
);
1436 device_remove_file(adev
->dev
,
1437 &dev_attr_pp_compute_power_profile
);
1440 void amdgpu_pm_compute_clocks(struct amdgpu_device
*adev
)
1442 struct drm_device
*ddev
= adev
->ddev
;
1443 struct drm_crtc
*crtc
;
1444 struct amdgpu_crtc
*amdgpu_crtc
;
1447 if (!adev
->pm
.dpm_enabled
)
1450 if (adev
->mode_info
.num_crtc
)
1451 amdgpu_display_bandwidth_update(adev
);
1453 for (i
= 0; i
< AMDGPU_MAX_RINGS
; i
++) {
1454 struct amdgpu_ring
*ring
= adev
->rings
[i
];
1455 if (ring
&& ring
->ready
)
1456 amdgpu_fence_wait_empty(ring
);
1459 if (adev
->powerplay
.pp_funcs
->dispatch_tasks
) {
1460 amdgpu_dpm_dispatch_task(adev
, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE
, NULL
, NULL
);
1462 mutex_lock(&adev
->pm
.mutex
);
1463 adev
->pm
.dpm
.new_active_crtcs
= 0;
1464 adev
->pm
.dpm
.new_active_crtc_count
= 0;
1465 if (adev
->mode_info
.num_crtc
&& adev
->mode_info
.mode_config_initialized
) {
1466 list_for_each_entry(crtc
,
1467 &ddev
->mode_config
.crtc_list
, head
) {
1468 amdgpu_crtc
= to_amdgpu_crtc(crtc
);
1469 if (amdgpu_crtc
->enabled
) {
1470 adev
->pm
.dpm
.new_active_crtcs
|= (1 << amdgpu_crtc
->crtc_id
);
1471 adev
->pm
.dpm
.new_active_crtc_count
++;
1475 /* update battery/ac status */
1476 if (power_supply_is_system_supplied() > 0)
1477 adev
->pm
.dpm
.ac_power
= true;
1479 adev
->pm
.dpm
.ac_power
= false;
1481 amdgpu_dpm_change_power_state_locked(adev
);
1483 mutex_unlock(&adev
->pm
.mutex
);
1490 #if defined(CONFIG_DEBUG_FS)
1492 static int amdgpu_debugfs_pm_info_pp(struct seq_file
*m
, struct amdgpu_device
*adev
)
1495 struct pp_gpu_power query
= {0};
1498 /* sanity check PP is enabled */
1499 if (!(adev
->powerplay
.pp_funcs
&&
1500 adev
->powerplay
.pp_funcs
->read_sensor
))
1504 size
= sizeof(value
);
1505 seq_printf(m
, "GFX Clocks and Power:\n");
1506 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GFX_MCLK
, (void *)&value
, &size
))
1507 seq_printf(m
, "\t%u MHz (MCLK)\n", value
/100);
1508 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GFX_SCLK
, (void *)&value
, &size
))
1509 seq_printf(m
, "\t%u MHz (SCLK)\n", value
/100);
1510 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDGFX
, (void *)&value
, &size
))
1511 seq_printf(m
, "\t%u mV (VDDGFX)\n", value
);
1512 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VDDNB
, (void *)&value
, &size
))
1513 seq_printf(m
, "\t%u mV (VDDNB)\n", value
);
1514 size
= sizeof(query
);
1515 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_POWER
, (void *)&query
, &size
)) {
1516 seq_printf(m
, "\t%u.%u W (VDDC)\n", query
.vddc_power
>> 8,
1517 query
.vddc_power
& 0xff);
1518 seq_printf(m
, "\t%u.%u W (VDDCI)\n", query
.vddci_power
>> 8,
1519 query
.vddci_power
& 0xff);
1520 seq_printf(m
, "\t%u.%u W (max GPU)\n", query
.max_gpu_power
>> 8,
1521 query
.max_gpu_power
& 0xff);
1522 seq_printf(m
, "\t%u.%u W (average GPU)\n", query
.average_gpu_power
>> 8,
1523 query
.average_gpu_power
& 0xff);
1525 size
= sizeof(value
);
1526 seq_printf(m
, "\n");
1529 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_TEMP
, (void *)&value
, &size
))
1530 seq_printf(m
, "GPU Temperature: %u C\n", value
/1000);
1533 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_GPU_LOAD
, (void *)&value
, &size
))
1534 seq_printf(m
, "GPU Load: %u %%\n", value
);
1535 seq_printf(m
, "\n");
1538 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_UVD_POWER
, (void *)&value
, &size
)) {
1540 seq_printf(m
, "UVD: Disabled\n");
1542 seq_printf(m
, "UVD: Enabled\n");
1543 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_UVD_DCLK
, (void *)&value
, &size
))
1544 seq_printf(m
, "\t%u MHz (DCLK)\n", value
/100);
1545 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_UVD_VCLK
, (void *)&value
, &size
))
1546 seq_printf(m
, "\t%u MHz (VCLK)\n", value
/100);
1549 seq_printf(m
, "\n");
1552 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VCE_POWER
, (void *)&value
, &size
)) {
1554 seq_printf(m
, "VCE: Disabled\n");
1556 seq_printf(m
, "VCE: Enabled\n");
1557 if (!amdgpu_dpm_read_sensor(adev
, AMDGPU_PP_SENSOR_VCE_ECCLK
, (void *)&value
, &size
))
1558 seq_printf(m
, "\t%u MHz (ECCLK)\n", value
/100);
1565 static void amdgpu_parse_cg_state(struct seq_file
*m
, u32 flags
)
1569 for (i
= 0; clocks
[i
].flag
; i
++)
1570 seq_printf(m
, "\t%s: %s\n", clocks
[i
].name
,
1571 (flags
& clocks
[i
].flag
) ? "On" : "Off");
1574 static int amdgpu_debugfs_pm_info(struct seq_file
*m
, void *data
)
1576 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1577 struct drm_device
*dev
= node
->minor
->dev
;
1578 struct amdgpu_device
*adev
= dev
->dev_private
;
1579 struct drm_device
*ddev
= adev
->ddev
;
1582 amdgpu_get_clockgating_state(adev
, &flags
);
1583 seq_printf(m
, "Clock Gating Flags Mask: 0x%x\n", flags
);
1584 amdgpu_parse_cg_state(m
, flags
);
1585 seq_printf(m
, "\n");
1587 if (!adev
->pm
.dpm_enabled
) {
1588 seq_printf(m
, "dpm not enabled\n");
1591 if ((adev
->flags
& AMD_IS_PX
) &&
1592 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
)) {
1593 seq_printf(m
, "PX asic powered off\n");
1594 } else if (adev
->powerplay
.pp_funcs
->debugfs_print_current_performance_level
) {
1595 mutex_lock(&adev
->pm
.mutex
);
1596 if (adev
->powerplay
.pp_funcs
->debugfs_print_current_performance_level
)
1597 adev
->powerplay
.pp_funcs
->debugfs_print_current_performance_level(adev
, m
);
1599 seq_printf(m
, "Debugfs support not implemented for this asic\n");
1600 mutex_unlock(&adev
->pm
.mutex
);
1602 return amdgpu_debugfs_pm_info_pp(m
, adev
);
1608 static const struct drm_info_list amdgpu_pm_info_list
[] = {
1609 {"amdgpu_pm_info", amdgpu_debugfs_pm_info
, 0, NULL
},
1613 static int amdgpu_debugfs_pm_init(struct amdgpu_device
*adev
)
1615 #if defined(CONFIG_DEBUG_FS)
1616 return amdgpu_debugfs_add_files(adev
, amdgpu_pm_info_list
, ARRAY_SIZE(amdgpu_pm_info_list
));