2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
33 #include <drm/amdgpu_drm.h>
39 * Most engines on the GPU are fed via ring buffers. Ring
40 * buffers are areas of GPU accessible memory that the host
41 * writes commands into and the GPU reads commands out of.
42 * There is a rptr (read pointer) that determines where the
43 * GPU is currently reading, and a wptr (write pointer)
44 * which determines where the host has written. When the
45 * pointers are equal, the ring is idle. When the host
46 * writes commands to the ring buffer, it increments the
47 * wptr. The GPU then starts fetching commands and executes
48 * them until the pointers are equal again.
50 static int amdgpu_debugfs_ring_init(struct amdgpu_device
*adev
,
51 struct amdgpu_ring
*ring
);
52 static void amdgpu_debugfs_ring_fini(struct amdgpu_ring
*ring
);
55 * amdgpu_ring_alloc - allocate space on the ring buffer
57 * @adev: amdgpu_device pointer
58 * @ring: amdgpu_ring structure holding ring information
59 * @ndw: number of dwords to allocate in the ring buffer
61 * Allocate @ndw dwords in the ring buffer (all asics).
62 * Returns 0 on success, error on failure.
64 int amdgpu_ring_alloc(struct amdgpu_ring
*ring
, unsigned ndw
)
66 /* Align requested size with padding so unlock_commit can
68 ndw
= (ndw
+ ring
->funcs
->align_mask
) & ~ring
->funcs
->align_mask
;
70 /* Make sure we aren't trying to allocate more space
71 * than the maximum for one submission
73 if (WARN_ON_ONCE(ndw
> ring
->max_dw
))
77 ring
->wptr_old
= ring
->wptr
;
79 if (ring
->funcs
->begin_use
)
80 ring
->funcs
->begin_use(ring
);
85 /** amdgpu_ring_insert_nop - insert NOP packets
87 * @ring: amdgpu_ring structure holding ring information
88 * @count: the number of NOP packets to insert
90 * This is the generic insert_nop function for rings except SDMA
92 void amdgpu_ring_insert_nop(struct amdgpu_ring
*ring
, uint32_t count
)
96 for (i
= 0; i
< count
; i
++)
97 amdgpu_ring_write(ring
, ring
->funcs
->nop
);
100 /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets
102 * @ring: amdgpu_ring structure holding ring information
103 * @ib: IB to add NOP packets to
105 * This is the generic pad_ib function for rings except SDMA
107 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring
*ring
, struct amdgpu_ib
*ib
)
109 while (ib
->length_dw
& ring
->funcs
->align_mask
)
110 ib
->ptr
[ib
->length_dw
++] = ring
->funcs
->nop
;
114 * amdgpu_ring_commit - tell the GPU to execute the new
115 * commands on the ring buffer
117 * @adev: amdgpu_device pointer
118 * @ring: amdgpu_ring structure holding ring information
120 * Update the wptr (write pointer) to tell the GPU to
121 * execute new commands on the ring buffer (all asics).
123 void amdgpu_ring_commit(struct amdgpu_ring
*ring
)
127 /* We pad to match fetch size */
128 count
= ring
->funcs
->align_mask
+ 1 -
129 (ring
->wptr
& ring
->funcs
->align_mask
);
130 count
%= ring
->funcs
->align_mask
+ 1;
131 ring
->funcs
->insert_nop(ring
, count
);
134 amdgpu_ring_set_wptr(ring
);
136 if (ring
->funcs
->end_use
)
137 ring
->funcs
->end_use(ring
);
139 amdgpu_ring_lru_touch(ring
->adev
, ring
);
143 * amdgpu_ring_undo - reset the wptr
145 * @ring: amdgpu_ring structure holding ring information
147 * Reset the driver's copy of the wptr (all asics).
149 void amdgpu_ring_undo(struct amdgpu_ring
*ring
)
151 ring
->wptr
= ring
->wptr_old
;
153 if (ring
->funcs
->end_use
)
154 ring
->funcs
->end_use(ring
);
158 * amdgpu_ring_priority_put - restore a ring's priority
160 * @ring: amdgpu_ring structure holding the information
161 * @priority: target priority
163 * Release a request for executing at @priority
165 void amdgpu_ring_priority_put(struct amdgpu_ring
*ring
,
166 enum amd_sched_priority priority
)
170 if (!ring
->funcs
->set_priority
)
173 if (atomic_dec_return(&ring
->num_jobs
[priority
]) > 0)
176 /* no need to restore if the job is already at the lowest priority */
177 if (priority
== AMD_SCHED_PRIORITY_NORMAL
)
180 mutex_lock(&ring
->priority_mutex
);
181 /* something higher prio is executing, no need to decay */
182 if (ring
->priority
> priority
)
185 /* decay priority to the next level with a job available */
186 for (i
= priority
; i
>= AMD_SCHED_PRIORITY_MIN
; i
--) {
187 if (i
== AMD_SCHED_PRIORITY_NORMAL
188 || atomic_read(&ring
->num_jobs
[i
])) {
190 ring
->funcs
->set_priority(ring
, i
);
196 mutex_unlock(&ring
->priority_mutex
);
200 * amdgpu_ring_priority_get - change the ring's priority
202 * @ring: amdgpu_ring structure holding the information
203 * @priority: target priority
205 * Request a ring's priority to be raised to @priority (refcounted).
207 void amdgpu_ring_priority_get(struct amdgpu_ring
*ring
,
208 enum amd_sched_priority priority
)
210 if (!ring
->funcs
->set_priority
)
213 atomic_inc(&ring
->num_jobs
[priority
]);
215 mutex_lock(&ring
->priority_mutex
);
216 if (priority
<= ring
->priority
)
219 ring
->priority
= priority
;
220 ring
->funcs
->set_priority(ring
, priority
);
223 mutex_unlock(&ring
->priority_mutex
);
227 * amdgpu_ring_init - init driver ring struct.
229 * @adev: amdgpu_device pointer
230 * @ring: amdgpu_ring structure holding ring information
231 * @max_ndw: maximum number of dw for ring alloc
232 * @nop: nop packet for this ring
234 * Initialize the driver information for the selected ring (all asics).
235 * Returns 0 on success, error on failure.
237 int amdgpu_ring_init(struct amdgpu_device
*adev
, struct amdgpu_ring
*ring
,
238 unsigned max_dw
, struct amdgpu_irq_src
*irq_src
,
242 int sched_hw_submission
= amdgpu_sched_hw_submission
;
244 /* Set the hw submission limit higher for KIQ because
245 * it's used for a number of gfx/compute tasks by both
246 * KFD and KGD which may have outstanding fences and
247 * it doesn't really use the gpu scheduler anyway;
248 * KIQ tasks get submitted directly to the ring.
250 if (ring
->funcs
->type
== AMDGPU_RING_TYPE_KIQ
)
251 sched_hw_submission
= max(sched_hw_submission
, 256);
253 if (ring
->adev
== NULL
) {
254 if (adev
->num_rings
>= AMDGPU_MAX_RINGS
)
258 ring
->idx
= adev
->num_rings
++;
259 adev
->rings
[ring
->idx
] = ring
;
260 r
= amdgpu_fence_driver_init_ring(ring
, sched_hw_submission
);
265 r
= amdgpu_wb_get(adev
, &ring
->rptr_offs
);
267 dev_err(adev
->dev
, "(%d) ring rptr_offs wb alloc failed\n", r
);
271 r
= amdgpu_wb_get(adev
, &ring
->wptr_offs
);
273 dev_err(adev
->dev
, "(%d) ring wptr_offs wb alloc failed\n", r
);
277 r
= amdgpu_wb_get(adev
, &ring
->fence_offs
);
279 dev_err(adev
->dev
, "(%d) ring fence_offs wb alloc failed\n", r
);
283 r
= amdgpu_wb_get(adev
, &ring
->cond_exe_offs
);
285 dev_err(adev
->dev
, "(%d) ring cond_exec_polling wb alloc failed\n", r
);
288 ring
->cond_exe_gpu_addr
= adev
->wb
.gpu_addr
+ (ring
->cond_exe_offs
* 4);
289 ring
->cond_exe_cpu_addr
= &adev
->wb
.wb
[ring
->cond_exe_offs
];
290 /* always set cond_exec_polling to CONTINUE */
291 *ring
->cond_exe_cpu_addr
= 1;
293 r
= amdgpu_fence_driver_start_ring(ring
, irq_src
, irq_type
);
295 dev_err(adev
->dev
, "failed initializing fences (%d).\n", r
);
299 ring
->ring_size
= roundup_pow_of_two(max_dw
* 4 * sched_hw_submission
);
301 ring
->buf_mask
= (ring
->ring_size
/ 4) - 1;
302 ring
->ptr_mask
= ring
->funcs
->support_64bit_ptrs
?
303 0xffffffffffffffff : ring
->buf_mask
;
304 /* Allocate ring buffer */
305 if (ring
->ring_obj
== NULL
) {
306 r
= amdgpu_bo_create_kernel(adev
, ring
->ring_size
, PAGE_SIZE
,
307 AMDGPU_GEM_DOMAIN_GTT
,
310 (void **)&ring
->ring
);
312 dev_err(adev
->dev
, "(%d) ring create failed\n", r
);
315 amdgpu_ring_clear_ring(ring
);
318 ring
->max_dw
= max_dw
;
319 ring
->priority
= AMD_SCHED_PRIORITY_NORMAL
;
320 mutex_init(&ring
->priority_mutex
);
321 INIT_LIST_HEAD(&ring
->lru_list
);
322 amdgpu_ring_lru_touch(adev
, ring
);
324 for (i
= 0; i
< AMD_SCHED_PRIORITY_MAX
; ++i
)
325 atomic_set(&ring
->num_jobs
[i
], 0);
327 if (amdgpu_debugfs_ring_init(adev
, ring
)) {
328 DRM_ERROR("Failed to register debugfs file for rings !\n");
335 * amdgpu_ring_fini - tear down the driver ring struct.
337 * @adev: amdgpu_device pointer
338 * @ring: amdgpu_ring structure holding ring information
340 * Tear down the driver information for the selected ring (all asics).
342 void amdgpu_ring_fini(struct amdgpu_ring
*ring
)
346 /* Not to finish a ring which is not initialized */
347 if (!(ring
->adev
) || !(ring
->adev
->rings
[ring
->idx
]))
350 amdgpu_wb_free(ring
->adev
, ring
->rptr_offs
);
351 amdgpu_wb_free(ring
->adev
, ring
->wptr_offs
);
353 amdgpu_wb_free(ring
->adev
, ring
->cond_exe_offs
);
354 amdgpu_wb_free(ring
->adev
, ring
->fence_offs
);
356 amdgpu_bo_free_kernel(&ring
->ring_obj
,
358 (void **)&ring
->ring
);
360 amdgpu_debugfs_ring_fini(ring
);
362 ring
->adev
->rings
[ring
->idx
] = NULL
;
365 static void amdgpu_ring_lru_touch_locked(struct amdgpu_device
*adev
,
366 struct amdgpu_ring
*ring
)
368 /* list_move_tail handles the case where ring isn't part of the list */
369 list_move_tail(&ring
->lru_list
, &adev
->ring_lru_list
);
372 static bool amdgpu_ring_is_blacklisted(struct amdgpu_ring
*ring
,
373 int *blacklist
, int num_blacklist
)
377 for (i
= 0; i
< num_blacklist
; i
++) {
378 if (ring
->idx
== blacklist
[i
])
386 * amdgpu_ring_lru_get - get the least recently used ring for a HW IP block
388 * @adev: amdgpu_device pointer
389 * @type: amdgpu_ring_type enum
390 * @blacklist: blacklisted ring ids array
391 * @num_blacklist: number of entries in @blacklist
392 * @lru_pipe_order: find a ring from the least recently used pipe
395 * Retrieve the amdgpu_ring structure for the least recently used ring of
396 * a specific IP block (all asics).
397 * Returns 0 on success, error on failure.
399 int amdgpu_ring_lru_get(struct amdgpu_device
*adev
, int type
,
400 int *blacklist
, int num_blacklist
,
401 bool lru_pipe_order
, struct amdgpu_ring
**ring
)
403 struct amdgpu_ring
*entry
;
405 /* List is sorted in LRU order, find first entry corresponding
406 * to the desired HW IP */
408 spin_lock(&adev
->ring_lru_list_lock
);
409 list_for_each_entry(entry
, &adev
->ring_lru_list
, lru_list
) {
410 if (entry
->funcs
->type
!= type
)
413 if (amdgpu_ring_is_blacklisted(entry
, blacklist
, num_blacklist
))
419 /* We are done for ring LRU */
424 /* Move all rings on the same pipe to the end of the list */
425 if (entry
->pipe
== (*ring
)->pipe
)
426 amdgpu_ring_lru_touch_locked(adev
, entry
);
429 /* Move the ring we found to the end of the list */
431 amdgpu_ring_lru_touch_locked(adev
, *ring
);
433 spin_unlock(&adev
->ring_lru_list_lock
);
436 DRM_ERROR("Ring LRU contains no entries for ring type:%d\n", type
);
444 * amdgpu_ring_lru_touch - mark a ring as recently being used
446 * @adev: amdgpu_device pointer
447 * @ring: ring to touch
449 * Move @ring to the tail of the lru list
451 void amdgpu_ring_lru_touch(struct amdgpu_device
*adev
, struct amdgpu_ring
*ring
)
453 spin_lock(&adev
->ring_lru_list_lock
);
454 amdgpu_ring_lru_touch_locked(adev
, ring
);
455 spin_unlock(&adev
->ring_lru_list_lock
);
461 #if defined(CONFIG_DEBUG_FS)
463 /* Layout of file is 12 bytes consisting of
466 * - driver's copy of wptr
468 * followed by n-words of ring data
470 static ssize_t
amdgpu_debugfs_ring_read(struct file
*f
, char __user
*buf
,
471 size_t size
, loff_t
*pos
)
473 struct amdgpu_ring
*ring
= file_inode(f
)->i_private
;
475 uint32_t value
, result
, early
[3];
477 if (*pos
& 3 || size
& 3)
483 early
[0] = amdgpu_ring_get_rptr(ring
);
484 early
[1] = amdgpu_ring_get_wptr(ring
) & ring
->buf_mask
;
485 early
[2] = ring
->wptr
& ring
->buf_mask
;
486 for (i
= *pos
/ 4; i
< 3 && size
; i
++) {
487 r
= put_user(early
[i
], (uint32_t *)buf
);
498 if (*pos
>= (ring
->ring_size
+ 12))
501 value
= ring
->ring
[(*pos
- 12)/4];
502 r
= put_user(value
, (uint32_t*)buf
);
514 static const struct file_operations amdgpu_debugfs_ring_fops
= {
515 .owner
= THIS_MODULE
,
516 .read
= amdgpu_debugfs_ring_read
,
517 .llseek
= default_llseek
522 static int amdgpu_debugfs_ring_init(struct amdgpu_device
*adev
,
523 struct amdgpu_ring
*ring
)
525 #if defined(CONFIG_DEBUG_FS)
526 struct drm_minor
*minor
= adev
->ddev
->primary
;
527 struct dentry
*ent
, *root
= minor
->debugfs_root
;
530 sprintf(name
, "amdgpu_ring_%s", ring
->name
);
532 ent
= debugfs_create_file(name
,
533 S_IFREG
| S_IRUGO
, root
,
534 ring
, &amdgpu_debugfs_ring_fops
);
538 i_size_write(ent
->d_inode
, ring
->ring_size
+ 12);
544 static void amdgpu_debugfs_ring_fini(struct amdgpu_ring
*ring
)
546 #if defined(CONFIG_DEBUG_FS)
547 debugfs_remove(ring
->ent
);