drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __AMDGPU_RLC_H__
  25 #define __AMDGPU_RLC_H__
  26
  27 #include "clearstate_defs.h"
  28
  29 /* firmware ID used in rlc toc */
  30 typedef enum _FIRMWARE_ID_ {
  31         FIRMWARE_ID_INVALID                                     = 0,
  32         FIRMWARE_ID_RLC_G_UCODE                                 = 1,
  33         FIRMWARE_ID_RLC_TOC                                     = 2,
  34         FIRMWARE_ID_RLCG_SCRATCH                                = 3,
  35         FIRMWARE_ID_RLC_SRM_ARAM                                = 4,
  36         FIRMWARE_ID_RLC_SRM_INDEX_ADDR                          = 5,
  37         FIRMWARE_ID_RLC_SRM_INDEX_DATA                          = 6,
  38         FIRMWARE_ID_RLC_P_UCODE                                 = 7,
  39         FIRMWARE_ID_RLC_V_UCODE                                 = 8,
  40         FIRMWARE_ID_RLX6_UCODE                                  = 9,
  41         FIRMWARE_ID_RLX6_DRAM_BOOT                              = 10,
  42         FIRMWARE_ID_GLOBAL_TAP_DELAYS                           = 11,
  43         FIRMWARE_ID_SE0_TAP_DELAYS                              = 12,
  44         FIRMWARE_ID_SE1_TAP_DELAYS                              = 13,
  45         FIRMWARE_ID_GLOBAL_SE0_SE1_SKEW_DELAYS                  = 14,
  46         FIRMWARE_ID_SDMA0_UCODE                                 = 15,
  47         FIRMWARE_ID_SDMA0_JT                                    = 16,
  48         FIRMWARE_ID_SDMA1_UCODE                                 = 17,
  49         FIRMWARE_ID_SDMA1_JT                                    = 18,
  50         FIRMWARE_ID_CP_CE                                       = 19,
  51         FIRMWARE_ID_CP_PFP                                      = 20,
  52         FIRMWARE_ID_CP_ME                                       = 21,
  53         FIRMWARE_ID_CP_MEC                                      = 22,
  54         FIRMWARE_ID_CP_MES                                      = 23,
  55         FIRMWARE_ID_MES_STACK                                   = 24,
  56         FIRMWARE_ID_RLC_SRM_DRAM_SR                             = 25,
  57         FIRMWARE_ID_RLCG_SCRATCH_SR                             = 26,
  58         FIRMWARE_ID_RLCP_SCRATCH_SR                             = 27,
  59         FIRMWARE_ID_RLCV_SCRATCH_SR                             = 28,
  60         FIRMWARE_ID_RLX6_DRAM_SR                                = 29,
  61         FIRMWARE_ID_SDMA0_PG_CONTEXT                            = 30,
  62         FIRMWARE_ID_SDMA1_PG_CONTEXT                            = 31,
  63         FIRMWARE_ID_GLOBAL_MUX_SELECT_RAM                       = 32,
  64         FIRMWARE_ID_SE0_MUX_SELECT_RAM                          = 33,
  65         FIRMWARE_ID_SE1_MUX_SELECT_RAM                          = 34,
  66         FIRMWARE_ID_ACCUM_CTRL_RAM                              = 35,
  67         FIRMWARE_ID_RLCP_CAM                                    = 36,
  68         FIRMWARE_ID_RLC_SPP_CAM_EXT                             = 37,
  69         FIRMWARE_ID_MAX                                         = 38,
  70 } FIRMWARE_ID;
  71
  72 typedef struct _RLC_TABLE_OF_CONTENT {
  73         union {
  74                 unsigned int    DW0;
  75                 struct {
  76                         unsigned int    offset          : 25;
  77                         unsigned int    id              : 7;
  78                 };
  79         };
  80
  81         union {
  82                 unsigned int    DW1;
  83                 struct {
  84                         unsigned int    load_at_boot            : 1;
  85                         unsigned int    load_at_vddgfx          : 1;
  86                         unsigned int    load_at_reset           : 1;
  87                         unsigned int    memory_destination      : 2;
  88                         unsigned int    vfflr_image_code        : 4;
  89                         unsigned int    load_mode_direct        : 1;
  90                         unsigned int    save_for_vddgfx         : 1;
  91                         unsigned int    save_for_vfflr          : 1;
  92                         unsigned int    reserved                : 1;
  93                         unsigned int    signed_source           : 1;
  94                         unsigned int    size                    : 18;
  95                 };
  96         };
  97
  98         union {
  99                 unsigned int    DW2;
 100                 struct {
 101                         unsigned int    indirect_addr_reg       : 16;
 102                         unsigned int    index                   : 16;
 103                 };
 104         };
 105
 106         union {
 107                 unsigned int    DW3;
 108                 struct {
 109                         unsigned int    indirect_data_reg       : 16;
 110                         unsigned int    indirect_start_offset   : 16;
 111                 };
 112         };
 113 } RLC_TABLE_OF_CONTENT;
 114
 115 #define RLC_TOC_MAX_SIZE                64
 116
 117 struct amdgpu_rlc_funcs {
 118         bool (*is_rlc_enabled)(struct amdgpu_device *adev);
 119         void (*set_safe_mode)(struct amdgpu_device *adev);
 120         void (*unset_safe_mode)(struct amdgpu_device *adev);
 121         int  (*init)(struct amdgpu_device *adev);
 122         u32  (*get_csb_size)(struct amdgpu_device *adev);
 123         void (*get_csb_buffer)(struct amdgpu_device *adev, volatile u32 *buffer);
 124         int  (*get_cp_table_num)(struct amdgpu_device *adev);
 125         int  (*resume)(struct amdgpu_device *adev);
 126         void (*stop)(struct amdgpu_device *adev);
 127         void (*reset)(struct amdgpu_device *adev);
 128         void (*start)(struct amdgpu_device *adev);
 129         void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned vmid);
 130         void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v);
 131         bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);
 132 };
 133
 134 struct amdgpu_rlc {
 135         /* for power gating */
 136         struct amdgpu_bo        *save_restore_obj;
 137         uint64_t                save_restore_gpu_addr;
 138         volatile uint32_t       *sr_ptr;
 139         const u32               *reg_list;
 140         u32                     reg_list_size;
 141         /* for clear state */
 142         struct amdgpu_bo        *clear_state_obj;
 143         uint64_t                clear_state_gpu_addr;
 144         volatile uint32_t       *cs_ptr;
 145         const struct cs_section_def   *cs_data;
 146         u32                     clear_state_size;
 147         /* for cp tables */
 148         struct amdgpu_bo        *cp_table_obj;
 149         uint64_t                cp_table_gpu_addr;
 150         volatile uint32_t       *cp_table_ptr;
 151         u32                     cp_table_size;
 152
 153         /* safe mode for updating CG/PG state */
 154         bool in_safe_mode;
 155         const struct amdgpu_rlc_funcs *funcs;
 156
 157         /* for firmware data */
 158         u32 save_and_restore_offset;
 159         u32 clear_state_descriptor_offset;
 160         u32 avail_scratch_ram_locations;
 161         u32 reg_restore_list_size;
 162         u32 reg_list_format_start;
 163         u32 reg_list_format_separate_start;
 164         u32 starting_offsets_start;
 165         u32 reg_list_format_size_bytes;
 166         u32 reg_list_size_bytes;
 167         u32 reg_list_format_direct_reg_list_length;
 168         u32 save_restore_list_cntl_size_bytes;
 169         u32 save_restore_list_gpm_size_bytes;
 170         u32 save_restore_list_srm_size_bytes;
 171
 172         u32 *register_list_format;
 173         u32 *register_restore;
 174         u8 *save_restore_list_cntl;
 175         u8 *save_restore_list_gpm;
 176         u8 *save_restore_list_srm;
 177
 178         bool is_rlc_v2_1;
 179
 180         /* for rlc autoload */
 181         struct amdgpu_bo        *rlc_autoload_bo;
 182         u64                     rlc_autoload_gpu_addr;
 183         void                    *rlc_autoload_ptr;
 184
 185         /* rlc toc buffer */
 186         struct amdgpu_bo        *rlc_toc_bo;
 187         uint64_t                rlc_toc_gpu_addr;
 188         void                    *rlc_toc_buf;
 189 };
 190
 191 void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev);
 192 void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev);
 193 int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws);
 194 int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev);
 195 int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev);
 196 void amdgpu_gfx_rlc_setup_cp_table(struct amdgpu_device *adev);
 197 void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev);
 198
 199 #endif