drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  */
  30 /* Algorithm:
  31  *
  32  * We store the last allocated bo in "hole", we always try to allocate
  33  * after the last allocated bo. Principle is that in a linear GPU ring
  34  * progression was is after last is the oldest bo we allocated and thus
  35  * the first one that should no longer be in use by the GPU.
  36  *
  37  * If it's not the case we skip over the bo after last to the closest
  38  * done bo if such one exist. If none exist and we are not asked to
  39  * block we report failure to allocate.
  40  *
  41  * If we are asked to block we wait on all the oldest fence of all
  42  * rings. We just wait for any of those fence to complete.
  43  */
  44 #include <drm/drmP.h>
  45 #include "amdgpu.h"
  46
  47 static void amdgpu_sa_bo_remove_locked(struct amdgpu_sa_bo *sa_bo);
  48 static void amdgpu_sa_bo_try_free(struct amdgpu_sa_manager *sa_manager);
  49
  50 int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
  51                               struct amdgpu_sa_manager *sa_manager,
  52                               unsigned size, u32 align, u32 domain)
  53 {
  54         int i, r;
  55
  56         init_waitqueue_head(&sa_manager->wq);
  57         sa_manager->bo = NULL;
  58         sa_manager->size = size;
  59         sa_manager->domain = domain;
  60         sa_manager->align = align;
  61         sa_manager->hole = &sa_manager->olist;
  62         INIT_LIST_HEAD(&sa_manager->olist);
  63         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
  64                 INIT_LIST_HEAD(&sa_manager->flist[i]);
  65         }
  66
  67         r = amdgpu_bo_create(adev, size, align, true,
  68                              domain, 0, NULL, &sa_manager->bo);
  69         if (r) {
  70                 dev_err(adev->dev, "(%d) failed to allocate bo for manager\n", r);
  71                 return r;
  72         }
  73
  74         return r;
  75 }
  76
  77 void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
  78                                struct amdgpu_sa_manager *sa_manager)
  79 {
  80         struct amdgpu_sa_bo *sa_bo, *tmp;
  81
  82         if (!list_empty(&sa_manager->olist)) {
  83                 sa_manager->hole = &sa_manager->olist,
  84                 amdgpu_sa_bo_try_free(sa_manager);
  85                 if (!list_empty(&sa_manager->olist)) {
  86                         dev_err(adev->dev, "sa_manager is not empty, clearing anyway\n");
  87                 }
  88         }
  89         list_for_each_entry_safe(sa_bo, tmp, &sa_manager->olist, olist) {
  90                 amdgpu_sa_bo_remove_locked(sa_bo);
  91         }
  92         amdgpu_bo_unref(&sa_manager->bo);
  93         sa_manager->size = 0;
  94 }
  95
  96 int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
  97                                struct amdgpu_sa_manager *sa_manager)
  98 {
  99         int r;
 100
 101         if (sa_manager->bo == NULL) {
 102                 dev_err(adev->dev, "no bo for sa manager\n");
 103                 return -EINVAL;
 104         }
 105
 106         /* map the buffer */
 107         r = amdgpu_bo_reserve(sa_manager->bo, false);
 108         if (r) {
 109                 dev_err(adev->dev, "(%d) failed to reserve manager bo\n", r);
 110                 return r;
 111         }
 112         r = amdgpu_bo_pin(sa_manager->bo, sa_manager->domain, &sa_manager->gpu_addr);
 113         if (r) {
 114                 amdgpu_bo_unreserve(sa_manager->bo);
 115                 dev_err(adev->dev, "(%d) failed to pin manager bo\n", r);
 116                 return r;
 117         }
 118         r = amdgpu_bo_kmap(sa_manager->bo, &sa_manager->cpu_ptr);
 119         amdgpu_bo_unreserve(sa_manager->bo);
 120         return r;
 121 }
 122
 123 int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev,
 124                                  struct amdgpu_sa_manager *sa_manager)
 125 {
 126         int r;
 127
 128         if (sa_manager->bo == NULL) {
 129                 dev_err(adev->dev, "no bo for sa manager\n");
 130                 return -EINVAL;
 131         }
 132
 133         r = amdgpu_bo_reserve(sa_manager->bo, false);
 134         if (!r) {
 135                 amdgpu_bo_kunmap(sa_manager->bo);
 136                 amdgpu_bo_unpin(sa_manager->bo);
 137                 amdgpu_bo_unreserve(sa_manager->bo);
 138         }
 139         return r;
 140 }
 141
 142 static uint32_t amdgpu_sa_get_ring_from_fence(struct fence *f)
 143 {
 144         struct amdgpu_fence *a_fence;
 145         struct amd_sched_fence *s_fence;
 146
 147         s_fence = to_amd_sched_fence(f);
 148         if (s_fence)
 149                 return s_fence->scheduler->ring_id;
 150         a_fence = to_amdgpu_fence(f);
 151         if (a_fence)
 152                 return a_fence->ring->idx;
 153         return 0;
 154 }
 155
 156 static void amdgpu_sa_bo_remove_locked(struct amdgpu_sa_bo *sa_bo)
 157 {
 158         struct amdgpu_sa_manager *sa_manager = sa_bo->manager;
 159         if (sa_manager->hole == &sa_bo->olist) {
 160                 sa_manager->hole = sa_bo->olist.prev;
 161         }
 162         list_del_init(&sa_bo->olist);
 163         list_del_init(&sa_bo->flist);
 164         fence_put(sa_bo->fence);
 165         kfree(sa_bo);
 166 }
 167
 168 static void amdgpu_sa_bo_try_free(struct amdgpu_sa_manager *sa_manager)
 169 {
 170         struct amdgpu_sa_bo *sa_bo, *tmp;
 171
 172         if (sa_manager->hole->next == &sa_manager->olist)
 173                 return;
 174
 175         sa_bo = list_entry(sa_manager->hole->next, struct amdgpu_sa_bo, olist);
 176         list_for_each_entry_safe_from(sa_bo, tmp, &sa_manager->olist, olist) {
 177                 if (sa_bo->fence == NULL ||
 178                     !fence_is_signaled(sa_bo->fence)) {
 179                         return;
 180                 }
 181                 amdgpu_sa_bo_remove_locked(sa_bo);
 182         }
 183 }
 184
 185 static inline unsigned amdgpu_sa_bo_hole_soffset(struct amdgpu_sa_manager *sa_manager)
 186 {
 187         struct list_head *hole = sa_manager->hole;
 188
 189         if (hole != &sa_manager->olist) {
 190                 return list_entry(hole, struct amdgpu_sa_bo, olist)->eoffset;
 191         }
 192         return 0;
 193 }
 194
 195 static inline unsigned amdgpu_sa_bo_hole_eoffset(struct amdgpu_sa_manager *sa_manager)
 196 {
 197         struct list_head *hole = sa_manager->hole;
 198
 199         if (hole->next != &sa_manager->olist) {
 200                 return list_entry(hole->next, struct amdgpu_sa_bo, olist)->soffset;
 201         }
 202         return sa_manager->size;
 203 }
 204
 205 static bool amdgpu_sa_bo_try_alloc(struct amdgpu_sa_manager *sa_manager,
 206                                    struct amdgpu_sa_bo *sa_bo,
 207                                    unsigned size, unsigned align)
 208 {
 209         unsigned soffset, eoffset, wasted;
 210
 211         soffset = amdgpu_sa_bo_hole_soffset(sa_manager);
 212         eoffset = amdgpu_sa_bo_hole_eoffset(sa_manager);
 213         wasted = (align - (soffset % align)) % align;
 214
 215         if ((eoffset - soffset) >= (size + wasted)) {
 216                 soffset += wasted;
 217
 218                 sa_bo->manager = sa_manager;
 219                 sa_bo->soffset = soffset;
 220                 sa_bo->eoffset = soffset + size;
 221                 list_add(&sa_bo->olist, sa_manager->hole);
 222                 INIT_LIST_HEAD(&sa_bo->flist);
 223                 sa_manager->hole = &sa_bo->olist;
 224                 return true;
 225         }
 226         return false;
 227 }
 228
 229 /**
 230  * amdgpu_sa_event - Check if we can stop waiting
 231  *
 232  * @sa_manager: pointer to the sa_manager
 233  * @size: number of bytes we want to allocate
 234  * @align: alignment we need to match
 235  *
 236  * Check if either there is a fence we can wait for or
 237  * enough free memory to satisfy the allocation directly
 238  */
 239 static bool amdgpu_sa_event(struct amdgpu_sa_manager *sa_manager,
 240                             unsigned size, unsigned align)
 241 {
 242         unsigned soffset, eoffset, wasted;
 243         int i;
 244
 245         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 246                 if (!list_empty(&sa_manager->flist[i])) {
 247                         return true;
 248                 }
 249         }
 250
 251         soffset = amdgpu_sa_bo_hole_soffset(sa_manager);
 252         eoffset = amdgpu_sa_bo_hole_eoffset(sa_manager);
 253         wasted = (align - (soffset % align)) % align;
 254
 255         if ((eoffset - soffset) >= (size + wasted)) {
 256                 return true;
 257         }
 258
 259         return false;
 260 }
 261
 262 static bool amdgpu_sa_bo_next_hole(struct amdgpu_sa_manager *sa_manager,
 263                                    struct fence **fences,
 264                                    unsigned *tries)
 265 {
 266         struct amdgpu_sa_bo *best_bo = NULL;
 267         unsigned i, soffset, best, tmp;
 268
 269         /* if hole points to the end of the buffer */
 270         if (sa_manager->hole->next == &sa_manager->olist) {
 271                 /* try again with its beginning */
 272                 sa_manager->hole = &sa_manager->olist;
 273                 return true;
 274         }
 275
 276         soffset = amdgpu_sa_bo_hole_soffset(sa_manager);
 277         /* to handle wrap around we add sa_manager->size */
 278         best = sa_manager->size * 2;
 279         /* go over all fence list and try to find the closest sa_bo
 280          * of the current last
 281          */
 282         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 283                 struct amdgpu_sa_bo *sa_bo;
 284
 285                 if (list_empty(&sa_manager->flist[i])) {
 286                         continue;
 287                 }
 288
 289                 sa_bo = list_first_entry(&sa_manager->flist[i],
 290                                          struct amdgpu_sa_bo, flist);
 291
 292                 if (!fence_is_signaled(sa_bo->fence)) {
 293                         fences[i] = sa_bo->fence;
 294                         continue;
 295                 }
 296
 297                 /* limit the number of tries each ring gets */
 298                 if (tries[i] > 2) {
 299                         continue;
 300                 }
 301
 302                 tmp = sa_bo->soffset;
 303                 if (tmp < soffset) {
 304                         /* wrap around, pretend it's after */
 305                         tmp += sa_manager->size;
 306                 }
 307                 tmp -= soffset;
 308                 if (tmp < best) {
 309                         /* this sa bo is the closest one */
 310                         best = tmp;
 311                         best_bo = sa_bo;
 312                 }
 313         }
 314
 315         if (best_bo) {
 316                 uint32_t idx = amdgpu_sa_get_ring_from_fence(best_bo->fence);
 317                 ++tries[idx];
 318                 sa_manager->hole = best_bo->olist.prev;
 319
 320                 /* we knew that this one is signaled,
 321                    so it's save to remote it */
 322                 amdgpu_sa_bo_remove_locked(best_bo);
 323                 return true;
 324         }
 325         return false;
 326 }
 327
 328 int amdgpu_sa_bo_new(struct amdgpu_device *adev,
 329                      struct amdgpu_sa_manager *sa_manager,
 330                      struct amdgpu_sa_bo **sa_bo,
 331                      unsigned size, unsigned align)
 332 {
 333         struct fence *fences[AMDGPU_MAX_RINGS];
 334         unsigned tries[AMDGPU_MAX_RINGS];
 335         int i, r;
 336         signed long t;
 337
 338         BUG_ON(align > sa_manager->align);
 339         BUG_ON(size > sa_manager->size);
 340
 341         *sa_bo = kmalloc(sizeof(struct amdgpu_sa_bo), GFP_KERNEL);
 342         if ((*sa_bo) == NULL) {
 343                 return -ENOMEM;
 344         }
 345         (*sa_bo)->manager = sa_manager;
 346         (*sa_bo)->fence = NULL;
 347         INIT_LIST_HEAD(&(*sa_bo)->olist);
 348         INIT_LIST_HEAD(&(*sa_bo)->flist);
 349
 350         spin_lock(&sa_manager->wq.lock);
 351         do {
 352                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 353                         fences[i] = NULL;
 354                         tries[i] = 0;
 355                 }
 356
 357                 do {
 358                         amdgpu_sa_bo_try_free(sa_manager);
 359
 360                         if (amdgpu_sa_bo_try_alloc(sa_manager, *sa_bo,
 361                                                    size, align)) {
 362                                 spin_unlock(&sa_manager->wq.lock);
 363                                 return 0;
 364                         }
 365
 366                         /* see if we can skip over some allocations */
 367                 } while (amdgpu_sa_bo_next_hole(sa_manager, fences, tries));
 368
 369                 spin_unlock(&sa_manager->wq.lock);
 370                 t = amdgpu_fence_wait_any(adev, fences, AMDGPU_MAX_RINGS,
 371                                           false, MAX_SCHEDULE_TIMEOUT);
 372                 r = (t > 0) ? 0 : t;
 373                 spin_lock(&sa_manager->wq.lock);
 374                 /* if we have nothing to wait for block */
 375                 if (r == -ENOENT) {
 376                         r = wait_event_interruptible_locked(
 377                                 sa_manager->wq,
 378                                 amdgpu_sa_event(sa_manager, size, align)
 379                         );
 380                 }
 381
 382         } while (!r);
 383
 384         spin_unlock(&sa_manager->wq.lock);
 385         kfree(*sa_bo);
 386         *sa_bo = NULL;
 387         return r;
 388 }
 389
 390 void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo,
 391                        struct fence *fence)
 392 {
 393         struct amdgpu_sa_manager *sa_manager;
 394
 395         if (sa_bo == NULL || *sa_bo == NULL) {
 396                 return;
 397         }
 398
 399         sa_manager = (*sa_bo)->manager;
 400         spin_lock(&sa_manager->wq.lock);
 401         if (fence && !fence_is_signaled(fence)) {
 402                 uint32_t idx;
 403                 (*sa_bo)->fence = fence_get(fence);
 404                 idx = amdgpu_sa_get_ring_from_fence(fence);
 405                 list_add_tail(&(*sa_bo)->flist, &sa_manager->flist[idx]);
 406         } else {
 407                 amdgpu_sa_bo_remove_locked(*sa_bo);
 408         }
 409         wake_up_all_locked(&sa_manager->wq);
 410         spin_unlock(&sa_manager->wq.lock);
 411         *sa_bo = NULL;
 412 }
 413
 414 #if defined(CONFIG_DEBUG_FS)
 415 void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
 416                                   struct seq_file *m)
 417 {
 418         struct amdgpu_sa_bo *i;
 419
 420         spin_lock(&sa_manager->wq.lock);
 421         list_for_each_entry(i, &sa_manager->olist, olist) {
 422                 uint64_t soffset = i->soffset + sa_manager->gpu_addr;
 423                 uint64_t eoffset = i->eoffset + sa_manager->gpu_addr;
 424                 if (&i->olist == sa_manager->hole) {
 425                         seq_printf(m, ">");
 426                 } else {
 427                         seq_printf(m, " ");
 428                 }
 429                 seq_printf(m, "[0x%010llx 0x%010llx] size %8lld",
 430                            soffset, eoffset, eoffset - soffset);
 431                 if (i->fence) {
 432                         struct amdgpu_fence *a_fence = to_amdgpu_fence(i->fence);
 433                         struct amd_sched_fence *s_fence = to_amd_sched_fence(i->fence);
 434                         if (a_fence)
 435                                 seq_printf(m, " protected by 0x%016llx on ring %d",
 436                                            a_fence->seq, a_fence->ring->idx);
 437                         if (s_fence)
 438                                 seq_printf(m, " protected by 0x%016x on ring %d",
 439                                            s_fence->base.seqno,
 440                                            s_fence->scheduler->ring_id);
 441
 442                 }
 443                 seq_printf(m, "\n");
 444         }
 445         spin_unlock(&sa_manager->wq.lock);
 446 }
 447 #endif