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git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
2 * Copyright 2011 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
32 * We store the last allocated bo in "hole", we always try to allocate
33 * after the last allocated bo. Principle is that in a linear GPU ring
34 * progression was is after last is the oldest bo we allocated and thus
35 * the first one that should no longer be in use by the GPU.
37 * If it's not the case we skip over the bo after last to the closest
38 * done bo if such one exist. If none exist and we are not asked to
39 * block we report failure to allocate.
41 * If we are asked to block we wait on all the oldest fence of all
42 * rings. We just wait for any of those fence to complete.
47 static void amdgpu_sa_bo_remove_locked(struct amdgpu_sa_bo
*sa_bo
);
48 static void amdgpu_sa_bo_try_free(struct amdgpu_sa_manager
*sa_manager
);
50 int amdgpu_sa_bo_manager_init(struct amdgpu_device
*adev
,
51 struct amdgpu_sa_manager
*sa_manager
,
52 unsigned size
, u32 align
, u32 domain
)
56 init_waitqueue_head(&sa_manager
->wq
);
57 sa_manager
->bo
= NULL
;
58 sa_manager
->size
= size
;
59 sa_manager
->domain
= domain
;
60 sa_manager
->align
= align
;
61 sa_manager
->hole
= &sa_manager
->olist
;
62 INIT_LIST_HEAD(&sa_manager
->olist
);
63 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
64 INIT_LIST_HEAD(&sa_manager
->flist
[i
]);
67 r
= amdgpu_bo_create(adev
, size
, align
, true,
68 domain
, 0, NULL
, &sa_manager
->bo
);
70 dev_err(adev
->dev
, "(%d) failed to allocate bo for manager\n", r
);
77 void amdgpu_sa_bo_manager_fini(struct amdgpu_device
*adev
,
78 struct amdgpu_sa_manager
*sa_manager
)
80 struct amdgpu_sa_bo
*sa_bo
, *tmp
;
82 if (!list_empty(&sa_manager
->olist
)) {
83 sa_manager
->hole
= &sa_manager
->olist
,
84 amdgpu_sa_bo_try_free(sa_manager
);
85 if (!list_empty(&sa_manager
->olist
)) {
86 dev_err(adev
->dev
, "sa_manager is not empty, clearing anyway\n");
89 list_for_each_entry_safe(sa_bo
, tmp
, &sa_manager
->olist
, olist
) {
90 amdgpu_sa_bo_remove_locked(sa_bo
);
92 amdgpu_bo_unref(&sa_manager
->bo
);
96 int amdgpu_sa_bo_manager_start(struct amdgpu_device
*adev
,
97 struct amdgpu_sa_manager
*sa_manager
)
101 if (sa_manager
->bo
== NULL
) {
102 dev_err(adev
->dev
, "no bo for sa manager\n");
107 r
= amdgpu_bo_reserve(sa_manager
->bo
, false);
109 dev_err(adev
->dev
, "(%d) failed to reserve manager bo\n", r
);
112 r
= amdgpu_bo_pin(sa_manager
->bo
, sa_manager
->domain
, &sa_manager
->gpu_addr
);
114 amdgpu_bo_unreserve(sa_manager
->bo
);
115 dev_err(adev
->dev
, "(%d) failed to pin manager bo\n", r
);
118 r
= amdgpu_bo_kmap(sa_manager
->bo
, &sa_manager
->cpu_ptr
);
119 amdgpu_bo_unreserve(sa_manager
->bo
);
123 int amdgpu_sa_bo_manager_suspend(struct amdgpu_device
*adev
,
124 struct amdgpu_sa_manager
*sa_manager
)
128 if (sa_manager
->bo
== NULL
) {
129 dev_err(adev
->dev
, "no bo for sa manager\n");
133 r
= amdgpu_bo_reserve(sa_manager
->bo
, false);
135 amdgpu_bo_kunmap(sa_manager
->bo
);
136 amdgpu_bo_unpin(sa_manager
->bo
);
137 amdgpu_bo_unreserve(sa_manager
->bo
);
142 static uint32_t amdgpu_sa_get_ring_from_fence(struct fence
*f
)
144 struct amdgpu_fence
*a_fence
;
145 struct amd_sched_fence
*s_fence
;
147 s_fence
= to_amd_sched_fence(f
);
149 return s_fence
->scheduler
->ring_id
;
150 a_fence
= to_amdgpu_fence(f
);
152 return a_fence
->ring
->idx
;
156 static void amdgpu_sa_bo_remove_locked(struct amdgpu_sa_bo
*sa_bo
)
158 struct amdgpu_sa_manager
*sa_manager
= sa_bo
->manager
;
159 if (sa_manager
->hole
== &sa_bo
->olist
) {
160 sa_manager
->hole
= sa_bo
->olist
.prev
;
162 list_del_init(&sa_bo
->olist
);
163 list_del_init(&sa_bo
->flist
);
164 fence_put(sa_bo
->fence
);
168 static void amdgpu_sa_bo_try_free(struct amdgpu_sa_manager
*sa_manager
)
170 struct amdgpu_sa_bo
*sa_bo
, *tmp
;
172 if (sa_manager
->hole
->next
== &sa_manager
->olist
)
175 sa_bo
= list_entry(sa_manager
->hole
->next
, struct amdgpu_sa_bo
, olist
);
176 list_for_each_entry_safe_from(sa_bo
, tmp
, &sa_manager
->olist
, olist
) {
177 if (sa_bo
->fence
== NULL
||
178 !fence_is_signaled(sa_bo
->fence
)) {
181 amdgpu_sa_bo_remove_locked(sa_bo
);
185 static inline unsigned amdgpu_sa_bo_hole_soffset(struct amdgpu_sa_manager
*sa_manager
)
187 struct list_head
*hole
= sa_manager
->hole
;
189 if (hole
!= &sa_manager
->olist
) {
190 return list_entry(hole
, struct amdgpu_sa_bo
, olist
)->eoffset
;
195 static inline unsigned amdgpu_sa_bo_hole_eoffset(struct amdgpu_sa_manager
*sa_manager
)
197 struct list_head
*hole
= sa_manager
->hole
;
199 if (hole
->next
!= &sa_manager
->olist
) {
200 return list_entry(hole
->next
, struct amdgpu_sa_bo
, olist
)->soffset
;
202 return sa_manager
->size
;
205 static bool amdgpu_sa_bo_try_alloc(struct amdgpu_sa_manager
*sa_manager
,
206 struct amdgpu_sa_bo
*sa_bo
,
207 unsigned size
, unsigned align
)
209 unsigned soffset
, eoffset
, wasted
;
211 soffset
= amdgpu_sa_bo_hole_soffset(sa_manager
);
212 eoffset
= amdgpu_sa_bo_hole_eoffset(sa_manager
);
213 wasted
= (align
- (soffset
% align
)) % align
;
215 if ((eoffset
- soffset
) >= (size
+ wasted
)) {
218 sa_bo
->manager
= sa_manager
;
219 sa_bo
->soffset
= soffset
;
220 sa_bo
->eoffset
= soffset
+ size
;
221 list_add(&sa_bo
->olist
, sa_manager
->hole
);
222 INIT_LIST_HEAD(&sa_bo
->flist
);
223 sa_manager
->hole
= &sa_bo
->olist
;
230 * amdgpu_sa_event - Check if we can stop waiting
232 * @sa_manager: pointer to the sa_manager
233 * @size: number of bytes we want to allocate
234 * @align: alignment we need to match
236 * Check if either there is a fence we can wait for or
237 * enough free memory to satisfy the allocation directly
239 static bool amdgpu_sa_event(struct amdgpu_sa_manager
*sa_manager
,
240 unsigned size
, unsigned align
)
242 unsigned soffset
, eoffset
, wasted
;
245 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
246 if (!list_empty(&sa_manager
->flist
[i
])) {
251 soffset
= amdgpu_sa_bo_hole_soffset(sa_manager
);
252 eoffset
= amdgpu_sa_bo_hole_eoffset(sa_manager
);
253 wasted
= (align
- (soffset
% align
)) % align
;
255 if ((eoffset
- soffset
) >= (size
+ wasted
)) {
262 static bool amdgpu_sa_bo_next_hole(struct amdgpu_sa_manager
*sa_manager
,
263 struct fence
**fences
,
266 struct amdgpu_sa_bo
*best_bo
= NULL
;
267 unsigned i
, soffset
, best
, tmp
;
269 /* if hole points to the end of the buffer */
270 if (sa_manager
->hole
->next
== &sa_manager
->olist
) {
271 /* try again with its beginning */
272 sa_manager
->hole
= &sa_manager
->olist
;
276 soffset
= amdgpu_sa_bo_hole_soffset(sa_manager
);
277 /* to handle wrap around we add sa_manager->size */
278 best
= sa_manager
->size
* 2;
279 /* go over all fence list and try to find the closest sa_bo
280 * of the current last
282 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
283 struct amdgpu_sa_bo
*sa_bo
;
285 if (list_empty(&sa_manager
->flist
[i
])) {
289 sa_bo
= list_first_entry(&sa_manager
->flist
[i
],
290 struct amdgpu_sa_bo
, flist
);
292 if (!fence_is_signaled(sa_bo
->fence
)) {
293 fences
[i
] = sa_bo
->fence
;
297 /* limit the number of tries each ring gets */
302 tmp
= sa_bo
->soffset
;
304 /* wrap around, pretend it's after */
305 tmp
+= sa_manager
->size
;
309 /* this sa bo is the closest one */
316 uint32_t idx
= amdgpu_sa_get_ring_from_fence(best_bo
->fence
);
318 sa_manager
->hole
= best_bo
->olist
.prev
;
320 /* we knew that this one is signaled,
321 so it's save to remote it */
322 amdgpu_sa_bo_remove_locked(best_bo
);
328 int amdgpu_sa_bo_new(struct amdgpu_device
*adev
,
329 struct amdgpu_sa_manager
*sa_manager
,
330 struct amdgpu_sa_bo
**sa_bo
,
331 unsigned size
, unsigned align
)
333 struct fence
*fences
[AMDGPU_MAX_RINGS
];
334 unsigned tries
[AMDGPU_MAX_RINGS
];
338 BUG_ON(align
> sa_manager
->align
);
339 BUG_ON(size
> sa_manager
->size
);
341 *sa_bo
= kmalloc(sizeof(struct amdgpu_sa_bo
), GFP_KERNEL
);
342 if ((*sa_bo
) == NULL
) {
345 (*sa_bo
)->manager
= sa_manager
;
346 (*sa_bo
)->fence
= NULL
;
347 INIT_LIST_HEAD(&(*sa_bo
)->olist
);
348 INIT_LIST_HEAD(&(*sa_bo
)->flist
);
350 spin_lock(&sa_manager
->wq
.lock
);
352 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
358 amdgpu_sa_bo_try_free(sa_manager
);
360 if (amdgpu_sa_bo_try_alloc(sa_manager
, *sa_bo
,
362 spin_unlock(&sa_manager
->wq
.lock
);
366 /* see if we can skip over some allocations */
367 } while (amdgpu_sa_bo_next_hole(sa_manager
, fences
, tries
));
369 spin_unlock(&sa_manager
->wq
.lock
);
370 t
= amdgpu_fence_wait_any(adev
, fences
, AMDGPU_MAX_RINGS
,
371 false, MAX_SCHEDULE_TIMEOUT
);
373 spin_lock(&sa_manager
->wq
.lock
);
374 /* if we have nothing to wait for block */
376 r
= wait_event_interruptible_locked(
378 amdgpu_sa_event(sa_manager
, size
, align
)
384 spin_unlock(&sa_manager
->wq
.lock
);
390 void amdgpu_sa_bo_free(struct amdgpu_device
*adev
, struct amdgpu_sa_bo
**sa_bo
,
393 struct amdgpu_sa_manager
*sa_manager
;
395 if (sa_bo
== NULL
|| *sa_bo
== NULL
) {
399 sa_manager
= (*sa_bo
)->manager
;
400 spin_lock(&sa_manager
->wq
.lock
);
401 if (fence
&& !fence_is_signaled(fence
)) {
403 (*sa_bo
)->fence
= fence_get(fence
);
404 idx
= amdgpu_sa_get_ring_from_fence(fence
);
405 list_add_tail(&(*sa_bo
)->flist
, &sa_manager
->flist
[idx
]);
407 amdgpu_sa_bo_remove_locked(*sa_bo
);
409 wake_up_all_locked(&sa_manager
->wq
);
410 spin_unlock(&sa_manager
->wq
.lock
);
414 #if defined(CONFIG_DEBUG_FS)
415 void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager
*sa_manager
,
418 struct amdgpu_sa_bo
*i
;
420 spin_lock(&sa_manager
->wq
.lock
);
421 list_for_each_entry(i
, &sa_manager
->olist
, olist
) {
422 uint64_t soffset
= i
->soffset
+ sa_manager
->gpu_addr
;
423 uint64_t eoffset
= i
->eoffset
+ sa_manager
->gpu_addr
;
424 if (&i
->olist
== sa_manager
->hole
) {
429 seq_printf(m
, "[0x%010llx 0x%010llx] size %8lld",
430 soffset
, eoffset
, eoffset
- soffset
);
432 struct amdgpu_fence
*a_fence
= to_amdgpu_fence(i
->fence
);
433 struct amd_sched_fence
*s_fence
= to_amd_sched_fence(i
->fence
);
435 seq_printf(m
, " protected by 0x%016llx on ring %d",
436 a_fence
->seq
, a_fence
->ring
->idx
);
438 seq_printf(m
, " protected by 0x%016x on ring %d",
440 s_fence
->scheduler
->ring_id
);
445 spin_unlock(&sa_manager
->wq
.lock
);