2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <ttm/ttm_bo_api.h>
33 #include <ttm/ttm_bo_driver.h>
34 #include <ttm/ttm_placement.h>
35 #include <ttm/ttm_module.h>
36 #include <ttm/ttm_page_alloc.h>
38 #include <drm/amdgpu_drm.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include <linux/swiotlb.h>
42 #include <linux/swap.h>
43 #include <linux/pagemap.h>
44 #include <linux/debugfs.h>
46 #include "bif/bif_4_1_d.h"
48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
50 static int amdgpu_ttm_debugfs_init(struct amdgpu_device
*adev
);
51 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device
*adev
);
53 static struct amdgpu_device
*amdgpu_get_adev(struct ttm_bo_device
*bdev
)
55 struct amdgpu_mman
*mman
;
56 struct amdgpu_device
*adev
;
58 mman
= container_of(bdev
, struct amdgpu_mman
, bdev
);
59 adev
= container_of(mman
, struct amdgpu_device
, mman
);
67 static int amdgpu_ttm_mem_global_init(struct drm_global_reference
*ref
)
69 return ttm_mem_global_init(ref
->object
);
72 static void amdgpu_ttm_mem_global_release(struct drm_global_reference
*ref
)
74 ttm_mem_global_release(ref
->object
);
77 static int amdgpu_ttm_global_init(struct amdgpu_device
*adev
)
79 struct drm_global_reference
*global_ref
;
80 struct amdgpu_ring
*ring
;
81 struct amd_sched_rq
*rq
;
84 adev
->mman
.mem_global_referenced
= false;
85 global_ref
= &adev
->mman
.mem_global_ref
;
86 global_ref
->global_type
= DRM_GLOBAL_TTM_MEM
;
87 global_ref
->size
= sizeof(struct ttm_mem_global
);
88 global_ref
->init
= &amdgpu_ttm_mem_global_init
;
89 global_ref
->release
= &amdgpu_ttm_mem_global_release
;
90 r
= drm_global_item_ref(global_ref
);
92 DRM_ERROR("Failed setting up TTM memory accounting "
97 adev
->mman
.bo_global_ref
.mem_glob
=
98 adev
->mman
.mem_global_ref
.object
;
99 global_ref
= &adev
->mman
.bo_global_ref
.ref
;
100 global_ref
->global_type
= DRM_GLOBAL_TTM_BO
;
101 global_ref
->size
= sizeof(struct ttm_bo_global
);
102 global_ref
->init
= &ttm_bo_global_init
;
103 global_ref
->release
= &ttm_bo_global_release
;
104 r
= drm_global_item_ref(global_ref
);
106 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
107 drm_global_item_unref(&adev
->mman
.mem_global_ref
);
111 ring
= adev
->mman
.buffer_funcs_ring
;
112 rq
= &ring
->sched
.sched_rq
[AMD_SCHED_PRIORITY_KERNEL
];
113 r
= amd_sched_entity_init(&ring
->sched
, &adev
->mman
.entity
,
114 rq
, amdgpu_sched_jobs
);
116 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
117 drm_global_item_unref(&adev
->mman
.mem_global_ref
);
118 drm_global_item_unref(&adev
->mman
.bo_global_ref
.ref
);
122 adev
->mman
.mem_global_referenced
= true;
127 static void amdgpu_ttm_global_fini(struct amdgpu_device
*adev
)
129 if (adev
->mman
.mem_global_referenced
) {
130 amd_sched_entity_fini(adev
->mman
.entity
.sched
,
132 drm_global_item_unref(&adev
->mman
.bo_global_ref
.ref
);
133 drm_global_item_unref(&adev
->mman
.mem_global_ref
);
134 adev
->mman
.mem_global_referenced
= false;
138 static int amdgpu_invalidate_caches(struct ttm_bo_device
*bdev
, uint32_t flags
)
143 static int amdgpu_init_mem_type(struct ttm_bo_device
*bdev
, uint32_t type
,
144 struct ttm_mem_type_manager
*man
)
146 struct amdgpu_device
*adev
;
148 adev
= amdgpu_get_adev(bdev
);
153 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
;
154 man
->available_caching
= TTM_PL_MASK_CACHING
;
155 man
->default_caching
= TTM_PL_FLAG_CACHED
;
158 man
->func
= &ttm_bo_manager_func
;
159 man
->gpu_offset
= adev
->mc
.gtt_start
;
160 man
->available_caching
= TTM_PL_MASK_CACHING
;
161 man
->default_caching
= TTM_PL_FLAG_CACHED
;
162 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
| TTM_MEMTYPE_FLAG_CMA
;
165 /* "On-card" video ram */
166 man
->func
= &ttm_bo_manager_func
;
167 man
->gpu_offset
= adev
->mc
.vram_start
;
168 man
->flags
= TTM_MEMTYPE_FLAG_FIXED
|
169 TTM_MEMTYPE_FLAG_MAPPABLE
;
170 man
->available_caching
= TTM_PL_FLAG_UNCACHED
| TTM_PL_FLAG_WC
;
171 man
->default_caching
= TTM_PL_FLAG_WC
;
176 /* On-chip GDS memory*/
177 man
->func
= &ttm_bo_manager_func
;
179 man
->flags
= TTM_MEMTYPE_FLAG_FIXED
| TTM_MEMTYPE_FLAG_CMA
;
180 man
->available_caching
= TTM_PL_FLAG_UNCACHED
;
181 man
->default_caching
= TTM_PL_FLAG_UNCACHED
;
184 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type
);
190 static void amdgpu_evict_flags(struct ttm_buffer_object
*bo
,
191 struct ttm_placement
*placement
)
193 struct amdgpu_bo
*rbo
;
194 static struct ttm_place placements
= {
197 .flags
= TTM_PL_MASK_CACHING
| TTM_PL_FLAG_SYSTEM
200 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo
)) {
201 placement
->placement
= &placements
;
202 placement
->busy_placement
= &placements
;
203 placement
->num_placement
= 1;
204 placement
->num_busy_placement
= 1;
207 rbo
= container_of(bo
, struct amdgpu_bo
, tbo
);
208 switch (bo
->mem
.mem_type
) {
210 if (rbo
->adev
->mman
.buffer_funcs_ring
->ready
== false)
211 amdgpu_ttm_placement_from_domain(rbo
, AMDGPU_GEM_DOMAIN_CPU
);
213 amdgpu_ttm_placement_from_domain(rbo
, AMDGPU_GEM_DOMAIN_GTT
);
217 amdgpu_ttm_placement_from_domain(rbo
, AMDGPU_GEM_DOMAIN_CPU
);
219 *placement
= rbo
->placement
;
222 static int amdgpu_verify_access(struct ttm_buffer_object
*bo
, struct file
*filp
)
224 struct amdgpu_bo
*rbo
= container_of(bo
, struct amdgpu_bo
, tbo
);
226 return drm_vma_node_verify_access(&rbo
->gem_base
.vma_node
, filp
);
229 static void amdgpu_move_null(struct ttm_buffer_object
*bo
,
230 struct ttm_mem_reg
*new_mem
)
232 struct ttm_mem_reg
*old_mem
= &bo
->mem
;
234 BUG_ON(old_mem
->mm_node
!= NULL
);
236 new_mem
->mm_node
= NULL
;
239 static int amdgpu_move_blit(struct ttm_buffer_object
*bo
,
240 bool evict
, bool no_wait_gpu
,
241 struct ttm_mem_reg
*new_mem
,
242 struct ttm_mem_reg
*old_mem
)
244 struct amdgpu_device
*adev
;
245 struct amdgpu_ring
*ring
;
246 uint64_t old_start
, new_start
;
250 adev
= amdgpu_get_adev(bo
->bdev
);
251 ring
= adev
->mman
.buffer_funcs_ring
;
252 old_start
= old_mem
->start
<< PAGE_SHIFT
;
253 new_start
= new_mem
->start
<< PAGE_SHIFT
;
255 switch (old_mem
->mem_type
) {
257 old_start
+= adev
->mc
.vram_start
;
260 old_start
+= adev
->mc
.gtt_start
;
263 DRM_ERROR("Unknown placement %d\n", old_mem
->mem_type
);
266 switch (new_mem
->mem_type
) {
268 new_start
+= adev
->mc
.vram_start
;
271 new_start
+= adev
->mc
.gtt_start
;
274 DRM_ERROR("Unknown placement %d\n", old_mem
->mem_type
);
278 DRM_ERROR("Trying to move memory with ring turned off.\n");
282 BUILD_BUG_ON((PAGE_SIZE
% AMDGPU_GPU_PAGE_SIZE
) != 0);
284 r
= amdgpu_copy_buffer(ring
, old_start
, new_start
,
285 new_mem
->num_pages
* PAGE_SIZE
, /* bytes */
287 /* FIXME: handle copy error */
288 r
= ttm_bo_move_accel_cleanup(bo
, fence
,
289 evict
, no_wait_gpu
, new_mem
);
294 static int amdgpu_move_vram_ram(struct ttm_buffer_object
*bo
,
295 bool evict
, bool interruptible
,
297 struct ttm_mem_reg
*new_mem
)
299 struct amdgpu_device
*adev
;
300 struct ttm_mem_reg
*old_mem
= &bo
->mem
;
301 struct ttm_mem_reg tmp_mem
;
302 struct ttm_place placements
;
303 struct ttm_placement placement
;
306 adev
= amdgpu_get_adev(bo
->bdev
);
308 tmp_mem
.mm_node
= NULL
;
309 placement
.num_placement
= 1;
310 placement
.placement
= &placements
;
311 placement
.num_busy_placement
= 1;
312 placement
.busy_placement
= &placements
;
315 placements
.flags
= TTM_PL_MASK_CACHING
| TTM_PL_FLAG_TT
;
316 r
= ttm_bo_mem_space(bo
, &placement
, &tmp_mem
,
317 interruptible
, no_wait_gpu
);
322 r
= ttm_tt_set_placement_caching(bo
->ttm
, tmp_mem
.placement
);
327 r
= ttm_tt_bind(bo
->ttm
, &tmp_mem
);
331 r
= amdgpu_move_blit(bo
, true, no_wait_gpu
, &tmp_mem
, old_mem
);
335 r
= ttm_bo_move_ttm(bo
, true, no_wait_gpu
, new_mem
);
337 ttm_bo_mem_put(bo
, &tmp_mem
);
341 static int amdgpu_move_ram_vram(struct ttm_buffer_object
*bo
,
342 bool evict
, bool interruptible
,
344 struct ttm_mem_reg
*new_mem
)
346 struct amdgpu_device
*adev
;
347 struct ttm_mem_reg
*old_mem
= &bo
->mem
;
348 struct ttm_mem_reg tmp_mem
;
349 struct ttm_placement placement
;
350 struct ttm_place placements
;
353 adev
= amdgpu_get_adev(bo
->bdev
);
355 tmp_mem
.mm_node
= NULL
;
356 placement
.num_placement
= 1;
357 placement
.placement
= &placements
;
358 placement
.num_busy_placement
= 1;
359 placement
.busy_placement
= &placements
;
362 placements
.flags
= TTM_PL_MASK_CACHING
| TTM_PL_FLAG_TT
;
363 r
= ttm_bo_mem_space(bo
, &placement
, &tmp_mem
,
364 interruptible
, no_wait_gpu
);
368 r
= ttm_bo_move_ttm(bo
, true, no_wait_gpu
, &tmp_mem
);
372 r
= amdgpu_move_blit(bo
, true, no_wait_gpu
, new_mem
, old_mem
);
377 ttm_bo_mem_put(bo
, &tmp_mem
);
381 static int amdgpu_bo_move(struct ttm_buffer_object
*bo
,
382 bool evict
, bool interruptible
,
384 struct ttm_mem_reg
*new_mem
)
386 struct amdgpu_device
*adev
;
387 struct amdgpu_bo
*abo
;
388 struct ttm_mem_reg
*old_mem
= &bo
->mem
;
391 /* Can't move a pinned BO */
392 abo
= container_of(bo
, struct amdgpu_bo
, tbo
);
393 if (WARN_ON_ONCE(abo
->pin_count
> 0))
396 adev
= amdgpu_get_adev(bo
->bdev
);
397 if (old_mem
->mem_type
== TTM_PL_SYSTEM
&& bo
->ttm
== NULL
) {
398 amdgpu_move_null(bo
, new_mem
);
401 if ((old_mem
->mem_type
== TTM_PL_TT
&&
402 new_mem
->mem_type
== TTM_PL_SYSTEM
) ||
403 (old_mem
->mem_type
== TTM_PL_SYSTEM
&&
404 new_mem
->mem_type
== TTM_PL_TT
)) {
406 amdgpu_move_null(bo
, new_mem
);
409 if (adev
->mman
.buffer_funcs
== NULL
||
410 adev
->mman
.buffer_funcs_ring
== NULL
||
411 !adev
->mman
.buffer_funcs_ring
->ready
) {
416 if (old_mem
->mem_type
== TTM_PL_VRAM
&&
417 new_mem
->mem_type
== TTM_PL_SYSTEM
) {
418 r
= amdgpu_move_vram_ram(bo
, evict
, interruptible
,
419 no_wait_gpu
, new_mem
);
420 } else if (old_mem
->mem_type
== TTM_PL_SYSTEM
&&
421 new_mem
->mem_type
== TTM_PL_VRAM
) {
422 r
= amdgpu_move_ram_vram(bo
, evict
, interruptible
,
423 no_wait_gpu
, new_mem
);
425 r
= amdgpu_move_blit(bo
, evict
, no_wait_gpu
, new_mem
, old_mem
);
430 r
= ttm_bo_move_memcpy(bo
, evict
, no_wait_gpu
, new_mem
);
436 /* update statistics */
437 atomic64_add((u64
)bo
->num_pages
<< PAGE_SHIFT
, &adev
->num_bytes_moved
);
441 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device
*bdev
, struct ttm_mem_reg
*mem
)
443 struct ttm_mem_type_manager
*man
= &bdev
->man
[mem
->mem_type
];
444 struct amdgpu_device
*adev
= amdgpu_get_adev(bdev
);
446 mem
->bus
.addr
= NULL
;
448 mem
->bus
.size
= mem
->num_pages
<< PAGE_SHIFT
;
450 mem
->bus
.is_iomem
= false;
451 if (!(man
->flags
& TTM_MEMTYPE_FLAG_MAPPABLE
))
453 switch (mem
->mem_type
) {
460 mem
->bus
.offset
= mem
->start
<< PAGE_SHIFT
;
461 /* check if it's visible */
462 if ((mem
->bus
.offset
+ mem
->bus
.size
) > adev
->mc
.visible_vram_size
)
464 mem
->bus
.base
= adev
->mc
.aper_base
;
465 mem
->bus
.is_iomem
= true;
468 * Alpha: use bus.addr to hold the ioremap() return,
469 * so we can modify bus.base below.
471 if (mem
->placement
& TTM_PL_FLAG_WC
)
473 ioremap_wc(mem
->bus
.base
+ mem
->bus
.offset
,
477 ioremap_nocache(mem
->bus
.base
+ mem
->bus
.offset
,
481 * Alpha: Use just the bus offset plus
482 * the hose/domain memory base for bus.base.
483 * It then can be used to build PTEs for VRAM
484 * access, as done in ttm_bo_vm_fault().
486 mem
->bus
.base
= (mem
->bus
.base
& 0x0ffffffffUL
) +
487 adev
->ddev
->hose
->dense_mem_base
;
496 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device
*bdev
, struct ttm_mem_reg
*mem
)
501 * TTM backend functions.
503 struct amdgpu_ttm_gup_task_list
{
504 struct list_head list
;
505 struct task_struct
*task
;
508 struct amdgpu_ttm_tt
{
509 struct ttm_dma_tt ttm
;
510 struct amdgpu_device
*adev
;
513 struct mm_struct
*usermm
;
515 spinlock_t guptasklock
;
516 struct list_head guptasks
;
517 atomic_t mmu_invalidations
;
520 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt
*ttm
, struct page
**pages
)
522 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
523 int write
= !(gtt
->userflags
& AMDGPU_GEM_USERPTR_READONLY
);
527 if (gtt
->userflags
& AMDGPU_GEM_USERPTR_ANONONLY
) {
528 /* check that we only use anonymous memory
529 to prevent problems with writeback */
530 unsigned long end
= gtt
->userptr
+ ttm
->num_pages
* PAGE_SIZE
;
531 struct vm_area_struct
*vma
;
533 vma
= find_vma(gtt
->usermm
, gtt
->userptr
);
534 if (!vma
|| vma
->vm_file
|| vma
->vm_end
< end
)
539 unsigned num_pages
= ttm
->num_pages
- pinned
;
540 uint64_t userptr
= gtt
->userptr
+ pinned
* PAGE_SIZE
;
541 struct page
**p
= pages
+ pinned
;
542 struct amdgpu_ttm_gup_task_list guptask
;
544 guptask
.task
= current
;
545 spin_lock(>t
->guptasklock
);
546 list_add(&guptask
.list
, >t
->guptasks
);
547 spin_unlock(>t
->guptasklock
);
549 r
= get_user_pages(userptr
, num_pages
, write
, 0, p
, NULL
);
551 spin_lock(>t
->guptasklock
);
552 list_del(&guptask
.list
);
553 spin_unlock(>t
->guptasklock
);
560 } while (pinned
< ttm
->num_pages
);
565 release_pages(pages
, pinned
, 0);
569 /* prepare the sg table with the user pages */
570 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt
*ttm
)
572 struct amdgpu_device
*adev
= amdgpu_get_adev(ttm
->bdev
);
573 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
577 int write
= !(gtt
->userflags
& AMDGPU_GEM_USERPTR_READONLY
);
578 enum dma_data_direction direction
= write
?
579 DMA_BIDIRECTIONAL
: DMA_TO_DEVICE
;
581 r
= sg_alloc_table_from_pages(ttm
->sg
, ttm
->pages
, ttm
->num_pages
, 0,
582 ttm
->num_pages
<< PAGE_SHIFT
,
588 nents
= dma_map_sg(adev
->dev
, ttm
->sg
->sgl
, ttm
->sg
->nents
, direction
);
589 if (nents
!= ttm
->sg
->nents
)
592 drm_prime_sg_to_page_addr_arrays(ttm
->sg
, ttm
->pages
,
593 gtt
->ttm
.dma_address
, ttm
->num_pages
);
602 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt
*ttm
)
604 struct amdgpu_device
*adev
= amdgpu_get_adev(ttm
->bdev
);
605 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
606 struct sg_page_iter sg_iter
;
608 int write
= !(gtt
->userflags
& AMDGPU_GEM_USERPTR_READONLY
);
609 enum dma_data_direction direction
= write
?
610 DMA_BIDIRECTIONAL
: DMA_TO_DEVICE
;
612 /* double check that we don't free the table twice */
616 /* free the sg table and pages again */
617 dma_unmap_sg(adev
->dev
, ttm
->sg
->sgl
, ttm
->sg
->nents
, direction
);
619 for_each_sg_page(ttm
->sg
->sgl
, &sg_iter
, ttm
->sg
->nents
, 0) {
620 struct page
*page
= sg_page_iter_page(&sg_iter
);
621 if (!(gtt
->userflags
& AMDGPU_GEM_USERPTR_READONLY
))
622 set_page_dirty(page
);
624 mark_page_accessed(page
);
628 sg_free_table(ttm
->sg
);
631 static int amdgpu_ttm_backend_bind(struct ttm_tt
*ttm
,
632 struct ttm_mem_reg
*bo_mem
)
634 struct amdgpu_ttm_tt
*gtt
= (void*)ttm
;
635 uint32_t flags
= amdgpu_ttm_tt_pte_flags(gtt
->adev
, ttm
, bo_mem
);
639 r
= amdgpu_ttm_tt_pin_userptr(ttm
);
641 DRM_ERROR("failed to pin userptr\n");
645 gtt
->offset
= (unsigned long)(bo_mem
->start
<< PAGE_SHIFT
);
646 if (!ttm
->num_pages
) {
647 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
648 ttm
->num_pages
, bo_mem
, ttm
);
651 if (bo_mem
->mem_type
== AMDGPU_PL_GDS
||
652 bo_mem
->mem_type
== AMDGPU_PL_GWS
||
653 bo_mem
->mem_type
== AMDGPU_PL_OA
)
656 r
= amdgpu_gart_bind(gtt
->adev
, gtt
->offset
, ttm
->num_pages
,
657 ttm
->pages
, gtt
->ttm
.dma_address
, flags
);
660 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
661 ttm
->num_pages
, (unsigned)gtt
->offset
);
667 static int amdgpu_ttm_backend_unbind(struct ttm_tt
*ttm
)
669 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
671 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
672 if (gtt
->adev
->gart
.ready
)
673 amdgpu_gart_unbind(gtt
->adev
, gtt
->offset
, ttm
->num_pages
);
676 amdgpu_ttm_tt_unpin_userptr(ttm
);
681 static void amdgpu_ttm_backend_destroy(struct ttm_tt
*ttm
)
683 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
685 ttm_dma_tt_fini(>t
->ttm
);
689 static struct ttm_backend_func amdgpu_backend_func
= {
690 .bind
= &amdgpu_ttm_backend_bind
,
691 .unbind
= &amdgpu_ttm_backend_unbind
,
692 .destroy
= &amdgpu_ttm_backend_destroy
,
695 static struct ttm_tt
*amdgpu_ttm_tt_create(struct ttm_bo_device
*bdev
,
696 unsigned long size
, uint32_t page_flags
,
697 struct page
*dummy_read_page
)
699 struct amdgpu_device
*adev
;
700 struct amdgpu_ttm_tt
*gtt
;
702 adev
= amdgpu_get_adev(bdev
);
704 gtt
= kzalloc(sizeof(struct amdgpu_ttm_tt
), GFP_KERNEL
);
708 gtt
->ttm
.ttm
.func
= &amdgpu_backend_func
;
710 if (ttm_dma_tt_init(>t
->ttm
, bdev
, size
, page_flags
, dummy_read_page
)) {
714 return >t
->ttm
.ttm
;
717 static int amdgpu_ttm_tt_populate(struct ttm_tt
*ttm
)
719 struct amdgpu_device
*adev
;
720 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
723 bool slave
= !!(ttm
->page_flags
& TTM_PAGE_FLAG_SG
);
725 if (ttm
->state
!= tt_unpopulated
)
728 if (gtt
&& gtt
->userptr
) {
729 ttm
->sg
= kzalloc(sizeof(struct sg_table
), GFP_KERNEL
);
733 ttm
->page_flags
|= TTM_PAGE_FLAG_SG
;
734 ttm
->state
= tt_unbound
;
738 if (slave
&& ttm
->sg
) {
739 drm_prime_sg_to_page_addr_arrays(ttm
->sg
, ttm
->pages
,
740 gtt
->ttm
.dma_address
, ttm
->num_pages
);
741 ttm
->state
= tt_unbound
;
745 adev
= amdgpu_get_adev(ttm
->bdev
);
747 #ifdef CONFIG_SWIOTLB
748 if (swiotlb_nr_tbl()) {
749 return ttm_dma_populate(>t
->ttm
, adev
->dev
);
753 r
= ttm_pool_populate(ttm
);
758 for (i
= 0; i
< ttm
->num_pages
; i
++) {
759 gtt
->ttm
.dma_address
[i
] = pci_map_page(adev
->pdev
, ttm
->pages
[i
],
761 PCI_DMA_BIDIRECTIONAL
);
762 if (pci_dma_mapping_error(adev
->pdev
, gtt
->ttm
.dma_address
[i
])) {
764 pci_unmap_page(adev
->pdev
, gtt
->ttm
.dma_address
[i
],
765 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
766 gtt
->ttm
.dma_address
[i
] = 0;
768 ttm_pool_unpopulate(ttm
);
775 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt
*ttm
)
777 struct amdgpu_device
*adev
;
778 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
780 bool slave
= !!(ttm
->page_flags
& TTM_PAGE_FLAG_SG
);
782 if (gtt
&& gtt
->userptr
) {
784 ttm
->page_flags
&= ~TTM_PAGE_FLAG_SG
;
791 adev
= amdgpu_get_adev(ttm
->bdev
);
793 #ifdef CONFIG_SWIOTLB
794 if (swiotlb_nr_tbl()) {
795 ttm_dma_unpopulate(>t
->ttm
, adev
->dev
);
800 for (i
= 0; i
< ttm
->num_pages
; i
++) {
801 if (gtt
->ttm
.dma_address
[i
]) {
802 pci_unmap_page(adev
->pdev
, gtt
->ttm
.dma_address
[i
],
803 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
807 ttm_pool_unpopulate(ttm
);
810 int amdgpu_ttm_tt_set_userptr(struct ttm_tt
*ttm
, uint64_t addr
,
813 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
819 gtt
->usermm
= current
->mm
;
820 gtt
->userflags
= flags
;
821 spin_lock_init(>t
->guptasklock
);
822 INIT_LIST_HEAD(>t
->guptasks
);
823 atomic_set(>t
->mmu_invalidations
, 0);
828 struct mm_struct
*amdgpu_ttm_tt_get_usermm(struct ttm_tt
*ttm
)
830 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
838 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt
*ttm
, unsigned long start
,
841 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
842 struct amdgpu_ttm_gup_task_list
*entry
;
845 if (gtt
== NULL
|| !gtt
->userptr
)
848 size
= (unsigned long)gtt
->ttm
.ttm
.num_pages
* PAGE_SIZE
;
849 if (gtt
->userptr
> end
|| gtt
->userptr
+ size
<= start
)
852 spin_lock(>t
->guptasklock
);
853 list_for_each_entry(entry
, >t
->guptasks
, list
) {
854 if (entry
->task
== current
) {
855 spin_unlock(>t
->guptasklock
);
859 spin_unlock(>t
->guptasklock
);
861 atomic_inc(>t
->mmu_invalidations
);
866 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt
*ttm
,
867 int *last_invalidated
)
869 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
870 int prev_invalidated
= *last_invalidated
;
872 *last_invalidated
= atomic_read(>t
->mmu_invalidations
);
873 return prev_invalidated
!= *last_invalidated
;
876 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt
*ttm
)
878 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
883 return !!(gtt
->userflags
& AMDGPU_GEM_USERPTR_READONLY
);
886 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device
*adev
, struct ttm_tt
*ttm
,
887 struct ttm_mem_reg
*mem
)
891 if (mem
&& mem
->mem_type
!= TTM_PL_SYSTEM
)
892 flags
|= AMDGPU_PTE_VALID
;
894 if (mem
&& mem
->mem_type
== TTM_PL_TT
) {
895 flags
|= AMDGPU_PTE_SYSTEM
;
897 if (ttm
->caching_state
== tt_cached
)
898 flags
|= AMDGPU_PTE_SNOOPED
;
901 if (adev
->asic_type
>= CHIP_TONGA
)
902 flags
|= AMDGPU_PTE_EXECUTABLE
;
904 flags
|= AMDGPU_PTE_READABLE
;
906 if (!amdgpu_ttm_tt_is_readonly(ttm
))
907 flags
|= AMDGPU_PTE_WRITEABLE
;
912 static struct ttm_bo_driver amdgpu_bo_driver
= {
913 .ttm_tt_create
= &amdgpu_ttm_tt_create
,
914 .ttm_tt_populate
= &amdgpu_ttm_tt_populate
,
915 .ttm_tt_unpopulate
= &amdgpu_ttm_tt_unpopulate
,
916 .invalidate_caches
= &amdgpu_invalidate_caches
,
917 .init_mem_type
= &amdgpu_init_mem_type
,
918 .evict_flags
= &amdgpu_evict_flags
,
919 .move
= &amdgpu_bo_move
,
920 .verify_access
= &amdgpu_verify_access
,
921 .move_notify
= &amdgpu_bo_move_notify
,
922 .fault_reserve_notify
= &amdgpu_bo_fault_reserve_notify
,
923 .io_mem_reserve
= &amdgpu_ttm_io_mem_reserve
,
924 .io_mem_free
= &amdgpu_ttm_io_mem_free
,
927 int amdgpu_ttm_init(struct amdgpu_device
*adev
)
931 r
= amdgpu_ttm_global_init(adev
);
935 /* No others user of address space so set it to 0 */
936 r
= ttm_bo_device_init(&adev
->mman
.bdev
,
937 adev
->mman
.bo_global_ref
.ref
.object
,
939 adev
->ddev
->anon_inode
->i_mapping
,
940 DRM_FILE_PAGE_OFFSET
,
943 DRM_ERROR("failed initializing buffer object driver(%d).\n", r
);
946 adev
->mman
.initialized
= true;
947 r
= ttm_bo_init_mm(&adev
->mman
.bdev
, TTM_PL_VRAM
,
948 adev
->mc
.real_vram_size
>> PAGE_SHIFT
);
950 DRM_ERROR("Failed initializing VRAM heap.\n");
953 /* Change the size here instead of the init above so only lpfn is affected */
954 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.visible_vram_size
);
956 r
= amdgpu_bo_create(adev
, 256 * 1024, PAGE_SIZE
, true,
957 AMDGPU_GEM_DOMAIN_VRAM
,
958 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
,
959 NULL
, NULL
, &adev
->stollen_vga_memory
);
963 r
= amdgpu_bo_reserve(adev
->stollen_vga_memory
, false);
966 r
= amdgpu_bo_pin(adev
->stollen_vga_memory
, AMDGPU_GEM_DOMAIN_VRAM
, NULL
);
967 amdgpu_bo_unreserve(adev
->stollen_vga_memory
);
969 amdgpu_bo_unref(&adev
->stollen_vga_memory
);
972 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
973 (unsigned) (adev
->mc
.real_vram_size
/ (1024 * 1024)));
974 r
= ttm_bo_init_mm(&adev
->mman
.bdev
, TTM_PL_TT
,
975 adev
->mc
.gtt_size
>> PAGE_SHIFT
);
977 DRM_ERROR("Failed initializing GTT heap.\n");
980 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
981 (unsigned)(adev
->mc
.gtt_size
/ (1024 * 1024)));
983 adev
->gds
.mem
.total_size
= adev
->gds
.mem
.total_size
<< AMDGPU_GDS_SHIFT
;
984 adev
->gds
.mem
.gfx_partition_size
= adev
->gds
.mem
.gfx_partition_size
<< AMDGPU_GDS_SHIFT
;
985 adev
->gds
.mem
.cs_partition_size
= adev
->gds
.mem
.cs_partition_size
<< AMDGPU_GDS_SHIFT
;
986 adev
->gds
.gws
.total_size
= adev
->gds
.gws
.total_size
<< AMDGPU_GWS_SHIFT
;
987 adev
->gds
.gws
.gfx_partition_size
= adev
->gds
.gws
.gfx_partition_size
<< AMDGPU_GWS_SHIFT
;
988 adev
->gds
.gws
.cs_partition_size
= adev
->gds
.gws
.cs_partition_size
<< AMDGPU_GWS_SHIFT
;
989 adev
->gds
.oa
.total_size
= adev
->gds
.oa
.total_size
<< AMDGPU_OA_SHIFT
;
990 adev
->gds
.oa
.gfx_partition_size
= adev
->gds
.oa
.gfx_partition_size
<< AMDGPU_OA_SHIFT
;
991 adev
->gds
.oa
.cs_partition_size
= adev
->gds
.oa
.cs_partition_size
<< AMDGPU_OA_SHIFT
;
993 r
= ttm_bo_init_mm(&adev
->mman
.bdev
, AMDGPU_PL_GDS
,
994 adev
->gds
.mem
.total_size
>> PAGE_SHIFT
);
996 DRM_ERROR("Failed initializing GDS heap.\n");
1001 r
= ttm_bo_init_mm(&adev
->mman
.bdev
, AMDGPU_PL_GWS
,
1002 adev
->gds
.gws
.total_size
>> PAGE_SHIFT
);
1004 DRM_ERROR("Failed initializing gws heap.\n");
1009 r
= ttm_bo_init_mm(&adev
->mman
.bdev
, AMDGPU_PL_OA
,
1010 adev
->gds
.oa
.total_size
>> PAGE_SHIFT
);
1012 DRM_ERROR("Failed initializing oa heap.\n");
1016 r
= amdgpu_ttm_debugfs_init(adev
);
1018 DRM_ERROR("Failed to init debugfs\n");
1024 void amdgpu_ttm_fini(struct amdgpu_device
*adev
)
1028 if (!adev
->mman
.initialized
)
1030 amdgpu_ttm_debugfs_fini(adev
);
1031 if (adev
->stollen_vga_memory
) {
1032 r
= amdgpu_bo_reserve(adev
->stollen_vga_memory
, false);
1034 amdgpu_bo_unpin(adev
->stollen_vga_memory
);
1035 amdgpu_bo_unreserve(adev
->stollen_vga_memory
);
1037 amdgpu_bo_unref(&adev
->stollen_vga_memory
);
1039 ttm_bo_clean_mm(&adev
->mman
.bdev
, TTM_PL_VRAM
);
1040 ttm_bo_clean_mm(&adev
->mman
.bdev
, TTM_PL_TT
);
1041 ttm_bo_clean_mm(&adev
->mman
.bdev
, AMDGPU_PL_GDS
);
1042 ttm_bo_clean_mm(&adev
->mman
.bdev
, AMDGPU_PL_GWS
);
1043 ttm_bo_clean_mm(&adev
->mman
.bdev
, AMDGPU_PL_OA
);
1044 ttm_bo_device_release(&adev
->mman
.bdev
);
1045 amdgpu_gart_fini(adev
);
1046 amdgpu_ttm_global_fini(adev
);
1047 adev
->mman
.initialized
= false;
1048 DRM_INFO("amdgpu: ttm finalized\n");
1051 /* this should only be called at bootup or when userspace
1053 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device
*adev
, u64 size
)
1055 struct ttm_mem_type_manager
*man
;
1057 if (!adev
->mman
.initialized
)
1060 man
= &adev
->mman
.bdev
.man
[TTM_PL_VRAM
];
1061 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1062 man
->size
= size
>> PAGE_SHIFT
;
1065 int amdgpu_mmap(struct file
*filp
, struct vm_area_struct
*vma
)
1067 struct drm_file
*file_priv
;
1068 struct amdgpu_device
*adev
;
1070 if (unlikely(vma
->vm_pgoff
< DRM_FILE_PAGE_OFFSET
))
1073 file_priv
= filp
->private_data
;
1074 adev
= file_priv
->minor
->dev
->dev_private
;
1078 return ttm_bo_mmap(filp
, vma
, &adev
->mman
.bdev
);
1081 int amdgpu_copy_buffer(struct amdgpu_ring
*ring
,
1082 uint64_t src_offset
,
1083 uint64_t dst_offset
,
1084 uint32_t byte_count
,
1085 struct reservation_object
*resv
,
1086 struct fence
**fence
)
1088 struct amdgpu_device
*adev
= ring
->adev
;
1089 struct amdgpu_job
*job
;
1092 unsigned num_loops
, num_dw
;
1096 max_bytes
= adev
->mman
.buffer_funcs
->copy_max_bytes
;
1097 num_loops
= DIV_ROUND_UP(byte_count
, max_bytes
);
1098 num_dw
= num_loops
* adev
->mman
.buffer_funcs
->copy_num_dw
;
1100 /* for IB padding */
1101 while (num_dw
& 0x7)
1104 r
= amdgpu_job_alloc_with_ib(adev
, num_dw
* 4, &job
);
1109 r
= amdgpu_sync_resv(adev
, &job
->sync
, resv
,
1110 AMDGPU_FENCE_OWNER_UNDEFINED
);
1112 DRM_ERROR("sync failed (%d).\n", r
);
1117 for (i
= 0; i
< num_loops
; i
++) {
1118 uint32_t cur_size_in_bytes
= min(byte_count
, max_bytes
);
1120 amdgpu_emit_copy_buffer(adev
, &job
->ibs
[0], src_offset
,
1121 dst_offset
, cur_size_in_bytes
);
1123 src_offset
+= cur_size_in_bytes
;
1124 dst_offset
+= cur_size_in_bytes
;
1125 byte_count
-= cur_size_in_bytes
;
1128 amdgpu_ring_pad_ib(ring
, &job
->ibs
[0]);
1129 WARN_ON(job
->ibs
[0].length_dw
> num_dw
);
1130 r
= amdgpu_job_submit(job
, ring
, &adev
->mman
.entity
,
1131 AMDGPU_FENCE_OWNER_UNDEFINED
, fence
);
1138 amdgpu_job_free(job
);
1142 #if defined(CONFIG_DEBUG_FS)
1144 static int amdgpu_mm_dump_table(struct seq_file
*m
, void *data
)
1146 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
1147 unsigned ttm_pl
= *(int *)node
->info_ent
->data
;
1148 struct drm_device
*dev
= node
->minor
->dev
;
1149 struct amdgpu_device
*adev
= dev
->dev_private
;
1150 struct drm_mm
*mm
= (struct drm_mm
*)adev
->mman
.bdev
.man
[ttm_pl
].priv
;
1152 struct ttm_bo_global
*glob
= adev
->mman
.bdev
.glob
;
1154 spin_lock(&glob
->lru_lock
);
1155 ret
= drm_mm_dump_table(m
, mm
);
1156 spin_unlock(&glob
->lru_lock
);
1157 if (ttm_pl
== TTM_PL_VRAM
)
1158 seq_printf(m
, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
1159 adev
->mman
.bdev
.man
[ttm_pl
].size
,
1160 (u64
)atomic64_read(&adev
->vram_usage
) >> 20,
1161 (u64
)atomic64_read(&adev
->vram_vis_usage
) >> 20);
1165 static int ttm_pl_vram
= TTM_PL_VRAM
;
1166 static int ttm_pl_tt
= TTM_PL_TT
;
1168 static struct drm_info_list amdgpu_ttm_debugfs_list
[] = {
1169 {"amdgpu_vram_mm", amdgpu_mm_dump_table
, 0, &ttm_pl_vram
},
1170 {"amdgpu_gtt_mm", amdgpu_mm_dump_table
, 0, &ttm_pl_tt
},
1171 {"ttm_page_pool", ttm_page_alloc_debugfs
, 0, NULL
},
1172 #ifdef CONFIG_SWIOTLB
1173 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs
, 0, NULL
}
1177 static ssize_t
amdgpu_ttm_vram_read(struct file
*f
, char __user
*buf
,
1178 size_t size
, loff_t
*pos
)
1180 struct amdgpu_device
*adev
= f
->f_inode
->i_private
;
1184 if (size
& 0x3 || *pos
& 0x3)
1188 unsigned long flags
;
1191 if (*pos
>= adev
->mc
.mc_vram_size
)
1194 spin_lock_irqsave(&adev
->mmio_idx_lock
, flags
);
1195 WREG32(mmMM_INDEX
, ((uint32_t)*pos
) | 0x80000000);
1196 WREG32(mmMM_INDEX_HI
, *pos
>> 31);
1197 value
= RREG32(mmMM_DATA
);
1198 spin_unlock_irqrestore(&adev
->mmio_idx_lock
, flags
);
1200 r
= put_user(value
, (uint32_t *)buf
);
1213 static const struct file_operations amdgpu_ttm_vram_fops
= {
1214 .owner
= THIS_MODULE
,
1215 .read
= amdgpu_ttm_vram_read
,
1216 .llseek
= default_llseek
1219 static ssize_t
amdgpu_ttm_gtt_read(struct file
*f
, char __user
*buf
,
1220 size_t size
, loff_t
*pos
)
1222 struct amdgpu_device
*adev
= f
->f_inode
->i_private
;
1227 loff_t p
= *pos
/ PAGE_SIZE
;
1228 unsigned off
= *pos
& ~PAGE_MASK
;
1229 size_t cur_size
= min_t(size_t, size
, PAGE_SIZE
- off
);
1233 if (p
>= adev
->gart
.num_cpu_pages
)
1236 page
= adev
->gart
.pages
[p
];
1241 r
= copy_to_user(buf
, ptr
, cur_size
);
1242 kunmap(adev
->gart
.pages
[p
]);
1244 r
= clear_user(buf
, cur_size
);
1258 static const struct file_operations amdgpu_ttm_gtt_fops
= {
1259 .owner
= THIS_MODULE
,
1260 .read
= amdgpu_ttm_gtt_read
,
1261 .llseek
= default_llseek
1266 static int amdgpu_ttm_debugfs_init(struct amdgpu_device
*adev
)
1268 #if defined(CONFIG_DEBUG_FS)
1271 struct drm_minor
*minor
= adev
->ddev
->primary
;
1272 struct dentry
*ent
, *root
= minor
->debugfs_root
;
1274 ent
= debugfs_create_file("amdgpu_vram", S_IFREG
| S_IRUGO
, root
,
1275 adev
, &amdgpu_ttm_vram_fops
);
1277 return PTR_ERR(ent
);
1278 i_size_write(ent
->d_inode
, adev
->mc
.mc_vram_size
);
1279 adev
->mman
.vram
= ent
;
1281 ent
= debugfs_create_file("amdgpu_gtt", S_IFREG
| S_IRUGO
, root
,
1282 adev
, &amdgpu_ttm_gtt_fops
);
1284 return PTR_ERR(ent
);
1285 i_size_write(ent
->d_inode
, adev
->mc
.gtt_size
);
1286 adev
->mman
.gtt
= ent
;
1288 count
= ARRAY_SIZE(amdgpu_ttm_debugfs_list
);
1290 #ifdef CONFIG_SWIOTLB
1291 if (!swiotlb_nr_tbl())
1295 return amdgpu_debugfs_add_files(adev
, amdgpu_ttm_debugfs_list
, count
);
1302 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device
*adev
)
1304 #if defined(CONFIG_DEBUG_FS)
1306 debugfs_remove(adev
->mman
.vram
);
1307 adev
->mman
.vram
= NULL
;
1309 debugfs_remove(adev
->mman
.gtt
);
1310 adev
->mman
.gtt
= NULL
;