drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef __AMDGPU_UCODE_H__
  24 #define __AMDGPU_UCODE_H__
  25
  26 struct common_firmware_header {
  27         uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
  28         uint32_t header_size_bytes; /* size of just the header in bytes */
  29         uint16_t header_version_major; /* header version */
  30         uint16_t header_version_minor; /* header version */
  31         uint16_t ip_version_major; /* IP version */
  32         uint16_t ip_version_minor; /* IP version */
  33         uint32_t ucode_version;
  34         uint32_t ucode_size_bytes; /* size of ucode in bytes */
  35         uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
  36         uint32_t crc32;  /* crc32 checksum of the payload */
  37 };
  38
  39 /* version_major=1, version_minor=0 */
  40 struct mc_firmware_header_v1_0 {
  41         struct common_firmware_header header;
  42         uint32_t io_debug_size_bytes; /* size of debug array in dwords */
  43         uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
  44 };
  45
  46 /* version_major=1, version_minor=0 */
  47 struct smc_firmware_header_v1_0 {
  48         struct common_firmware_header header;
  49         uint32_t ucode_start_addr;
  50 };
  51
  52 /* version_major=1, version_minor=0 */
  53 struct psp_firmware_header_v1_0 {
  54         struct common_firmware_header header;
  55         uint32_t ucode_feature_version;
  56         uint32_t sos_offset_bytes;
  57         uint32_t sos_size_bytes;
  58 };
  59
  60 /* version_major=1, version_minor=0 */
  61 struct gfx_firmware_header_v1_0 {
  62         struct common_firmware_header header;
  63         uint32_t ucode_feature_version;
  64         uint32_t jt_offset; /* jt location */
  65         uint32_t jt_size;  /* size of jt */
  66 };
  67
  68 /* version_major=1, version_minor=0 */
  69 struct rlc_firmware_header_v1_0 {
  70         struct common_firmware_header header;
  71         uint32_t ucode_feature_version;
  72         uint32_t save_and_restore_offset;
  73         uint32_t clear_state_descriptor_offset;
  74         uint32_t avail_scratch_ram_locations;
  75         uint32_t master_pkt_description_offset;
  76 };
  77
  78 /* version_major=2, version_minor=0 */
  79 struct rlc_firmware_header_v2_0 {
  80         struct common_firmware_header header;
  81         uint32_t ucode_feature_version;
  82         uint32_t jt_offset; /* jt location */
  83         uint32_t jt_size;  /* size of jt */
  84         uint32_t save_and_restore_offset;
  85         uint32_t clear_state_descriptor_offset;
  86         uint32_t avail_scratch_ram_locations;
  87         uint32_t reg_restore_list_size;
  88         uint32_t reg_list_format_start;
  89         uint32_t reg_list_format_separate_start;
  90         uint32_t starting_offsets_start;
  91         uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */
  92         uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */
  93         uint32_t reg_list_size_bytes; /* size of reg list array in bytes */
  94         uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */
  95         uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */
  96         uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */
  97         uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */
  98         uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
  99 };
 100
 101 /* version_major=1, version_minor=0 */
 102 struct sdma_firmware_header_v1_0 {
 103         struct common_firmware_header header;
 104         uint32_t ucode_feature_version;
 105         uint32_t ucode_change_version;
 106         uint32_t jt_offset; /* jt location */
 107         uint32_t jt_size; /* size of jt */
 108 };
 109
 110 /* version_major=1, version_minor=1 */
 111 struct sdma_firmware_header_v1_1 {
 112         struct sdma_firmware_header_v1_0 v1_0;
 113         uint32_t digest_size;
 114 };
 115
 116 /* gpu info payload */
 117 struct gpu_info_firmware_v1_0 {
 118         uint32_t gc_num_se;
 119         uint32_t gc_num_cu_per_sh;
 120         uint32_t gc_num_sh_per_se;
 121         uint32_t gc_num_rb_per_se;
 122         uint32_t gc_num_tccs;
 123         uint32_t gc_num_gprs;
 124         uint32_t gc_num_max_gs_thds;
 125         uint32_t gc_gs_table_depth;
 126         uint32_t gc_gsprim_buff_depth;
 127         uint32_t gc_parameter_cache_depth;
 128         uint32_t gc_double_offchip_lds_buffer;
 129         uint32_t gc_wave_size;
 130         uint32_t gc_max_waves_per_simd;
 131         uint32_t gc_max_scratch_slots_per_cu;
 132         uint32_t gc_lds_size;
 133 };
 134
 135 /* version_major=1, version_minor=0 */
 136 struct gpu_info_firmware_header_v1_0 {
 137         struct common_firmware_header header;
 138         uint16_t version_major; /* version */
 139         uint16_t version_minor; /* version */
 140 };
 141
 142 /* header is fixed size */
 143 union amdgpu_firmware_header {
 144         struct common_firmware_header common;
 145         struct mc_firmware_header_v1_0 mc;
 146         struct smc_firmware_header_v1_0 smc;
 147         struct psp_firmware_header_v1_0 psp;
 148         struct gfx_firmware_header_v1_0 gfx;
 149         struct rlc_firmware_header_v1_0 rlc;
 150         struct rlc_firmware_header_v2_0 rlc_v2_0;
 151         struct sdma_firmware_header_v1_0 sdma;
 152         struct sdma_firmware_header_v1_1 sdma_v1_1;
 153         struct gpu_info_firmware_header_v1_0 gpu_info;
 154         uint8_t raw[0x100];
 155 };
 156
 157 /*
 158  * fw loading support
 159  */
 160 enum AMDGPU_UCODE_ID {
 161         AMDGPU_UCODE_ID_SDMA0 = 0,
 162         AMDGPU_UCODE_ID_SDMA1,
 163         AMDGPU_UCODE_ID_CP_CE,
 164         AMDGPU_UCODE_ID_CP_PFP,
 165         AMDGPU_UCODE_ID_CP_ME,
 166         AMDGPU_UCODE_ID_CP_MEC1,
 167         AMDGPU_UCODE_ID_CP_MEC1_JT,
 168         AMDGPU_UCODE_ID_CP_MEC2,
 169         AMDGPU_UCODE_ID_CP_MEC2_JT,
 170         AMDGPU_UCODE_ID_RLC_G,
 171         AMDGPU_UCODE_ID_STORAGE,
 172         AMDGPU_UCODE_ID_SMC,
 173         AMDGPU_UCODE_ID_UVD,
 174         AMDGPU_UCODE_ID_VCE,
 175         AMDGPU_UCODE_ID_MAXIMUM,
 176 };
 177
 178 /* engine firmware status */
 179 enum AMDGPU_UCODE_STATUS {
 180         AMDGPU_UCODE_STATUS_INVALID,
 181         AMDGPU_UCODE_STATUS_NOT_LOADED,
 182         AMDGPU_UCODE_STATUS_LOADED,
 183 };
 184
 185 /* conform to smu_ucode_xfer_cz.h */
 186 #define AMDGPU_SDMA0_UCODE_LOADED       0x00000001
 187 #define AMDGPU_SDMA1_UCODE_LOADED       0x00000002
 188 #define AMDGPU_CPCE_UCODE_LOADED        0x00000004
 189 #define AMDGPU_CPPFP_UCODE_LOADED       0x00000008
 190 #define AMDGPU_CPME_UCODE_LOADED        0x00000010
 191 #define AMDGPU_CPMEC1_UCODE_LOADED      0x00000020
 192 #define AMDGPU_CPMEC2_UCODE_LOADED      0x00000040
 193 #define AMDGPU_CPRLC_UCODE_LOADED       0x00000100
 194
 195 /* amdgpu firmware info */
 196 struct amdgpu_firmware_info {
 197         /* ucode ID */
 198         enum AMDGPU_UCODE_ID ucode_id;
 199         /* request_firmware */
 200         const struct firmware *fw;
 201         /* starting mc address */
 202         uint64_t mc_addr;
 203         /* kernel linear address */
 204         void *kaddr;
 205         /* ucode_size_bytes */
 206         uint32_t ucode_size;
 207 };
 208
 209 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
 210 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
 211 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
 212 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
 213 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
 214 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr);
 215 int amdgpu_ucode_validate(const struct firmware *fw);
 216 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
 217                                 uint16_t hdr_major, uint16_t hdr_minor);
 218 int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
 219 int amdgpu_ucode_fini_bo(struct amdgpu_device *adev);
 220
 221 enum amdgpu_firmware_load_type
 222 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type);
 223
 224 #endif