2 * Copyright 2011 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Christian König <deathsimple@vodafone.de>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
37 #include "amdgpu_pm.h"
38 #include "amdgpu_uvd.h"
40 #include "uvd/uvd_4_2_d.h"
42 /* 1 second timeout */
43 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000)
45 /* Firmware versions for VI */
46 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8))
47 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8))
48 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8))
49 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8))
51 /* Polaris10/11 firmware version */
52 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
55 #ifdef CONFIG_DRM_AMDGPU_CIK
56 #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin"
57 #define FIRMWARE_KABINI "radeon/kabini_uvd.bin"
58 #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin"
59 #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin"
60 #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin"
62 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin"
63 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin"
64 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin"
65 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin"
66 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin"
67 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin"
68 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin"
70 #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin"
72 #define mmUVD_GPCOM_VCPU_DATA0_VEGA10 (0x03c4 + 0x7e00)
73 #define mmUVD_GPCOM_VCPU_DATA1_VEGA10 (0x03c5 + 0x7e00)
74 #define mmUVD_GPCOM_VCPU_CMD_VEGA10 (0x03c3 + 0x7e00)
75 #define mmUVD_NO_OP_VEGA10 (0x03ff + 0x7e00)
76 #define mmUVD_ENGINE_CNTL_VEGA10 (0x03c6 + 0x7e00)
79 * amdgpu_uvd_cs_ctx - Command submission parser context
81 * Used for emulating virtual memory support on UVD 4.2.
83 struct amdgpu_uvd_cs_ctx
{
84 struct amdgpu_cs_parser
*parser
;
86 unsigned data0
, data1
;
90 /* does the IB has a msg command */
93 /* minimum buffer sizes */
97 #ifdef CONFIG_DRM_AMDGPU_CIK
98 MODULE_FIRMWARE(FIRMWARE_BONAIRE
);
99 MODULE_FIRMWARE(FIRMWARE_KABINI
);
100 MODULE_FIRMWARE(FIRMWARE_KAVERI
);
101 MODULE_FIRMWARE(FIRMWARE_HAWAII
);
102 MODULE_FIRMWARE(FIRMWARE_MULLINS
);
104 MODULE_FIRMWARE(FIRMWARE_TONGA
);
105 MODULE_FIRMWARE(FIRMWARE_CARRIZO
);
106 MODULE_FIRMWARE(FIRMWARE_FIJI
);
107 MODULE_FIRMWARE(FIRMWARE_STONEY
);
108 MODULE_FIRMWARE(FIRMWARE_POLARIS10
);
109 MODULE_FIRMWARE(FIRMWARE_POLARIS11
);
110 MODULE_FIRMWARE(FIRMWARE_POLARIS12
);
112 MODULE_FIRMWARE(FIRMWARE_VEGA10
);
114 static void amdgpu_uvd_idle_work_handler(struct work_struct
*work
);
116 int amdgpu_uvd_sw_init(struct amdgpu_device
*adev
)
118 struct amdgpu_ring
*ring
;
119 struct amd_sched_rq
*rq
;
120 unsigned long bo_size
;
122 const struct common_firmware_header
*hdr
;
123 unsigned version_major
, version_minor
, family_id
;
126 INIT_DELAYED_WORK(&adev
->uvd
.idle_work
, amdgpu_uvd_idle_work_handler
);
128 switch (adev
->asic_type
) {
129 #ifdef CONFIG_DRM_AMDGPU_CIK
131 fw_name
= FIRMWARE_BONAIRE
;
134 fw_name
= FIRMWARE_KABINI
;
137 fw_name
= FIRMWARE_KAVERI
;
140 fw_name
= FIRMWARE_HAWAII
;
143 fw_name
= FIRMWARE_MULLINS
;
147 fw_name
= FIRMWARE_TONGA
;
150 fw_name
= FIRMWARE_FIJI
;
153 fw_name
= FIRMWARE_CARRIZO
;
156 fw_name
= FIRMWARE_STONEY
;
159 fw_name
= FIRMWARE_POLARIS10
;
162 fw_name
= FIRMWARE_POLARIS11
;
165 fw_name
= FIRMWARE_VEGA10
;
168 fw_name
= FIRMWARE_POLARIS12
;
174 r
= request_firmware(&adev
->uvd
.fw
, fw_name
, adev
->dev
);
176 dev_err(adev
->dev
, "amdgpu_uvd: Can't load firmware \"%s\"\n",
181 r
= amdgpu_ucode_validate(adev
->uvd
.fw
);
183 dev_err(adev
->dev
, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
185 release_firmware(adev
->uvd
.fw
);
190 /* Set the default UVD handles that the firmware can handle */
191 adev
->uvd
.max_handles
= AMDGPU_DEFAULT_UVD_HANDLES
;
193 hdr
= (const struct common_firmware_header
*)adev
->uvd
.fw
->data
;
194 family_id
= le32_to_cpu(hdr
->ucode_version
) & 0xff;
195 version_major
= (le32_to_cpu(hdr
->ucode_version
) >> 24) & 0xff;
196 version_minor
= (le32_to_cpu(hdr
->ucode_version
) >> 8) & 0xff;
197 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
198 version_major
, version_minor
, family_id
);
201 * Limit the number of UVD handles depending on microcode major
202 * and minor versions. The firmware version which has 40 UVD
203 * instances support is 1.80. So all subsequent versions should
204 * also have the same support.
206 if ((version_major
> 0x01) ||
207 ((version_major
== 0x01) && (version_minor
>= 0x50)))
208 adev
->uvd
.max_handles
= AMDGPU_MAX_UVD_HANDLES
;
210 adev
->uvd
.fw_version
= ((version_major
<< 24) | (version_minor
<< 16) |
213 if ((adev
->asic_type
== CHIP_POLARIS10
||
214 adev
->asic_type
== CHIP_POLARIS11
) &&
215 (adev
->uvd
.fw_version
< FW_1_66_16
))
216 DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n",
217 version_major
, version_minor
);
219 bo_size
= AMDGPU_UVD_STACK_SIZE
+ AMDGPU_UVD_HEAP_SIZE
220 + AMDGPU_UVD_SESSION_SIZE
* adev
->uvd
.max_handles
;
221 if (adev
->firmware
.load_type
!= AMDGPU_FW_LOAD_PSP
)
222 bo_size
+= AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr
->ucode_size_bytes
) + 8);
224 r
= amdgpu_bo_create_kernel(adev
, bo_size
, PAGE_SIZE
,
225 AMDGPU_GEM_DOMAIN_VRAM
, &adev
->uvd
.vcpu_bo
,
226 &adev
->uvd
.gpu_addr
, &adev
->uvd
.cpu_addr
);
228 dev_err(adev
->dev
, "(%d) failed to allocate UVD bo\n", r
);
232 ring
= &adev
->uvd
.ring
;
233 rq
= &ring
->sched
.sched_rq
[AMD_SCHED_PRIORITY_NORMAL
];
234 r
= amd_sched_entity_init(&ring
->sched
, &adev
->uvd
.entity
,
235 rq
, amdgpu_sched_jobs
, NULL
);
237 DRM_ERROR("Failed setting up UVD run queue.\n");
241 for (i
= 0; i
< adev
->uvd
.max_handles
; ++i
) {
242 atomic_set(&adev
->uvd
.handles
[i
], 0);
243 adev
->uvd
.filp
[i
] = NULL
;
246 /* from uvd v5.0 HW addressing capacity increased to 64 bits */
247 if (!amdgpu_ip_block_version_cmp(adev
, AMD_IP_BLOCK_TYPE_UVD
, 5, 0))
248 adev
->uvd
.address_64_bit
= true;
250 switch (adev
->asic_type
) {
252 adev
->uvd
.use_ctx_buf
= adev
->uvd
.fw_version
>= FW_1_65_10
;
255 adev
->uvd
.use_ctx_buf
= adev
->uvd
.fw_version
>= FW_1_87_11
;
258 adev
->uvd
.use_ctx_buf
= adev
->uvd
.fw_version
>= FW_1_87_12
;
261 adev
->uvd
.use_ctx_buf
= adev
->uvd
.fw_version
>= FW_1_37_15
;
264 adev
->uvd
.use_ctx_buf
= adev
->asic_type
>= CHIP_POLARIS10
;
270 int amdgpu_uvd_sw_fini(struct amdgpu_device
*adev
)
273 kfree(adev
->uvd
.saved_bo
);
275 amd_sched_entity_fini(&adev
->uvd
.ring
.sched
, &adev
->uvd
.entity
);
277 amdgpu_bo_free_kernel(&adev
->uvd
.vcpu_bo
,
279 (void **)&adev
->uvd
.cpu_addr
);
281 amdgpu_ring_fini(&adev
->uvd
.ring
);
283 for (i
= 0; i
< AMDGPU_MAX_UVD_ENC_RINGS
; ++i
)
284 amdgpu_ring_fini(&adev
->uvd
.ring_enc
[i
]);
286 release_firmware(adev
->uvd
.fw
);
291 int amdgpu_uvd_suspend(struct amdgpu_device
*adev
)
297 if (adev
->uvd
.vcpu_bo
== NULL
)
300 for (i
= 0; i
< adev
->uvd
.max_handles
; ++i
)
301 if (atomic_read(&adev
->uvd
.handles
[i
]))
304 if (i
== AMDGPU_MAX_UVD_HANDLES
)
307 cancel_delayed_work_sync(&adev
->uvd
.idle_work
);
309 size
= amdgpu_bo_size(adev
->uvd
.vcpu_bo
);
310 ptr
= adev
->uvd
.cpu_addr
;
312 adev
->uvd
.saved_bo
= kmalloc(size
, GFP_KERNEL
);
313 if (!adev
->uvd
.saved_bo
)
316 memcpy_fromio(adev
->uvd
.saved_bo
, ptr
, size
);
321 int amdgpu_uvd_resume(struct amdgpu_device
*adev
)
326 if (adev
->uvd
.vcpu_bo
== NULL
)
329 size
= amdgpu_bo_size(adev
->uvd
.vcpu_bo
);
330 ptr
= adev
->uvd
.cpu_addr
;
332 if (adev
->uvd
.saved_bo
!= NULL
) {
333 memcpy_toio(ptr
, adev
->uvd
.saved_bo
, size
);
334 kfree(adev
->uvd
.saved_bo
);
335 adev
->uvd
.saved_bo
= NULL
;
337 const struct common_firmware_header
*hdr
;
340 hdr
= (const struct common_firmware_header
*)adev
->uvd
.fw
->data
;
341 if (adev
->firmware
.load_type
!= AMDGPU_FW_LOAD_PSP
) {
342 offset
= le32_to_cpu(hdr
->ucode_array_offset_bytes
);
343 memcpy_toio(adev
->uvd
.cpu_addr
, adev
->uvd
.fw
->data
+ offset
,
344 le32_to_cpu(hdr
->ucode_size_bytes
));
345 size
-= le32_to_cpu(hdr
->ucode_size_bytes
);
346 ptr
+= le32_to_cpu(hdr
->ucode_size_bytes
);
348 memset_io(ptr
, 0, size
);
354 void amdgpu_uvd_free_handles(struct amdgpu_device
*adev
, struct drm_file
*filp
)
356 struct amdgpu_ring
*ring
= &adev
->uvd
.ring
;
359 for (i
= 0; i
< adev
->uvd
.max_handles
; ++i
) {
360 uint32_t handle
= atomic_read(&adev
->uvd
.handles
[i
]);
361 if (handle
!= 0 && adev
->uvd
.filp
[i
] == filp
) {
362 struct dma_fence
*fence
;
364 r
= amdgpu_uvd_get_destroy_msg(ring
, handle
,
367 DRM_ERROR("Error destroying UVD (%d)!\n", r
);
371 dma_fence_wait(fence
, false);
372 dma_fence_put(fence
);
374 adev
->uvd
.filp
[i
] = NULL
;
375 atomic_set(&adev
->uvd
.handles
[i
], 0);
380 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo
*abo
)
383 for (i
= 0; i
< abo
->placement
.num_placement
; ++i
) {
384 abo
->placements
[i
].fpfn
= 0 >> PAGE_SHIFT
;
385 abo
->placements
[i
].lpfn
= (256 * 1024 * 1024) >> PAGE_SHIFT
;
389 static u64
amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx
*ctx
)
394 lo
= amdgpu_get_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->data0
);
395 hi
= amdgpu_get_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->data1
);
396 addr
= ((uint64_t)lo
) | (((uint64_t)hi
) << 32);
402 * amdgpu_uvd_cs_pass1 - first parsing round
404 * @ctx: UVD parser context
406 * Make sure UVD message and feedback buffers are in VRAM and
407 * nobody is violating an 256MB boundary.
409 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx
*ctx
)
411 struct amdgpu_bo_va_mapping
*mapping
;
412 struct amdgpu_bo
*bo
;
414 uint64_t addr
= amdgpu_uvd_get_addr_from_ctx(ctx
);
417 r
= amdgpu_cs_find_mapping(ctx
->parser
, addr
, &bo
, &mapping
);
419 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr
);
423 if (!ctx
->parser
->adev
->uvd
.address_64_bit
) {
424 /* check if it's a message or feedback command */
425 cmd
= amdgpu_get_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->idx
) >> 1;
426 if (cmd
== 0x0 || cmd
== 0x3) {
427 /* yes, force it into VRAM */
428 uint32_t domain
= AMDGPU_GEM_DOMAIN_VRAM
;
429 amdgpu_ttm_placement_from_domain(bo
, domain
);
431 amdgpu_uvd_force_into_uvd_segment(bo
);
433 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, false, false);
440 * amdgpu_uvd_cs_msg_decode - handle UVD decode message
442 * @msg: pointer to message structure
443 * @buf_sizes: returned buffer sizes
445 * Peek into the decode message and calculate the necessary buffer sizes.
447 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device
*adev
, uint32_t *msg
,
448 unsigned buf_sizes
[])
450 unsigned stream_type
= msg
[4];
451 unsigned width
= msg
[6];
452 unsigned height
= msg
[7];
453 unsigned dpb_size
= msg
[9];
454 unsigned pitch
= msg
[28];
455 unsigned level
= msg
[57];
457 unsigned width_in_mb
= width
/ 16;
458 unsigned height_in_mb
= ALIGN(height
/ 16, 2);
459 unsigned fs_in_mb
= width_in_mb
* height_in_mb
;
461 unsigned image_size
, tmp
, min_dpb_size
, num_dpb_buffer
;
462 unsigned min_ctx_size
= ~0;
464 image_size
= width
* height
;
465 image_size
+= image_size
/ 2;
466 image_size
= ALIGN(image_size
, 1024);
468 switch (stream_type
) {
472 num_dpb_buffer
= 8100 / fs_in_mb
;
475 num_dpb_buffer
= 18000 / fs_in_mb
;
478 num_dpb_buffer
= 20480 / fs_in_mb
;
481 num_dpb_buffer
= 32768 / fs_in_mb
;
484 num_dpb_buffer
= 34816 / fs_in_mb
;
487 num_dpb_buffer
= 110400 / fs_in_mb
;
490 num_dpb_buffer
= 184320 / fs_in_mb
;
493 num_dpb_buffer
= 184320 / fs_in_mb
;
497 if (num_dpb_buffer
> 17)
500 /* reference picture buffer */
501 min_dpb_size
= image_size
* num_dpb_buffer
;
503 /* macroblock context buffer */
504 min_dpb_size
+= width_in_mb
* height_in_mb
* num_dpb_buffer
* 192;
506 /* IT surface buffer */
507 min_dpb_size
+= width_in_mb
* height_in_mb
* 32;
512 /* reference picture buffer */
513 min_dpb_size
= image_size
* 3;
516 min_dpb_size
+= width_in_mb
* height_in_mb
* 128;
518 /* IT surface buffer */
519 min_dpb_size
+= width_in_mb
* 64;
521 /* DB surface buffer */
522 min_dpb_size
+= width_in_mb
* 128;
525 tmp
= max(width_in_mb
, height_in_mb
);
526 min_dpb_size
+= ALIGN(tmp
* 7 * 16, 64);
531 /* reference picture buffer */
532 min_dpb_size
= image_size
* 3;
537 /* reference picture buffer */
538 min_dpb_size
= image_size
* 3;
541 min_dpb_size
+= width_in_mb
* height_in_mb
* 64;
543 /* IT surface buffer */
544 min_dpb_size
+= ALIGN(width_in_mb
* height_in_mb
* 32, 64);
547 case 7: /* H264 Perf */
550 num_dpb_buffer
= 8100 / fs_in_mb
;
553 num_dpb_buffer
= 18000 / fs_in_mb
;
556 num_dpb_buffer
= 20480 / fs_in_mb
;
559 num_dpb_buffer
= 32768 / fs_in_mb
;
562 num_dpb_buffer
= 34816 / fs_in_mb
;
565 num_dpb_buffer
= 110400 / fs_in_mb
;
568 num_dpb_buffer
= 184320 / fs_in_mb
;
571 num_dpb_buffer
= 184320 / fs_in_mb
;
575 if (num_dpb_buffer
> 17)
578 /* reference picture buffer */
579 min_dpb_size
= image_size
* num_dpb_buffer
;
581 if (!adev
->uvd
.use_ctx_buf
){
582 /* macroblock context buffer */
584 width_in_mb
* height_in_mb
* num_dpb_buffer
* 192;
586 /* IT surface buffer */
587 min_dpb_size
+= width_in_mb
* height_in_mb
* 32;
589 /* macroblock context buffer */
591 width_in_mb
* height_in_mb
* num_dpb_buffer
* 192;
600 image_size
= (ALIGN(width
, 16) * ALIGN(height
, 16) * 3) / 2;
601 image_size
= ALIGN(image_size
, 256);
603 num_dpb_buffer
= (le32_to_cpu(msg
[59]) & 0xff) + 2;
604 min_dpb_size
= image_size
* num_dpb_buffer
;
605 min_ctx_size
= ((width
+ 255) / 16) * ((height
+ 255) / 16)
606 * 16 * num_dpb_buffer
+ 52 * 1024;
610 DRM_ERROR("UVD codec not handled %d!\n", stream_type
);
615 DRM_ERROR("Invalid UVD decoding target pitch!\n");
619 if (dpb_size
< min_dpb_size
) {
620 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
621 dpb_size
, min_dpb_size
);
625 buf_sizes
[0x1] = dpb_size
;
626 buf_sizes
[0x2] = image_size
;
627 buf_sizes
[0x4] = min_ctx_size
;
632 * amdgpu_uvd_cs_msg - handle UVD message
634 * @ctx: UVD parser context
635 * @bo: buffer object containing the message
636 * @offset: offset into the buffer object
638 * Peek into the UVD message and extract the session id.
639 * Make sure that we don't open up to many sessions.
641 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx
*ctx
,
642 struct amdgpu_bo
*bo
, unsigned offset
)
644 struct amdgpu_device
*adev
= ctx
->parser
->adev
;
645 int32_t *msg
, msg_type
, handle
;
651 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
655 r
= amdgpu_bo_kmap(bo
, &ptr
);
657 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r
);
667 DRM_ERROR("Invalid UVD handle!\n");
673 /* it's a create msg, calc image size (width * height) */
674 amdgpu_bo_kunmap(bo
);
676 /* try to alloc a new handle */
677 for (i
= 0; i
< adev
->uvd
.max_handles
; ++i
) {
678 if (atomic_read(&adev
->uvd
.handles
[i
]) == handle
) {
679 DRM_ERROR("Handle 0x%x already in use!\n", handle
);
683 if (!atomic_cmpxchg(&adev
->uvd
.handles
[i
], 0, handle
)) {
684 adev
->uvd
.filp
[i
] = ctx
->parser
->filp
;
689 DRM_ERROR("No more free UVD handles!\n");
693 /* it's a decode msg, calc buffer sizes */
694 r
= amdgpu_uvd_cs_msg_decode(adev
, msg
, ctx
->buf_sizes
);
695 amdgpu_bo_kunmap(bo
);
699 /* validate the handle */
700 for (i
= 0; i
< adev
->uvd
.max_handles
; ++i
) {
701 if (atomic_read(&adev
->uvd
.handles
[i
]) == handle
) {
702 if (adev
->uvd
.filp
[i
] != ctx
->parser
->filp
) {
703 DRM_ERROR("UVD handle collision detected!\n");
710 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle
);
714 /* it's a destroy msg, free the handle */
715 for (i
= 0; i
< adev
->uvd
.max_handles
; ++i
)
716 atomic_cmpxchg(&adev
->uvd
.handles
[i
], handle
, 0);
717 amdgpu_bo_kunmap(bo
);
721 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type
);
729 * amdgpu_uvd_cs_pass2 - second parsing round
731 * @ctx: UVD parser context
733 * Patch buffer addresses, make sure buffer sizes are correct.
735 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx
*ctx
)
737 struct amdgpu_bo_va_mapping
*mapping
;
738 struct amdgpu_bo
*bo
;
741 uint64_t addr
= amdgpu_uvd_get_addr_from_ctx(ctx
);
744 r
= amdgpu_cs_find_mapping(ctx
->parser
, addr
, &bo
, &mapping
);
746 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr
);
750 start
= amdgpu_bo_gpu_offset(bo
);
752 end
= (mapping
->last
+ 1 - mapping
->start
);
753 end
= end
* AMDGPU_GPU_PAGE_SIZE
+ start
;
755 addr
-= mapping
->start
* AMDGPU_GPU_PAGE_SIZE
;
758 amdgpu_set_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->data0
,
759 lower_32_bits(start
));
760 amdgpu_set_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->data1
,
761 upper_32_bits(start
));
763 cmd
= amdgpu_get_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->idx
) >> 1;
765 if ((end
- start
) < ctx
->buf_sizes
[cmd
]) {
766 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd
,
767 (unsigned)(end
- start
),
768 ctx
->buf_sizes
[cmd
]);
772 } else if (cmd
== 0x206) {
773 if ((end
- start
) < ctx
->buf_sizes
[4]) {
774 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd
,
775 (unsigned)(end
- start
),
779 } else if ((cmd
!= 0x100) && (cmd
!= 0x204)) {
780 DRM_ERROR("invalid UVD command %X!\n", cmd
);
784 if (!ctx
->parser
->adev
->uvd
.address_64_bit
) {
785 if ((start
>> 28) != ((end
- 1) >> 28)) {
786 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
791 if ((cmd
== 0 || cmd
== 0x3) &&
792 (start
>> 28) != (ctx
->parser
->adev
->uvd
.gpu_addr
>> 28)) {
793 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
800 ctx
->has_msg_cmd
= true;
801 r
= amdgpu_uvd_cs_msg(ctx
, bo
, addr
);
804 } else if (!ctx
->has_msg_cmd
) {
805 DRM_ERROR("Message needed before other commands are send!\n");
813 * amdgpu_uvd_cs_reg - parse register writes
815 * @ctx: UVD parser context
816 * @cb: callback function
818 * Parse the register writes, call cb on each complete command.
820 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx
*ctx
,
821 int (*cb
)(struct amdgpu_uvd_cs_ctx
*ctx
))
823 struct amdgpu_ib
*ib
= &ctx
->parser
->job
->ibs
[ctx
->ib_idx
];
827 for (i
= 0; i
<= ctx
->count
; ++i
) {
828 unsigned reg
= ctx
->reg
+ i
;
830 if (ctx
->idx
>= ib
->length_dw
) {
831 DRM_ERROR("Register command after end of CS!\n");
836 case mmUVD_GPCOM_VCPU_DATA0
:
837 ctx
->data0
= ctx
->idx
;
839 case mmUVD_GPCOM_VCPU_DATA1
:
840 ctx
->data1
= ctx
->idx
;
842 case mmUVD_GPCOM_VCPU_CMD
:
847 case mmUVD_ENGINE_CNTL
:
851 DRM_ERROR("Invalid reg 0x%X!\n", reg
);
860 * amdgpu_uvd_cs_packets - parse UVD packets
862 * @ctx: UVD parser context
863 * @cb: callback function
865 * Parse the command stream packets.
867 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx
*ctx
,
868 int (*cb
)(struct amdgpu_uvd_cs_ctx
*ctx
))
870 struct amdgpu_ib
*ib
= &ctx
->parser
->job
->ibs
[ctx
->ib_idx
];
873 for (ctx
->idx
= 0 ; ctx
->idx
< ib
->length_dw
; ) {
874 uint32_t cmd
= amdgpu_get_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->idx
);
875 unsigned type
= CP_PACKET_GET_TYPE(cmd
);
878 ctx
->reg
= CP_PACKET0_GET_REG(cmd
);
879 ctx
->count
= CP_PACKET_GET_COUNT(cmd
);
880 r
= amdgpu_uvd_cs_reg(ctx
, cb
);
888 DRM_ERROR("Unknown packet type %d !\n", type
);
896 * amdgpu_uvd_ring_parse_cs - UVD command submission parser
898 * @parser: Command submission parser context
900 * Parse the command stream, patch in addresses as necessary.
902 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser
*parser
, uint32_t ib_idx
)
904 struct amdgpu_uvd_cs_ctx ctx
= {};
905 unsigned buf_sizes
[] = {
907 [0x00000001] = 0xFFFFFFFF,
908 [0x00000002] = 0xFFFFFFFF,
910 [0x00000004] = 0xFFFFFFFF,
912 struct amdgpu_ib
*ib
= &parser
->job
->ibs
[ib_idx
];
915 parser
->job
->vm
= NULL
;
916 ib
->gpu_addr
= amdgpu_sa_bo_gpu_addr(ib
->sa_bo
);
918 if (ib
->length_dw
% 16) {
919 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
925 ctx
.buf_sizes
= buf_sizes
;
928 /* first round only required on chips without UVD 64 bit address support */
929 if (!parser
->adev
->uvd
.address_64_bit
) {
930 /* first round, make sure the buffers are actually in the UVD segment */
931 r
= amdgpu_uvd_cs_packets(&ctx
, amdgpu_uvd_cs_pass1
);
936 /* second round, patch buffer addresses into the command stream */
937 r
= amdgpu_uvd_cs_packets(&ctx
, amdgpu_uvd_cs_pass2
);
941 if (!ctx
.has_msg_cmd
) {
942 DRM_ERROR("UVD-IBs need a msg command!\n");
949 static int amdgpu_uvd_send_msg(struct amdgpu_ring
*ring
, struct amdgpu_bo
*bo
,
950 bool direct
, struct dma_fence
**fence
)
952 struct ttm_validate_buffer tv
;
953 struct ww_acquire_ctx ticket
;
954 struct list_head head
;
955 struct amdgpu_job
*job
;
956 struct amdgpu_ib
*ib
;
957 struct dma_fence
*f
= NULL
;
958 struct amdgpu_device
*adev
= ring
->adev
;
963 memset(&tv
, 0, sizeof(tv
));
966 INIT_LIST_HEAD(&head
);
967 list_add(&tv
.head
, &head
);
969 r
= ttm_eu_reserve_buffers(&ticket
, &head
, true, NULL
);
973 if (!ring
->adev
->uvd
.address_64_bit
) {
974 amdgpu_ttm_placement_from_domain(bo
, AMDGPU_GEM_DOMAIN_VRAM
);
975 amdgpu_uvd_force_into_uvd_segment(bo
);
978 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, true, false);
982 r
= amdgpu_job_alloc_with_ib(adev
, 64, &job
);
986 if (adev
->asic_type
>= CHIP_VEGA10
) {
987 data
[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0_VEGA10
, 0);
988 data
[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1_VEGA10
, 0);
989 data
[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD_VEGA10
, 0);
990 data
[3] = PACKET0(mmUVD_NO_OP_VEGA10
, 0);
992 data
[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0
, 0);
993 data
[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1
, 0);
994 data
[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD
, 0);
995 data
[3] = PACKET0(mmUVD_NO_OP
, 0);
999 addr
= amdgpu_bo_gpu_offset(bo
);
1000 ib
->ptr
[0] = data
[0];
1002 ib
->ptr
[2] = data
[1];
1003 ib
->ptr
[3] = addr
>> 32;
1004 ib
->ptr
[4] = data
[2];
1006 for (i
= 6; i
< 16; i
+= 2) {
1007 ib
->ptr
[i
] = data
[3];
1013 r
= amdgpu_ib_schedule(ring
, 1, ib
, NULL
, &f
);
1014 job
->fence
= dma_fence_get(f
);
1018 amdgpu_job_free(job
);
1020 r
= amdgpu_job_submit(job
, ring
, &adev
->uvd
.entity
,
1021 AMDGPU_FENCE_OWNER_UNDEFINED
, &f
);
1026 ttm_eu_fence_buffer_objects(&ticket
, &head
, f
);
1029 *fence
= dma_fence_get(f
);
1030 amdgpu_bo_unref(&bo
);
1036 amdgpu_job_free(job
);
1039 ttm_eu_backoff_reservation(&ticket
, &head
);
1043 /* multiple fence commands without any stream commands in between can
1044 crash the vcpu so just try to emmit a dummy create/destroy msg to
1046 int amdgpu_uvd_get_create_msg(struct amdgpu_ring
*ring
, uint32_t handle
,
1047 struct dma_fence
**fence
)
1049 struct amdgpu_device
*adev
= ring
->adev
;
1050 struct amdgpu_bo
*bo
;
1054 r
= amdgpu_bo_create(adev
, 1024, PAGE_SIZE
, true,
1055 AMDGPU_GEM_DOMAIN_VRAM
,
1056 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
|
1057 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
,
1058 NULL
, NULL
, 0, &bo
);
1062 r
= amdgpu_bo_reserve(bo
, false);
1064 amdgpu_bo_unref(&bo
);
1068 r
= amdgpu_bo_kmap(bo
, (void **)&msg
);
1070 amdgpu_bo_unreserve(bo
);
1071 amdgpu_bo_unref(&bo
);
1075 /* stitch together an UVD create msg */
1076 msg
[0] = cpu_to_le32(0x00000de4);
1077 msg
[1] = cpu_to_le32(0x00000000);
1078 msg
[2] = cpu_to_le32(handle
);
1079 msg
[3] = cpu_to_le32(0x00000000);
1080 msg
[4] = cpu_to_le32(0x00000000);
1081 msg
[5] = cpu_to_le32(0x00000000);
1082 msg
[6] = cpu_to_le32(0x00000000);
1083 msg
[7] = cpu_to_le32(0x00000780);
1084 msg
[8] = cpu_to_le32(0x00000440);
1085 msg
[9] = cpu_to_le32(0x00000000);
1086 msg
[10] = cpu_to_le32(0x01b37000);
1087 for (i
= 11; i
< 1024; ++i
)
1088 msg
[i
] = cpu_to_le32(0x0);
1090 amdgpu_bo_kunmap(bo
);
1091 amdgpu_bo_unreserve(bo
);
1093 return amdgpu_uvd_send_msg(ring
, bo
, true, fence
);
1096 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring
*ring
, uint32_t handle
,
1097 bool direct
, struct dma_fence
**fence
)
1099 struct amdgpu_device
*adev
= ring
->adev
;
1100 struct amdgpu_bo
*bo
;
1104 r
= amdgpu_bo_create(adev
, 1024, PAGE_SIZE
, true,
1105 AMDGPU_GEM_DOMAIN_VRAM
,
1106 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
|
1107 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
,
1108 NULL
, NULL
, 0, &bo
);
1112 r
= amdgpu_bo_reserve(bo
, false);
1114 amdgpu_bo_unref(&bo
);
1118 r
= amdgpu_bo_kmap(bo
, (void **)&msg
);
1120 amdgpu_bo_unreserve(bo
);
1121 amdgpu_bo_unref(&bo
);
1125 /* stitch together an UVD destroy msg */
1126 msg
[0] = cpu_to_le32(0x00000de4);
1127 msg
[1] = cpu_to_le32(0x00000002);
1128 msg
[2] = cpu_to_le32(handle
);
1129 msg
[3] = cpu_to_le32(0x00000000);
1130 for (i
= 4; i
< 1024; ++i
)
1131 msg
[i
] = cpu_to_le32(0x0);
1133 amdgpu_bo_kunmap(bo
);
1134 amdgpu_bo_unreserve(bo
);
1136 return amdgpu_uvd_send_msg(ring
, bo
, direct
, fence
);
1139 static void amdgpu_uvd_idle_work_handler(struct work_struct
*work
)
1141 struct amdgpu_device
*adev
=
1142 container_of(work
, struct amdgpu_device
, uvd
.idle_work
.work
);
1143 unsigned fences
= amdgpu_fence_count_emitted(&adev
->uvd
.ring
);
1145 if (amdgpu_sriov_vf(adev
))
1149 if (adev
->pm
.dpm_enabled
) {
1150 amdgpu_dpm_enable_uvd(adev
, false);
1152 amdgpu_asic_set_uvd_clocks(adev
, 0, 0);
1153 /* shutdown the UVD block */
1154 amdgpu_set_powergating_state(adev
, AMD_IP_BLOCK_TYPE_UVD
,
1156 amdgpu_set_clockgating_state(adev
, AMD_IP_BLOCK_TYPE_UVD
,
1160 schedule_delayed_work(&adev
->uvd
.idle_work
, UVD_IDLE_TIMEOUT
);
1164 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring
*ring
)
1166 struct amdgpu_device
*adev
= ring
->adev
;
1167 bool set_clocks
= !cancel_delayed_work_sync(&adev
->uvd
.idle_work
);
1169 if (amdgpu_sriov_vf(adev
))
1173 if (adev
->pm
.dpm_enabled
) {
1174 amdgpu_dpm_enable_uvd(adev
, true);
1176 amdgpu_asic_set_uvd_clocks(adev
, 53300, 40000);
1177 amdgpu_set_clockgating_state(adev
, AMD_IP_BLOCK_TYPE_UVD
,
1178 AMD_CG_STATE_UNGATE
);
1179 amdgpu_set_powergating_state(adev
, AMD_IP_BLOCK_TYPE_UVD
,
1180 AMD_PG_STATE_UNGATE
);
1185 void amdgpu_uvd_ring_end_use(struct amdgpu_ring
*ring
)
1187 schedule_delayed_work(&ring
->adev
->uvd
.idle_work
, UVD_IDLE_TIMEOUT
);
1191 * amdgpu_uvd_ring_test_ib - test ib execution
1193 * @ring: amdgpu_ring pointer
1195 * Test if we can successfully execute an IB
1197 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring
*ring
, long timeout
)
1199 struct dma_fence
*fence
;
1202 r
= amdgpu_uvd_get_create_msg(ring
, 1, NULL
);
1204 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r
);
1208 r
= amdgpu_uvd_get_destroy_msg(ring
, 1, true, &fence
);
1210 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r
);
1214 r
= dma_fence_wait_timeout(fence
, false, timeout
);
1216 DRM_ERROR("amdgpu: IB test timed out.\n");
1219 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r
);
1221 DRM_INFO("ib test on ring %d succeeded\n", ring
->idx
);
1225 dma_fence_put(fence
);
1232 * amdgpu_uvd_used_handles - returns used UVD handles
1234 * @adev: amdgpu_device pointer
1236 * Returns the number of UVD handles in use
1238 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device
*adev
)
1241 uint32_t used_handles
= 0;
1243 for (i
= 0; i
< adev
->uvd
.max_handles
; ++i
) {
1245 * Handles can be freed in any order, and not
1246 * necessarily linear. So we need to count
1247 * all non-zero handles.
1249 if (atomic_read(&adev
->uvd
.handles
[i
]))
1253 return used_handles
;