drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #define MAX_KIQ_REG_WAIT        100000000 /* in usecs */
  26
  27 int amdgpu_allocate_static_csa(struct amdgpu_device *adev)
  28 {
  29         int r;
  30         void *ptr;
  31
  32         r = amdgpu_bo_create_kernel(adev, AMDGPU_CSA_SIZE, PAGE_SIZE,
  33                                 AMDGPU_GEM_DOMAIN_VRAM, &adev->virt.csa_obj,
  34                                 &adev->virt.csa_vmid0_addr, &ptr);
  35         if (r)
  36                 return r;
  37
  38         memset(ptr, 0, AMDGPU_CSA_SIZE);
  39         return 0;
  40 }
  41
  42 /*
  43  * amdgpu_map_static_csa should be called during amdgpu_vm_init
  44  * it maps virtual address "AMDGPU_VA_RESERVED_SIZE - AMDGPU_CSA_SIZE"
  45  * to this VM, and each command submission of GFX should use this virtual
  46  * address within META_DATA init package to support SRIOV gfx preemption.
  47  */
  48
  49 int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
  50                           struct amdgpu_bo_va **bo_va)
  51 {
  52         struct ww_acquire_ctx ticket;
  53         struct list_head list;
  54         struct amdgpu_bo_list_entry pd;
  55         struct ttm_validate_buffer csa_tv;
  56         int r;
  57
  58         INIT_LIST_HEAD(&list);
  59         INIT_LIST_HEAD(&csa_tv.head);
  60         csa_tv.bo = &adev->virt.csa_obj->tbo;
  61         csa_tv.shared = true;
  62
  63         list_add(&csa_tv.head, &list);
  64         amdgpu_vm_get_pd_bo(vm, &list, &pd);
  65
  66         r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
  67         if (r) {
  68                 DRM_ERROR("failed to reserve CSA,PD BOs: err=%d\n", r);
  69                 return r;
  70         }
  71
  72         *bo_va = amdgpu_vm_bo_add(adev, vm, adev->virt.csa_obj);
  73         if (!*bo_va) {
  74                 ttm_eu_backoff_reservation(&ticket, &list);
  75                 DRM_ERROR("failed to create bo_va for static CSA\n");
  76                 return -ENOMEM;
  77         }
  78
  79         r = amdgpu_vm_alloc_pts(adev, (*bo_va)->base.vm, AMDGPU_CSA_VADDR,
  80                                 AMDGPU_CSA_SIZE);
  81         if (r) {
  82                 DRM_ERROR("failed to allocate pts for static CSA, err=%d\n", r);
  83                 amdgpu_vm_bo_rmv(adev, *bo_va);
  84                 ttm_eu_backoff_reservation(&ticket, &list);
  85                 return r;
  86         }
  87
  88         r = amdgpu_vm_bo_map(adev, *bo_va, AMDGPU_CSA_VADDR, 0, AMDGPU_CSA_SIZE,
  89                              AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE |
  90                              AMDGPU_PTE_EXECUTABLE);
  91
  92         if (r) {
  93                 DRM_ERROR("failed to do bo_map on static CSA, err=%d\n", r);
  94                 amdgpu_vm_bo_rmv(adev, *bo_va);
  95                 ttm_eu_backoff_reservation(&ticket, &list);
  96                 return r;
  97         }
  98
  99         ttm_eu_backoff_reservation(&ticket, &list);
 100         return 0;
 101 }
 102
 103 void amdgpu_virt_init_setting(struct amdgpu_device *adev)
 104 {
 105         /* enable virtual display */
 106         adev->mode_info.num_crtc = 1;
 107         adev->enable_virtual_display = true;
 108         adev->cg_flags = 0;
 109         adev->pg_flags = 0;
 110
 111         mutex_init(&adev->virt.lock_reset);
 112 }
 113
 114 uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
 115 {
 116         signed long r;
 117         uint32_t val, seq;
 118         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 119         struct amdgpu_ring *ring = &kiq->ring;
 120
 121         BUG_ON(!ring->funcs->emit_rreg);
 122
 123         spin_lock(&kiq->ring_lock);
 124         amdgpu_ring_alloc(ring, 32);
 125         amdgpu_ring_emit_rreg(ring, reg);
 126         amdgpu_fence_emit_polling(ring, &seq);
 127         amdgpu_ring_commit(ring);
 128         spin_unlock(&kiq->ring_lock);
 129
 130         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 131         if (r < 1) {
 132                 DRM_ERROR("wait for kiq fence error: %ld\n", r);
 133                 return ~0;
 134         }
 135         val = adev->wb.wb[adev->virt.reg_val_offs];
 136
 137         return val;
 138 }
 139
 140 void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 141 {
 142         signed long r;
 143         uint32_t seq;
 144         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 145         struct amdgpu_ring *ring = &kiq->ring;
 146
 147         BUG_ON(!ring->funcs->emit_wreg);
 148
 149         spin_lock(&kiq->ring_lock);
 150         amdgpu_ring_alloc(ring, 32);
 151         amdgpu_ring_emit_wreg(ring, reg, v);
 152         amdgpu_fence_emit_polling(ring, &seq);
 153         amdgpu_ring_commit(ring);
 154         spin_unlock(&kiq->ring_lock);
 155
 156         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 157         if (r < 1)
 158                 DRM_ERROR("wait for kiq fence error: %ld\n", r);
 159 }
 160
 161 /**
 162  * amdgpu_virt_request_full_gpu() - request full gpu access
 163  * @amdgpu:     amdgpu device.
 164  * @init:       is driver init time.
 165  * When start to init/fini driver, first need to request full gpu access.
 166  * Return: Zero if request success, otherwise will return error.
 167  */
 168 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init)
 169 {
 170         struct amdgpu_virt *virt = &adev->virt;
 171         int r;
 172
 173         if (virt->ops && virt->ops->req_full_gpu) {
 174                 r = virt->ops->req_full_gpu(adev, init);
 175                 if (r)
 176                         return r;
 177
 178                 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
 179         }
 180
 181         return 0;
 182 }
 183
 184 /**
 185  * amdgpu_virt_release_full_gpu() - release full gpu access
 186  * @amdgpu:     amdgpu device.
 187  * @init:       is driver init time.
 188  * When finishing driver init/fini, need to release full gpu access.
 189  * Return: Zero if release success, otherwise will returen error.
 190  */
 191 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init)
 192 {
 193         struct amdgpu_virt *virt = &adev->virt;
 194         int r;
 195
 196         if (virt->ops && virt->ops->rel_full_gpu) {
 197                 r = virt->ops->rel_full_gpu(adev, init);
 198                 if (r)
 199                         return r;
 200
 201                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
 202         }
 203         return 0;
 204 }
 205
 206 /**
 207  * amdgpu_virt_reset_gpu() - reset gpu
 208  * @amdgpu:     amdgpu device.
 209  * Send reset command to GPU hypervisor to reset GPU that VM is using
 210  * Return: Zero if reset success, otherwise will return error.
 211  */
 212 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev)
 213 {
 214         struct amdgpu_virt *virt = &adev->virt;
 215         int r;
 216
 217         if (virt->ops && virt->ops->reset_gpu) {
 218                 r = virt->ops->reset_gpu(adev);
 219                 if (r)
 220                         return r;
 221
 222                 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
 223         }
 224
 225         return 0;
 226 }
 227
 228 /**
 229  * amdgpu_virt_alloc_mm_table() - alloc memory for mm table
 230  * @amdgpu:     amdgpu device.
 231  * MM table is used by UVD and VCE for its initialization
 232  * Return: Zero if allocate success.
 233  */
 234 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev)
 235 {
 236         int r;
 237
 238         if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr)
 239                 return 0;
 240
 241         r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
 242                                     AMDGPU_GEM_DOMAIN_VRAM,
 243                                     &adev->virt.mm_table.bo,
 244                                     &adev->virt.mm_table.gpu_addr,
 245                                     (void *)&adev->virt.mm_table.cpu_addr);
 246         if (r) {
 247                 DRM_ERROR("failed to alloc mm table and error = %d.\n", r);
 248                 return r;
 249         }
 250
 251         memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE);
 252         DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n",
 253                  adev->virt.mm_table.gpu_addr,
 254                  adev->virt.mm_table.cpu_addr);
 255         return 0;
 256 }
 257
 258 /**
 259  * amdgpu_virt_free_mm_table() - free mm table memory
 260  * @amdgpu:     amdgpu device.
 261  * Free MM table memory
 262  */
 263 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev)
 264 {
 265         if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr)
 266                 return;
 267
 268         amdgpu_bo_free_kernel(&adev->virt.mm_table.bo,
 269                               &adev->virt.mm_table.gpu_addr,
 270                               (void *)&adev->virt.mm_table.cpu_addr);
 271         adev->virt.mm_table.gpu_addr = 0;
 272 }
 273
 274
 275 int amdgpu_virt_fw_reserve_get_checksum(void *obj,
 276                                         unsigned long obj_size,
 277                                         unsigned int key,
 278                                         unsigned int chksum)
 279 {
 280         unsigned int ret = key;
 281         unsigned long i = 0;
 282         unsigned char *pos;
 283
 284         pos = (char *)obj;
 285         /* calculate checksum */
 286         for (i = 0; i < obj_size; ++i)
 287                 ret += *(pos + i);
 288         /* minus the chksum itself */
 289         pos = (char *)&chksum;
 290         for (i = 0; i < sizeof(chksum); ++i)
 291                 ret -= *(pos + i);
 292         return ret;
 293 }
 294
 295 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
 296 {
 297         uint32_t pf2vf_ver = 0;
 298         uint32_t pf2vf_size = 0;
 299         uint32_t checksum = 0;
 300         uint32_t checkval;
 301         char *str;
 302
 303         adev->virt.fw_reserve.p_pf2vf = NULL;
 304         adev->virt.fw_reserve.p_vf2pf = NULL;
 305
 306         if (adev->fw_vram_usage.va != NULL) {
 307                 adev->virt.fw_reserve.p_pf2vf =
 308                         (struct amdgim_pf2vf_info_header *)(
 309                         adev->fw_vram_usage.va + AMDGIM_DATAEXCHANGE_OFFSET);
 310                 pf2vf_ver = adev->virt.fw_reserve.p_pf2vf->version;
 311                 AMDGPU_FW_VRAM_PF2VF_READ(adev, header.size, &pf2vf_size);
 312                 AMDGPU_FW_VRAM_PF2VF_READ(adev, checksum, &checksum);
 313
 314                 /* pf2vf message must be in 4K */
 315                 if (pf2vf_size > 0 && pf2vf_size < 4096) {
 316                         checkval = amdgpu_virt_fw_reserve_get_checksum(
 317                                 adev->virt.fw_reserve.p_pf2vf, pf2vf_size,
 318                                 adev->virt.fw_reserve.checksum_key, checksum);
 319                         if (checkval == checksum) {
 320                                 adev->virt.fw_reserve.p_vf2pf =
 321                                         ((void *)adev->virt.fw_reserve.p_pf2vf +
 322                                         pf2vf_size);
 323                                 memset((void *)adev->virt.fw_reserve.p_vf2pf, 0,
 324                                         sizeof(amdgim_vf2pf_info));
 325                                 AMDGPU_FW_VRAM_VF2PF_WRITE(adev, header.version,
 326                                         AMDGPU_FW_VRAM_VF2PF_VER);
 327                                 AMDGPU_FW_VRAM_VF2PF_WRITE(adev, header.size,
 328                                         sizeof(amdgim_vf2pf_info));
 329                                 AMDGPU_FW_VRAM_VF2PF_READ(adev, driver_version,
 330                                         &str);
 331                                 if (THIS_MODULE->version != NULL)
 332                                         strcpy(str, THIS_MODULE->version);
 333                                 else
 334                                         strcpy(str, "N/A");
 335                                 AMDGPU_FW_VRAM_VF2PF_WRITE(adev, driver_cert,
 336                                         0);
 337                                 AMDGPU_FW_VRAM_VF2PF_WRITE(adev, checksum,
 338                                         amdgpu_virt_fw_reserve_get_checksum(
 339                                         adev->virt.fw_reserve.p_vf2pf,
 340                                         pf2vf_size,
 341                                         adev->virt.fw_reserve.checksum_key, 0));
 342                         }
 343                 }
 344         }
 345 }
 346
 347