2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/dma-fence-array.h>
29 #include <linux/interval_tree_generic.h>
30 #include <linux/idr.h>
32 #include <drm/amdgpu_drm.h>
34 #include "amdgpu_trace.h"
35 #include "amdgpu_amdkfd.h"
36 #include "amdgpu_gmc.h"
41 * GPUVM is similar to the legacy gart on older asics, however
42 * rather than there being a single global gart table
43 * for the entire GPU, there are multiple VM page tables active
44 * at any given time. The VM page tables can contain a mix
45 * vram pages and system memory pages and system memory pages
46 * can be mapped as snooped (cached system pages) or unsnooped
47 * (uncached system pages).
48 * Each VM has an ID associated with it and there is a page table
49 * associated with each VMID. When execting a command buffer,
50 * the kernel tells the the ring what VMID to use for that command
51 * buffer. VMIDs are allocated dynamically as commands are submitted.
52 * The userspace drivers maintain their own address space and the kernel
53 * sets up their pages tables accordingly when they submit their
54 * command buffers and a VMID is assigned.
55 * Cayman/Trinity support up to 8 active VMs at any given time;
59 #define START(node) ((node)->start)
60 #define LAST(node) ((node)->last)
62 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping
, rb
, uint64_t, __subtree_last
,
63 START
, LAST
, static, amdgpu_vm_it
)
69 * struct amdgpu_pte_update_params - Local structure
71 * Encapsulate some VM table update parameters to reduce
72 * the number of function parameters
75 struct amdgpu_pte_update_params
{
78 * @adev: amdgpu device we do this update for
80 struct amdgpu_device
*adev
;
83 * @vm: optional amdgpu_vm we do this update for
88 * @src: address where to copy page table entries from
93 * @ib: indirect buffer to fill with commands
98 * @func: Function which actually does the update
100 void (*func
)(struct amdgpu_pte_update_params
*params
,
101 struct amdgpu_bo
*bo
, uint64_t pe
,
102 uint64_t addr
, unsigned count
, uint32_t incr
,
107 * DMA addresses to use for mapping, used during VM update by CPU
109 dma_addr_t
*pages_addr
;
113 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
115 struct amdgpu_prt_cb
{
118 * @adev: amdgpu device
120 struct amdgpu_device
*adev
;
125 struct dma_fence_cb cb
;
129 * amdgpu_vm_level_shift - return the addr shift for each level
131 * @adev: amdgpu_device pointer
135 * The number of bits the pfn needs to be right shifted for a level.
137 static unsigned amdgpu_vm_level_shift(struct amdgpu_device
*adev
,
140 unsigned shift
= 0xff;
146 shift
= 9 * (AMDGPU_VM_PDB0
- level
) +
147 adev
->vm_manager
.block_size
;
153 dev_err(adev
->dev
, "the level%d isn't supported.\n", level
);
160 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
162 * @adev: amdgpu_device pointer
166 * The number of entries in a page directory or page table.
168 static unsigned amdgpu_vm_num_entries(struct amdgpu_device
*adev
,
171 unsigned shift
= amdgpu_vm_level_shift(adev
,
172 adev
->vm_manager
.root_level
);
174 if (level
== adev
->vm_manager
.root_level
)
175 /* For the root directory */
176 return round_up(adev
->vm_manager
.max_pfn
, 1ULL << shift
) >> shift
;
177 else if (level
!= AMDGPU_VM_PTB
)
178 /* Everything in between */
181 /* For the page tables on the leaves */
182 return AMDGPU_VM_PTE_COUNT(adev
);
186 * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
188 * @adev: amdgpu_device pointer
192 * The mask to extract the entry number of a PD/PT from an address.
194 static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device
*adev
,
197 if (level
<= adev
->vm_manager
.root_level
)
199 else if (level
!= AMDGPU_VM_PTB
)
202 return AMDGPU_VM_PTE_COUNT(adev
) - 1;
206 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
208 * @adev: amdgpu_device pointer
212 * The size of the BO for a page directory or page table in bytes.
214 static unsigned amdgpu_vm_bo_size(struct amdgpu_device
*adev
, unsigned level
)
216 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev
, level
) * 8);
220 * amdgpu_vm_bo_evicted - vm_bo is evicted
222 * @vm_bo: vm_bo which is evicted
224 * State for PDs/PTs and per VM BOs which are not at the location they should
227 static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base
*vm_bo
)
229 struct amdgpu_vm
*vm
= vm_bo
->vm
;
230 struct amdgpu_bo
*bo
= vm_bo
->bo
;
233 if (bo
->tbo
.type
== ttm_bo_type_kernel
)
234 list_move(&vm_bo
->vm_status
, &vm
->evicted
);
236 list_move_tail(&vm_bo
->vm_status
, &vm
->evicted
);
240 * amdgpu_vm_bo_relocated - vm_bo is reloacted
242 * @vm_bo: vm_bo which is relocated
244 * State for PDs/PTs which needs to update their parent PD.
246 static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base
*vm_bo
)
248 list_move(&vm_bo
->vm_status
, &vm_bo
->vm
->relocated
);
252 * amdgpu_vm_bo_moved - vm_bo is moved
254 * @vm_bo: vm_bo which is moved
256 * State for per VM BOs which are moved, but that change is not yet reflected
257 * in the page tables.
259 static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base
*vm_bo
)
261 list_move(&vm_bo
->vm_status
, &vm_bo
->vm
->moved
);
265 * amdgpu_vm_bo_idle - vm_bo is idle
267 * @vm_bo: vm_bo which is now idle
269 * State for PDs/PTs and per VM BOs which have gone through the state machine
272 static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base
*vm_bo
)
274 list_move(&vm_bo
->vm_status
, &vm_bo
->vm
->idle
);
275 vm_bo
->moved
= false;
279 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
281 * @vm_bo: vm_bo which is now invalidated
283 * State for normal BOs which are invalidated and that change not yet reflected
286 static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base
*vm_bo
)
288 spin_lock(&vm_bo
->vm
->invalidated_lock
);
289 list_move(&vm_bo
->vm_status
, &vm_bo
->vm
->invalidated
);
290 spin_unlock(&vm_bo
->vm
->invalidated_lock
);
294 * amdgpu_vm_bo_done - vm_bo is done
296 * @vm_bo: vm_bo which is now done
298 * State for normal BOs which are invalidated and that change has been updated
301 static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base
*vm_bo
)
303 spin_lock(&vm_bo
->vm
->invalidated_lock
);
304 list_del_init(&vm_bo
->vm_status
);
305 spin_unlock(&vm_bo
->vm
->invalidated_lock
);
309 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
311 * @base: base structure for tracking BO usage in a VM
312 * @vm: vm to which bo is to be added
313 * @bo: amdgpu buffer object
315 * Initialize a bo_va_base structure and add it to the appropriate lists
318 static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base
*base
,
319 struct amdgpu_vm
*vm
,
320 struct amdgpu_bo
*bo
)
325 INIT_LIST_HEAD(&base
->vm_status
);
329 base
->next
= bo
->vm_bo
;
332 if (bo
->tbo
.resv
!= vm
->root
.base
.bo
->tbo
.resv
)
335 vm
->bulk_moveable
= false;
336 if (bo
->tbo
.type
== ttm_bo_type_kernel
)
337 amdgpu_vm_bo_relocated(base
);
339 amdgpu_vm_bo_idle(base
);
341 if (bo
->preferred_domains
&
342 amdgpu_mem_type_to_domain(bo
->tbo
.mem
.mem_type
))
346 * we checked all the prerequisites, but it looks like this per vm bo
347 * is currently evicted. add the bo to the evicted list to make sure it
348 * is validated on next vm use to avoid fault.
350 amdgpu_vm_bo_evicted(base
);
354 * amdgpu_vm_pt_parent - get the parent page directory
356 * @pt: child page table
358 * Helper to get the parent entry for the child page table. NULL if we are at
359 * the root page directory.
361 static struct amdgpu_vm_pt
*amdgpu_vm_pt_parent(struct amdgpu_vm_pt
*pt
)
363 struct amdgpu_bo
*parent
= pt
->base
.bo
->parent
;
368 return container_of(parent
->vm_bo
, struct amdgpu_vm_pt
, base
);
372 * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
374 struct amdgpu_vm_pt_cursor
{
376 struct amdgpu_vm_pt
*parent
;
377 struct amdgpu_vm_pt
*entry
;
382 * amdgpu_vm_pt_start - start PD/PT walk
384 * @adev: amdgpu_device pointer
385 * @vm: amdgpu_vm structure
386 * @start: start address of the walk
387 * @cursor: state to initialize
389 * Initialize a amdgpu_vm_pt_cursor to start a walk.
391 static void amdgpu_vm_pt_start(struct amdgpu_device
*adev
,
392 struct amdgpu_vm
*vm
, uint64_t start
,
393 struct amdgpu_vm_pt_cursor
*cursor
)
396 cursor
->parent
= NULL
;
397 cursor
->entry
= &vm
->root
;
398 cursor
->level
= adev
->vm_manager
.root_level
;
402 * amdgpu_vm_pt_descendant - go to child node
404 * @adev: amdgpu_device pointer
405 * @cursor: current state
407 * Walk to the child node of the current node.
409 * True if the walk was possible, false otherwise.
411 static bool amdgpu_vm_pt_descendant(struct amdgpu_device
*adev
,
412 struct amdgpu_vm_pt_cursor
*cursor
)
414 unsigned mask
, shift
, idx
;
416 if (!cursor
->entry
->entries
)
419 BUG_ON(!cursor
->entry
->base
.bo
);
420 mask
= amdgpu_vm_entries_mask(adev
, cursor
->level
);
421 shift
= amdgpu_vm_level_shift(adev
, cursor
->level
);
424 idx
= (cursor
->pfn
>> shift
) & mask
;
425 cursor
->parent
= cursor
->entry
;
426 cursor
->entry
= &cursor
->entry
->entries
[idx
];
431 * amdgpu_vm_pt_sibling - go to sibling node
433 * @adev: amdgpu_device pointer
434 * @cursor: current state
436 * Walk to the sibling node of the current node.
438 * True if the walk was possible, false otherwise.
440 static bool amdgpu_vm_pt_sibling(struct amdgpu_device
*adev
,
441 struct amdgpu_vm_pt_cursor
*cursor
)
443 unsigned shift
, num_entries
;
445 /* Root doesn't have a sibling */
449 /* Go to our parents and see if we got a sibling */
450 shift
= amdgpu_vm_level_shift(adev
, cursor
->level
- 1);
451 num_entries
= amdgpu_vm_num_entries(adev
, cursor
->level
- 1);
453 if (cursor
->entry
== &cursor
->parent
->entries
[num_entries
- 1])
456 cursor
->pfn
+= 1ULL << shift
;
457 cursor
->pfn
&= ~((1ULL << shift
) - 1);
463 * amdgpu_vm_pt_ancestor - go to parent node
465 * @cursor: current state
467 * Walk to the parent node of the current node.
469 * True if the walk was possible, false otherwise.
471 static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor
*cursor
)
477 cursor
->entry
= cursor
->parent
;
478 cursor
->parent
= amdgpu_vm_pt_parent(cursor
->parent
);
483 * amdgpu_vm_pt_next - get next PD/PT in hieratchy
485 * @adev: amdgpu_device pointer
486 * @cursor: current state
488 * Walk the PD/PT tree to the next node.
490 static void amdgpu_vm_pt_next(struct amdgpu_device
*adev
,
491 struct amdgpu_vm_pt_cursor
*cursor
)
493 /* First try a newborn child */
494 if (amdgpu_vm_pt_descendant(adev
, cursor
))
497 /* If that didn't worked try to find a sibling */
498 while (!amdgpu_vm_pt_sibling(adev
, cursor
)) {
499 /* No sibling, go to our parents and grandparents */
500 if (!amdgpu_vm_pt_ancestor(cursor
)) {
508 * amdgpu_vm_pt_first_leaf - get first leaf PD/PT
510 * @adev: amdgpu_device pointer
511 * @vm: amdgpu_vm structure
512 * @start: start addr of the walk
513 * @cursor: state to initialize
515 * Start a walk and go directly to the leaf node.
517 static void amdgpu_vm_pt_first_leaf(struct amdgpu_device
*adev
,
518 struct amdgpu_vm
*vm
, uint64_t start
,
519 struct amdgpu_vm_pt_cursor
*cursor
)
521 amdgpu_vm_pt_start(adev
, vm
, start
, cursor
);
522 while (amdgpu_vm_pt_descendant(adev
, cursor
));
526 * amdgpu_vm_pt_next_leaf - get next leaf PD/PT
528 * @adev: amdgpu_device pointer
529 * @cursor: current state
531 * Walk the PD/PT tree to the next leaf node.
533 static void amdgpu_vm_pt_next_leaf(struct amdgpu_device
*adev
,
534 struct amdgpu_vm_pt_cursor
*cursor
)
536 amdgpu_vm_pt_next(adev
, cursor
);
537 if (cursor
->pfn
!= ~0ll)
538 while (amdgpu_vm_pt_descendant(adev
, cursor
));
542 * for_each_amdgpu_vm_pt_leaf - walk over all leaf PDs/PTs in the hierarchy
544 #define for_each_amdgpu_vm_pt_leaf(adev, vm, start, end, cursor) \
545 for (amdgpu_vm_pt_first_leaf((adev), (vm), (start), &(cursor)); \
546 (cursor).pfn <= end; amdgpu_vm_pt_next_leaf((adev), &(cursor)))
549 * amdgpu_vm_pt_first_dfs - start a deep first search
551 * @adev: amdgpu_device structure
552 * @vm: amdgpu_vm structure
553 * @cursor: state to initialize
555 * Starts a deep first traversal of the PD/PT tree.
557 static void amdgpu_vm_pt_first_dfs(struct amdgpu_device
*adev
,
558 struct amdgpu_vm
*vm
,
559 struct amdgpu_vm_pt_cursor
*cursor
)
561 amdgpu_vm_pt_start(adev
, vm
, 0, cursor
);
562 while (amdgpu_vm_pt_descendant(adev
, cursor
));
566 * amdgpu_vm_pt_next_dfs - get the next node for a deep first search
568 * @adev: amdgpu_device structure
569 * @cursor: current state
571 * Move the cursor to the next node in a deep first search.
573 static void amdgpu_vm_pt_next_dfs(struct amdgpu_device
*adev
,
574 struct amdgpu_vm_pt_cursor
*cursor
)
580 cursor
->entry
= NULL
;
581 else if (amdgpu_vm_pt_sibling(adev
, cursor
))
582 while (amdgpu_vm_pt_descendant(adev
, cursor
));
584 amdgpu_vm_pt_ancestor(cursor
);
588 * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs
590 #define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, cursor, entry) \
591 for (amdgpu_vm_pt_first_dfs((adev), (vm), &(cursor)), \
592 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\
593 (entry); (entry) = (cursor).entry, \
594 amdgpu_vm_pt_next_dfs((adev), &(cursor)))
597 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
599 * @vm: vm providing the BOs
600 * @validated: head of validation list
601 * @entry: entry to add
603 * Add the page directory to the list of BOs to
604 * validate for command submission.
606 void amdgpu_vm_get_pd_bo(struct amdgpu_vm
*vm
,
607 struct list_head
*validated
,
608 struct amdgpu_bo_list_entry
*entry
)
611 entry
->tv
.bo
= &vm
->root
.base
.bo
->tbo
;
612 /* One for the VM updates, one for TTM and one for the CS job */
613 entry
->tv
.num_shared
= 3;
614 entry
->user_pages
= NULL
;
615 list_add(&entry
->tv
.head
, validated
);
618 void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object
*bo
)
620 struct amdgpu_bo
*abo
;
621 struct amdgpu_vm_bo_base
*bo_base
;
623 if (!amdgpu_bo_is_amdgpu_bo(bo
))
626 if (bo
->mem
.placement
& TTM_PL_FLAG_NO_EVICT
)
629 abo
= ttm_to_amdgpu_bo(bo
);
632 for (bo_base
= abo
->vm_bo
; bo_base
; bo_base
= bo_base
->next
) {
633 struct amdgpu_vm
*vm
= bo_base
->vm
;
635 if (abo
->tbo
.resv
== vm
->root
.base
.bo
->tbo
.resv
)
636 vm
->bulk_moveable
= false;
641 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
643 * @adev: amdgpu device pointer
644 * @vm: vm providing the BOs
646 * Move all BOs to the end of LRU and remember their positions to put them
649 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device
*adev
,
650 struct amdgpu_vm
*vm
)
652 struct ttm_bo_global
*glob
= adev
->mman
.bdev
.glob
;
653 struct amdgpu_vm_bo_base
*bo_base
;
655 if (vm
->bulk_moveable
) {
656 spin_lock(&glob
->lru_lock
);
657 ttm_bo_bulk_move_lru_tail(&vm
->lru_bulk_move
);
658 spin_unlock(&glob
->lru_lock
);
662 memset(&vm
->lru_bulk_move
, 0, sizeof(vm
->lru_bulk_move
));
664 spin_lock(&glob
->lru_lock
);
665 list_for_each_entry(bo_base
, &vm
->idle
, vm_status
) {
666 struct amdgpu_bo
*bo
= bo_base
->bo
;
671 ttm_bo_move_to_lru_tail(&bo
->tbo
, &vm
->lru_bulk_move
);
673 ttm_bo_move_to_lru_tail(&bo
->shadow
->tbo
,
676 spin_unlock(&glob
->lru_lock
);
678 vm
->bulk_moveable
= true;
682 * amdgpu_vm_validate_pt_bos - validate the page table BOs
684 * @adev: amdgpu device pointer
685 * @vm: vm providing the BOs
686 * @validate: callback to do the validation
687 * @param: parameter for the validation callback
689 * Validate the page table BOs on command submission if neccessary.
694 int amdgpu_vm_validate_pt_bos(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
695 int (*validate
)(void *p
, struct amdgpu_bo
*bo
),
698 struct amdgpu_vm_bo_base
*bo_base
, *tmp
;
701 list_for_each_entry_safe(bo_base
, tmp
, &vm
->evicted
, vm_status
) {
702 struct amdgpu_bo
*bo
= bo_base
->bo
;
704 r
= validate(param
, bo
);
708 if (bo
->tbo
.type
!= ttm_bo_type_kernel
) {
709 amdgpu_vm_bo_moved(bo_base
);
711 if (vm
->use_cpu_for_update
)
712 r
= amdgpu_bo_kmap(bo
, NULL
);
714 r
= amdgpu_ttm_alloc_gart(&bo
->tbo
);
718 r
= amdgpu_ttm_alloc_gart(&bo
->shadow
->tbo
);
722 amdgpu_vm_bo_relocated(bo_base
);
730 * amdgpu_vm_ready - check VM is ready for updates
734 * Check if all VM PDs/PTs are ready for updates
737 * True if eviction list is empty.
739 bool amdgpu_vm_ready(struct amdgpu_vm
*vm
)
741 return list_empty(&vm
->evicted
);
745 * amdgpu_vm_clear_bo - initially clear the PDs/PTs
747 * @adev: amdgpu_device pointer
748 * @vm: VM to clear BO from
750 * @level: level this BO is at
751 * @pte_support_ats: indicate ATS support from PTE
753 * Root PD needs to be reserved when calling this.
756 * 0 on success, errno otherwise.
758 static int amdgpu_vm_clear_bo(struct amdgpu_device
*adev
,
759 struct amdgpu_vm
*vm
, struct amdgpu_bo
*bo
,
760 unsigned level
, bool pte_support_ats
)
762 struct ttm_operation_ctx ctx
= { true, false };
763 struct dma_fence
*fence
= NULL
;
764 unsigned entries
, ats_entries
;
765 struct amdgpu_ring
*ring
;
766 struct amdgpu_job
*job
;
770 entries
= amdgpu_bo_size(bo
) / 8;
772 if (pte_support_ats
) {
773 if (level
== adev
->vm_manager
.root_level
) {
774 ats_entries
= amdgpu_vm_level_shift(adev
, level
);
775 ats_entries
+= AMDGPU_GPU_PAGE_SHIFT
;
776 ats_entries
= AMDGPU_GMC_HOLE_START
>> ats_entries
;
777 ats_entries
= min(ats_entries
, entries
);
778 entries
-= ats_entries
;
780 ats_entries
= entries
;
787 ring
= container_of(vm
->entity
.rq
->sched
, struct amdgpu_ring
, sched
);
789 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, &ctx
);
793 r
= amdgpu_ttm_alloc_gart(&bo
->tbo
);
797 r
= amdgpu_job_alloc_with_ib(adev
, 64, &job
);
801 addr
= amdgpu_bo_gpu_offset(bo
);
805 ats_value
= AMDGPU_PTE_DEFAULT_ATC
;
806 if (level
!= AMDGPU_VM_PTB
)
807 ats_value
|= AMDGPU_PDE_PTE
;
809 amdgpu_vm_set_pte_pde(adev
, &job
->ibs
[0], addr
, 0,
810 ats_entries
, 0, ats_value
);
811 addr
+= ats_entries
* 8;
817 /* Workaround for fault priority problem on GMC9 */
818 if (level
== AMDGPU_VM_PTB
&& adev
->asic_type
>= CHIP_VEGA10
)
819 value
= AMDGPU_PTE_EXECUTABLE
;
821 amdgpu_vm_set_pte_pde(adev
, &job
->ibs
[0], addr
, 0,
825 amdgpu_ring_pad_ib(ring
, &job
->ibs
[0]);
827 WARN_ON(job
->ibs
[0].length_dw
> 64);
828 r
= amdgpu_sync_resv(adev
, &job
->sync
, bo
->tbo
.resv
,
829 AMDGPU_FENCE_OWNER_KFD
, false);
833 r
= amdgpu_job_submit(job
, &vm
->entity
, AMDGPU_FENCE_OWNER_UNDEFINED
,
838 amdgpu_bo_fence(bo
, fence
, true);
839 dma_fence_put(fence
);
842 return amdgpu_vm_clear_bo(adev
, vm
, bo
->shadow
,
843 level
, pte_support_ats
);
848 amdgpu_job_free(job
);
855 * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
857 * @adev: amdgpu_device pointer
859 * @bp: resulting BO allocation parameters
861 static void amdgpu_vm_bo_param(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
862 int level
, struct amdgpu_bo_param
*bp
)
864 memset(bp
, 0, sizeof(*bp
));
866 bp
->size
= amdgpu_vm_bo_size(adev
, level
);
867 bp
->byte_align
= AMDGPU_GPU_PAGE_SIZE
;
868 bp
->domain
= AMDGPU_GEM_DOMAIN_VRAM
;
869 bp
->domain
= amdgpu_bo_get_preferred_pin_domain(adev
, bp
->domain
);
870 bp
->flags
= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
|
871 AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
872 if (vm
->use_cpu_for_update
)
873 bp
->flags
|= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
;
874 else if (!vm
->root
.base
.bo
|| vm
->root
.base
.bo
->shadow
)
875 bp
->flags
|= AMDGPU_GEM_CREATE_SHADOW
;
876 bp
->type
= ttm_bo_type_kernel
;
877 if (vm
->root
.base
.bo
)
878 bp
->resv
= vm
->root
.base
.bo
->tbo
.resv
;
882 * amdgpu_vm_alloc_pts - Allocate page tables.
884 * @adev: amdgpu_device pointer
885 * @vm: VM to allocate page tables for
886 * @saddr: Start address which needs to be allocated
887 * @size: Size from start address we need.
889 * Make sure the page directories and page tables are allocated
892 * 0 on success, errno otherwise.
894 int amdgpu_vm_alloc_pts(struct amdgpu_device
*adev
,
895 struct amdgpu_vm
*vm
,
896 uint64_t saddr
, uint64_t size
)
898 struct amdgpu_vm_pt_cursor cursor
;
899 struct amdgpu_bo
*pt
;
904 /* validate the parameters */
905 if (saddr
& AMDGPU_GPU_PAGE_MASK
|| size
& AMDGPU_GPU_PAGE_MASK
)
908 eaddr
= saddr
+ size
- 1;
910 if (vm
->pte_support_ats
)
911 ats
= saddr
< AMDGPU_GMC_HOLE_START
;
913 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
914 eaddr
/= AMDGPU_GPU_PAGE_SIZE
;
916 if (eaddr
>= adev
->vm_manager
.max_pfn
) {
917 dev_err(adev
->dev
, "va above limit (0x%08llX >= 0x%08llX)\n",
918 eaddr
, adev
->vm_manager
.max_pfn
);
922 for_each_amdgpu_vm_pt_leaf(adev
, vm
, saddr
, eaddr
, cursor
) {
923 struct amdgpu_vm_pt
*entry
= cursor
.entry
;
924 struct amdgpu_bo_param bp
;
926 if (cursor
.level
< AMDGPU_VM_PTB
) {
927 unsigned num_entries
;
929 num_entries
= amdgpu_vm_num_entries(adev
, cursor
.level
);
930 entry
->entries
= kvmalloc_array(num_entries
,
931 sizeof(*entry
->entries
),
942 amdgpu_vm_bo_param(adev
, vm
, cursor
.level
, &bp
);
944 r
= amdgpu_bo_create(adev
, &bp
, &pt
);
948 r
= amdgpu_vm_clear_bo(adev
, vm
, pt
, cursor
.level
, ats
);
952 if (vm
->use_cpu_for_update
) {
953 r
= amdgpu_bo_kmap(pt
, NULL
);
958 /* Keep a reference to the root directory to avoid
959 * freeing them up in the wrong order.
961 pt
->parent
= amdgpu_bo_ref(cursor
.parent
->base
.bo
);
963 amdgpu_vm_bo_base_init(&entry
->base
, vm
, pt
);
969 amdgpu_bo_unref(&pt
->shadow
);
970 amdgpu_bo_unref(&pt
);
975 * amdgpu_vm_free_pts - free PD/PT levels
977 * @adev: amdgpu device structure
978 * @vm: amdgpu vm structure
980 * Free the page directory or page table level and all sub levels.
982 static void amdgpu_vm_free_pts(struct amdgpu_device
*adev
,
983 struct amdgpu_vm
*vm
)
985 struct amdgpu_vm_pt_cursor cursor
;
986 struct amdgpu_vm_pt
*entry
;
988 for_each_amdgpu_vm_pt_dfs_safe(adev
, vm
, cursor
, entry
) {
990 if (entry
->base
.bo
) {
991 entry
->base
.bo
->vm_bo
= NULL
;
992 list_del(&entry
->base
.vm_status
);
993 amdgpu_bo_unref(&entry
->base
.bo
->shadow
);
994 amdgpu_bo_unref(&entry
->base
.bo
);
996 kvfree(entry
->entries
);
999 BUG_ON(vm
->root
.base
.bo
);
1003 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
1005 * @adev: amdgpu_device pointer
1007 void amdgpu_vm_check_compute_bug(struct amdgpu_device
*adev
)
1009 const struct amdgpu_ip_block
*ip_block
;
1010 bool has_compute_vm_bug
;
1011 struct amdgpu_ring
*ring
;
1014 has_compute_vm_bug
= false;
1016 ip_block
= amdgpu_device_ip_get_ip_block(adev
, AMD_IP_BLOCK_TYPE_GFX
);
1018 /* Compute has a VM bug for GFX version < 7.
1019 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
1020 if (ip_block
->version
->major
<= 7)
1021 has_compute_vm_bug
= true;
1022 else if (ip_block
->version
->major
== 8)
1023 if (adev
->gfx
.mec_fw_version
< 673)
1024 has_compute_vm_bug
= true;
1027 for (i
= 0; i
< adev
->num_rings
; i
++) {
1028 ring
= adev
->rings
[i
];
1029 if (ring
->funcs
->type
== AMDGPU_RING_TYPE_COMPUTE
)
1030 /* only compute rings */
1031 ring
->has_compute_vm_bug
= has_compute_vm_bug
;
1033 ring
->has_compute_vm_bug
= false;
1038 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
1040 * @ring: ring on which the job will be submitted
1041 * @job: job to submit
1044 * True if sync is needed.
1046 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring
*ring
,
1047 struct amdgpu_job
*job
)
1049 struct amdgpu_device
*adev
= ring
->adev
;
1050 unsigned vmhub
= ring
->funcs
->vmhub
;
1051 struct amdgpu_vmid_mgr
*id_mgr
= &adev
->vm_manager
.id_mgr
[vmhub
];
1052 struct amdgpu_vmid
*id
;
1053 bool gds_switch_needed
;
1054 bool vm_flush_needed
= job
->vm_needs_flush
|| ring
->has_compute_vm_bug
;
1058 id
= &id_mgr
->ids
[job
->vmid
];
1059 gds_switch_needed
= ring
->funcs
->emit_gds_switch
&& (
1060 id
->gds_base
!= job
->gds_base
||
1061 id
->gds_size
!= job
->gds_size
||
1062 id
->gws_base
!= job
->gws_base
||
1063 id
->gws_size
!= job
->gws_size
||
1064 id
->oa_base
!= job
->oa_base
||
1065 id
->oa_size
!= job
->oa_size
);
1067 if (amdgpu_vmid_had_gpu_reset(adev
, id
))
1070 return vm_flush_needed
|| gds_switch_needed
;
1074 * amdgpu_vm_flush - hardware flush the vm
1076 * @ring: ring to use for flush
1078 * @need_pipe_sync: is pipe sync needed
1080 * Emit a VM flush when it is necessary.
1083 * 0 on success, errno otherwise.
1085 int amdgpu_vm_flush(struct amdgpu_ring
*ring
, struct amdgpu_job
*job
, bool need_pipe_sync
)
1087 struct amdgpu_device
*adev
= ring
->adev
;
1088 unsigned vmhub
= ring
->funcs
->vmhub
;
1089 struct amdgpu_vmid_mgr
*id_mgr
= &adev
->vm_manager
.id_mgr
[vmhub
];
1090 struct amdgpu_vmid
*id
= &id_mgr
->ids
[job
->vmid
];
1091 bool gds_switch_needed
= ring
->funcs
->emit_gds_switch
&& (
1092 id
->gds_base
!= job
->gds_base
||
1093 id
->gds_size
!= job
->gds_size
||
1094 id
->gws_base
!= job
->gws_base
||
1095 id
->gws_size
!= job
->gws_size
||
1096 id
->oa_base
!= job
->oa_base
||
1097 id
->oa_size
!= job
->oa_size
);
1098 bool vm_flush_needed
= job
->vm_needs_flush
;
1099 bool pasid_mapping_needed
= id
->pasid
!= job
->pasid
||
1100 !id
->pasid_mapping
||
1101 !dma_fence_is_signaled(id
->pasid_mapping
);
1102 struct dma_fence
*fence
= NULL
;
1103 unsigned patch_offset
= 0;
1106 if (amdgpu_vmid_had_gpu_reset(adev
, id
)) {
1107 gds_switch_needed
= true;
1108 vm_flush_needed
= true;
1109 pasid_mapping_needed
= true;
1112 gds_switch_needed
&= !!ring
->funcs
->emit_gds_switch
;
1113 vm_flush_needed
&= !!ring
->funcs
->emit_vm_flush
&&
1114 job
->vm_pd_addr
!= AMDGPU_BO_INVALID_OFFSET
;
1115 pasid_mapping_needed
&= adev
->gmc
.gmc_funcs
->emit_pasid_mapping
&&
1116 ring
->funcs
->emit_wreg
;
1118 if (!vm_flush_needed
&& !gds_switch_needed
&& !need_pipe_sync
)
1121 if (ring
->funcs
->init_cond_exec
)
1122 patch_offset
= amdgpu_ring_init_cond_exec(ring
);
1125 amdgpu_ring_emit_pipeline_sync(ring
);
1127 if (vm_flush_needed
) {
1128 trace_amdgpu_vm_flush(ring
, job
->vmid
, job
->vm_pd_addr
);
1129 amdgpu_ring_emit_vm_flush(ring
, job
->vmid
, job
->vm_pd_addr
);
1132 if (pasid_mapping_needed
)
1133 amdgpu_gmc_emit_pasid_mapping(ring
, job
->vmid
, job
->pasid
);
1135 if (vm_flush_needed
|| pasid_mapping_needed
) {
1136 r
= amdgpu_fence_emit(ring
, &fence
, 0);
1141 if (vm_flush_needed
) {
1142 mutex_lock(&id_mgr
->lock
);
1143 dma_fence_put(id
->last_flush
);
1144 id
->last_flush
= dma_fence_get(fence
);
1145 id
->current_gpu_reset_count
=
1146 atomic_read(&adev
->gpu_reset_counter
);
1147 mutex_unlock(&id_mgr
->lock
);
1150 if (pasid_mapping_needed
) {
1151 id
->pasid
= job
->pasid
;
1152 dma_fence_put(id
->pasid_mapping
);
1153 id
->pasid_mapping
= dma_fence_get(fence
);
1155 dma_fence_put(fence
);
1157 if (ring
->funcs
->emit_gds_switch
&& gds_switch_needed
) {
1158 id
->gds_base
= job
->gds_base
;
1159 id
->gds_size
= job
->gds_size
;
1160 id
->gws_base
= job
->gws_base
;
1161 id
->gws_size
= job
->gws_size
;
1162 id
->oa_base
= job
->oa_base
;
1163 id
->oa_size
= job
->oa_size
;
1164 amdgpu_ring_emit_gds_switch(ring
, job
->vmid
, job
->gds_base
,
1165 job
->gds_size
, job
->gws_base
,
1166 job
->gws_size
, job
->oa_base
,
1170 if (ring
->funcs
->patch_cond_exec
)
1171 amdgpu_ring_patch_cond_exec(ring
, patch_offset
);
1173 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
1174 if (ring
->funcs
->emit_switch_buffer
) {
1175 amdgpu_ring_emit_switch_buffer(ring
);
1176 amdgpu_ring_emit_switch_buffer(ring
);
1182 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
1185 * @bo: requested buffer object
1187 * Find @bo inside the requested vm.
1188 * Search inside the @bos vm list for the requested vm
1189 * Returns the found bo_va or NULL if none is found
1191 * Object has to be reserved!
1194 * Found bo_va or NULL.
1196 struct amdgpu_bo_va
*amdgpu_vm_bo_find(struct amdgpu_vm
*vm
,
1197 struct amdgpu_bo
*bo
)
1199 struct amdgpu_vm_bo_base
*base
;
1201 for (base
= bo
->vm_bo
; base
; base
= base
->next
) {
1205 return container_of(base
, struct amdgpu_bo_va
, base
);
1211 * amdgpu_vm_do_set_ptes - helper to call the right asic function
1213 * @params: see amdgpu_pte_update_params definition
1214 * @bo: PD/PT to update
1215 * @pe: addr of the page entry
1216 * @addr: dst addr to write into pe
1217 * @count: number of page entries to update
1218 * @incr: increase next addr by incr bytes
1219 * @flags: hw access flags
1221 * Traces the parameters and calls the right asic functions
1222 * to setup the page table using the DMA.
1224 static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params
*params
,
1225 struct amdgpu_bo
*bo
,
1226 uint64_t pe
, uint64_t addr
,
1227 unsigned count
, uint32_t incr
,
1230 pe
+= amdgpu_bo_gpu_offset(bo
);
1231 trace_amdgpu_vm_set_ptes(pe
, addr
, count
, incr
, flags
);
1234 amdgpu_vm_write_pte(params
->adev
, params
->ib
, pe
,
1235 addr
| flags
, count
, incr
);
1238 amdgpu_vm_set_pte_pde(params
->adev
, params
->ib
, pe
, addr
,
1239 count
, incr
, flags
);
1244 * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART
1246 * @params: see amdgpu_pte_update_params definition
1247 * @bo: PD/PT to update
1248 * @pe: addr of the page entry
1249 * @addr: dst addr to write into pe
1250 * @count: number of page entries to update
1251 * @incr: increase next addr by incr bytes
1252 * @flags: hw access flags
1254 * Traces the parameters and calls the DMA function to copy the PTEs.
1256 static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params
*params
,
1257 struct amdgpu_bo
*bo
,
1258 uint64_t pe
, uint64_t addr
,
1259 unsigned count
, uint32_t incr
,
1262 uint64_t src
= (params
->src
+ (addr
>> 12) * 8);
1264 pe
+= amdgpu_bo_gpu_offset(bo
);
1265 trace_amdgpu_vm_copy_ptes(pe
, src
, count
);
1267 amdgpu_vm_copy_pte(params
->adev
, params
->ib
, pe
, src
, count
);
1271 * amdgpu_vm_map_gart - Resolve gart mapping of addr
1273 * @pages_addr: optional DMA address to use for lookup
1274 * @addr: the unmapped addr
1276 * Look up the physical address of the page that the pte resolves
1280 * The pointer for the page table entry.
1282 static uint64_t amdgpu_vm_map_gart(const dma_addr_t
*pages_addr
, uint64_t addr
)
1286 /* page table offset */
1287 result
= pages_addr
[addr
>> PAGE_SHIFT
];
1289 /* in case cpu page size != gpu page size*/
1290 result
|= addr
& (~PAGE_MASK
);
1292 result
&= 0xFFFFFFFFFFFFF000ULL
;
1298 * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU
1300 * @params: see amdgpu_pte_update_params definition
1301 * @bo: PD/PT to update
1302 * @pe: kmap addr of the page entry
1303 * @addr: dst addr to write into pe
1304 * @count: number of page entries to update
1305 * @incr: increase next addr by incr bytes
1306 * @flags: hw access flags
1308 * Write count number of PT/PD entries directly.
1310 static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params
*params
,
1311 struct amdgpu_bo
*bo
,
1312 uint64_t pe
, uint64_t addr
,
1313 unsigned count
, uint32_t incr
,
1319 pe
+= (unsigned long)amdgpu_bo_kptr(bo
);
1321 trace_amdgpu_vm_set_ptes(pe
, addr
, count
, incr
, flags
);
1323 for (i
= 0; i
< count
; i
++) {
1324 value
= params
->pages_addr
?
1325 amdgpu_vm_map_gart(params
->pages_addr
, addr
) :
1327 amdgpu_gmc_set_pte_pde(params
->adev
, (void *)(uintptr_t)pe
,
1334 * amdgpu_vm_update_func - helper to call update function
1336 * Calls the update function for both the given BO as well as its shadow.
1338 static void amdgpu_vm_update_func(struct amdgpu_pte_update_params
*params
,
1339 struct amdgpu_bo
*bo
,
1340 uint64_t pe
, uint64_t addr
,
1341 unsigned count
, uint32_t incr
,
1345 params
->func(params
, bo
->shadow
, pe
, addr
, count
, incr
, flags
);
1346 params
->func(params
, bo
, pe
, addr
, count
, incr
, flags
);
1350 * amdgpu_vm_update_pde - update a single level in the hierarchy
1352 * @param: parameters for the update
1354 * @parent: parent directory
1355 * @entry: entry to update
1357 * Makes sure the requested entry in parent is up to date.
1359 static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params
*params
,
1360 struct amdgpu_vm
*vm
,
1361 struct amdgpu_vm_pt
*parent
,
1362 struct amdgpu_vm_pt
*entry
)
1364 struct amdgpu_bo
*bo
= parent
->base
.bo
, *pbo
;
1365 uint64_t pde
, pt
, flags
;
1368 /* Don't update huge pages here */
1372 for (level
= 0, pbo
= bo
->parent
; pbo
; ++level
)
1375 level
+= params
->adev
->vm_manager
.root_level
;
1376 amdgpu_gmc_get_pde_for_bo(entry
->base
.bo
, level
, &pt
, &flags
);
1377 pde
= (entry
- parent
->entries
) * 8;
1378 amdgpu_vm_update_func(params
, bo
, pde
, pt
, 1, 0, flags
);
1382 * amdgpu_vm_invalidate_pds - mark all PDs as invalid
1384 * @adev: amdgpu_device pointer
1387 * Mark all PD level as invalid after an error.
1389 static void amdgpu_vm_invalidate_pds(struct amdgpu_device
*adev
,
1390 struct amdgpu_vm
*vm
)
1392 struct amdgpu_vm_pt_cursor cursor
;
1393 struct amdgpu_vm_pt
*entry
;
1395 for_each_amdgpu_vm_pt_dfs_safe(adev
, vm
, cursor
, entry
)
1396 if (entry
->base
.bo
&& !entry
->base
.moved
)
1397 amdgpu_vm_bo_relocated(&entry
->base
);
1401 * amdgpu_vm_update_directories - make sure that all directories are valid
1403 * @adev: amdgpu_device pointer
1406 * Makes sure all directories are up to date.
1409 * 0 for success, error for failure.
1411 int amdgpu_vm_update_directories(struct amdgpu_device
*adev
,
1412 struct amdgpu_vm
*vm
)
1414 struct amdgpu_pte_update_params params
;
1415 struct amdgpu_job
*job
;
1419 if (list_empty(&vm
->relocated
))
1423 memset(¶ms
, 0, sizeof(params
));
1426 if (vm
->use_cpu_for_update
) {
1427 r
= amdgpu_bo_sync_wait(vm
->root
.base
.bo
,
1428 AMDGPU_FENCE_OWNER_VM
, true);
1432 params
.func
= amdgpu_vm_cpu_set_ptes
;
1435 r
= amdgpu_job_alloc_with_ib(adev
, ndw
* 4, &job
);
1439 params
.ib
= &job
->ibs
[0];
1440 params
.func
= amdgpu_vm_do_set_ptes
;
1443 while (!list_empty(&vm
->relocated
)) {
1444 struct amdgpu_vm_pt
*pt
, *entry
;
1446 entry
= list_first_entry(&vm
->relocated
, struct amdgpu_vm_pt
,
1448 amdgpu_vm_bo_idle(&entry
->base
);
1450 pt
= amdgpu_vm_pt_parent(entry
);
1454 amdgpu_vm_update_pde(¶ms
, vm
, pt
, entry
);
1456 if (!vm
->use_cpu_for_update
&&
1457 (ndw
- params
.ib
->length_dw
) < 32)
1461 if (vm
->use_cpu_for_update
) {
1464 amdgpu_asic_flush_hdp(adev
, NULL
);
1465 } else if (params
.ib
->length_dw
== 0) {
1466 amdgpu_job_free(job
);
1468 struct amdgpu_bo
*root
= vm
->root
.base
.bo
;
1469 struct amdgpu_ring
*ring
;
1470 struct dma_fence
*fence
;
1472 ring
= container_of(vm
->entity
.rq
->sched
, struct amdgpu_ring
,
1475 amdgpu_ring_pad_ib(ring
, params
.ib
);
1476 amdgpu_sync_resv(adev
, &job
->sync
, root
->tbo
.resv
,
1477 AMDGPU_FENCE_OWNER_VM
, false);
1478 WARN_ON(params
.ib
->length_dw
> ndw
);
1479 r
= amdgpu_job_submit(job
, &vm
->entity
, AMDGPU_FENCE_OWNER_VM
,
1484 amdgpu_bo_fence(root
, fence
, true);
1485 dma_fence_put(vm
->last_update
);
1486 vm
->last_update
= fence
;
1489 if (!list_empty(&vm
->relocated
))
1495 amdgpu_vm_invalidate_pds(adev
, vm
);
1496 amdgpu_job_free(job
);
1501 * amdgpu_vm_update_flags - figure out flags for PTE updates
1503 * Make sure to set the right flags for the PTEs at the desired level.
1505 static void amdgpu_vm_update_flags(struct amdgpu_pte_update_params
*params
,
1506 struct amdgpu_bo
*bo
, unsigned level
,
1507 uint64_t pe
, uint64_t addr
,
1508 unsigned count
, uint32_t incr
,
1512 if (level
!= AMDGPU_VM_PTB
) {
1513 flags
|= AMDGPU_PDE_PTE
;
1514 amdgpu_gmc_get_vm_pde(params
->adev
, level
, &addr
, &flags
);
1516 } else if (params
->adev
->asic_type
>= CHIP_VEGA10
&&
1517 !(flags
& AMDGPU_PTE_VALID
) &&
1518 !(flags
& AMDGPU_PTE_PRT
)) {
1520 /* Workaround for fault priority problem on GMC9 */
1521 flags
|= AMDGPU_PTE_EXECUTABLE
;
1524 amdgpu_vm_update_func(params
, bo
, pe
, addr
, count
, incr
, flags
);
1528 * amdgpu_vm_fragment - get fragment for PTEs
1530 * @params: see amdgpu_pte_update_params definition
1531 * @start: first PTE to handle
1532 * @end: last PTE to handle
1533 * @flags: hw mapping flags
1534 * @frag: resulting fragment size
1535 * @frag_end: end of this fragment
1537 * Returns the first possible fragment for the start and end address.
1539 static void amdgpu_vm_fragment(struct amdgpu_pte_update_params
*params
,
1540 uint64_t start
, uint64_t end
, uint64_t flags
,
1541 unsigned int *frag
, uint64_t *frag_end
)
1544 * The MC L1 TLB supports variable sized pages, based on a fragment
1545 * field in the PTE. When this field is set to a non-zero value, page
1546 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1547 * flags are considered valid for all PTEs within the fragment range
1548 * and corresponding mappings are assumed to be physically contiguous.
1550 * The L1 TLB can store a single PTE for the whole fragment,
1551 * significantly increasing the space available for translation
1552 * caching. This leads to large improvements in throughput when the
1553 * TLB is under pressure.
1555 * The L2 TLB distributes small and large fragments into two
1556 * asymmetric partitions. The large fragment cache is significantly
1557 * larger. Thus, we try to use large fragments wherever possible.
1558 * Userspace can support this by aligning virtual base address and
1559 * allocation size to the fragment size.
1561 * Starting with Vega10 the fragment size only controls the L1. The L2
1562 * is now directly feed with small/huge/giant pages from the walker.
1566 if (params
->adev
->asic_type
< CHIP_VEGA10
)
1567 max_frag
= params
->adev
->vm_manager
.fragment_size
;
1571 /* system pages are non continuously */
1578 /* This intentionally wraps around if no bit is set */
1579 *frag
= min((unsigned)ffs(start
) - 1, (unsigned)fls64(end
- start
) - 1);
1580 if (*frag
>= max_frag
) {
1582 *frag_end
= end
& ~((1ULL << max_frag
) - 1);
1584 *frag_end
= start
+ (1 << *frag
);
1589 * amdgpu_vm_update_ptes - make sure that page tables are valid
1591 * @params: see amdgpu_pte_update_params definition
1592 * @start: start of GPU address range
1593 * @end: end of GPU address range
1594 * @dst: destination address to map to, the next dst inside the function
1595 * @flags: mapping flags
1597 * Update the page tables in the range @start - @end.
1600 * 0 for success, -EINVAL for failure.
1602 static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params
*params
,
1603 uint64_t start
, uint64_t end
,
1604 uint64_t dst
, uint64_t flags
)
1606 struct amdgpu_device
*adev
= params
->adev
;
1607 struct amdgpu_vm_pt_cursor cursor
;
1608 uint64_t frag_start
= start
, frag_end
;
1611 /* figure out the initial fragment */
1612 amdgpu_vm_fragment(params
, frag_start
, end
, flags
, &frag
, &frag_end
);
1614 /* walk over the address space and update the PTs */
1615 amdgpu_vm_pt_start(adev
, params
->vm
, start
, &cursor
);
1616 while (cursor
.pfn
< end
) {
1617 struct amdgpu_bo
*pt
= cursor
.entry
->base
.bo
;
1618 unsigned shift
, parent_shift
, mask
;
1619 uint64_t incr
, entry_end
, pe_start
;
1624 /* The root level can't be a huge page */
1625 if (cursor
.level
== adev
->vm_manager
.root_level
) {
1626 if (!amdgpu_vm_pt_descendant(adev
, &cursor
))
1631 /* If it isn't already handled it can't be a huge page */
1632 if (cursor
.entry
->huge
) {
1633 /* Add the entry to the relocated list to update it. */
1634 cursor
.entry
->huge
= false;
1635 amdgpu_vm_bo_relocated(&cursor
.entry
->base
);
1638 shift
= amdgpu_vm_level_shift(adev
, cursor
.level
);
1639 parent_shift
= amdgpu_vm_level_shift(adev
, cursor
.level
- 1);
1640 if (adev
->asic_type
< CHIP_VEGA10
) {
1641 /* No huge page support before GMC v9 */
1642 if (cursor
.level
!= AMDGPU_VM_PTB
) {
1643 if (!amdgpu_vm_pt_descendant(adev
, &cursor
))
1647 } else if (frag
< shift
) {
1648 /* We can't use this level when the fragment size is
1649 * smaller than the address shift. Go to the next
1650 * child entry and try again.
1652 if (!amdgpu_vm_pt_descendant(adev
, &cursor
))
1655 } else if (frag
>= parent_shift
&&
1656 cursor
.level
- 1 != adev
->vm_manager
.root_level
) {
1657 /* If the fragment size is even larger than the parent
1658 * shift we should go up one level and check it again
1659 * unless one level up is the root level.
1661 if (!amdgpu_vm_pt_ancestor(&cursor
))
1666 /* Looks good so far, calculate parameters for the update */
1667 incr
= (uint64_t)AMDGPU_GPU_PAGE_SIZE
<< shift
;
1668 mask
= amdgpu_vm_entries_mask(adev
, cursor
.level
);
1669 pe_start
= ((cursor
.pfn
>> shift
) & mask
) * 8;
1670 entry_end
= (uint64_t)(mask
+ 1) << shift
;
1671 entry_end
+= cursor
.pfn
& ~(entry_end
- 1);
1672 entry_end
= min(entry_end
, end
);
1675 uint64_t upd_end
= min(entry_end
, frag_end
);
1676 unsigned nptes
= (upd_end
- frag_start
) >> shift
;
1678 amdgpu_vm_update_flags(params
, pt
, cursor
.level
,
1679 pe_start
, dst
, nptes
, incr
,
1680 flags
| AMDGPU_PTE_FRAG(frag
));
1682 pe_start
+= nptes
* 8;
1683 dst
+= (uint64_t)nptes
* AMDGPU_GPU_PAGE_SIZE
<< shift
;
1685 frag_start
= upd_end
;
1686 if (frag_start
>= frag_end
) {
1687 /* figure out the next fragment */
1688 amdgpu_vm_fragment(params
, frag_start
, end
,
1689 flags
, &frag
, &frag_end
);
1693 } while (frag_start
< entry_end
);
1695 if (amdgpu_vm_pt_descendant(adev
, &cursor
)) {
1696 /* Mark all child entries as huge */
1697 while (cursor
.pfn
< frag_start
) {
1698 cursor
.entry
->huge
= true;
1699 amdgpu_vm_pt_next(adev
, &cursor
);
1702 } else if (frag
>= shift
) {
1703 /* or just move on to the next on the same level. */
1704 amdgpu_vm_pt_next(adev
, &cursor
);
1712 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1714 * @adev: amdgpu_device pointer
1715 * @exclusive: fence we need to sync to
1716 * @pages_addr: DMA addresses to use for mapping
1718 * @start: start of mapped range
1719 * @last: last mapped entry
1720 * @flags: flags for the entries
1721 * @addr: addr to set the area to
1722 * @fence: optional resulting fence
1724 * Fill in the page table entries between @start and @last.
1727 * 0 for success, -EINVAL for failure.
1729 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device
*adev
,
1730 struct dma_fence
*exclusive
,
1731 dma_addr_t
*pages_addr
,
1732 struct amdgpu_vm
*vm
,
1733 uint64_t start
, uint64_t last
,
1734 uint64_t flags
, uint64_t addr
,
1735 struct dma_fence
**fence
)
1737 struct amdgpu_ring
*ring
;
1738 void *owner
= AMDGPU_FENCE_OWNER_VM
;
1739 unsigned nptes
, ncmds
, ndw
;
1740 struct amdgpu_job
*job
;
1741 struct amdgpu_pte_update_params params
;
1742 struct dma_fence
*f
= NULL
;
1745 memset(¶ms
, 0, sizeof(params
));
1749 /* sync to everything except eviction fences on unmapping */
1750 if (!(flags
& AMDGPU_PTE_VALID
))
1751 owner
= AMDGPU_FENCE_OWNER_KFD
;
1753 if (vm
->use_cpu_for_update
) {
1754 /* params.src is used as flag to indicate system Memory */
1758 /* Wait for PT BOs to be idle. PTs share the same resv. object
1761 r
= amdgpu_bo_sync_wait(vm
->root
.base
.bo
, owner
, true);
1765 /* Wait for any BO move to be completed */
1767 r
= dma_fence_wait(exclusive
, true);
1772 params
.func
= amdgpu_vm_cpu_set_ptes
;
1773 params
.pages_addr
= pages_addr
;
1774 return amdgpu_vm_update_ptes(¶ms
, start
, last
+ 1,
1778 ring
= container_of(vm
->entity
.rq
->sched
, struct amdgpu_ring
, sched
);
1780 nptes
= last
- start
+ 1;
1783 * reserve space for two commands every (1 << BLOCK_SIZE)
1784 * entries or 2k dwords (whatever is smaller)
1786 ncmds
= ((nptes
>> min(adev
->vm_manager
.block_size
, 11u)) + 1);
1788 /* The second command is for the shadow pagetables. */
1789 if (vm
->root
.base
.bo
->shadow
)
1796 /* copy commands needed */
1797 ndw
+= ncmds
* adev
->vm_manager
.vm_pte_funcs
->copy_pte_num_dw
;
1802 params
.func
= amdgpu_vm_do_copy_ptes
;
1805 /* set page commands needed */
1808 /* extra commands for begin/end fragments */
1809 ncmds
= 2 * adev
->vm_manager
.fragment_size
;
1810 if (vm
->root
.base
.bo
->shadow
)
1815 params
.func
= amdgpu_vm_do_set_ptes
;
1818 r
= amdgpu_job_alloc_with_ib(adev
, ndw
* 4, &job
);
1822 params
.ib
= &job
->ibs
[0];
1828 /* Put the PTEs at the end of the IB. */
1829 i
= ndw
- nptes
* 2;
1830 pte
= (uint64_t *)&(job
->ibs
->ptr
[i
]);
1831 params
.src
= job
->ibs
->gpu_addr
+ i
* 4;
1833 for (i
= 0; i
< nptes
; ++i
) {
1834 pte
[i
] = amdgpu_vm_map_gart(pages_addr
, addr
+ i
*
1835 AMDGPU_GPU_PAGE_SIZE
);
1841 r
= amdgpu_sync_fence(adev
, &job
->sync
, exclusive
, false);
1845 r
= amdgpu_sync_resv(adev
, &job
->sync
, vm
->root
.base
.bo
->tbo
.resv
,
1850 r
= amdgpu_vm_update_ptes(¶ms
, start
, last
+ 1, addr
, flags
);
1854 amdgpu_ring_pad_ib(ring
, params
.ib
);
1855 WARN_ON(params
.ib
->length_dw
> ndw
);
1856 r
= amdgpu_job_submit(job
, &vm
->entity
, AMDGPU_FENCE_OWNER_VM
, &f
);
1860 amdgpu_bo_fence(vm
->root
.base
.bo
, f
, true);
1861 dma_fence_put(*fence
);
1866 amdgpu_job_free(job
);
1871 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
1873 * @adev: amdgpu_device pointer
1874 * @exclusive: fence we need to sync to
1875 * @pages_addr: DMA addresses to use for mapping
1877 * @mapping: mapped range and flags to use for the update
1878 * @flags: HW flags for the mapping
1879 * @nodes: array of drm_mm_nodes with the MC addresses
1880 * @fence: optional resulting fence
1882 * Split the mapping into smaller chunks so that each update fits
1886 * 0 for success, -EINVAL for failure.
1888 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device
*adev
,
1889 struct dma_fence
*exclusive
,
1890 dma_addr_t
*pages_addr
,
1891 struct amdgpu_vm
*vm
,
1892 struct amdgpu_bo_va_mapping
*mapping
,
1894 struct drm_mm_node
*nodes
,
1895 struct dma_fence
**fence
)
1897 unsigned min_linear_pages
= 1 << adev
->vm_manager
.fragment_size
;
1898 uint64_t pfn
, start
= mapping
->start
;
1901 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1902 * but in case of something, we filter the flags in first place
1904 if (!(mapping
->flags
& AMDGPU_PTE_READABLE
))
1905 flags
&= ~AMDGPU_PTE_READABLE
;
1906 if (!(mapping
->flags
& AMDGPU_PTE_WRITEABLE
))
1907 flags
&= ~AMDGPU_PTE_WRITEABLE
;
1909 flags
&= ~AMDGPU_PTE_EXECUTABLE
;
1910 flags
|= mapping
->flags
& AMDGPU_PTE_EXECUTABLE
;
1912 flags
&= ~AMDGPU_PTE_MTYPE_MASK
;
1913 flags
|= (mapping
->flags
& AMDGPU_PTE_MTYPE_MASK
);
1915 if ((mapping
->flags
& AMDGPU_PTE_PRT
) &&
1916 (adev
->asic_type
>= CHIP_VEGA10
)) {
1917 flags
|= AMDGPU_PTE_PRT
;
1918 flags
&= ~AMDGPU_PTE_VALID
;
1921 trace_amdgpu_vm_bo_update(mapping
);
1923 pfn
= mapping
->offset
>> PAGE_SHIFT
;
1925 while (pfn
>= nodes
->size
) {
1932 dma_addr_t
*dma_addr
= NULL
;
1933 uint64_t max_entries
;
1934 uint64_t addr
, last
;
1937 addr
= nodes
->start
<< PAGE_SHIFT
;
1938 max_entries
= (nodes
->size
- pfn
) *
1939 AMDGPU_GPU_PAGES_IN_CPU_PAGE
;
1942 max_entries
= S64_MAX
;
1948 max_entries
= min(max_entries
, 16ull * 1024ull);
1950 count
< max_entries
/ AMDGPU_GPU_PAGES_IN_CPU_PAGE
;
1952 uint64_t idx
= pfn
+ count
;
1954 if (pages_addr
[idx
] !=
1955 (pages_addr
[idx
- 1] + PAGE_SIZE
))
1959 if (count
< min_linear_pages
) {
1960 addr
= pfn
<< PAGE_SHIFT
;
1961 dma_addr
= pages_addr
;
1963 addr
= pages_addr
[pfn
];
1964 max_entries
= count
* AMDGPU_GPU_PAGES_IN_CPU_PAGE
;
1967 } else if (flags
& AMDGPU_PTE_VALID
) {
1968 addr
+= adev
->vm_manager
.vram_base_offset
;
1969 addr
+= pfn
<< PAGE_SHIFT
;
1972 last
= min((uint64_t)mapping
->last
, start
+ max_entries
- 1);
1973 r
= amdgpu_vm_bo_update_mapping(adev
, exclusive
, dma_addr
, vm
,
1974 start
, last
, flags
, addr
,
1979 pfn
+= (last
- start
+ 1) / AMDGPU_GPU_PAGES_IN_CPU_PAGE
;
1980 if (nodes
&& nodes
->size
== pfn
) {
1986 } while (unlikely(start
!= mapping
->last
+ 1));
1992 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1994 * @adev: amdgpu_device pointer
1995 * @bo_va: requested BO and VM object
1996 * @clear: if true clear the entries
1998 * Fill in the page table entries for @bo_va.
2001 * 0 for success, -EINVAL for failure.
2003 int amdgpu_vm_bo_update(struct amdgpu_device
*adev
,
2004 struct amdgpu_bo_va
*bo_va
,
2007 struct amdgpu_bo
*bo
= bo_va
->base
.bo
;
2008 struct amdgpu_vm
*vm
= bo_va
->base
.vm
;
2009 struct amdgpu_bo_va_mapping
*mapping
;
2010 dma_addr_t
*pages_addr
= NULL
;
2011 struct ttm_mem_reg
*mem
;
2012 struct drm_mm_node
*nodes
;
2013 struct dma_fence
*exclusive
, **last_update
;
2022 struct ttm_dma_tt
*ttm
;
2025 nodes
= mem
->mm_node
;
2026 if (mem
->mem_type
== TTM_PL_TT
) {
2027 ttm
= container_of(bo
->tbo
.ttm
, struct ttm_dma_tt
, ttm
);
2028 pages_addr
= ttm
->dma_address
;
2030 exclusive
= reservation_object_get_excl(bo
->tbo
.resv
);
2034 flags
= amdgpu_ttm_tt_pte_flags(adev
, bo
->tbo
.ttm
, mem
);
2038 if (clear
|| (bo
&& bo
->tbo
.resv
== vm
->root
.base
.bo
->tbo
.resv
))
2039 last_update
= &vm
->last_update
;
2041 last_update
= &bo_va
->last_pt_update
;
2043 if (!clear
&& bo_va
->base
.moved
) {
2044 bo_va
->base
.moved
= false;
2045 list_splice_init(&bo_va
->valids
, &bo_va
->invalids
);
2047 } else if (bo_va
->cleared
!= clear
) {
2048 list_splice_init(&bo_va
->valids
, &bo_va
->invalids
);
2051 list_for_each_entry(mapping
, &bo_va
->invalids
, list
) {
2052 r
= amdgpu_vm_bo_split_mapping(adev
, exclusive
, pages_addr
, vm
,
2053 mapping
, flags
, nodes
,
2059 if (vm
->use_cpu_for_update
) {
2062 amdgpu_asic_flush_hdp(adev
, NULL
);
2065 /* If the BO is not in its preferred location add it back to
2066 * the evicted list so that it gets validated again on the
2067 * next command submission.
2069 if (bo
&& bo
->tbo
.resv
== vm
->root
.base
.bo
->tbo
.resv
) {
2070 uint32_t mem_type
= bo
->tbo
.mem
.mem_type
;
2072 if (!(bo
->preferred_domains
& amdgpu_mem_type_to_domain(mem_type
)))
2073 amdgpu_vm_bo_evicted(&bo_va
->base
);
2075 amdgpu_vm_bo_idle(&bo_va
->base
);
2077 amdgpu_vm_bo_done(&bo_va
->base
);
2080 list_splice_init(&bo_va
->invalids
, &bo_va
->valids
);
2081 bo_va
->cleared
= clear
;
2083 if (trace_amdgpu_vm_bo_mapping_enabled()) {
2084 list_for_each_entry(mapping
, &bo_va
->valids
, list
)
2085 trace_amdgpu_vm_bo_mapping(mapping
);
2092 * amdgpu_vm_update_prt_state - update the global PRT state
2094 * @adev: amdgpu_device pointer
2096 static void amdgpu_vm_update_prt_state(struct amdgpu_device
*adev
)
2098 unsigned long flags
;
2101 spin_lock_irqsave(&adev
->vm_manager
.prt_lock
, flags
);
2102 enable
= !!atomic_read(&adev
->vm_manager
.num_prt_users
);
2103 adev
->gmc
.gmc_funcs
->set_prt(adev
, enable
);
2104 spin_unlock_irqrestore(&adev
->vm_manager
.prt_lock
, flags
);
2108 * amdgpu_vm_prt_get - add a PRT user
2110 * @adev: amdgpu_device pointer
2112 static void amdgpu_vm_prt_get(struct amdgpu_device
*adev
)
2114 if (!adev
->gmc
.gmc_funcs
->set_prt
)
2117 if (atomic_inc_return(&adev
->vm_manager
.num_prt_users
) == 1)
2118 amdgpu_vm_update_prt_state(adev
);
2122 * amdgpu_vm_prt_put - drop a PRT user
2124 * @adev: amdgpu_device pointer
2126 static void amdgpu_vm_prt_put(struct amdgpu_device
*adev
)
2128 if (atomic_dec_return(&adev
->vm_manager
.num_prt_users
) == 0)
2129 amdgpu_vm_update_prt_state(adev
);
2133 * amdgpu_vm_prt_cb - callback for updating the PRT status
2135 * @fence: fence for the callback
2136 * @_cb: the callback function
2138 static void amdgpu_vm_prt_cb(struct dma_fence
*fence
, struct dma_fence_cb
*_cb
)
2140 struct amdgpu_prt_cb
*cb
= container_of(_cb
, struct amdgpu_prt_cb
, cb
);
2142 amdgpu_vm_prt_put(cb
->adev
);
2147 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
2149 * @adev: amdgpu_device pointer
2150 * @fence: fence for the callback
2152 static void amdgpu_vm_add_prt_cb(struct amdgpu_device
*adev
,
2153 struct dma_fence
*fence
)
2155 struct amdgpu_prt_cb
*cb
;
2157 if (!adev
->gmc
.gmc_funcs
->set_prt
)
2160 cb
= kmalloc(sizeof(struct amdgpu_prt_cb
), GFP_KERNEL
);
2162 /* Last resort when we are OOM */
2164 dma_fence_wait(fence
, false);
2166 amdgpu_vm_prt_put(adev
);
2169 if (!fence
|| dma_fence_add_callback(fence
, &cb
->cb
,
2171 amdgpu_vm_prt_cb(fence
, &cb
->cb
);
2176 * amdgpu_vm_free_mapping - free a mapping
2178 * @adev: amdgpu_device pointer
2180 * @mapping: mapping to be freed
2181 * @fence: fence of the unmap operation
2183 * Free a mapping and make sure we decrease the PRT usage count if applicable.
2185 static void amdgpu_vm_free_mapping(struct amdgpu_device
*adev
,
2186 struct amdgpu_vm
*vm
,
2187 struct amdgpu_bo_va_mapping
*mapping
,
2188 struct dma_fence
*fence
)
2190 if (mapping
->flags
& AMDGPU_PTE_PRT
)
2191 amdgpu_vm_add_prt_cb(adev
, fence
);
2196 * amdgpu_vm_prt_fini - finish all prt mappings
2198 * @adev: amdgpu_device pointer
2201 * Register a cleanup callback to disable PRT support after VM dies.
2203 static void amdgpu_vm_prt_fini(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
2205 struct reservation_object
*resv
= vm
->root
.base
.bo
->tbo
.resv
;
2206 struct dma_fence
*excl
, **shared
;
2207 unsigned i
, shared_count
;
2210 r
= reservation_object_get_fences_rcu(resv
, &excl
,
2211 &shared_count
, &shared
);
2213 /* Not enough memory to grab the fence list, as last resort
2214 * block for all the fences to complete.
2216 reservation_object_wait_timeout_rcu(resv
, true, false,
2217 MAX_SCHEDULE_TIMEOUT
);
2221 /* Add a callback for each fence in the reservation object */
2222 amdgpu_vm_prt_get(adev
);
2223 amdgpu_vm_add_prt_cb(adev
, excl
);
2225 for (i
= 0; i
< shared_count
; ++i
) {
2226 amdgpu_vm_prt_get(adev
);
2227 amdgpu_vm_add_prt_cb(adev
, shared
[i
]);
2234 * amdgpu_vm_clear_freed - clear freed BOs in the PT
2236 * @adev: amdgpu_device pointer
2238 * @fence: optional resulting fence (unchanged if no work needed to be done
2239 * or if an error occurred)
2241 * Make sure all freed BOs are cleared in the PT.
2242 * PTs have to be reserved and mutex must be locked!
2248 int amdgpu_vm_clear_freed(struct amdgpu_device
*adev
,
2249 struct amdgpu_vm
*vm
,
2250 struct dma_fence
**fence
)
2252 struct amdgpu_bo_va_mapping
*mapping
;
2253 uint64_t init_pte_value
= 0;
2254 struct dma_fence
*f
= NULL
;
2257 while (!list_empty(&vm
->freed
)) {
2258 mapping
= list_first_entry(&vm
->freed
,
2259 struct amdgpu_bo_va_mapping
, list
);
2260 list_del(&mapping
->list
);
2262 if (vm
->pte_support_ats
&&
2263 mapping
->start
< AMDGPU_GMC_HOLE_START
)
2264 init_pte_value
= AMDGPU_PTE_DEFAULT_ATC
;
2266 r
= amdgpu_vm_bo_update_mapping(adev
, NULL
, NULL
, vm
,
2267 mapping
->start
, mapping
->last
,
2268 init_pte_value
, 0, &f
);
2269 amdgpu_vm_free_mapping(adev
, vm
, mapping
, f
);
2277 dma_fence_put(*fence
);
2288 * amdgpu_vm_handle_moved - handle moved BOs in the PT
2290 * @adev: amdgpu_device pointer
2293 * Make sure all BOs which are moved are updated in the PTs.
2298 * PTs have to be reserved!
2300 int amdgpu_vm_handle_moved(struct amdgpu_device
*adev
,
2301 struct amdgpu_vm
*vm
)
2303 struct amdgpu_bo_va
*bo_va
, *tmp
;
2304 struct reservation_object
*resv
;
2308 list_for_each_entry_safe(bo_va
, tmp
, &vm
->moved
, base
.vm_status
) {
2309 /* Per VM BOs never need to bo cleared in the page tables */
2310 r
= amdgpu_vm_bo_update(adev
, bo_va
, false);
2315 spin_lock(&vm
->invalidated_lock
);
2316 while (!list_empty(&vm
->invalidated
)) {
2317 bo_va
= list_first_entry(&vm
->invalidated
, struct amdgpu_bo_va
,
2319 resv
= bo_va
->base
.bo
->tbo
.resv
;
2320 spin_unlock(&vm
->invalidated_lock
);
2322 /* Try to reserve the BO to avoid clearing its ptes */
2323 if (!amdgpu_vm_debug
&& reservation_object_trylock(resv
))
2325 /* Somebody else is using the BO right now */
2329 r
= amdgpu_vm_bo_update(adev
, bo_va
, clear
);
2334 reservation_object_unlock(resv
);
2335 spin_lock(&vm
->invalidated_lock
);
2337 spin_unlock(&vm
->invalidated_lock
);
2343 * amdgpu_vm_bo_add - add a bo to a specific vm
2345 * @adev: amdgpu_device pointer
2347 * @bo: amdgpu buffer object
2349 * Add @bo into the requested vm.
2350 * Add @bo to the list of bos associated with the vm
2353 * Newly added bo_va or NULL for failure
2355 * Object has to be reserved!
2357 struct amdgpu_bo_va
*amdgpu_vm_bo_add(struct amdgpu_device
*adev
,
2358 struct amdgpu_vm
*vm
,
2359 struct amdgpu_bo
*bo
)
2361 struct amdgpu_bo_va
*bo_va
;
2363 bo_va
= kzalloc(sizeof(struct amdgpu_bo_va
), GFP_KERNEL
);
2364 if (bo_va
== NULL
) {
2367 amdgpu_vm_bo_base_init(&bo_va
->base
, vm
, bo
);
2369 bo_va
->ref_count
= 1;
2370 INIT_LIST_HEAD(&bo_va
->valids
);
2371 INIT_LIST_HEAD(&bo_va
->invalids
);
2378 * amdgpu_vm_bo_insert_mapping - insert a new mapping
2380 * @adev: amdgpu_device pointer
2381 * @bo_va: bo_va to store the address
2382 * @mapping: the mapping to insert
2384 * Insert a new mapping into all structures.
2386 static void amdgpu_vm_bo_insert_map(struct amdgpu_device
*adev
,
2387 struct amdgpu_bo_va
*bo_va
,
2388 struct amdgpu_bo_va_mapping
*mapping
)
2390 struct amdgpu_vm
*vm
= bo_va
->base
.vm
;
2391 struct amdgpu_bo
*bo
= bo_va
->base
.bo
;
2393 mapping
->bo_va
= bo_va
;
2394 list_add(&mapping
->list
, &bo_va
->invalids
);
2395 amdgpu_vm_it_insert(mapping
, &vm
->va
);
2397 if (mapping
->flags
& AMDGPU_PTE_PRT
)
2398 amdgpu_vm_prt_get(adev
);
2400 if (bo
&& bo
->tbo
.resv
== vm
->root
.base
.bo
->tbo
.resv
&&
2401 !bo_va
->base
.moved
) {
2402 list_move(&bo_va
->base
.vm_status
, &vm
->moved
);
2404 trace_amdgpu_vm_bo_map(bo_va
, mapping
);
2408 * amdgpu_vm_bo_map - map bo inside a vm
2410 * @adev: amdgpu_device pointer
2411 * @bo_va: bo_va to store the address
2412 * @saddr: where to map the BO
2413 * @offset: requested offset in the BO
2414 * @size: BO size in bytes
2415 * @flags: attributes of pages (read/write/valid/etc.)
2417 * Add a mapping of the BO at the specefied addr into the VM.
2420 * 0 for success, error for failure.
2422 * Object has to be reserved and unreserved outside!
2424 int amdgpu_vm_bo_map(struct amdgpu_device
*adev
,
2425 struct amdgpu_bo_va
*bo_va
,
2426 uint64_t saddr
, uint64_t offset
,
2427 uint64_t size
, uint64_t flags
)
2429 struct amdgpu_bo_va_mapping
*mapping
, *tmp
;
2430 struct amdgpu_bo
*bo
= bo_va
->base
.bo
;
2431 struct amdgpu_vm
*vm
= bo_va
->base
.vm
;
2434 /* validate the parameters */
2435 if (saddr
& AMDGPU_GPU_PAGE_MASK
|| offset
& AMDGPU_GPU_PAGE_MASK
||
2436 size
== 0 || size
& AMDGPU_GPU_PAGE_MASK
)
2439 /* make sure object fit at this offset */
2440 eaddr
= saddr
+ size
- 1;
2441 if (saddr
>= eaddr
||
2442 (bo
&& offset
+ size
> amdgpu_bo_size(bo
)))
2445 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
2446 eaddr
/= AMDGPU_GPU_PAGE_SIZE
;
2448 tmp
= amdgpu_vm_it_iter_first(&vm
->va
, saddr
, eaddr
);
2450 /* bo and tmp overlap, invalid addr */
2451 dev_err(adev
->dev
, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2452 "0x%010Lx-0x%010Lx\n", bo
, saddr
, eaddr
,
2453 tmp
->start
, tmp
->last
+ 1);
2457 mapping
= kmalloc(sizeof(*mapping
), GFP_KERNEL
);
2461 mapping
->start
= saddr
;
2462 mapping
->last
= eaddr
;
2463 mapping
->offset
= offset
;
2464 mapping
->flags
= flags
;
2466 amdgpu_vm_bo_insert_map(adev
, bo_va
, mapping
);
2472 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
2474 * @adev: amdgpu_device pointer
2475 * @bo_va: bo_va to store the address
2476 * @saddr: where to map the BO
2477 * @offset: requested offset in the BO
2478 * @size: BO size in bytes
2479 * @flags: attributes of pages (read/write/valid/etc.)
2481 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
2482 * mappings as we do so.
2485 * 0 for success, error for failure.
2487 * Object has to be reserved and unreserved outside!
2489 int amdgpu_vm_bo_replace_map(struct amdgpu_device
*adev
,
2490 struct amdgpu_bo_va
*bo_va
,
2491 uint64_t saddr
, uint64_t offset
,
2492 uint64_t size
, uint64_t flags
)
2494 struct amdgpu_bo_va_mapping
*mapping
;
2495 struct amdgpu_bo
*bo
= bo_va
->base
.bo
;
2499 /* validate the parameters */
2500 if (saddr
& AMDGPU_GPU_PAGE_MASK
|| offset
& AMDGPU_GPU_PAGE_MASK
||
2501 size
== 0 || size
& AMDGPU_GPU_PAGE_MASK
)
2504 /* make sure object fit at this offset */
2505 eaddr
= saddr
+ size
- 1;
2506 if (saddr
>= eaddr
||
2507 (bo
&& offset
+ size
> amdgpu_bo_size(bo
)))
2510 /* Allocate all the needed memory */
2511 mapping
= kmalloc(sizeof(*mapping
), GFP_KERNEL
);
2515 r
= amdgpu_vm_bo_clear_mappings(adev
, bo_va
->base
.vm
, saddr
, size
);
2521 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
2522 eaddr
/= AMDGPU_GPU_PAGE_SIZE
;
2524 mapping
->start
= saddr
;
2525 mapping
->last
= eaddr
;
2526 mapping
->offset
= offset
;
2527 mapping
->flags
= flags
;
2529 amdgpu_vm_bo_insert_map(adev
, bo_va
, mapping
);
2535 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2537 * @adev: amdgpu_device pointer
2538 * @bo_va: bo_va to remove the address from
2539 * @saddr: where to the BO is mapped
2541 * Remove a mapping of the BO at the specefied addr from the VM.
2544 * 0 for success, error for failure.
2546 * Object has to be reserved and unreserved outside!
2548 int amdgpu_vm_bo_unmap(struct amdgpu_device
*adev
,
2549 struct amdgpu_bo_va
*bo_va
,
2552 struct amdgpu_bo_va_mapping
*mapping
;
2553 struct amdgpu_vm
*vm
= bo_va
->base
.vm
;
2556 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
2558 list_for_each_entry(mapping
, &bo_va
->valids
, list
) {
2559 if (mapping
->start
== saddr
)
2563 if (&mapping
->list
== &bo_va
->valids
) {
2566 list_for_each_entry(mapping
, &bo_va
->invalids
, list
) {
2567 if (mapping
->start
== saddr
)
2571 if (&mapping
->list
== &bo_va
->invalids
)
2575 list_del(&mapping
->list
);
2576 amdgpu_vm_it_remove(mapping
, &vm
->va
);
2577 mapping
->bo_va
= NULL
;
2578 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
2581 list_add(&mapping
->list
, &vm
->freed
);
2583 amdgpu_vm_free_mapping(adev
, vm
, mapping
,
2584 bo_va
->last_pt_update
);
2590 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2592 * @adev: amdgpu_device pointer
2593 * @vm: VM structure to use
2594 * @saddr: start of the range
2595 * @size: size of the range
2597 * Remove all mappings in a range, split them as appropriate.
2600 * 0 for success, error for failure.
2602 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device
*adev
,
2603 struct amdgpu_vm
*vm
,
2604 uint64_t saddr
, uint64_t size
)
2606 struct amdgpu_bo_va_mapping
*before
, *after
, *tmp
, *next
;
2610 eaddr
= saddr
+ size
- 1;
2611 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
2612 eaddr
/= AMDGPU_GPU_PAGE_SIZE
;
2614 /* Allocate all the needed memory */
2615 before
= kzalloc(sizeof(*before
), GFP_KERNEL
);
2618 INIT_LIST_HEAD(&before
->list
);
2620 after
= kzalloc(sizeof(*after
), GFP_KERNEL
);
2625 INIT_LIST_HEAD(&after
->list
);
2627 /* Now gather all removed mappings */
2628 tmp
= amdgpu_vm_it_iter_first(&vm
->va
, saddr
, eaddr
);
2630 /* Remember mapping split at the start */
2631 if (tmp
->start
< saddr
) {
2632 before
->start
= tmp
->start
;
2633 before
->last
= saddr
- 1;
2634 before
->offset
= tmp
->offset
;
2635 before
->flags
= tmp
->flags
;
2636 before
->bo_va
= tmp
->bo_va
;
2637 list_add(&before
->list
, &tmp
->bo_va
->invalids
);
2640 /* Remember mapping split at the end */
2641 if (tmp
->last
> eaddr
) {
2642 after
->start
= eaddr
+ 1;
2643 after
->last
= tmp
->last
;
2644 after
->offset
= tmp
->offset
;
2645 after
->offset
+= after
->start
- tmp
->start
;
2646 after
->flags
= tmp
->flags
;
2647 after
->bo_va
= tmp
->bo_va
;
2648 list_add(&after
->list
, &tmp
->bo_va
->invalids
);
2651 list_del(&tmp
->list
);
2652 list_add(&tmp
->list
, &removed
);
2654 tmp
= amdgpu_vm_it_iter_next(tmp
, saddr
, eaddr
);
2657 /* And free them up */
2658 list_for_each_entry_safe(tmp
, next
, &removed
, list
) {
2659 amdgpu_vm_it_remove(tmp
, &vm
->va
);
2660 list_del(&tmp
->list
);
2662 if (tmp
->start
< saddr
)
2664 if (tmp
->last
> eaddr
)
2668 list_add(&tmp
->list
, &vm
->freed
);
2669 trace_amdgpu_vm_bo_unmap(NULL
, tmp
);
2672 /* Insert partial mapping before the range */
2673 if (!list_empty(&before
->list
)) {
2674 amdgpu_vm_it_insert(before
, &vm
->va
);
2675 if (before
->flags
& AMDGPU_PTE_PRT
)
2676 amdgpu_vm_prt_get(adev
);
2681 /* Insert partial mapping after the range */
2682 if (!list_empty(&after
->list
)) {
2683 amdgpu_vm_it_insert(after
, &vm
->va
);
2684 if (after
->flags
& AMDGPU_PTE_PRT
)
2685 amdgpu_vm_prt_get(adev
);
2694 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2696 * @vm: the requested VM
2697 * @addr: the address
2699 * Find a mapping by it's address.
2702 * The amdgpu_bo_va_mapping matching for addr or NULL
2705 struct amdgpu_bo_va_mapping
*amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm
*vm
,
2708 return amdgpu_vm_it_iter_first(&vm
->va
, addr
, addr
);
2712 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
2714 * @vm: the requested vm
2715 * @ticket: CS ticket
2717 * Trace all mappings of BOs reserved during a command submission.
2719 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm
*vm
, struct ww_acquire_ctx
*ticket
)
2721 struct amdgpu_bo_va_mapping
*mapping
;
2723 if (!trace_amdgpu_vm_bo_cs_enabled())
2726 for (mapping
= amdgpu_vm_it_iter_first(&vm
->va
, 0, U64_MAX
); mapping
;
2727 mapping
= amdgpu_vm_it_iter_next(mapping
, 0, U64_MAX
)) {
2728 if (mapping
->bo_va
&& mapping
->bo_va
->base
.bo
) {
2729 struct amdgpu_bo
*bo
;
2731 bo
= mapping
->bo_va
->base
.bo
;
2732 if (READ_ONCE(bo
->tbo
.resv
->lock
.ctx
) != ticket
)
2736 trace_amdgpu_vm_bo_cs(mapping
);
2741 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2743 * @adev: amdgpu_device pointer
2744 * @bo_va: requested bo_va
2746 * Remove @bo_va->bo from the requested vm.
2748 * Object have to be reserved!
2750 void amdgpu_vm_bo_rmv(struct amdgpu_device
*adev
,
2751 struct amdgpu_bo_va
*bo_va
)
2753 struct amdgpu_bo_va_mapping
*mapping
, *next
;
2754 struct amdgpu_bo
*bo
= bo_va
->base
.bo
;
2755 struct amdgpu_vm
*vm
= bo_va
->base
.vm
;
2756 struct amdgpu_vm_bo_base
**base
;
2759 if (bo
->tbo
.resv
== vm
->root
.base
.bo
->tbo
.resv
)
2760 vm
->bulk_moveable
= false;
2762 for (base
= &bo_va
->base
.bo
->vm_bo
; *base
;
2763 base
= &(*base
)->next
) {
2764 if (*base
!= &bo_va
->base
)
2767 *base
= bo_va
->base
.next
;
2772 spin_lock(&vm
->invalidated_lock
);
2773 list_del(&bo_va
->base
.vm_status
);
2774 spin_unlock(&vm
->invalidated_lock
);
2776 list_for_each_entry_safe(mapping
, next
, &bo_va
->valids
, list
) {
2777 list_del(&mapping
->list
);
2778 amdgpu_vm_it_remove(mapping
, &vm
->va
);
2779 mapping
->bo_va
= NULL
;
2780 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
2781 list_add(&mapping
->list
, &vm
->freed
);
2783 list_for_each_entry_safe(mapping
, next
, &bo_va
->invalids
, list
) {
2784 list_del(&mapping
->list
);
2785 amdgpu_vm_it_remove(mapping
, &vm
->va
);
2786 amdgpu_vm_free_mapping(adev
, vm
, mapping
,
2787 bo_va
->last_pt_update
);
2790 dma_fence_put(bo_va
->last_pt_update
);
2795 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2797 * @adev: amdgpu_device pointer
2798 * @bo: amdgpu buffer object
2799 * @evicted: is the BO evicted
2801 * Mark @bo as invalid.
2803 void amdgpu_vm_bo_invalidate(struct amdgpu_device
*adev
,
2804 struct amdgpu_bo
*bo
, bool evicted
)
2806 struct amdgpu_vm_bo_base
*bo_base
;
2808 /* shadow bo doesn't have bo base, its validation needs its parent */
2809 if (bo
->parent
&& bo
->parent
->shadow
== bo
)
2812 for (bo_base
= bo
->vm_bo
; bo_base
; bo_base
= bo_base
->next
) {
2813 struct amdgpu_vm
*vm
= bo_base
->vm
;
2815 if (evicted
&& bo
->tbo
.resv
== vm
->root
.base
.bo
->tbo
.resv
) {
2816 amdgpu_vm_bo_evicted(bo_base
);
2822 bo_base
->moved
= true;
2824 if (bo
->tbo
.type
== ttm_bo_type_kernel
)
2825 amdgpu_vm_bo_relocated(bo_base
);
2826 else if (bo
->tbo
.resv
== vm
->root
.base
.bo
->tbo
.resv
)
2827 amdgpu_vm_bo_moved(bo_base
);
2829 amdgpu_vm_bo_invalidated(bo_base
);
2834 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2839 * VM page table as power of two
2841 static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size
)
2843 /* Total bits covered by PD + PTs */
2844 unsigned bits
= ilog2(vm_size
) + 18;
2846 /* Make sure the PD is 4K in size up to 8GB address space.
2847 Above that split equal between PD and PTs */
2851 return ((bits
+ 3) / 2);
2855 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2857 * @adev: amdgpu_device pointer
2858 * @min_vm_size: the minimum vm size in GB if it's set auto
2859 * @fragment_size_default: Default PTE fragment size
2860 * @max_level: max VMPT level
2861 * @max_bits: max address space size in bits
2864 void amdgpu_vm_adjust_size(struct amdgpu_device
*adev
, uint32_t min_vm_size
,
2865 uint32_t fragment_size_default
, unsigned max_level
,
2868 unsigned int max_size
= 1 << (max_bits
- 30);
2869 unsigned int vm_size
;
2872 /* adjust vm size first */
2873 if (amdgpu_vm_size
!= -1) {
2874 vm_size
= amdgpu_vm_size
;
2875 if (vm_size
> max_size
) {
2876 dev_warn(adev
->dev
, "VM size (%d) too large, max is %u GB\n",
2877 amdgpu_vm_size
, max_size
);
2882 unsigned int phys_ram_gb
;
2884 /* Optimal VM size depends on the amount of physical
2885 * RAM available. Underlying requirements and
2888 * - Need to map system memory and VRAM from all GPUs
2889 * - VRAM from other GPUs not known here
2890 * - Assume VRAM <= system memory
2891 * - On GFX8 and older, VM space can be segmented for
2893 * - Need to allow room for fragmentation, guard pages etc.
2895 * This adds up to a rough guess of system memory x3.
2896 * Round up to power of two to maximize the available
2897 * VM size with the given page table size.
2900 phys_ram_gb
= ((uint64_t)si
.totalram
* si
.mem_unit
+
2901 (1 << 30) - 1) >> 30;
2902 vm_size
= roundup_pow_of_two(
2903 min(max(phys_ram_gb
* 3, min_vm_size
), max_size
));
2906 adev
->vm_manager
.max_pfn
= (uint64_t)vm_size
<< 18;
2908 tmp
= roundup_pow_of_two(adev
->vm_manager
.max_pfn
);
2909 if (amdgpu_vm_block_size
!= -1)
2910 tmp
>>= amdgpu_vm_block_size
- 9;
2911 tmp
= DIV_ROUND_UP(fls64(tmp
) - 1, 9) - 1;
2912 adev
->vm_manager
.num_level
= min(max_level
, (unsigned)tmp
);
2913 switch (adev
->vm_manager
.num_level
) {
2915 adev
->vm_manager
.root_level
= AMDGPU_VM_PDB2
;
2918 adev
->vm_manager
.root_level
= AMDGPU_VM_PDB1
;
2921 adev
->vm_manager
.root_level
= AMDGPU_VM_PDB0
;
2924 dev_err(adev
->dev
, "VMPT only supports 2~4+1 levels\n");
2926 /* block size depends on vm size and hw setup*/
2927 if (amdgpu_vm_block_size
!= -1)
2928 adev
->vm_manager
.block_size
=
2929 min((unsigned)amdgpu_vm_block_size
, max_bits
2930 - AMDGPU_GPU_PAGE_SHIFT
2931 - 9 * adev
->vm_manager
.num_level
);
2932 else if (adev
->vm_manager
.num_level
> 1)
2933 adev
->vm_manager
.block_size
= 9;
2935 adev
->vm_manager
.block_size
= amdgpu_vm_get_block_size(tmp
);
2937 if (amdgpu_vm_fragment_size
== -1)
2938 adev
->vm_manager
.fragment_size
= fragment_size_default
;
2940 adev
->vm_manager
.fragment_size
= amdgpu_vm_fragment_size
;
2942 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2943 vm_size
, adev
->vm_manager
.num_level
+ 1,
2944 adev
->vm_manager
.block_size
,
2945 adev
->vm_manager
.fragment_size
);
2948 static struct amdgpu_retryfault_hashtable
*init_fault_hash(void)
2950 struct amdgpu_retryfault_hashtable
*fault_hash
;
2952 fault_hash
= kmalloc(sizeof(*fault_hash
), GFP_KERNEL
);
2956 INIT_CHASH_TABLE(fault_hash
->hash
,
2957 AMDGPU_PAGEFAULT_HASH_BITS
, 8, 0);
2958 spin_lock_init(&fault_hash
->lock
);
2959 fault_hash
->count
= 0;
2965 * amdgpu_vm_init - initialize a vm instance
2967 * @adev: amdgpu_device pointer
2969 * @vm_context: Indicates if it GFX or Compute context
2970 * @pasid: Process address space identifier
2975 * 0 for success, error for failure.
2977 int amdgpu_vm_init(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
2978 int vm_context
, unsigned int pasid
)
2980 struct amdgpu_bo_param bp
;
2981 struct amdgpu_bo
*root
;
2984 vm
->va
= RB_ROOT_CACHED
;
2985 for (i
= 0; i
< AMDGPU_MAX_VMHUBS
; i
++)
2986 vm
->reserved_vmid
[i
] = NULL
;
2987 INIT_LIST_HEAD(&vm
->evicted
);
2988 INIT_LIST_HEAD(&vm
->relocated
);
2989 INIT_LIST_HEAD(&vm
->moved
);
2990 INIT_LIST_HEAD(&vm
->idle
);
2991 INIT_LIST_HEAD(&vm
->invalidated
);
2992 spin_lock_init(&vm
->invalidated_lock
);
2993 INIT_LIST_HEAD(&vm
->freed
);
2995 /* create scheduler entity for page table updates */
2996 r
= drm_sched_entity_init(&vm
->entity
, adev
->vm_manager
.vm_pte_rqs
,
2997 adev
->vm_manager
.vm_pte_num_rqs
, NULL
);
3001 vm
->pte_support_ats
= false;
3003 if (vm_context
== AMDGPU_VM_CONTEXT_COMPUTE
) {
3004 vm
->use_cpu_for_update
= !!(adev
->vm_manager
.vm_update_mode
&
3005 AMDGPU_VM_USE_CPU_FOR_COMPUTE
);
3007 if (adev
->asic_type
== CHIP_RAVEN
)
3008 vm
->pte_support_ats
= true;
3010 vm
->use_cpu_for_update
= !!(adev
->vm_manager
.vm_update_mode
&
3011 AMDGPU_VM_USE_CPU_FOR_GFX
);
3013 DRM_DEBUG_DRIVER("VM update mode is %s\n",
3014 vm
->use_cpu_for_update
? "CPU" : "SDMA");
3015 WARN_ONCE((vm
->use_cpu_for_update
&& !amdgpu_gmc_vram_full_visible(&adev
->gmc
)),
3016 "CPU update of VM recommended only for large BAR system\n");
3017 vm
->last_update
= NULL
;
3019 amdgpu_vm_bo_param(adev
, vm
, adev
->vm_manager
.root_level
, &bp
);
3020 if (vm_context
== AMDGPU_VM_CONTEXT_COMPUTE
)
3021 bp
.flags
&= ~AMDGPU_GEM_CREATE_SHADOW
;
3022 r
= amdgpu_bo_create(adev
, &bp
, &root
);
3024 goto error_free_sched_entity
;
3026 r
= amdgpu_bo_reserve(root
, true);
3028 goto error_free_root
;
3030 r
= reservation_object_reserve_shared(root
->tbo
.resv
, 1);
3032 goto error_unreserve
;
3034 r
= amdgpu_vm_clear_bo(adev
, vm
, root
,
3035 adev
->vm_manager
.root_level
,
3036 vm
->pte_support_ats
);
3038 goto error_unreserve
;
3040 amdgpu_vm_bo_base_init(&vm
->root
.base
, vm
, root
);
3041 amdgpu_bo_unreserve(vm
->root
.base
.bo
);
3044 unsigned long flags
;
3046 spin_lock_irqsave(&adev
->vm_manager
.pasid_lock
, flags
);
3047 r
= idr_alloc(&adev
->vm_manager
.pasid_idr
, vm
, pasid
, pasid
+ 1,
3049 spin_unlock_irqrestore(&adev
->vm_manager
.pasid_lock
, flags
);
3051 goto error_free_root
;
3056 vm
->fault_hash
= init_fault_hash();
3057 if (!vm
->fault_hash
) {
3059 goto error_free_root
;
3062 INIT_KFIFO(vm
->faults
);
3067 amdgpu_bo_unreserve(vm
->root
.base
.bo
);
3070 amdgpu_bo_unref(&vm
->root
.base
.bo
->shadow
);
3071 amdgpu_bo_unref(&vm
->root
.base
.bo
);
3072 vm
->root
.base
.bo
= NULL
;
3074 error_free_sched_entity
:
3075 drm_sched_entity_destroy(&vm
->entity
);
3081 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
3083 * @adev: amdgpu_device pointer
3086 * This only works on GFX VMs that don't have any BOs added and no
3087 * page tables allocated yet.
3089 * Changes the following VM parameters:
3090 * - use_cpu_for_update
3091 * - pte_supports_ats
3092 * - pasid (old PASID is released, because compute manages its own PASIDs)
3094 * Reinitializes the page directory to reflect the changed ATS
3098 * 0 for success, -errno for errors.
3100 int amdgpu_vm_make_compute(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
, unsigned int pasid
)
3102 bool pte_support_ats
= (adev
->asic_type
== CHIP_RAVEN
);
3105 r
= amdgpu_bo_reserve(vm
->root
.base
.bo
, true);
3110 if (!RB_EMPTY_ROOT(&vm
->va
.rb_root
) || vm
->root
.entries
) {
3116 unsigned long flags
;
3118 spin_lock_irqsave(&adev
->vm_manager
.pasid_lock
, flags
);
3119 r
= idr_alloc(&adev
->vm_manager
.pasid_idr
, vm
, pasid
, pasid
+ 1,
3121 spin_unlock_irqrestore(&adev
->vm_manager
.pasid_lock
, flags
);
3128 /* Check if PD needs to be reinitialized and do it before
3129 * changing any other state, in case it fails.
3131 if (pte_support_ats
!= vm
->pte_support_ats
) {
3132 r
= amdgpu_vm_clear_bo(adev
, vm
, vm
->root
.base
.bo
,
3133 adev
->vm_manager
.root_level
,
3139 /* Update VM state */
3140 vm
->use_cpu_for_update
= !!(adev
->vm_manager
.vm_update_mode
&
3141 AMDGPU_VM_USE_CPU_FOR_COMPUTE
);
3142 vm
->pte_support_ats
= pte_support_ats
;
3143 DRM_DEBUG_DRIVER("VM update mode is %s\n",
3144 vm
->use_cpu_for_update
? "CPU" : "SDMA");
3145 WARN_ONCE((vm
->use_cpu_for_update
&& !amdgpu_gmc_vram_full_visible(&adev
->gmc
)),
3146 "CPU update of VM recommended only for large BAR system\n");
3149 unsigned long flags
;
3151 spin_lock_irqsave(&adev
->vm_manager
.pasid_lock
, flags
);
3152 idr_remove(&adev
->vm_manager
.pasid_idr
, vm
->pasid
);
3153 spin_unlock_irqrestore(&adev
->vm_manager
.pasid_lock
, flags
);
3155 /* Free the original amdgpu allocated pasid
3156 * Will be replaced with kfd allocated pasid
3158 amdgpu_pasid_free(vm
->pasid
);
3162 /* Free the shadow bo for compute VM */
3163 amdgpu_bo_unref(&vm
->root
.base
.bo
->shadow
);
3172 unsigned long flags
;
3174 spin_lock_irqsave(&adev
->vm_manager
.pasid_lock
, flags
);
3175 idr_remove(&adev
->vm_manager
.pasid_idr
, pasid
);
3176 spin_unlock_irqrestore(&adev
->vm_manager
.pasid_lock
, flags
);
3179 amdgpu_bo_unreserve(vm
->root
.base
.bo
);
3184 * amdgpu_vm_release_compute - release a compute vm
3185 * @adev: amdgpu_device pointer
3186 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
3188 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
3189 * pasid from vm. Compute should stop use of vm after this call.
3191 void amdgpu_vm_release_compute(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
3194 unsigned long flags
;
3196 spin_lock_irqsave(&adev
->vm_manager
.pasid_lock
, flags
);
3197 idr_remove(&adev
->vm_manager
.pasid_idr
, vm
->pasid
);
3198 spin_unlock_irqrestore(&adev
->vm_manager
.pasid_lock
, flags
);
3204 * amdgpu_vm_fini - tear down a vm instance
3206 * @adev: amdgpu_device pointer
3210 * Unbind the VM and remove all bos from the vm bo list
3212 void amdgpu_vm_fini(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
3214 struct amdgpu_bo_va_mapping
*mapping
, *tmp
;
3215 bool prt_fini_needed
= !!adev
->gmc
.gmc_funcs
->set_prt
;
3216 struct amdgpu_bo
*root
;
3220 amdgpu_amdkfd_gpuvm_destroy_cb(adev
, vm
);
3222 /* Clear pending page faults from IH when the VM is destroyed */
3223 while (kfifo_get(&vm
->faults
, &fault
))
3224 amdgpu_vm_clear_fault(vm
->fault_hash
, fault
);
3227 unsigned long flags
;
3229 spin_lock_irqsave(&adev
->vm_manager
.pasid_lock
, flags
);
3230 idr_remove(&adev
->vm_manager
.pasid_idr
, vm
->pasid
);
3231 spin_unlock_irqrestore(&adev
->vm_manager
.pasid_lock
, flags
);
3234 kfree(vm
->fault_hash
);
3235 vm
->fault_hash
= NULL
;
3237 drm_sched_entity_destroy(&vm
->entity
);
3239 if (!RB_EMPTY_ROOT(&vm
->va
.rb_root
)) {
3240 dev_err(adev
->dev
, "still active bo inside vm\n");
3242 rbtree_postorder_for_each_entry_safe(mapping
, tmp
,
3243 &vm
->va
.rb_root
, rb
) {
3244 /* Don't remove the mapping here, we don't want to trigger a
3245 * rebalance and the tree is about to be destroyed anyway.
3247 list_del(&mapping
->list
);
3250 list_for_each_entry_safe(mapping
, tmp
, &vm
->freed
, list
) {
3251 if (mapping
->flags
& AMDGPU_PTE_PRT
&& prt_fini_needed
) {
3252 amdgpu_vm_prt_fini(adev
, vm
);
3253 prt_fini_needed
= false;
3256 list_del(&mapping
->list
);
3257 amdgpu_vm_free_mapping(adev
, vm
, mapping
, NULL
);
3260 root
= amdgpu_bo_ref(vm
->root
.base
.bo
);
3261 r
= amdgpu_bo_reserve(root
, true);
3263 dev_err(adev
->dev
, "Leaking page tables because BO reservation failed\n");
3265 amdgpu_vm_free_pts(adev
, vm
);
3266 amdgpu_bo_unreserve(root
);
3268 amdgpu_bo_unref(&root
);
3269 dma_fence_put(vm
->last_update
);
3270 for (i
= 0; i
< AMDGPU_MAX_VMHUBS
; i
++)
3271 amdgpu_vmid_free_reserved(adev
, vm
, i
);
3275 * amdgpu_vm_manager_init - init the VM manager
3277 * @adev: amdgpu_device pointer
3279 * Initialize the VM manager structures
3281 void amdgpu_vm_manager_init(struct amdgpu_device
*adev
)
3285 amdgpu_vmid_mgr_init(adev
);
3287 adev
->vm_manager
.fence_context
=
3288 dma_fence_context_alloc(AMDGPU_MAX_RINGS
);
3289 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
)
3290 adev
->vm_manager
.seqno
[i
] = 0;
3292 spin_lock_init(&adev
->vm_manager
.prt_lock
);
3293 atomic_set(&adev
->vm_manager
.num_prt_users
, 0);
3295 /* If not overridden by the user, by default, only in large BAR systems
3296 * Compute VM tables will be updated by CPU
3298 #ifdef CONFIG_X86_64
3299 if (amdgpu_vm_update_mode
== -1) {
3300 if (amdgpu_gmc_vram_full_visible(&adev
->gmc
))
3301 adev
->vm_manager
.vm_update_mode
=
3302 AMDGPU_VM_USE_CPU_FOR_COMPUTE
;
3304 adev
->vm_manager
.vm_update_mode
= 0;
3306 adev
->vm_manager
.vm_update_mode
= amdgpu_vm_update_mode
;
3308 adev
->vm_manager
.vm_update_mode
= 0;
3311 idr_init(&adev
->vm_manager
.pasid_idr
);
3312 spin_lock_init(&adev
->vm_manager
.pasid_lock
);
3316 * amdgpu_vm_manager_fini - cleanup VM manager
3318 * @adev: amdgpu_device pointer
3320 * Cleanup the VM manager and free resources.
3322 void amdgpu_vm_manager_fini(struct amdgpu_device
*adev
)
3324 WARN_ON(!idr_is_empty(&adev
->vm_manager
.pasid_idr
));
3325 idr_destroy(&adev
->vm_manager
.pasid_idr
);
3327 amdgpu_vmid_mgr_fini(adev
);
3331 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
3333 * @dev: drm device pointer
3334 * @data: drm_amdgpu_vm
3335 * @filp: drm file pointer
3338 * 0 for success, -errno for errors.
3340 int amdgpu_vm_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
)
3342 union drm_amdgpu_vm
*args
= data
;
3343 struct amdgpu_device
*adev
= dev
->dev_private
;
3344 struct amdgpu_fpriv
*fpriv
= filp
->driver_priv
;
3347 switch (args
->in
.op
) {
3348 case AMDGPU_VM_OP_RESERVE_VMID
:
3349 /* current, we only have requirement to reserve vmid from gfxhub */
3350 r
= amdgpu_vmid_alloc_reserved(adev
, &fpriv
->vm
, AMDGPU_GFXHUB
);
3354 case AMDGPU_VM_OP_UNRESERVE_VMID
:
3355 amdgpu_vmid_free_reserved(adev
, &fpriv
->vm
, AMDGPU_GFXHUB
);
3365 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
3367 * @adev: drm device pointer
3368 * @pasid: PASID identifier for VM
3369 * @task_info: task_info to fill.
3371 void amdgpu_vm_get_task_info(struct amdgpu_device
*adev
, unsigned int pasid
,
3372 struct amdgpu_task_info
*task_info
)
3374 struct amdgpu_vm
*vm
;
3375 unsigned long flags
;
3377 spin_lock_irqsave(&adev
->vm_manager
.pasid_lock
, flags
);
3379 vm
= idr_find(&adev
->vm_manager
.pasid_idr
, pasid
);
3381 *task_info
= vm
->task_info
;
3383 spin_unlock_irqrestore(&adev
->vm_manager
.pasid_lock
, flags
);
3387 * amdgpu_vm_set_task_info - Sets VMs task info.
3389 * @vm: vm for which to set the info
3391 void amdgpu_vm_set_task_info(struct amdgpu_vm
*vm
)
3393 if (!vm
->task_info
.pid
) {
3394 vm
->task_info
.pid
= current
->pid
;
3395 get_task_comm(vm
->task_info
.task_name
, current
);
3397 if (current
->group_leader
->mm
== current
->mm
) {
3398 vm
->task_info
.tgid
= current
->group_leader
->pid
;
3399 get_task_comm(vm
->task_info
.process_name
, current
->group_leader
);
3405 * amdgpu_vm_add_fault - Add a page fault record to fault hash table
3407 * @fault_hash: fault hash table
3408 * @key: 64-bit encoding of PASID and address
3410 * This should be called when a retry page fault interrupt is
3411 * received. If this is a new page fault, it will be added to a hash
3412 * table. The return value indicates whether this is a new fault, or
3413 * a fault that was already known and is already being handled.
3415 * If there are too many pending page faults, this will fail. Retry
3416 * interrupts should be ignored in this case until there is enough
3419 * Returns 0 if the fault was added, 1 if the fault was already known,
3420 * -ENOSPC if there are too many pending faults.
3422 int amdgpu_vm_add_fault(struct amdgpu_retryfault_hashtable
*fault_hash
, u64 key
)
3424 unsigned long flags
;
3427 if (WARN_ON_ONCE(!fault_hash
))
3428 /* Should be allocated in amdgpu_vm_init
3432 spin_lock_irqsave(&fault_hash
->lock
, flags
);
3434 /* Only let the hash table fill up to 50% for best performance */
3435 if (fault_hash
->count
>= (1 << (AMDGPU_PAGEFAULT_HASH_BITS
-1)))
3438 r
= chash_table_copy_in(&fault_hash
->hash
, key
, NULL
);
3440 fault_hash
->count
++;
3442 /* chash_table_copy_in should never fail unless we're losing count */
3443 WARN_ON_ONCE(r
< 0);
3446 spin_unlock_irqrestore(&fault_hash
->lock
, flags
);
3451 * amdgpu_vm_clear_fault - Remove a page fault record
3453 * @fault_hash: fault hash table
3454 * @key: 64-bit encoding of PASID and address
3456 * This should be called when a page fault has been handled. Any
3457 * future interrupt with this key will be processed as a new
3460 void amdgpu_vm_clear_fault(struct amdgpu_retryfault_hashtable
*fault_hash
, u64 key
)
3462 unsigned long flags
;
3468 spin_lock_irqsave(&fault_hash
->lock
, flags
);
3470 r
= chash_table_remove(&fault_hash
->hash
, key
, NULL
);
3471 if (!WARN_ON_ONCE(r
< 0)) {
3472 fault_hash
->count
--;
3473 WARN_ON_ONCE(fault_hash
->count
< 0);
3476 spin_unlock_irqrestore(&fault_hash
->lock
, flags
);