2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/dma-fence-array.h>
29 #include <linux/interval_tree_generic.h>
30 #include <linux/idr.h>
32 #include <drm/amdgpu_drm.h>
34 #include "amdgpu_trace.h"
39 * PASIDs are global address space identifiers that can be shared
40 * between the GPU, an IOMMU and the driver. VMs on different devices
41 * may use the same PASID if they share the same address
42 * space. Therefore PASIDs are allocated using a global IDA. VMs are
43 * looked up from the PASID per amdgpu_device.
45 static DEFINE_IDA(amdgpu_vm_pasid_ida
);
48 * amdgpu_vm_alloc_pasid - Allocate a PASID
49 * @bits: Maximum width of the PASID in bits, must be at least 1
51 * Allocates a PASID of the given width while keeping smaller PASIDs
52 * available if possible.
54 * Returns a positive integer on success. Returns %-EINVAL if bits==0.
55 * Returns %-ENOSPC if no PASID was available. Returns %-ENOMEM on
56 * memory allocation failure.
58 int amdgpu_vm_alloc_pasid(unsigned int bits
)
62 for (bits
= min(bits
, 31U); bits
> 0; bits
--) {
63 pasid
= ida_simple_get(&amdgpu_vm_pasid_ida
,
64 1U << (bits
- 1), 1U << bits
,
74 * amdgpu_vm_free_pasid - Free a PASID
75 * @pasid: PASID to free
77 void amdgpu_vm_free_pasid(unsigned int pasid
)
79 ida_simple_remove(&amdgpu_vm_pasid_ida
, pasid
);
84 * GPUVM is similar to the legacy gart on older asics, however
85 * rather than there being a single global gart table
86 * for the entire GPU, there are multiple VM page tables active
87 * at any given time. The VM page tables can contain a mix
88 * vram pages and system memory pages and system memory pages
89 * can be mapped as snooped (cached system pages) or unsnooped
90 * (uncached system pages).
91 * Each VM has an ID associated with it and there is a page table
92 * associated with each VMID. When execting a command buffer,
93 * the kernel tells the the ring what VMID to use for that command
94 * buffer. VMIDs are allocated dynamically as commands are submitted.
95 * The userspace drivers maintain their own address space and the kernel
96 * sets up their pages tables accordingly when they submit their
97 * command buffers and a VMID is assigned.
98 * Cayman/Trinity support up to 8 active VMs at any given time;
102 #define START(node) ((node)->start)
103 #define LAST(node) ((node)->last)
105 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping
, rb
, uint64_t, __subtree_last
,
106 START
, LAST
, static, amdgpu_vm_it
)
111 /* Local structure. Encapsulate some VM table update parameters to reduce
112 * the number of function parameters
114 struct amdgpu_pte_update_params
{
115 /* amdgpu device we do this update for */
116 struct amdgpu_device
*adev
;
117 /* optional amdgpu_vm we do this update for */
118 struct amdgpu_vm
*vm
;
119 /* address where to copy page table entries from */
121 /* indirect buffer to fill with commands */
122 struct amdgpu_ib
*ib
;
123 /* Function which actually does the update */
124 void (*func
)(struct amdgpu_pte_update_params
*params
, uint64_t pe
,
125 uint64_t addr
, unsigned count
, uint32_t incr
,
127 /* The next two are used during VM update by CPU
128 * DMA addresses to use for mapping
129 * Kernel pointer of PD/PT BO that needs to be updated
131 dma_addr_t
*pages_addr
;
135 /* Helper to disable partial resident texture feature from a fence callback */
136 struct amdgpu_prt_cb
{
137 struct amdgpu_device
*adev
;
138 struct dma_fence_cb cb
;
142 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
144 * @adev: amdgpu_device pointer
146 * Calculate the number of entries in a page directory or page table.
148 static unsigned amdgpu_vm_num_entries(struct amdgpu_device
*adev
,
152 /* For the root directory */
153 return adev
->vm_manager
.max_pfn
>>
154 (adev
->vm_manager
.block_size
*
155 adev
->vm_manager
.num_level
);
156 else if (level
== adev
->vm_manager
.num_level
)
157 /* For the page tables on the leaves */
158 return AMDGPU_VM_PTE_COUNT(adev
);
160 /* Everything in between */
161 return 1 << adev
->vm_manager
.block_size
;
165 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
167 * @adev: amdgpu_device pointer
169 * Calculate the size of the BO for a page directory or page table in bytes.
171 static unsigned amdgpu_vm_bo_size(struct amdgpu_device
*adev
, unsigned level
)
173 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev
, level
) * 8);
177 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
179 * @vm: vm providing the BOs
180 * @validated: head of validation list
181 * @entry: entry to add
183 * Add the page directory to the list of BOs to
184 * validate for command submission.
186 void amdgpu_vm_get_pd_bo(struct amdgpu_vm
*vm
,
187 struct list_head
*validated
,
188 struct amdgpu_bo_list_entry
*entry
)
190 entry
->robj
= vm
->root
.base
.bo
;
192 entry
->tv
.bo
= &entry
->robj
->tbo
;
193 entry
->tv
.shared
= true;
194 entry
->user_pages
= NULL
;
195 list_add(&entry
->tv
.head
, validated
);
199 * amdgpu_vm_validate_pt_bos - validate the page table BOs
201 * @adev: amdgpu device pointer
202 * @vm: vm providing the BOs
203 * @validate: callback to do the validation
204 * @param: parameter for the validation callback
206 * Validate the page table BOs on command submission if neccessary.
208 int amdgpu_vm_validate_pt_bos(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
209 int (*validate
)(void *p
, struct amdgpu_bo
*bo
),
212 struct ttm_bo_global
*glob
= adev
->mman
.bdev
.glob
;
215 spin_lock(&vm
->status_lock
);
216 while (!list_empty(&vm
->evicted
)) {
217 struct amdgpu_vm_bo_base
*bo_base
;
218 struct amdgpu_bo
*bo
;
220 bo_base
= list_first_entry(&vm
->evicted
,
221 struct amdgpu_vm_bo_base
,
223 spin_unlock(&vm
->status_lock
);
228 r
= validate(param
, bo
);
232 spin_lock(&glob
->lru_lock
);
233 ttm_bo_move_to_lru_tail(&bo
->tbo
);
235 ttm_bo_move_to_lru_tail(&bo
->shadow
->tbo
);
236 spin_unlock(&glob
->lru_lock
);
239 if (bo
->tbo
.type
== ttm_bo_type_kernel
&&
240 vm
->use_cpu_for_update
) {
241 r
= amdgpu_bo_kmap(bo
, NULL
);
246 spin_lock(&vm
->status_lock
);
247 if (bo
->tbo
.type
!= ttm_bo_type_kernel
)
248 list_move(&bo_base
->vm_status
, &vm
->moved
);
250 list_move(&bo_base
->vm_status
, &vm
->relocated
);
252 spin_unlock(&vm
->status_lock
);
258 * amdgpu_vm_ready - check VM is ready for updates
262 * Check if all VM PDs/PTs are ready for updates
264 bool amdgpu_vm_ready(struct amdgpu_vm
*vm
)
268 spin_lock(&vm
->status_lock
);
269 ready
= list_empty(&vm
->evicted
);
270 spin_unlock(&vm
->status_lock
);
276 * amdgpu_vm_alloc_levels - allocate the PD/PT levels
278 * @adev: amdgpu_device pointer
280 * @saddr: start of the address range
281 * @eaddr: end of the address range
283 * Make sure the page directories and page tables are allocated
285 static int amdgpu_vm_alloc_levels(struct amdgpu_device
*adev
,
286 struct amdgpu_vm
*vm
,
287 struct amdgpu_vm_pt
*parent
,
288 uint64_t saddr
, uint64_t eaddr
,
291 unsigned shift
= (adev
->vm_manager
.num_level
- level
) *
292 adev
->vm_manager
.block_size
;
293 unsigned pt_idx
, from
, to
;
296 uint64_t init_value
= 0;
298 if (!parent
->entries
) {
299 unsigned num_entries
= amdgpu_vm_num_entries(adev
, level
);
301 parent
->entries
= kvmalloc_array(num_entries
,
302 sizeof(struct amdgpu_vm_pt
),
303 GFP_KERNEL
| __GFP_ZERO
);
304 if (!parent
->entries
)
306 memset(parent
->entries
, 0 , sizeof(struct amdgpu_vm_pt
));
309 from
= saddr
>> shift
;
311 if (from
>= amdgpu_vm_num_entries(adev
, level
) ||
312 to
>= amdgpu_vm_num_entries(adev
, level
))
315 if (to
> parent
->last_entry_used
)
316 parent
->last_entry_used
= to
;
319 saddr
= saddr
& ((1 << shift
) - 1);
320 eaddr
= eaddr
& ((1 << shift
) - 1);
322 flags
= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
|
323 AMDGPU_GEM_CREATE_VRAM_CLEARED
;
324 if (vm
->use_cpu_for_update
)
325 flags
|= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
;
327 flags
|= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS
|
328 AMDGPU_GEM_CREATE_SHADOW
);
330 if (vm
->pte_support_ats
) {
331 init_value
= AMDGPU_PTE_SYSTEM
;
332 if (level
!= adev
->vm_manager
.num_level
- 1)
333 init_value
|= AMDGPU_PDE_PTE
;
336 /* walk over the address space and allocate the page tables */
337 for (pt_idx
= from
; pt_idx
<= to
; ++pt_idx
) {
338 struct reservation_object
*resv
= vm
->root
.base
.bo
->tbo
.resv
;
339 struct amdgpu_vm_pt
*entry
= &parent
->entries
[pt_idx
];
340 struct amdgpu_bo
*pt
;
342 if (!entry
->base
.bo
) {
343 r
= amdgpu_bo_create(adev
,
344 amdgpu_vm_bo_size(adev
, level
),
345 AMDGPU_GPU_PAGE_SIZE
, true,
346 AMDGPU_GEM_DOMAIN_VRAM
,
348 NULL
, resv
, init_value
, &pt
);
352 if (vm
->use_cpu_for_update
) {
353 r
= amdgpu_bo_kmap(pt
, NULL
);
355 amdgpu_bo_unref(&pt
);
360 /* Keep a reference to the root directory to avoid
361 * freeing them up in the wrong order.
363 pt
->parent
= amdgpu_bo_ref(parent
->base
.bo
);
367 list_add_tail(&entry
->base
.bo_list
, &pt
->va
);
368 spin_lock(&vm
->status_lock
);
369 list_add(&entry
->base
.vm_status
, &vm
->relocated
);
370 spin_unlock(&vm
->status_lock
);
374 if (level
< adev
->vm_manager
.num_level
) {
375 uint64_t sub_saddr
= (pt_idx
== from
) ? saddr
: 0;
376 uint64_t sub_eaddr
= (pt_idx
== to
) ? eaddr
:
378 r
= amdgpu_vm_alloc_levels(adev
, vm
, entry
, sub_saddr
,
389 * amdgpu_vm_alloc_pts - Allocate page tables.
391 * @adev: amdgpu_device pointer
392 * @vm: VM to allocate page tables for
393 * @saddr: Start address which needs to be allocated
394 * @size: Size from start address we need.
396 * Make sure the page tables are allocated.
398 int amdgpu_vm_alloc_pts(struct amdgpu_device
*adev
,
399 struct amdgpu_vm
*vm
,
400 uint64_t saddr
, uint64_t size
)
405 /* validate the parameters */
406 if (saddr
& AMDGPU_GPU_PAGE_MASK
|| size
& AMDGPU_GPU_PAGE_MASK
)
409 eaddr
= saddr
+ size
- 1;
410 last_pfn
= eaddr
/ AMDGPU_GPU_PAGE_SIZE
;
411 if (last_pfn
>= adev
->vm_manager
.max_pfn
) {
412 dev_err(adev
->dev
, "va above limit (0x%08llX >= 0x%08llX)\n",
413 last_pfn
, adev
->vm_manager
.max_pfn
);
417 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
418 eaddr
/= AMDGPU_GPU_PAGE_SIZE
;
420 return amdgpu_vm_alloc_levels(adev
, vm
, &vm
->root
, saddr
, eaddr
, 0);
424 * amdgpu_vm_had_gpu_reset - check if reset occured since last use
426 * @adev: amdgpu_device pointer
427 * @id: VMID structure
429 * Check if GPU reset occured since last use of the VMID.
431 static bool amdgpu_vm_had_gpu_reset(struct amdgpu_device
*adev
,
432 struct amdgpu_vm_id
*id
)
434 return id
->current_gpu_reset_count
!=
435 atomic_read(&adev
->gpu_reset_counter
);
438 static bool amdgpu_vm_reserved_vmid_ready(struct amdgpu_vm
*vm
, unsigned vmhub
)
440 return !!vm
->reserved_vmid
[vmhub
];
443 /* idr_mgr->lock must be held */
444 static int amdgpu_vm_grab_reserved_vmid_locked(struct amdgpu_vm
*vm
,
445 struct amdgpu_ring
*ring
,
446 struct amdgpu_sync
*sync
,
447 struct dma_fence
*fence
,
448 struct amdgpu_job
*job
)
450 struct amdgpu_device
*adev
= ring
->adev
;
451 unsigned vmhub
= ring
->funcs
->vmhub
;
452 uint64_t fence_context
= adev
->fence_context
+ ring
->idx
;
453 struct amdgpu_vm_id
*id
= vm
->reserved_vmid
[vmhub
];
454 struct amdgpu_vm_id_manager
*id_mgr
= &adev
->vm_manager
.id_mgr
[vmhub
];
455 struct dma_fence
*updates
= sync
->last_vm_update
;
457 struct dma_fence
*flushed
, *tmp
;
458 bool needs_flush
= vm
->use_cpu_for_update
;
460 flushed
= id
->flushed_updates
;
461 if ((amdgpu_vm_had_gpu_reset(adev
, id
)) ||
462 (atomic64_read(&id
->owner
) != vm
->client_id
) ||
463 (job
->vm_pd_addr
!= id
->pd_gpu_addr
) ||
464 (updates
&& (!flushed
|| updates
->context
!= flushed
->context
||
465 dma_fence_is_later(updates
, flushed
))) ||
466 (!id
->last_flush
|| (id
->last_flush
->context
!= fence_context
&&
467 !dma_fence_is_signaled(id
->last_flush
)))) {
469 /* to prevent one context starved by another context */
471 tmp
= amdgpu_sync_peek_fence(&id
->active
, ring
);
473 r
= amdgpu_sync_fence(adev
, sync
, tmp
);
478 /* Good we can use this VMID. Remember this submission as
481 r
= amdgpu_sync_fence(ring
->adev
, &id
->active
, fence
);
485 if (updates
&& (!flushed
|| updates
->context
!= flushed
->context
||
486 dma_fence_is_later(updates
, flushed
))) {
487 dma_fence_put(id
->flushed_updates
);
488 id
->flushed_updates
= dma_fence_get(updates
);
490 id
->pd_gpu_addr
= job
->vm_pd_addr
;
491 atomic64_set(&id
->owner
, vm
->client_id
);
492 job
->vm_needs_flush
= needs_flush
;
494 dma_fence_put(id
->last_flush
);
495 id
->last_flush
= NULL
;
497 job
->vm_id
= id
- id_mgr
->ids
;
498 trace_amdgpu_vm_grab_id(vm
, ring
, job
);
504 * amdgpu_vm_grab_id - allocate the next free VMID
506 * @vm: vm to allocate id for
507 * @ring: ring we want to submit job to
508 * @sync: sync object where we add dependencies
509 * @fence: fence protecting ID from reuse
511 * Allocate an id for the vm, adding fences to the sync obj as necessary.
513 int amdgpu_vm_grab_id(struct amdgpu_vm
*vm
, struct amdgpu_ring
*ring
,
514 struct amdgpu_sync
*sync
, struct dma_fence
*fence
,
515 struct amdgpu_job
*job
)
517 struct amdgpu_device
*adev
= ring
->adev
;
518 unsigned vmhub
= ring
->funcs
->vmhub
;
519 struct amdgpu_vm_id_manager
*id_mgr
= &adev
->vm_manager
.id_mgr
[vmhub
];
520 uint64_t fence_context
= adev
->fence_context
+ ring
->idx
;
521 struct dma_fence
*updates
= sync
->last_vm_update
;
522 struct amdgpu_vm_id
*id
, *idle
;
523 struct dma_fence
**fences
;
527 mutex_lock(&id_mgr
->lock
);
528 if (amdgpu_vm_reserved_vmid_ready(vm
, vmhub
)) {
529 r
= amdgpu_vm_grab_reserved_vmid_locked(vm
, ring
, sync
, fence
, job
);
530 mutex_unlock(&id_mgr
->lock
);
533 fences
= kmalloc_array(sizeof(void *), id_mgr
->num_ids
, GFP_KERNEL
);
535 mutex_unlock(&id_mgr
->lock
);
538 /* Check if we have an idle VMID */
540 list_for_each_entry(idle
, &id_mgr
->ids_lru
, list
) {
541 fences
[i
] = amdgpu_sync_peek_fence(&idle
->active
, ring
);
547 /* If we can't find a idle VMID to use, wait till one becomes available */
548 if (&idle
->list
== &id_mgr
->ids_lru
) {
549 u64 fence_context
= adev
->vm_manager
.fence_context
+ ring
->idx
;
550 unsigned seqno
= ++adev
->vm_manager
.seqno
[ring
->idx
];
551 struct dma_fence_array
*array
;
554 for (j
= 0; j
< i
; ++j
)
555 dma_fence_get(fences
[j
]);
557 array
= dma_fence_array_create(i
, fences
, fence_context
,
560 for (j
= 0; j
< i
; ++j
)
561 dma_fence_put(fences
[j
]);
568 r
= amdgpu_sync_fence(ring
->adev
, sync
, &array
->base
);
569 dma_fence_put(&array
->base
);
573 mutex_unlock(&id_mgr
->lock
);
579 job
->vm_needs_flush
= vm
->use_cpu_for_update
;
580 /* Check if we can use a VMID already assigned to this VM */
581 list_for_each_entry_reverse(id
, &id_mgr
->ids_lru
, list
) {
582 struct dma_fence
*flushed
;
583 bool needs_flush
= vm
->use_cpu_for_update
;
585 /* Check all the prerequisites to using this VMID */
586 if (amdgpu_vm_had_gpu_reset(adev
, id
))
589 if (atomic64_read(&id
->owner
) != vm
->client_id
)
592 if (job
->vm_pd_addr
!= id
->pd_gpu_addr
)
595 if (!id
->last_flush
||
596 (id
->last_flush
->context
!= fence_context
&&
597 !dma_fence_is_signaled(id
->last_flush
)))
600 flushed
= id
->flushed_updates
;
601 if (updates
&& (!flushed
|| dma_fence_is_later(updates
, flushed
)))
604 /* Concurrent flushes are only possible starting with Vega10 */
605 if (adev
->asic_type
< CHIP_VEGA10
&& needs_flush
)
608 /* Good we can use this VMID. Remember this submission as
611 r
= amdgpu_sync_fence(ring
->adev
, &id
->active
, fence
);
615 if (updates
&& (!flushed
|| dma_fence_is_later(updates
, flushed
))) {
616 dma_fence_put(id
->flushed_updates
);
617 id
->flushed_updates
= dma_fence_get(updates
);
623 goto no_flush_needed
;
627 /* Still no ID to use? Then use the idle one found earlier */
630 /* Remember this submission as user of the VMID */
631 r
= amdgpu_sync_fence(ring
->adev
, &id
->active
, fence
);
635 id
->pd_gpu_addr
= job
->vm_pd_addr
;
636 dma_fence_put(id
->flushed_updates
);
637 id
->flushed_updates
= dma_fence_get(updates
);
638 atomic64_set(&id
->owner
, vm
->client_id
);
641 job
->vm_needs_flush
= true;
642 dma_fence_put(id
->last_flush
);
643 id
->last_flush
= NULL
;
646 list_move_tail(&id
->list
, &id_mgr
->ids_lru
);
648 job
->vm_id
= id
- id_mgr
->ids
;
649 trace_amdgpu_vm_grab_id(vm
, ring
, job
);
652 mutex_unlock(&id_mgr
->lock
);
656 static void amdgpu_vm_free_reserved_vmid(struct amdgpu_device
*adev
,
657 struct amdgpu_vm
*vm
,
660 struct amdgpu_vm_id_manager
*id_mgr
= &adev
->vm_manager
.id_mgr
[vmhub
];
662 mutex_lock(&id_mgr
->lock
);
663 if (vm
->reserved_vmid
[vmhub
]) {
664 list_add(&vm
->reserved_vmid
[vmhub
]->list
,
666 vm
->reserved_vmid
[vmhub
] = NULL
;
667 atomic_dec(&id_mgr
->reserved_vmid_num
);
669 mutex_unlock(&id_mgr
->lock
);
672 static int amdgpu_vm_alloc_reserved_vmid(struct amdgpu_device
*adev
,
673 struct amdgpu_vm
*vm
,
676 struct amdgpu_vm_id_manager
*id_mgr
;
677 struct amdgpu_vm_id
*idle
;
680 id_mgr
= &adev
->vm_manager
.id_mgr
[vmhub
];
681 mutex_lock(&id_mgr
->lock
);
682 if (vm
->reserved_vmid
[vmhub
])
684 if (atomic_inc_return(&id_mgr
->reserved_vmid_num
) >
685 AMDGPU_VM_MAX_RESERVED_VMID
) {
686 DRM_ERROR("Over limitation of reserved vmid\n");
687 atomic_dec(&id_mgr
->reserved_vmid_num
);
691 /* Select the first entry VMID */
692 idle
= list_first_entry(&id_mgr
->ids_lru
, struct amdgpu_vm_id
, list
);
693 list_del_init(&idle
->list
);
694 vm
->reserved_vmid
[vmhub
] = idle
;
695 mutex_unlock(&id_mgr
->lock
);
699 mutex_unlock(&id_mgr
->lock
);
704 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
706 * @adev: amdgpu_device pointer
708 void amdgpu_vm_check_compute_bug(struct amdgpu_device
*adev
)
710 const struct amdgpu_ip_block
*ip_block
;
711 bool has_compute_vm_bug
;
712 struct amdgpu_ring
*ring
;
715 has_compute_vm_bug
= false;
717 ip_block
= amdgpu_get_ip_block(adev
, AMD_IP_BLOCK_TYPE_GFX
);
719 /* Compute has a VM bug for GFX version < 7.
720 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
721 if (ip_block
->version
->major
<= 7)
722 has_compute_vm_bug
= true;
723 else if (ip_block
->version
->major
== 8)
724 if (adev
->gfx
.mec_fw_version
< 673)
725 has_compute_vm_bug
= true;
728 for (i
= 0; i
< adev
->num_rings
; i
++) {
729 ring
= adev
->rings
[i
];
730 if (ring
->funcs
->type
== AMDGPU_RING_TYPE_COMPUTE
)
731 /* only compute rings */
732 ring
->has_compute_vm_bug
= has_compute_vm_bug
;
734 ring
->has_compute_vm_bug
= false;
738 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring
*ring
,
739 struct amdgpu_job
*job
)
741 struct amdgpu_device
*adev
= ring
->adev
;
742 unsigned vmhub
= ring
->funcs
->vmhub
;
743 struct amdgpu_vm_id_manager
*id_mgr
= &adev
->vm_manager
.id_mgr
[vmhub
];
744 struct amdgpu_vm_id
*id
;
745 bool gds_switch_needed
;
746 bool vm_flush_needed
= job
->vm_needs_flush
|| ring
->has_compute_vm_bug
;
750 id
= &id_mgr
->ids
[job
->vm_id
];
751 gds_switch_needed
= ring
->funcs
->emit_gds_switch
&& (
752 id
->gds_base
!= job
->gds_base
||
753 id
->gds_size
!= job
->gds_size
||
754 id
->gws_base
!= job
->gws_base
||
755 id
->gws_size
!= job
->gws_size
||
756 id
->oa_base
!= job
->oa_base
||
757 id
->oa_size
!= job
->oa_size
);
759 if (amdgpu_vm_had_gpu_reset(adev
, id
))
762 return vm_flush_needed
|| gds_switch_needed
;
765 static bool amdgpu_vm_is_large_bar(struct amdgpu_device
*adev
)
767 return (adev
->mc
.real_vram_size
== adev
->mc
.visible_vram_size
);
771 * amdgpu_vm_flush - hardware flush the vm
773 * @ring: ring to use for flush
774 * @vm_id: vmid number to use
775 * @pd_addr: address of the page directory
777 * Emit a VM flush when it is necessary.
779 int amdgpu_vm_flush(struct amdgpu_ring
*ring
, struct amdgpu_job
*job
, bool need_pipe_sync
)
781 struct amdgpu_device
*adev
= ring
->adev
;
782 unsigned vmhub
= ring
->funcs
->vmhub
;
783 struct amdgpu_vm_id_manager
*id_mgr
= &adev
->vm_manager
.id_mgr
[vmhub
];
784 struct amdgpu_vm_id
*id
= &id_mgr
->ids
[job
->vm_id
];
785 bool gds_switch_needed
= ring
->funcs
->emit_gds_switch
&& (
786 id
->gds_base
!= job
->gds_base
||
787 id
->gds_size
!= job
->gds_size
||
788 id
->gws_base
!= job
->gws_base
||
789 id
->gws_size
!= job
->gws_size
||
790 id
->oa_base
!= job
->oa_base
||
791 id
->oa_size
!= job
->oa_size
);
792 bool vm_flush_needed
= job
->vm_needs_flush
;
793 unsigned patch_offset
= 0;
796 if (amdgpu_vm_had_gpu_reset(adev
, id
)) {
797 gds_switch_needed
= true;
798 vm_flush_needed
= true;
801 if (!vm_flush_needed
&& !gds_switch_needed
&& !need_pipe_sync
)
804 if (ring
->funcs
->init_cond_exec
)
805 patch_offset
= amdgpu_ring_init_cond_exec(ring
);
808 amdgpu_ring_emit_pipeline_sync(ring
);
810 if (ring
->funcs
->emit_vm_flush
&& vm_flush_needed
) {
811 struct dma_fence
*fence
;
813 trace_amdgpu_vm_flush(ring
, job
->vm_id
, job
->vm_pd_addr
);
814 amdgpu_ring_emit_vm_flush(ring
, job
->vm_id
, job
->vm_pd_addr
);
816 r
= amdgpu_fence_emit(ring
, &fence
);
820 mutex_lock(&id_mgr
->lock
);
821 dma_fence_put(id
->last_flush
);
822 id
->last_flush
= fence
;
823 id
->current_gpu_reset_count
= atomic_read(&adev
->gpu_reset_counter
);
824 mutex_unlock(&id_mgr
->lock
);
827 if (ring
->funcs
->emit_gds_switch
&& gds_switch_needed
) {
828 id
->gds_base
= job
->gds_base
;
829 id
->gds_size
= job
->gds_size
;
830 id
->gws_base
= job
->gws_base
;
831 id
->gws_size
= job
->gws_size
;
832 id
->oa_base
= job
->oa_base
;
833 id
->oa_size
= job
->oa_size
;
834 amdgpu_ring_emit_gds_switch(ring
, job
->vm_id
, job
->gds_base
,
835 job
->gds_size
, job
->gws_base
,
836 job
->gws_size
, job
->oa_base
,
840 if (ring
->funcs
->patch_cond_exec
)
841 amdgpu_ring_patch_cond_exec(ring
, patch_offset
);
843 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
844 if (ring
->funcs
->emit_switch_buffer
) {
845 amdgpu_ring_emit_switch_buffer(ring
);
846 amdgpu_ring_emit_switch_buffer(ring
);
852 * amdgpu_vm_reset_id - reset VMID to zero
854 * @adev: amdgpu device structure
855 * @vm_id: vmid number to use
857 * Reset saved GDW, GWS and OA to force switch on next flush.
859 void amdgpu_vm_reset_id(struct amdgpu_device
*adev
, unsigned vmhub
,
862 struct amdgpu_vm_id_manager
*id_mgr
= &adev
->vm_manager
.id_mgr
[vmhub
];
863 struct amdgpu_vm_id
*id
= &id_mgr
->ids
[vmid
];
865 atomic64_set(&id
->owner
, 0);
875 * amdgpu_vm_reset_all_id - reset VMID to zero
877 * @adev: amdgpu device structure
879 * Reset VMID to force flush on next use
881 void amdgpu_vm_reset_all_ids(struct amdgpu_device
*adev
)
885 for (i
= 0; i
< AMDGPU_MAX_VMHUBS
; ++i
) {
886 struct amdgpu_vm_id_manager
*id_mgr
=
887 &adev
->vm_manager
.id_mgr
[i
];
889 for (j
= 1; j
< id_mgr
->num_ids
; ++j
)
890 amdgpu_vm_reset_id(adev
, i
, j
);
895 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
898 * @bo: requested buffer object
900 * Find @bo inside the requested vm.
901 * Search inside the @bos vm list for the requested vm
902 * Returns the found bo_va or NULL if none is found
904 * Object has to be reserved!
906 struct amdgpu_bo_va
*amdgpu_vm_bo_find(struct amdgpu_vm
*vm
,
907 struct amdgpu_bo
*bo
)
909 struct amdgpu_bo_va
*bo_va
;
911 list_for_each_entry(bo_va
, &bo
->va
, base
.bo_list
) {
912 if (bo_va
->base
.vm
== vm
) {
920 * amdgpu_vm_do_set_ptes - helper to call the right asic function
922 * @params: see amdgpu_pte_update_params definition
923 * @pe: addr of the page entry
924 * @addr: dst addr to write into pe
925 * @count: number of page entries to update
926 * @incr: increase next addr by incr bytes
927 * @flags: hw access flags
929 * Traces the parameters and calls the right asic functions
930 * to setup the page table using the DMA.
932 static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params
*params
,
933 uint64_t pe
, uint64_t addr
,
934 unsigned count
, uint32_t incr
,
937 trace_amdgpu_vm_set_ptes(pe
, addr
, count
, incr
, flags
);
940 amdgpu_vm_write_pte(params
->adev
, params
->ib
, pe
,
941 addr
| flags
, count
, incr
);
944 amdgpu_vm_set_pte_pde(params
->adev
, params
->ib
, pe
, addr
,
950 * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART
952 * @params: see amdgpu_pte_update_params definition
953 * @pe: addr of the page entry
954 * @addr: dst addr to write into pe
955 * @count: number of page entries to update
956 * @incr: increase next addr by incr bytes
957 * @flags: hw access flags
959 * Traces the parameters and calls the DMA function to copy the PTEs.
961 static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params
*params
,
962 uint64_t pe
, uint64_t addr
,
963 unsigned count
, uint32_t incr
,
966 uint64_t src
= (params
->src
+ (addr
>> 12) * 8);
969 trace_amdgpu_vm_copy_ptes(pe
, src
, count
);
971 amdgpu_vm_copy_pte(params
->adev
, params
->ib
, pe
, src
, count
);
975 * amdgpu_vm_map_gart - Resolve gart mapping of addr
977 * @pages_addr: optional DMA address to use for lookup
978 * @addr: the unmapped addr
980 * Look up the physical address of the page that the pte resolves
981 * to and return the pointer for the page table entry.
983 static uint64_t amdgpu_vm_map_gart(const dma_addr_t
*pages_addr
, uint64_t addr
)
987 /* page table offset */
988 result
= pages_addr
[addr
>> PAGE_SHIFT
];
990 /* in case cpu page size != gpu page size*/
991 result
|= addr
& (~PAGE_MASK
);
993 result
&= 0xFFFFFFFFFFFFF000ULL
;
999 * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU
1001 * @params: see amdgpu_pte_update_params definition
1002 * @pe: kmap addr of the page entry
1003 * @addr: dst addr to write into pe
1004 * @count: number of page entries to update
1005 * @incr: increase next addr by incr bytes
1006 * @flags: hw access flags
1008 * Write count number of PT/PD entries directly.
1010 static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params
*params
,
1011 uint64_t pe
, uint64_t addr
,
1012 unsigned count
, uint32_t incr
,
1018 trace_amdgpu_vm_set_ptes(pe
, addr
, count
, incr
, flags
);
1020 for (i
= 0; i
< count
; i
++) {
1021 value
= params
->pages_addr
?
1022 amdgpu_vm_map_gart(params
->pages_addr
, addr
) :
1024 amdgpu_gart_set_pte_pde(params
->adev
, (void *)(uintptr_t)pe
,
1030 static int amdgpu_vm_wait_pd(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
1033 struct amdgpu_sync sync
;
1036 amdgpu_sync_create(&sync
);
1037 amdgpu_sync_resv(adev
, &sync
, vm
->root
.base
.bo
->tbo
.resv
, owner
);
1038 r
= amdgpu_sync_wait(&sync
, true);
1039 amdgpu_sync_free(&sync
);
1045 * amdgpu_vm_update_level - update a single level in the hierarchy
1047 * @adev: amdgpu_device pointer
1049 * @parent: parent directory
1051 * Makes sure all entries in @parent are up to date.
1052 * Returns 0 for success, error for failure.
1054 static int amdgpu_vm_update_level(struct amdgpu_device
*adev
,
1055 struct amdgpu_vm
*vm
,
1056 struct amdgpu_vm_pt
*parent
)
1058 struct amdgpu_bo
*shadow
;
1059 struct amdgpu_ring
*ring
= NULL
;
1060 uint64_t pd_addr
, shadow_addr
= 0;
1061 uint64_t last_pde
= ~0, last_pt
= ~0, last_shadow
= ~0;
1062 unsigned count
= 0, pt_idx
, ndw
= 0;
1063 struct amdgpu_job
*job
;
1064 struct amdgpu_pte_update_params params
;
1065 struct dma_fence
*fence
= NULL
;
1070 if (!parent
->entries
)
1073 memset(¶ms
, 0, sizeof(params
));
1075 shadow
= parent
->base
.bo
->shadow
;
1077 if (vm
->use_cpu_for_update
) {
1078 pd_addr
= (unsigned long)amdgpu_bo_kptr(parent
->base
.bo
);
1079 r
= amdgpu_vm_wait_pd(adev
, vm
, AMDGPU_FENCE_OWNER_VM
);
1083 params
.func
= amdgpu_vm_cpu_set_ptes
;
1085 ring
= container_of(vm
->entity
.sched
, struct amdgpu_ring
,
1091 /* assume the worst case */
1092 ndw
+= parent
->last_entry_used
* 6;
1094 pd_addr
= amdgpu_bo_gpu_offset(parent
->base
.bo
);
1097 shadow_addr
= amdgpu_bo_gpu_offset(shadow
);
1103 r
= amdgpu_job_alloc_with_ib(adev
, ndw
* 4, &job
);
1107 params
.ib
= &job
->ibs
[0];
1108 params
.func
= amdgpu_vm_do_set_ptes
;
1112 /* walk over the address space and update the directory */
1113 for (pt_idx
= 0; pt_idx
<= parent
->last_entry_used
; ++pt_idx
) {
1114 struct amdgpu_vm_pt
*entry
= &parent
->entries
[pt_idx
];
1115 struct amdgpu_bo
*bo
= entry
->base
.bo
;
1121 spin_lock(&vm
->status_lock
);
1122 list_del_init(&entry
->base
.vm_status
);
1123 spin_unlock(&vm
->status_lock
);
1125 pt
= amdgpu_bo_gpu_offset(bo
);
1126 pt
= amdgpu_gart_get_vm_pde(adev
, pt
);
1127 /* Don't update huge pages here */
1128 if ((parent
->entries
[pt_idx
].addr
& AMDGPU_PDE_PTE
) ||
1129 parent
->entries
[pt_idx
].addr
== (pt
| AMDGPU_PTE_VALID
))
1132 parent
->entries
[pt_idx
].addr
= pt
| AMDGPU_PTE_VALID
;
1134 pde
= pd_addr
+ pt_idx
* 8;
1135 incr
= amdgpu_bo_size(bo
);
1136 if (((last_pde
+ 8 * count
) != pde
) ||
1137 ((last_pt
+ incr
* count
) != pt
) ||
1138 (count
== AMDGPU_VM_MAX_UPDATE_SIZE
)) {
1142 params
.func(¶ms
,
1148 params
.func(¶ms
, last_pde
,
1149 last_pt
, count
, incr
,
1155 last_shadow
= shadow_addr
+ pt_idx
* 8;
1163 if (vm
->root
.base
.bo
->shadow
)
1164 params
.func(¶ms
, last_shadow
, last_pt
,
1165 count
, incr
, AMDGPU_PTE_VALID
);
1167 params
.func(¶ms
, last_pde
, last_pt
,
1168 count
, incr
, AMDGPU_PTE_VALID
);
1171 if (!vm
->use_cpu_for_update
) {
1172 if (params
.ib
->length_dw
== 0) {
1173 amdgpu_job_free(job
);
1175 amdgpu_ring_pad_ib(ring
, params
.ib
);
1176 amdgpu_sync_resv(adev
, &job
->sync
,
1177 parent
->base
.bo
->tbo
.resv
,
1178 AMDGPU_FENCE_OWNER_VM
);
1180 amdgpu_sync_resv(adev
, &job
->sync
,
1182 AMDGPU_FENCE_OWNER_VM
);
1184 WARN_ON(params
.ib
->length_dw
> ndw
);
1185 r
= amdgpu_job_submit(job
, ring
, &vm
->entity
,
1186 AMDGPU_FENCE_OWNER_VM
, &fence
);
1190 amdgpu_bo_fence(parent
->base
.bo
, fence
, true);
1191 dma_fence_put(vm
->last_update
);
1192 vm
->last_update
= fence
;
1199 amdgpu_job_free(job
);
1204 * amdgpu_vm_invalidate_level - mark all PD levels as invalid
1206 * @parent: parent PD
1208 * Mark all PD level as invalid after an error.
1210 static void amdgpu_vm_invalidate_level(struct amdgpu_vm
*vm
,
1211 struct amdgpu_vm_pt
*parent
)
1216 * Recurse into the subdirectories. This recursion is harmless because
1217 * we only have a maximum of 5 layers.
1219 for (pt_idx
= 0; pt_idx
<= parent
->last_entry_used
; ++pt_idx
) {
1220 struct amdgpu_vm_pt
*entry
= &parent
->entries
[pt_idx
];
1222 if (!entry
->base
.bo
)
1225 entry
->addr
= ~0ULL;
1226 spin_lock(&vm
->status_lock
);
1227 if (list_empty(&entry
->base
.vm_status
))
1228 list_add(&entry
->base
.vm_status
, &vm
->relocated
);
1229 spin_unlock(&vm
->status_lock
);
1230 amdgpu_vm_invalidate_level(vm
, entry
);
1235 * amdgpu_vm_update_directories - make sure that all directories are valid
1237 * @adev: amdgpu_device pointer
1240 * Makes sure all directories are up to date.
1241 * Returns 0 for success, error for failure.
1243 int amdgpu_vm_update_directories(struct amdgpu_device
*adev
,
1244 struct amdgpu_vm
*vm
)
1248 spin_lock(&vm
->status_lock
);
1249 while (!list_empty(&vm
->relocated
)) {
1250 struct amdgpu_vm_bo_base
*bo_base
;
1251 struct amdgpu_bo
*bo
;
1253 bo_base
= list_first_entry(&vm
->relocated
,
1254 struct amdgpu_vm_bo_base
,
1256 spin_unlock(&vm
->status_lock
);
1258 bo
= bo_base
->bo
->parent
;
1260 struct amdgpu_vm_bo_base
*parent
;
1261 struct amdgpu_vm_pt
*pt
;
1263 parent
= list_first_entry(&bo
->va
,
1264 struct amdgpu_vm_bo_base
,
1266 pt
= container_of(parent
, struct amdgpu_vm_pt
, base
);
1268 r
= amdgpu_vm_update_level(adev
, vm
, pt
);
1270 amdgpu_vm_invalidate_level(vm
, &vm
->root
);
1273 spin_lock(&vm
->status_lock
);
1275 spin_lock(&vm
->status_lock
);
1276 list_del_init(&bo_base
->vm_status
);
1279 spin_unlock(&vm
->status_lock
);
1281 if (vm
->use_cpu_for_update
) {
1284 amdgpu_gart_flush_gpu_tlb(adev
, 0);
1291 * amdgpu_vm_find_entry - find the entry for an address
1293 * @p: see amdgpu_pte_update_params definition
1294 * @addr: virtual address in question
1295 * @entry: resulting entry or NULL
1296 * @parent: parent entry
1298 * Find the vm_pt entry and it's parent for the given address.
1300 void amdgpu_vm_get_entry(struct amdgpu_pte_update_params
*p
, uint64_t addr
,
1301 struct amdgpu_vm_pt
**entry
,
1302 struct amdgpu_vm_pt
**parent
)
1304 unsigned idx
, level
= p
->adev
->vm_manager
.num_level
;
1307 *entry
= &p
->vm
->root
;
1308 while ((*entry
)->entries
) {
1309 idx
= addr
>> (p
->adev
->vm_manager
.block_size
* level
--);
1310 idx
%= amdgpu_bo_size((*entry
)->base
.bo
) / 8;
1312 *entry
= &(*entry
)->entries
[idx
];
1320 * amdgpu_vm_handle_huge_pages - handle updating the PD with huge pages
1322 * @p: see amdgpu_pte_update_params definition
1323 * @entry: vm_pt entry to check
1324 * @parent: parent entry
1325 * @nptes: number of PTEs updated with this operation
1326 * @dst: destination address where the PTEs should point to
1327 * @flags: access flags fro the PTEs
1329 * Check if we can update the PD with a huge page.
1331 static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params
*p
,
1332 struct amdgpu_vm_pt
*entry
,
1333 struct amdgpu_vm_pt
*parent
,
1334 unsigned nptes
, uint64_t dst
,
1337 bool use_cpu_update
= (p
->func
== amdgpu_vm_cpu_set_ptes
);
1338 uint64_t pd_addr
, pde
;
1340 /* In the case of a mixed PT the PDE must point to it*/
1341 if (p
->adev
->asic_type
< CHIP_VEGA10
||
1342 nptes
!= AMDGPU_VM_PTE_COUNT(p
->adev
) ||
1344 !(flags
& AMDGPU_PTE_VALID
)) {
1346 dst
= amdgpu_bo_gpu_offset(entry
->base
.bo
);
1347 dst
= amdgpu_gart_get_vm_pde(p
->adev
, dst
);
1348 flags
= AMDGPU_PTE_VALID
;
1350 /* Set the huge page flag to stop scanning at this PDE */
1351 flags
|= AMDGPU_PDE_PTE
;
1354 if (entry
->addr
== (dst
| flags
))
1357 entry
->addr
= (dst
| flags
);
1359 if (use_cpu_update
) {
1360 /* In case a huge page is replaced with a system
1361 * memory mapping, p->pages_addr != NULL and
1362 * amdgpu_vm_cpu_set_ptes would try to translate dst
1363 * through amdgpu_vm_map_gart. But dst is already a
1364 * GPU address (of the page table). Disable
1365 * amdgpu_vm_map_gart temporarily.
1369 tmp
= p
->pages_addr
;
1370 p
->pages_addr
= NULL
;
1372 pd_addr
= (unsigned long)amdgpu_bo_kptr(parent
->base
.bo
);
1373 pde
= pd_addr
+ (entry
- parent
->entries
) * 8;
1374 amdgpu_vm_cpu_set_ptes(p
, pde
, dst
, 1, 0, flags
);
1376 p
->pages_addr
= tmp
;
1378 if (parent
->base
.bo
->shadow
) {
1379 pd_addr
= amdgpu_bo_gpu_offset(parent
->base
.bo
->shadow
);
1380 pde
= pd_addr
+ (entry
- parent
->entries
) * 8;
1381 amdgpu_vm_do_set_ptes(p
, pde
, dst
, 1, 0, flags
);
1383 pd_addr
= amdgpu_bo_gpu_offset(parent
->base
.bo
);
1384 pde
= pd_addr
+ (entry
- parent
->entries
) * 8;
1385 amdgpu_vm_do_set_ptes(p
, pde
, dst
, 1, 0, flags
);
1390 * amdgpu_vm_update_ptes - make sure that page tables are valid
1392 * @params: see amdgpu_pte_update_params definition
1394 * @start: start of GPU address range
1395 * @end: end of GPU address range
1396 * @dst: destination address to map to, the next dst inside the function
1397 * @flags: mapping flags
1399 * Update the page tables in the range @start - @end.
1400 * Returns 0 for success, -EINVAL for failure.
1402 static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params
*params
,
1403 uint64_t start
, uint64_t end
,
1404 uint64_t dst
, uint64_t flags
)
1406 struct amdgpu_device
*adev
= params
->adev
;
1407 const uint64_t mask
= AMDGPU_VM_PTE_COUNT(adev
) - 1;
1409 uint64_t addr
, pe_start
;
1410 struct amdgpu_bo
*pt
;
1412 bool use_cpu_update
= (params
->func
== amdgpu_vm_cpu_set_ptes
);
1414 /* walk over the address space and update the page tables */
1415 for (addr
= start
; addr
< end
; addr
+= nptes
,
1416 dst
+= nptes
* AMDGPU_GPU_PAGE_SIZE
) {
1417 struct amdgpu_vm_pt
*entry
, *parent
;
1419 amdgpu_vm_get_entry(params
, addr
, &entry
, &parent
);
1423 if ((addr
& ~mask
) == (end
& ~mask
))
1426 nptes
= AMDGPU_VM_PTE_COUNT(adev
) - (addr
& mask
);
1428 amdgpu_vm_handle_huge_pages(params
, entry
, parent
,
1430 /* We don't need to update PTEs for huge pages */
1431 if (entry
->addr
& AMDGPU_PDE_PTE
)
1434 pt
= entry
->base
.bo
;
1435 if (use_cpu_update
) {
1436 pe_start
= (unsigned long)amdgpu_bo_kptr(pt
);
1439 pe_start
= amdgpu_bo_gpu_offset(pt
->shadow
);
1440 pe_start
+= (addr
& mask
) * 8;
1441 params
->func(params
, pe_start
, dst
, nptes
,
1442 AMDGPU_GPU_PAGE_SIZE
, flags
);
1444 pe_start
= amdgpu_bo_gpu_offset(pt
);
1447 pe_start
+= (addr
& mask
) * 8;
1448 params
->func(params
, pe_start
, dst
, nptes
,
1449 AMDGPU_GPU_PAGE_SIZE
, flags
);
1456 * amdgpu_vm_frag_ptes - add fragment information to PTEs
1458 * @params: see amdgpu_pte_update_params definition
1460 * @start: first PTE to handle
1461 * @end: last PTE to handle
1462 * @dst: addr those PTEs should point to
1463 * @flags: hw mapping flags
1464 * Returns 0 for success, -EINVAL for failure.
1466 static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params
*params
,
1467 uint64_t start
, uint64_t end
,
1468 uint64_t dst
, uint64_t flags
)
1471 * The MC L1 TLB supports variable sized pages, based on a fragment
1472 * field in the PTE. When this field is set to a non-zero value, page
1473 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1474 * flags are considered valid for all PTEs within the fragment range
1475 * and corresponding mappings are assumed to be physically contiguous.
1477 * The L1 TLB can store a single PTE for the whole fragment,
1478 * significantly increasing the space available for translation
1479 * caching. This leads to large improvements in throughput when the
1480 * TLB is under pressure.
1482 * The L2 TLB distributes small and large fragments into two
1483 * asymmetric partitions. The large fragment cache is significantly
1484 * larger. Thus, we try to use large fragments wherever possible.
1485 * Userspace can support this by aligning virtual base address and
1486 * allocation size to the fragment size.
1488 unsigned max_frag
= params
->adev
->vm_manager
.fragment_size
;
1491 /* system pages are non continuously */
1492 if (params
->src
|| !(flags
& AMDGPU_PTE_VALID
))
1493 return amdgpu_vm_update_ptes(params
, start
, end
, dst
, flags
);
1495 while (start
!= end
) {
1496 uint64_t frag_flags
, frag_end
;
1499 /* This intentionally wraps around if no bit is set */
1500 frag
= min((unsigned)ffs(start
) - 1,
1501 (unsigned)fls64(end
- start
) - 1);
1502 if (frag
>= max_frag
) {
1503 frag_flags
= AMDGPU_PTE_FRAG(max_frag
);
1504 frag_end
= end
& ~((1ULL << max_frag
) - 1);
1506 frag_flags
= AMDGPU_PTE_FRAG(frag
);
1507 frag_end
= start
+ (1 << frag
);
1510 r
= amdgpu_vm_update_ptes(params
, start
, frag_end
, dst
,
1511 flags
| frag_flags
);
1515 dst
+= (frag_end
- start
) * AMDGPU_GPU_PAGE_SIZE
;
1523 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1525 * @adev: amdgpu_device pointer
1526 * @exclusive: fence we need to sync to
1527 * @pages_addr: DMA addresses to use for mapping
1529 * @start: start of mapped range
1530 * @last: last mapped entry
1531 * @flags: flags for the entries
1532 * @addr: addr to set the area to
1533 * @fence: optional resulting fence
1535 * Fill in the page table entries between @start and @last.
1536 * Returns 0 for success, -EINVAL for failure.
1538 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device
*adev
,
1539 struct dma_fence
*exclusive
,
1540 dma_addr_t
*pages_addr
,
1541 struct amdgpu_vm
*vm
,
1542 uint64_t start
, uint64_t last
,
1543 uint64_t flags
, uint64_t addr
,
1544 struct dma_fence
**fence
)
1546 struct amdgpu_ring
*ring
;
1547 void *owner
= AMDGPU_FENCE_OWNER_VM
;
1548 unsigned nptes
, ncmds
, ndw
;
1549 struct amdgpu_job
*job
;
1550 struct amdgpu_pte_update_params params
;
1551 struct dma_fence
*f
= NULL
;
1554 memset(¶ms
, 0, sizeof(params
));
1558 /* sync to everything on unmapping */
1559 if (!(flags
& AMDGPU_PTE_VALID
))
1560 owner
= AMDGPU_FENCE_OWNER_UNDEFINED
;
1562 if (vm
->use_cpu_for_update
) {
1563 /* params.src is used as flag to indicate system Memory */
1567 /* Wait for PT BOs to be free. PTs share the same resv. object
1570 r
= amdgpu_vm_wait_pd(adev
, vm
, owner
);
1574 params
.func
= amdgpu_vm_cpu_set_ptes
;
1575 params
.pages_addr
= pages_addr
;
1576 return amdgpu_vm_frag_ptes(¶ms
, start
, last
+ 1,
1580 ring
= container_of(vm
->entity
.sched
, struct amdgpu_ring
, sched
);
1582 nptes
= last
- start
+ 1;
1585 * reserve space for two commands every (1 << BLOCK_SIZE)
1586 * entries or 2k dwords (whatever is smaller)
1588 * The second command is for the shadow pagetables.
1590 ncmds
= ((nptes
>> min(adev
->vm_manager
.block_size
, 11u)) + 1) * 2;
1595 /* one PDE write for each huge page */
1596 ndw
+= ((nptes
>> adev
->vm_manager
.block_size
) + 1) * 6;
1599 /* copy commands needed */
1600 ndw
+= ncmds
* adev
->vm_manager
.vm_pte_funcs
->copy_pte_num_dw
;
1605 params
.func
= amdgpu_vm_do_copy_ptes
;
1608 /* set page commands needed */
1609 ndw
+= ncmds
* adev
->vm_manager
.vm_pte_funcs
->set_pte_pde_num_dw
;
1611 /* extra commands for begin/end fragments */
1612 ndw
+= 2 * adev
->vm_manager
.vm_pte_funcs
->set_pte_pde_num_dw
1613 * adev
->vm_manager
.fragment_size
;
1615 params
.func
= amdgpu_vm_do_set_ptes
;
1618 r
= amdgpu_job_alloc_with_ib(adev
, ndw
* 4, &job
);
1622 params
.ib
= &job
->ibs
[0];
1628 /* Put the PTEs at the end of the IB. */
1629 i
= ndw
- nptes
* 2;
1630 pte
= (uint64_t *)&(job
->ibs
->ptr
[i
]);
1631 params
.src
= job
->ibs
->gpu_addr
+ i
* 4;
1633 for (i
= 0; i
< nptes
; ++i
) {
1634 pte
[i
] = amdgpu_vm_map_gart(pages_addr
, addr
+ i
*
1635 AMDGPU_GPU_PAGE_SIZE
);
1641 r
= amdgpu_sync_fence(adev
, &job
->sync
, exclusive
);
1645 r
= amdgpu_sync_resv(adev
, &job
->sync
, vm
->root
.base
.bo
->tbo
.resv
,
1650 r
= reservation_object_reserve_shared(vm
->root
.base
.bo
->tbo
.resv
);
1654 r
= amdgpu_vm_frag_ptes(¶ms
, start
, last
+ 1, addr
, flags
);
1658 amdgpu_ring_pad_ib(ring
, params
.ib
);
1659 WARN_ON(params
.ib
->length_dw
> ndw
);
1660 r
= amdgpu_job_submit(job
, ring
, &vm
->entity
,
1661 AMDGPU_FENCE_OWNER_VM
, &f
);
1665 amdgpu_bo_fence(vm
->root
.base
.bo
, f
, true);
1666 dma_fence_put(*fence
);
1671 amdgpu_job_free(job
);
1672 amdgpu_vm_invalidate_level(vm
, &vm
->root
);
1677 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
1679 * @adev: amdgpu_device pointer
1680 * @exclusive: fence we need to sync to
1681 * @pages_addr: DMA addresses to use for mapping
1683 * @mapping: mapped range and flags to use for the update
1684 * @flags: HW flags for the mapping
1685 * @nodes: array of drm_mm_nodes with the MC addresses
1686 * @fence: optional resulting fence
1688 * Split the mapping into smaller chunks so that each update fits
1690 * Returns 0 for success, -EINVAL for failure.
1692 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device
*adev
,
1693 struct dma_fence
*exclusive
,
1694 dma_addr_t
*pages_addr
,
1695 struct amdgpu_vm
*vm
,
1696 struct amdgpu_bo_va_mapping
*mapping
,
1698 struct drm_mm_node
*nodes
,
1699 struct dma_fence
**fence
)
1701 uint64_t pfn
, start
= mapping
->start
;
1704 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1705 * but in case of something, we filter the flags in first place
1707 if (!(mapping
->flags
& AMDGPU_PTE_READABLE
))
1708 flags
&= ~AMDGPU_PTE_READABLE
;
1709 if (!(mapping
->flags
& AMDGPU_PTE_WRITEABLE
))
1710 flags
&= ~AMDGPU_PTE_WRITEABLE
;
1712 flags
&= ~AMDGPU_PTE_EXECUTABLE
;
1713 flags
|= mapping
->flags
& AMDGPU_PTE_EXECUTABLE
;
1715 flags
&= ~AMDGPU_PTE_MTYPE_MASK
;
1716 flags
|= (mapping
->flags
& AMDGPU_PTE_MTYPE_MASK
);
1718 if ((mapping
->flags
& AMDGPU_PTE_PRT
) &&
1719 (adev
->asic_type
>= CHIP_VEGA10
)) {
1720 flags
|= AMDGPU_PTE_PRT
;
1721 flags
&= ~AMDGPU_PTE_VALID
;
1724 trace_amdgpu_vm_bo_update(mapping
);
1726 pfn
= mapping
->offset
>> PAGE_SHIFT
;
1728 while (pfn
>= nodes
->size
) {
1735 uint64_t max_entries
;
1736 uint64_t addr
, last
;
1739 addr
= nodes
->start
<< PAGE_SHIFT
;
1740 max_entries
= (nodes
->size
- pfn
) *
1741 (PAGE_SIZE
/ AMDGPU_GPU_PAGE_SIZE
);
1744 max_entries
= S64_MAX
;
1748 max_entries
= min(max_entries
, 16ull * 1024ull);
1750 } else if (flags
& AMDGPU_PTE_VALID
) {
1751 addr
+= adev
->vm_manager
.vram_base_offset
;
1753 addr
+= pfn
<< PAGE_SHIFT
;
1755 last
= min((uint64_t)mapping
->last
, start
+ max_entries
- 1);
1756 r
= amdgpu_vm_bo_update_mapping(adev
, exclusive
, pages_addr
, vm
,
1757 start
, last
, flags
, addr
,
1762 pfn
+= last
- start
+ 1;
1763 if (nodes
&& nodes
->size
== pfn
) {
1769 } while (unlikely(start
!= mapping
->last
+ 1));
1775 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1777 * @adev: amdgpu_device pointer
1778 * @bo_va: requested BO and VM object
1779 * @clear: if true clear the entries
1781 * Fill in the page table entries for @bo_va.
1782 * Returns 0 for success, -EINVAL for failure.
1784 int amdgpu_vm_bo_update(struct amdgpu_device
*adev
,
1785 struct amdgpu_bo_va
*bo_va
,
1788 struct amdgpu_bo
*bo
= bo_va
->base
.bo
;
1789 struct amdgpu_vm
*vm
= bo_va
->base
.vm
;
1790 struct amdgpu_bo_va_mapping
*mapping
;
1791 dma_addr_t
*pages_addr
= NULL
;
1792 struct ttm_mem_reg
*mem
;
1793 struct drm_mm_node
*nodes
;
1794 struct dma_fence
*exclusive
, **last_update
;
1798 if (clear
|| !bo_va
->base
.bo
) {
1803 struct ttm_dma_tt
*ttm
;
1805 mem
= &bo_va
->base
.bo
->tbo
.mem
;
1806 nodes
= mem
->mm_node
;
1807 if (mem
->mem_type
== TTM_PL_TT
) {
1808 ttm
= container_of(bo_va
->base
.bo
->tbo
.ttm
,
1809 struct ttm_dma_tt
, ttm
);
1810 pages_addr
= ttm
->dma_address
;
1812 exclusive
= reservation_object_get_excl(bo
->tbo
.resv
);
1816 flags
= amdgpu_ttm_tt_pte_flags(adev
, bo
->tbo
.ttm
, mem
);
1820 if (clear
|| (bo
&& bo
->tbo
.resv
== vm
->root
.base
.bo
->tbo
.resv
))
1821 last_update
= &vm
->last_update
;
1823 last_update
= &bo_va
->last_pt_update
;
1825 if (!clear
&& bo_va
->base
.moved
) {
1826 bo_va
->base
.moved
= false;
1827 list_splice_init(&bo_va
->valids
, &bo_va
->invalids
);
1829 } else if (bo_va
->cleared
!= clear
) {
1830 list_splice_init(&bo_va
->valids
, &bo_va
->invalids
);
1833 list_for_each_entry(mapping
, &bo_va
->invalids
, list
) {
1834 r
= amdgpu_vm_bo_split_mapping(adev
, exclusive
, pages_addr
, vm
,
1835 mapping
, flags
, nodes
,
1841 if (vm
->use_cpu_for_update
) {
1844 amdgpu_gart_flush_gpu_tlb(adev
, 0);
1847 spin_lock(&vm
->status_lock
);
1848 list_del_init(&bo_va
->base
.vm_status
);
1849 spin_unlock(&vm
->status_lock
);
1851 list_splice_init(&bo_va
->invalids
, &bo_va
->valids
);
1852 bo_va
->cleared
= clear
;
1854 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1855 list_for_each_entry(mapping
, &bo_va
->valids
, list
)
1856 trace_amdgpu_vm_bo_mapping(mapping
);
1863 * amdgpu_vm_update_prt_state - update the global PRT state
1865 static void amdgpu_vm_update_prt_state(struct amdgpu_device
*adev
)
1867 unsigned long flags
;
1870 spin_lock_irqsave(&adev
->vm_manager
.prt_lock
, flags
);
1871 enable
= !!atomic_read(&adev
->vm_manager
.num_prt_users
);
1872 adev
->gart
.gart_funcs
->set_prt(adev
, enable
);
1873 spin_unlock_irqrestore(&adev
->vm_manager
.prt_lock
, flags
);
1877 * amdgpu_vm_prt_get - add a PRT user
1879 static void amdgpu_vm_prt_get(struct amdgpu_device
*adev
)
1881 if (!adev
->gart
.gart_funcs
->set_prt
)
1884 if (atomic_inc_return(&adev
->vm_manager
.num_prt_users
) == 1)
1885 amdgpu_vm_update_prt_state(adev
);
1889 * amdgpu_vm_prt_put - drop a PRT user
1891 static void amdgpu_vm_prt_put(struct amdgpu_device
*adev
)
1893 if (atomic_dec_return(&adev
->vm_manager
.num_prt_users
) == 0)
1894 amdgpu_vm_update_prt_state(adev
);
1898 * amdgpu_vm_prt_cb - callback for updating the PRT status
1900 static void amdgpu_vm_prt_cb(struct dma_fence
*fence
, struct dma_fence_cb
*_cb
)
1902 struct amdgpu_prt_cb
*cb
= container_of(_cb
, struct amdgpu_prt_cb
, cb
);
1904 amdgpu_vm_prt_put(cb
->adev
);
1909 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1911 static void amdgpu_vm_add_prt_cb(struct amdgpu_device
*adev
,
1912 struct dma_fence
*fence
)
1914 struct amdgpu_prt_cb
*cb
;
1916 if (!adev
->gart
.gart_funcs
->set_prt
)
1919 cb
= kmalloc(sizeof(struct amdgpu_prt_cb
), GFP_KERNEL
);
1921 /* Last resort when we are OOM */
1923 dma_fence_wait(fence
, false);
1925 amdgpu_vm_prt_put(adev
);
1928 if (!fence
|| dma_fence_add_callback(fence
, &cb
->cb
,
1930 amdgpu_vm_prt_cb(fence
, &cb
->cb
);
1935 * amdgpu_vm_free_mapping - free a mapping
1937 * @adev: amdgpu_device pointer
1939 * @mapping: mapping to be freed
1940 * @fence: fence of the unmap operation
1942 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1944 static void amdgpu_vm_free_mapping(struct amdgpu_device
*adev
,
1945 struct amdgpu_vm
*vm
,
1946 struct amdgpu_bo_va_mapping
*mapping
,
1947 struct dma_fence
*fence
)
1949 if (mapping
->flags
& AMDGPU_PTE_PRT
)
1950 amdgpu_vm_add_prt_cb(adev
, fence
);
1955 * amdgpu_vm_prt_fini - finish all prt mappings
1957 * @adev: amdgpu_device pointer
1960 * Register a cleanup callback to disable PRT support after VM dies.
1962 static void amdgpu_vm_prt_fini(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
1964 struct reservation_object
*resv
= vm
->root
.base
.bo
->tbo
.resv
;
1965 struct dma_fence
*excl
, **shared
;
1966 unsigned i
, shared_count
;
1969 r
= reservation_object_get_fences_rcu(resv
, &excl
,
1970 &shared_count
, &shared
);
1972 /* Not enough memory to grab the fence list, as last resort
1973 * block for all the fences to complete.
1975 reservation_object_wait_timeout_rcu(resv
, true, false,
1976 MAX_SCHEDULE_TIMEOUT
);
1980 /* Add a callback for each fence in the reservation object */
1981 amdgpu_vm_prt_get(adev
);
1982 amdgpu_vm_add_prt_cb(adev
, excl
);
1984 for (i
= 0; i
< shared_count
; ++i
) {
1985 amdgpu_vm_prt_get(adev
);
1986 amdgpu_vm_add_prt_cb(adev
, shared
[i
]);
1993 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1995 * @adev: amdgpu_device pointer
1997 * @fence: optional resulting fence (unchanged if no work needed to be done
1998 * or if an error occurred)
2000 * Make sure all freed BOs are cleared in the PT.
2001 * Returns 0 for success.
2003 * PTs have to be reserved and mutex must be locked!
2005 int amdgpu_vm_clear_freed(struct amdgpu_device
*adev
,
2006 struct amdgpu_vm
*vm
,
2007 struct dma_fence
**fence
)
2009 struct amdgpu_bo_va_mapping
*mapping
;
2010 struct dma_fence
*f
= NULL
;
2012 uint64_t init_pte_value
= 0;
2014 while (!list_empty(&vm
->freed
)) {
2015 mapping
= list_first_entry(&vm
->freed
,
2016 struct amdgpu_bo_va_mapping
, list
);
2017 list_del(&mapping
->list
);
2019 if (vm
->pte_support_ats
)
2020 init_pte_value
= AMDGPU_PTE_SYSTEM
;
2022 r
= amdgpu_vm_bo_update_mapping(adev
, NULL
, NULL
, vm
,
2023 mapping
->start
, mapping
->last
,
2024 init_pte_value
, 0, &f
);
2025 amdgpu_vm_free_mapping(adev
, vm
, mapping
, f
);
2033 dma_fence_put(*fence
);
2044 * amdgpu_vm_handle_moved - handle moved BOs in the PT
2046 * @adev: amdgpu_device pointer
2048 * @sync: sync object to add fences to
2050 * Make sure all BOs which are moved are updated in the PTs.
2051 * Returns 0 for success.
2053 * PTs have to be reserved!
2055 int amdgpu_vm_handle_moved(struct amdgpu_device
*adev
,
2056 struct amdgpu_vm
*vm
)
2061 spin_lock(&vm
->status_lock
);
2062 while (!list_empty(&vm
->moved
)) {
2063 struct amdgpu_bo_va
*bo_va
;
2065 bo_va
= list_first_entry(&vm
->moved
,
2066 struct amdgpu_bo_va
, base
.vm_status
);
2067 spin_unlock(&vm
->status_lock
);
2069 /* Per VM BOs never need to bo cleared in the page tables */
2070 clear
= bo_va
->base
.bo
->tbo
.resv
!= vm
->root
.base
.bo
->tbo
.resv
;
2072 r
= amdgpu_vm_bo_update(adev
, bo_va
, clear
);
2076 spin_lock(&vm
->status_lock
);
2078 spin_unlock(&vm
->status_lock
);
2084 * amdgpu_vm_bo_add - add a bo to a specific vm
2086 * @adev: amdgpu_device pointer
2088 * @bo: amdgpu buffer object
2090 * Add @bo into the requested vm.
2091 * Add @bo to the list of bos associated with the vm
2092 * Returns newly added bo_va or NULL for failure
2094 * Object has to be reserved!
2096 struct amdgpu_bo_va
*amdgpu_vm_bo_add(struct amdgpu_device
*adev
,
2097 struct amdgpu_vm
*vm
,
2098 struct amdgpu_bo
*bo
)
2100 struct amdgpu_bo_va
*bo_va
;
2102 bo_va
= kzalloc(sizeof(struct amdgpu_bo_va
), GFP_KERNEL
);
2103 if (bo_va
== NULL
) {
2106 bo_va
->base
.vm
= vm
;
2107 bo_va
->base
.bo
= bo
;
2108 INIT_LIST_HEAD(&bo_va
->base
.bo_list
);
2109 INIT_LIST_HEAD(&bo_va
->base
.vm_status
);
2111 bo_va
->ref_count
= 1;
2112 INIT_LIST_HEAD(&bo_va
->valids
);
2113 INIT_LIST_HEAD(&bo_va
->invalids
);
2116 list_add_tail(&bo_va
->base
.bo_list
, &bo
->va
);
2123 * amdgpu_vm_bo_insert_mapping - insert a new mapping
2125 * @adev: amdgpu_device pointer
2126 * @bo_va: bo_va to store the address
2127 * @mapping: the mapping to insert
2129 * Insert a new mapping into all structures.
2131 static void amdgpu_vm_bo_insert_map(struct amdgpu_device
*adev
,
2132 struct amdgpu_bo_va
*bo_va
,
2133 struct amdgpu_bo_va_mapping
*mapping
)
2135 struct amdgpu_vm
*vm
= bo_va
->base
.vm
;
2136 struct amdgpu_bo
*bo
= bo_va
->base
.bo
;
2138 mapping
->bo_va
= bo_va
;
2139 list_add(&mapping
->list
, &bo_va
->invalids
);
2140 amdgpu_vm_it_insert(mapping
, &vm
->va
);
2142 if (mapping
->flags
& AMDGPU_PTE_PRT
)
2143 amdgpu_vm_prt_get(adev
);
2145 if (bo
&& bo
->tbo
.resv
== vm
->root
.base
.bo
->tbo
.resv
) {
2146 spin_lock(&vm
->status_lock
);
2147 if (list_empty(&bo_va
->base
.vm_status
))
2148 list_add(&bo_va
->base
.vm_status
, &vm
->moved
);
2149 spin_unlock(&vm
->status_lock
);
2151 trace_amdgpu_vm_bo_map(bo_va
, mapping
);
2155 * amdgpu_vm_bo_map - map bo inside a vm
2157 * @adev: amdgpu_device pointer
2158 * @bo_va: bo_va to store the address
2159 * @saddr: where to map the BO
2160 * @offset: requested offset in the BO
2161 * @flags: attributes of pages (read/write/valid/etc.)
2163 * Add a mapping of the BO at the specefied addr into the VM.
2164 * Returns 0 for success, error for failure.
2166 * Object has to be reserved and unreserved outside!
2168 int amdgpu_vm_bo_map(struct amdgpu_device
*adev
,
2169 struct amdgpu_bo_va
*bo_va
,
2170 uint64_t saddr
, uint64_t offset
,
2171 uint64_t size
, uint64_t flags
)
2173 struct amdgpu_bo_va_mapping
*mapping
, *tmp
;
2174 struct amdgpu_bo
*bo
= bo_va
->base
.bo
;
2175 struct amdgpu_vm
*vm
= bo_va
->base
.vm
;
2178 /* validate the parameters */
2179 if (saddr
& AMDGPU_GPU_PAGE_MASK
|| offset
& AMDGPU_GPU_PAGE_MASK
||
2180 size
== 0 || size
& AMDGPU_GPU_PAGE_MASK
)
2183 /* make sure object fit at this offset */
2184 eaddr
= saddr
+ size
- 1;
2185 if (saddr
>= eaddr
||
2186 (bo
&& offset
+ size
> amdgpu_bo_size(bo
)))
2189 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
2190 eaddr
/= AMDGPU_GPU_PAGE_SIZE
;
2192 tmp
= amdgpu_vm_it_iter_first(&vm
->va
, saddr
, eaddr
);
2194 /* bo and tmp overlap, invalid addr */
2195 dev_err(adev
->dev
, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2196 "0x%010Lx-0x%010Lx\n", bo
, saddr
, eaddr
,
2197 tmp
->start
, tmp
->last
+ 1);
2201 mapping
= kmalloc(sizeof(*mapping
), GFP_KERNEL
);
2205 mapping
->start
= saddr
;
2206 mapping
->last
= eaddr
;
2207 mapping
->offset
= offset
;
2208 mapping
->flags
= flags
;
2210 amdgpu_vm_bo_insert_map(adev
, bo_va
, mapping
);
2216 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
2218 * @adev: amdgpu_device pointer
2219 * @bo_va: bo_va to store the address
2220 * @saddr: where to map the BO
2221 * @offset: requested offset in the BO
2222 * @flags: attributes of pages (read/write/valid/etc.)
2224 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
2225 * mappings as we do so.
2226 * Returns 0 for success, error for failure.
2228 * Object has to be reserved and unreserved outside!
2230 int amdgpu_vm_bo_replace_map(struct amdgpu_device
*adev
,
2231 struct amdgpu_bo_va
*bo_va
,
2232 uint64_t saddr
, uint64_t offset
,
2233 uint64_t size
, uint64_t flags
)
2235 struct amdgpu_bo_va_mapping
*mapping
;
2236 struct amdgpu_bo
*bo
= bo_va
->base
.bo
;
2240 /* validate the parameters */
2241 if (saddr
& AMDGPU_GPU_PAGE_MASK
|| offset
& AMDGPU_GPU_PAGE_MASK
||
2242 size
== 0 || size
& AMDGPU_GPU_PAGE_MASK
)
2245 /* make sure object fit at this offset */
2246 eaddr
= saddr
+ size
- 1;
2247 if (saddr
>= eaddr
||
2248 (bo
&& offset
+ size
> amdgpu_bo_size(bo
)))
2251 /* Allocate all the needed memory */
2252 mapping
= kmalloc(sizeof(*mapping
), GFP_KERNEL
);
2256 r
= amdgpu_vm_bo_clear_mappings(adev
, bo_va
->base
.vm
, saddr
, size
);
2262 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
2263 eaddr
/= AMDGPU_GPU_PAGE_SIZE
;
2265 mapping
->start
= saddr
;
2266 mapping
->last
= eaddr
;
2267 mapping
->offset
= offset
;
2268 mapping
->flags
= flags
;
2270 amdgpu_vm_bo_insert_map(adev
, bo_va
, mapping
);
2276 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2278 * @adev: amdgpu_device pointer
2279 * @bo_va: bo_va to remove the address from
2280 * @saddr: where to the BO is mapped
2282 * Remove a mapping of the BO at the specefied addr from the VM.
2283 * Returns 0 for success, error for failure.
2285 * Object has to be reserved and unreserved outside!
2287 int amdgpu_vm_bo_unmap(struct amdgpu_device
*adev
,
2288 struct amdgpu_bo_va
*bo_va
,
2291 struct amdgpu_bo_va_mapping
*mapping
;
2292 struct amdgpu_vm
*vm
= bo_va
->base
.vm
;
2295 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
2297 list_for_each_entry(mapping
, &bo_va
->valids
, list
) {
2298 if (mapping
->start
== saddr
)
2302 if (&mapping
->list
== &bo_va
->valids
) {
2305 list_for_each_entry(mapping
, &bo_va
->invalids
, list
) {
2306 if (mapping
->start
== saddr
)
2310 if (&mapping
->list
== &bo_va
->invalids
)
2314 list_del(&mapping
->list
);
2315 amdgpu_vm_it_remove(mapping
, &vm
->va
);
2316 mapping
->bo_va
= NULL
;
2317 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
2320 list_add(&mapping
->list
, &vm
->freed
);
2322 amdgpu_vm_free_mapping(adev
, vm
, mapping
,
2323 bo_va
->last_pt_update
);
2329 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2331 * @adev: amdgpu_device pointer
2332 * @vm: VM structure to use
2333 * @saddr: start of the range
2334 * @size: size of the range
2336 * Remove all mappings in a range, split them as appropriate.
2337 * Returns 0 for success, error for failure.
2339 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device
*adev
,
2340 struct amdgpu_vm
*vm
,
2341 uint64_t saddr
, uint64_t size
)
2343 struct amdgpu_bo_va_mapping
*before
, *after
, *tmp
, *next
;
2347 eaddr
= saddr
+ size
- 1;
2348 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
2349 eaddr
/= AMDGPU_GPU_PAGE_SIZE
;
2351 /* Allocate all the needed memory */
2352 before
= kzalloc(sizeof(*before
), GFP_KERNEL
);
2355 INIT_LIST_HEAD(&before
->list
);
2357 after
= kzalloc(sizeof(*after
), GFP_KERNEL
);
2362 INIT_LIST_HEAD(&after
->list
);
2364 /* Now gather all removed mappings */
2365 tmp
= amdgpu_vm_it_iter_first(&vm
->va
, saddr
, eaddr
);
2367 /* Remember mapping split at the start */
2368 if (tmp
->start
< saddr
) {
2369 before
->start
= tmp
->start
;
2370 before
->last
= saddr
- 1;
2371 before
->offset
= tmp
->offset
;
2372 before
->flags
= tmp
->flags
;
2373 list_add(&before
->list
, &tmp
->list
);
2376 /* Remember mapping split at the end */
2377 if (tmp
->last
> eaddr
) {
2378 after
->start
= eaddr
+ 1;
2379 after
->last
= tmp
->last
;
2380 after
->offset
= tmp
->offset
;
2381 after
->offset
+= after
->start
- tmp
->start
;
2382 after
->flags
= tmp
->flags
;
2383 list_add(&after
->list
, &tmp
->list
);
2386 list_del(&tmp
->list
);
2387 list_add(&tmp
->list
, &removed
);
2389 tmp
= amdgpu_vm_it_iter_next(tmp
, saddr
, eaddr
);
2392 /* And free them up */
2393 list_for_each_entry_safe(tmp
, next
, &removed
, list
) {
2394 amdgpu_vm_it_remove(tmp
, &vm
->va
);
2395 list_del(&tmp
->list
);
2397 if (tmp
->start
< saddr
)
2399 if (tmp
->last
> eaddr
)
2403 list_add(&tmp
->list
, &vm
->freed
);
2404 trace_amdgpu_vm_bo_unmap(NULL
, tmp
);
2407 /* Insert partial mapping before the range */
2408 if (!list_empty(&before
->list
)) {
2409 amdgpu_vm_it_insert(before
, &vm
->va
);
2410 if (before
->flags
& AMDGPU_PTE_PRT
)
2411 amdgpu_vm_prt_get(adev
);
2416 /* Insert partial mapping after the range */
2417 if (!list_empty(&after
->list
)) {
2418 amdgpu_vm_it_insert(after
, &vm
->va
);
2419 if (after
->flags
& AMDGPU_PTE_PRT
)
2420 amdgpu_vm_prt_get(adev
);
2429 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2431 * @vm: the requested VM
2433 * Find a mapping by it's address.
2435 struct amdgpu_bo_va_mapping
*amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm
*vm
,
2438 return amdgpu_vm_it_iter_first(&vm
->va
, addr
, addr
);
2442 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2444 * @adev: amdgpu_device pointer
2445 * @bo_va: requested bo_va
2447 * Remove @bo_va->bo from the requested vm.
2449 * Object have to be reserved!
2451 void amdgpu_vm_bo_rmv(struct amdgpu_device
*adev
,
2452 struct amdgpu_bo_va
*bo_va
)
2454 struct amdgpu_bo_va_mapping
*mapping
, *next
;
2455 struct amdgpu_vm
*vm
= bo_va
->base
.vm
;
2457 list_del(&bo_va
->base
.bo_list
);
2459 spin_lock(&vm
->status_lock
);
2460 list_del(&bo_va
->base
.vm_status
);
2461 spin_unlock(&vm
->status_lock
);
2463 list_for_each_entry_safe(mapping
, next
, &bo_va
->valids
, list
) {
2464 list_del(&mapping
->list
);
2465 amdgpu_vm_it_remove(mapping
, &vm
->va
);
2466 mapping
->bo_va
= NULL
;
2467 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
2468 list_add(&mapping
->list
, &vm
->freed
);
2470 list_for_each_entry_safe(mapping
, next
, &bo_va
->invalids
, list
) {
2471 list_del(&mapping
->list
);
2472 amdgpu_vm_it_remove(mapping
, &vm
->va
);
2473 amdgpu_vm_free_mapping(adev
, vm
, mapping
,
2474 bo_va
->last_pt_update
);
2477 dma_fence_put(bo_va
->last_pt_update
);
2482 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2484 * @adev: amdgpu_device pointer
2486 * @bo: amdgpu buffer object
2488 * Mark @bo as invalid.
2490 void amdgpu_vm_bo_invalidate(struct amdgpu_device
*adev
,
2491 struct amdgpu_bo
*bo
, bool evicted
)
2493 struct amdgpu_vm_bo_base
*bo_base
;
2495 list_for_each_entry(bo_base
, &bo
->va
, bo_list
) {
2496 struct amdgpu_vm
*vm
= bo_base
->vm
;
2498 bo_base
->moved
= true;
2499 if (evicted
&& bo
->tbo
.resv
== vm
->root
.base
.bo
->tbo
.resv
) {
2500 spin_lock(&bo_base
->vm
->status_lock
);
2501 if (bo
->tbo
.type
== ttm_bo_type_kernel
)
2502 list_move(&bo_base
->vm_status
, &vm
->evicted
);
2504 list_move_tail(&bo_base
->vm_status
,
2506 spin_unlock(&bo_base
->vm
->status_lock
);
2510 if (bo
->tbo
.type
== ttm_bo_type_kernel
) {
2511 spin_lock(&bo_base
->vm
->status_lock
);
2512 if (list_empty(&bo_base
->vm_status
))
2513 list_add(&bo_base
->vm_status
, &vm
->relocated
);
2514 spin_unlock(&bo_base
->vm
->status_lock
);
2518 spin_lock(&bo_base
->vm
->status_lock
);
2519 if (list_empty(&bo_base
->vm_status
))
2520 list_add(&bo_base
->vm_status
, &vm
->moved
);
2521 spin_unlock(&bo_base
->vm
->status_lock
);
2525 static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size
)
2527 /* Total bits covered by PD + PTs */
2528 unsigned bits
= ilog2(vm_size
) + 18;
2530 /* Make sure the PD is 4K in size up to 8GB address space.
2531 Above that split equal between PD and PTs */
2535 return ((bits
+ 3) / 2);
2539 * amdgpu_vm_set_fragment_size - adjust fragment size in PTE
2541 * @adev: amdgpu_device pointer
2542 * @fragment_size_default: the default fragment size if it's set auto
2544 void amdgpu_vm_set_fragment_size(struct amdgpu_device
*adev
,
2545 uint32_t fragment_size_default
)
2547 if (amdgpu_vm_fragment_size
== -1)
2548 adev
->vm_manager
.fragment_size
= fragment_size_default
;
2550 adev
->vm_manager
.fragment_size
= amdgpu_vm_fragment_size
;
2554 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2556 * @adev: amdgpu_device pointer
2557 * @vm_size: the default vm size if it's set auto
2559 void amdgpu_vm_adjust_size(struct amdgpu_device
*adev
, uint64_t vm_size
,
2560 uint32_t fragment_size_default
)
2562 /* adjust vm size firstly */
2563 if (amdgpu_vm_size
== -1)
2564 adev
->vm_manager
.vm_size
= vm_size
;
2566 adev
->vm_manager
.vm_size
= amdgpu_vm_size
;
2568 /* block size depends on vm size */
2569 if (amdgpu_vm_block_size
== -1)
2570 adev
->vm_manager
.block_size
=
2571 amdgpu_vm_get_block_size(adev
->vm_manager
.vm_size
);
2573 adev
->vm_manager
.block_size
= amdgpu_vm_block_size
;
2575 amdgpu_vm_set_fragment_size(adev
, fragment_size_default
);
2577 DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n",
2578 adev
->vm_manager
.vm_size
, adev
->vm_manager
.block_size
,
2579 adev
->vm_manager
.fragment_size
);
2583 * amdgpu_vm_init - initialize a vm instance
2585 * @adev: amdgpu_device pointer
2587 * @vm_context: Indicates if it GFX or Compute context
2591 int amdgpu_vm_init(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
2592 int vm_context
, unsigned int pasid
)
2594 const unsigned align
= min(AMDGPU_VM_PTB_ALIGN_SIZE
,
2595 AMDGPU_VM_PTE_COUNT(adev
) * 8);
2596 unsigned ring_instance
;
2597 struct amdgpu_ring
*ring
;
2598 struct amd_sched_rq
*rq
;
2601 uint64_t init_pde_value
= 0;
2603 vm
->va
= RB_ROOT_CACHED
;
2604 vm
->client_id
= atomic64_inc_return(&adev
->vm_manager
.client_counter
);
2605 for (i
= 0; i
< AMDGPU_MAX_VMHUBS
; i
++)
2606 vm
->reserved_vmid
[i
] = NULL
;
2607 spin_lock_init(&vm
->status_lock
);
2608 INIT_LIST_HEAD(&vm
->evicted
);
2609 INIT_LIST_HEAD(&vm
->relocated
);
2610 INIT_LIST_HEAD(&vm
->moved
);
2611 INIT_LIST_HEAD(&vm
->freed
);
2613 /* create scheduler entity for page table updates */
2615 ring_instance
= atomic_inc_return(&adev
->vm_manager
.vm_pte_next_ring
);
2616 ring_instance
%= adev
->vm_manager
.vm_pte_num_rings
;
2617 ring
= adev
->vm_manager
.vm_pte_rings
[ring_instance
];
2618 rq
= &ring
->sched
.sched_rq
[AMD_SCHED_PRIORITY_KERNEL
];
2619 r
= amd_sched_entity_init(&ring
->sched
, &vm
->entity
,
2620 rq
, amdgpu_sched_jobs
);
2624 vm
->pte_support_ats
= false;
2626 if (vm_context
== AMDGPU_VM_CONTEXT_COMPUTE
) {
2627 vm
->use_cpu_for_update
= !!(adev
->vm_manager
.vm_update_mode
&
2628 AMDGPU_VM_USE_CPU_FOR_COMPUTE
);
2630 if (adev
->asic_type
== CHIP_RAVEN
) {
2631 vm
->pte_support_ats
= true;
2632 init_pde_value
= AMDGPU_PTE_SYSTEM
| AMDGPU_PDE_PTE
;
2635 vm
->use_cpu_for_update
= !!(adev
->vm_manager
.vm_update_mode
&
2636 AMDGPU_VM_USE_CPU_FOR_GFX
);
2637 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2638 vm
->use_cpu_for_update
? "CPU" : "SDMA");
2639 WARN_ONCE((vm
->use_cpu_for_update
& !amdgpu_vm_is_large_bar(adev
)),
2640 "CPU update of VM recommended only for large BAR system\n");
2641 vm
->last_update
= NULL
;
2643 flags
= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
|
2644 AMDGPU_GEM_CREATE_VRAM_CLEARED
;
2645 if (vm
->use_cpu_for_update
)
2646 flags
|= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
;
2648 flags
|= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS
|
2649 AMDGPU_GEM_CREATE_SHADOW
);
2651 r
= amdgpu_bo_create(adev
, amdgpu_vm_bo_size(adev
, 0), align
, true,
2652 AMDGPU_GEM_DOMAIN_VRAM
,
2654 NULL
, NULL
, init_pde_value
, &vm
->root
.base
.bo
);
2656 goto error_free_sched_entity
;
2658 vm
->root
.base
.vm
= vm
;
2659 list_add_tail(&vm
->root
.base
.bo_list
, &vm
->root
.base
.bo
->va
);
2660 INIT_LIST_HEAD(&vm
->root
.base
.vm_status
);
2662 if (vm
->use_cpu_for_update
) {
2663 r
= amdgpu_bo_reserve(vm
->root
.base
.bo
, false);
2665 goto error_free_root
;
2667 r
= amdgpu_bo_kmap(vm
->root
.base
.bo
, NULL
);
2668 amdgpu_bo_unreserve(vm
->root
.base
.bo
);
2670 goto error_free_root
;
2674 unsigned long flags
;
2676 spin_lock_irqsave(&adev
->vm_manager
.pasid_lock
, flags
);
2677 r
= idr_alloc(&adev
->vm_manager
.pasid_idr
, vm
, pasid
, pasid
+ 1,
2679 spin_unlock_irqrestore(&adev
->vm_manager
.pasid_lock
, flags
);
2681 goto error_free_root
;
2686 INIT_KFIFO(vm
->faults
);
2687 vm
->fault_credit
= 16;
2692 amdgpu_bo_unref(&vm
->root
.base
.bo
->shadow
);
2693 amdgpu_bo_unref(&vm
->root
.base
.bo
);
2694 vm
->root
.base
.bo
= NULL
;
2696 error_free_sched_entity
:
2697 amd_sched_entity_fini(&ring
->sched
, &vm
->entity
);
2703 * amdgpu_vm_free_levels - free PD/PT levels
2705 * @level: PD/PT starting level to free
2707 * Free the page directory or page table level and all sub levels.
2709 static void amdgpu_vm_free_levels(struct amdgpu_vm_pt
*level
)
2713 if (level
->base
.bo
) {
2714 list_del(&level
->base
.bo_list
);
2715 list_del(&level
->base
.vm_status
);
2716 amdgpu_bo_unref(&level
->base
.bo
->shadow
);
2717 amdgpu_bo_unref(&level
->base
.bo
);
2721 for (i
= 0; i
<= level
->last_entry_used
; i
++)
2722 amdgpu_vm_free_levels(&level
->entries
[i
]);
2724 kvfree(level
->entries
);
2728 * amdgpu_vm_fini - tear down a vm instance
2730 * @adev: amdgpu_device pointer
2734 * Unbind the VM and remove all bos from the vm bo list
2736 void amdgpu_vm_fini(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
2738 struct amdgpu_bo_va_mapping
*mapping
, *tmp
;
2739 bool prt_fini_needed
= !!adev
->gart
.gart_funcs
->set_prt
;
2743 /* Clear pending page faults from IH when the VM is destroyed */
2744 while (kfifo_get(&vm
->faults
, &fault
))
2745 amdgpu_ih_clear_fault(adev
, fault
);
2748 unsigned long flags
;
2750 spin_lock_irqsave(&adev
->vm_manager
.pasid_lock
, flags
);
2751 idr_remove(&adev
->vm_manager
.pasid_idr
, vm
->pasid
);
2752 spin_unlock_irqrestore(&adev
->vm_manager
.pasid_lock
, flags
);
2755 amd_sched_entity_fini(vm
->entity
.sched
, &vm
->entity
);
2757 if (!RB_EMPTY_ROOT(&vm
->va
.rb_root
)) {
2758 dev_err(adev
->dev
, "still active bo inside vm\n");
2760 rbtree_postorder_for_each_entry_safe(mapping
, tmp
,
2761 &vm
->va
.rb_root
, rb
) {
2762 list_del(&mapping
->list
);
2763 amdgpu_vm_it_remove(mapping
, &vm
->va
);
2766 list_for_each_entry_safe(mapping
, tmp
, &vm
->freed
, list
) {
2767 if (mapping
->flags
& AMDGPU_PTE_PRT
&& prt_fini_needed
) {
2768 amdgpu_vm_prt_fini(adev
, vm
);
2769 prt_fini_needed
= false;
2772 list_del(&mapping
->list
);
2773 amdgpu_vm_free_mapping(adev
, vm
, mapping
, NULL
);
2776 amdgpu_vm_free_levels(&vm
->root
);
2777 dma_fence_put(vm
->last_update
);
2778 for (i
= 0; i
< AMDGPU_MAX_VMHUBS
; i
++)
2779 amdgpu_vm_free_reserved_vmid(adev
, vm
, i
);
2783 * amdgpu_vm_pasid_fault_credit - Check fault credit for given PASID
2785 * @adev: amdgpu_device pointer
2786 * @pasid: PASID do identify the VM
2788 * This function is expected to be called in interrupt context. Returns
2789 * true if there was fault credit, false otherwise
2791 bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device
*adev
,
2794 struct amdgpu_vm
*vm
;
2796 spin_lock(&adev
->vm_manager
.pasid_lock
);
2797 vm
= idr_find(&adev
->vm_manager
.pasid_idr
, pasid
);
2798 spin_unlock(&adev
->vm_manager
.pasid_lock
);
2800 /* VM not found, can't track fault credit */
2803 /* No lock needed. only accessed by IRQ handler */
2804 if (!vm
->fault_credit
)
2805 /* Too many faults in this VM */
2813 * amdgpu_vm_manager_init - init the VM manager
2815 * @adev: amdgpu_device pointer
2817 * Initialize the VM manager structures
2819 void amdgpu_vm_manager_init(struct amdgpu_device
*adev
)
2823 for (i
= 0; i
< AMDGPU_MAX_VMHUBS
; ++i
) {
2824 struct amdgpu_vm_id_manager
*id_mgr
=
2825 &adev
->vm_manager
.id_mgr
[i
];
2827 mutex_init(&id_mgr
->lock
);
2828 INIT_LIST_HEAD(&id_mgr
->ids_lru
);
2829 atomic_set(&id_mgr
->reserved_vmid_num
, 0);
2831 /* skip over VMID 0, since it is the system VM */
2832 for (j
= 1; j
< id_mgr
->num_ids
; ++j
) {
2833 amdgpu_vm_reset_id(adev
, i
, j
);
2834 amdgpu_sync_create(&id_mgr
->ids
[i
].active
);
2835 list_add_tail(&id_mgr
->ids
[j
].list
, &id_mgr
->ids_lru
);
2839 adev
->vm_manager
.fence_context
=
2840 dma_fence_context_alloc(AMDGPU_MAX_RINGS
);
2841 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
)
2842 adev
->vm_manager
.seqno
[i
] = 0;
2844 atomic_set(&adev
->vm_manager
.vm_pte_next_ring
, 0);
2845 atomic64_set(&adev
->vm_manager
.client_counter
, 0);
2846 spin_lock_init(&adev
->vm_manager
.prt_lock
);
2847 atomic_set(&adev
->vm_manager
.num_prt_users
, 0);
2849 /* If not overridden by the user, by default, only in large BAR systems
2850 * Compute VM tables will be updated by CPU
2852 #ifdef CONFIG_X86_64
2853 if (amdgpu_vm_update_mode
== -1) {
2854 if (amdgpu_vm_is_large_bar(adev
))
2855 adev
->vm_manager
.vm_update_mode
=
2856 AMDGPU_VM_USE_CPU_FOR_COMPUTE
;
2858 adev
->vm_manager
.vm_update_mode
= 0;
2860 adev
->vm_manager
.vm_update_mode
= amdgpu_vm_update_mode
;
2862 adev
->vm_manager
.vm_update_mode
= 0;
2865 idr_init(&adev
->vm_manager
.pasid_idr
);
2866 spin_lock_init(&adev
->vm_manager
.pasid_lock
);
2870 * amdgpu_vm_manager_fini - cleanup VM manager
2872 * @adev: amdgpu_device pointer
2874 * Cleanup the VM manager and free resources.
2876 void amdgpu_vm_manager_fini(struct amdgpu_device
*adev
)
2880 WARN_ON(!idr_is_empty(&adev
->vm_manager
.pasid_idr
));
2881 idr_destroy(&adev
->vm_manager
.pasid_idr
);
2883 for (i
= 0; i
< AMDGPU_MAX_VMHUBS
; ++i
) {
2884 struct amdgpu_vm_id_manager
*id_mgr
=
2885 &adev
->vm_manager
.id_mgr
[i
];
2887 mutex_destroy(&id_mgr
->lock
);
2888 for (j
= 0; j
< AMDGPU_NUM_VM
; ++j
) {
2889 struct amdgpu_vm_id
*id
= &id_mgr
->ids
[j
];
2891 amdgpu_sync_free(&id
->active
);
2892 dma_fence_put(id
->flushed_updates
);
2893 dma_fence_put(id
->last_flush
);
2898 int amdgpu_vm_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
)
2900 union drm_amdgpu_vm
*args
= data
;
2901 struct amdgpu_device
*adev
= dev
->dev_private
;
2902 struct amdgpu_fpriv
*fpriv
= filp
->driver_priv
;
2905 switch (args
->in
.op
) {
2906 case AMDGPU_VM_OP_RESERVE_VMID
:
2907 /* current, we only have requirement to reserve vmid from gfxhub */
2908 r
= amdgpu_vm_alloc_reserved_vmid(adev
, &fpriv
->vm
,
2913 case AMDGPU_VM_OP_UNRESERVE_VMID
:
2914 amdgpu_vm_free_reserved_vmid(adev
, &fpriv
->vm
, AMDGPU_GFXHUB
);