2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/fence-array.h>
30 #include <drm/amdgpu_drm.h>
32 #include "amdgpu_trace.h"
36 * GPUVM is similar to the legacy gart on older asics, however
37 * rather than there being a single global gart table
38 * for the entire GPU, there are multiple VM page tables active
39 * at any given time. The VM page tables can contain a mix
40 * vram pages and system memory pages and system memory pages
41 * can be mapped as snooped (cached system pages) or unsnooped
42 * (uncached system pages).
43 * Each VM has an ID associated with it and there is a page table
44 * associated with each VMID. When execting a command buffer,
45 * the kernel tells the the ring what VMID to use for that command
46 * buffer. VMIDs are allocated dynamically as commands are submitted.
47 * The userspace drivers maintain their own address space and the kernel
48 * sets up their pages tables accordingly when they submit their
49 * command buffers and a VMID is assigned.
50 * Cayman/Trinity support up to 8 active VMs at any given time;
54 /* Special value that no flush is necessary */
55 #define AMDGPU_VM_NO_FLUSH (~0ll)
57 /* Local structure. Encapsulate some VM table update parameters to reduce
58 * the number of function parameters
60 struct amdgpu_pte_update_params
{
61 /* address where to copy page table entries from */
63 /* DMA addresses to use for mapping */
64 dma_addr_t
*pages_addr
;
65 /* indirect buffer to fill with commands */
70 * amdgpu_vm_num_pde - return the number of page directory entries
72 * @adev: amdgpu_device pointer
74 * Calculate the number of page directory entries.
76 static unsigned amdgpu_vm_num_pdes(struct amdgpu_device
*adev
)
78 return adev
->vm_manager
.max_pfn
>> amdgpu_vm_block_size
;
82 * amdgpu_vm_directory_size - returns the size of the page directory in bytes
84 * @adev: amdgpu_device pointer
86 * Calculate the size of the page directory in bytes.
88 static unsigned amdgpu_vm_directory_size(struct amdgpu_device
*adev
)
90 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev
) * 8);
94 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
96 * @vm: vm providing the BOs
97 * @validated: head of validation list
98 * @entry: entry to add
100 * Add the page directory to the list of BOs to
101 * validate for command submission.
103 void amdgpu_vm_get_pd_bo(struct amdgpu_vm
*vm
,
104 struct list_head
*validated
,
105 struct amdgpu_bo_list_entry
*entry
)
107 entry
->robj
= vm
->page_directory
;
109 entry
->tv
.bo
= &vm
->page_directory
->tbo
;
110 entry
->tv
.shared
= true;
111 entry
->user_pages
= NULL
;
112 list_add(&entry
->tv
.head
, validated
);
116 * amdgpu_vm_get_bos - add the vm BOs to a duplicates list
118 * @adev: amdgpu device pointer
119 * @vm: vm providing the BOs
120 * @duplicates: head of duplicates list
122 * Add the page directory to the BO duplicates list
123 * for command submission.
125 void amdgpu_vm_get_pt_bos(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
126 struct list_head
*duplicates
)
128 uint64_t num_evictions
;
131 /* We only need to validate the page tables
132 * if they aren't already valid.
134 num_evictions
= atomic64_read(&adev
->num_evictions
);
135 if (num_evictions
== vm
->last_eviction_counter
)
138 /* add the vm page table to the list */
139 for (i
= 0; i
<= vm
->max_pde_used
; ++i
) {
140 struct amdgpu_bo_list_entry
*entry
= &vm
->page_tables
[i
].entry
;
145 list_add(&entry
->tv
.head
, duplicates
);
151 * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail
153 * @adev: amdgpu device instance
154 * @vm: vm providing the BOs
156 * Move the PT BOs to the tail of the LRU.
158 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device
*adev
,
159 struct amdgpu_vm
*vm
)
161 struct ttm_bo_global
*glob
= adev
->mman
.bdev
.glob
;
164 spin_lock(&glob
->lru_lock
);
165 for (i
= 0; i
<= vm
->max_pde_used
; ++i
) {
166 struct amdgpu_bo_list_entry
*entry
= &vm
->page_tables
[i
].entry
;
171 ttm_bo_move_to_lru_tail(&entry
->robj
->tbo
);
173 spin_unlock(&glob
->lru_lock
);
176 static bool amdgpu_vm_is_gpu_reset(struct amdgpu_device
*adev
,
177 struct amdgpu_vm_id
*id
)
179 return id
->current_gpu_reset_count
!=
180 atomic_read(&adev
->gpu_reset_counter
) ? true : false;
184 * amdgpu_vm_grab_id - allocate the next free VMID
186 * @vm: vm to allocate id for
187 * @ring: ring we want to submit job to
188 * @sync: sync object where we add dependencies
189 * @fence: fence protecting ID from reuse
191 * Allocate an id for the vm, adding fences to the sync obj as necessary.
193 int amdgpu_vm_grab_id(struct amdgpu_vm
*vm
, struct amdgpu_ring
*ring
,
194 struct amdgpu_sync
*sync
, struct fence
*fence
,
195 struct amdgpu_job
*job
)
197 struct amdgpu_device
*adev
= ring
->adev
;
198 uint64_t fence_context
= adev
->fence_context
+ ring
->idx
;
199 struct fence
*updates
= sync
->last_vm_update
;
200 struct amdgpu_vm_id
*id
, *idle
;
201 struct fence
**fences
;
205 fences
= kmalloc_array(sizeof(void *), adev
->vm_manager
.num_ids
,
210 mutex_lock(&adev
->vm_manager
.lock
);
212 /* Check if we have an idle VMID */
214 list_for_each_entry(idle
, &adev
->vm_manager
.ids_lru
, list
) {
215 fences
[i
] = amdgpu_sync_peek_fence(&idle
->active
, ring
);
221 /* If we can't find a idle VMID to use, wait till one becomes available */
222 if (&idle
->list
== &adev
->vm_manager
.ids_lru
) {
223 u64 fence_context
= adev
->vm_manager
.fence_context
+ ring
->idx
;
224 unsigned seqno
= ++adev
->vm_manager
.seqno
[ring
->idx
];
225 struct fence_array
*array
;
228 for (j
= 0; j
< i
; ++j
)
229 fence_get(fences
[j
]);
231 array
= fence_array_create(i
, fences
, fence_context
,
234 for (j
= 0; j
< i
; ++j
)
235 fence_put(fences
[j
]);
242 r
= amdgpu_sync_fence(ring
->adev
, sync
, &array
->base
);
243 fence_put(&array
->base
);
247 mutex_unlock(&adev
->vm_manager
.lock
);
253 job
->vm_needs_flush
= true;
254 /* Check if we can use a VMID already assigned to this VM */
257 struct fence
*flushed
;
260 if (i
== AMDGPU_MAX_RINGS
)
263 /* Check all the prerequisites to using this VMID */
266 if (amdgpu_vm_is_gpu_reset(adev
, id
))
269 if (atomic64_read(&id
->owner
) != vm
->client_id
)
272 if (job
->vm_pd_addr
!= id
->pd_gpu_addr
)
278 if (id
->last_flush
->context
!= fence_context
&&
279 !fence_is_signaled(id
->last_flush
))
282 flushed
= id
->flushed_updates
;
284 (!flushed
|| fence_is_later(updates
, flushed
)))
287 /* Good we can use this VMID. Remember this submission as
290 r
= amdgpu_sync_fence(ring
->adev
, &id
->active
, fence
);
294 id
->current_gpu_reset_count
= atomic_read(&adev
->gpu_reset_counter
);
295 list_move_tail(&id
->list
, &adev
->vm_manager
.ids_lru
);
296 vm
->ids
[ring
->idx
] = id
;
298 job
->vm_id
= id
- adev
->vm_manager
.ids
;
299 job
->vm_needs_flush
= false;
300 trace_amdgpu_vm_grab_id(vm
, ring
->idx
, job
);
302 mutex_unlock(&adev
->vm_manager
.lock
);
305 } while (i
!= ring
->idx
);
307 /* Still no ID to use? Then use the idle one found earlier */
310 /* Remember this submission as user of the VMID */
311 r
= amdgpu_sync_fence(ring
->adev
, &id
->active
, fence
);
315 fence_put(id
->first
);
316 id
->first
= fence_get(fence
);
318 fence_put(id
->last_flush
);
319 id
->last_flush
= NULL
;
321 fence_put(id
->flushed_updates
);
322 id
->flushed_updates
= fence_get(updates
);
324 id
->pd_gpu_addr
= job
->vm_pd_addr
;
325 id
->current_gpu_reset_count
= atomic_read(&adev
->gpu_reset_counter
);
326 list_move_tail(&id
->list
, &adev
->vm_manager
.ids_lru
);
327 atomic64_set(&id
->owner
, vm
->client_id
);
328 vm
->ids
[ring
->idx
] = id
;
330 job
->vm_id
= id
- adev
->vm_manager
.ids
;
331 trace_amdgpu_vm_grab_id(vm
, ring
->idx
, job
);
334 mutex_unlock(&adev
->vm_manager
.lock
);
338 static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring
*ring
)
340 struct amdgpu_device
*adev
= ring
->adev
;
341 const struct amdgpu_ip_block_version
*ip_block
;
343 if (ring
->type
!= AMDGPU_RING_TYPE_COMPUTE
)
344 /* only compute rings */
347 ip_block
= amdgpu_get_ip_block(adev
, AMD_IP_BLOCK_TYPE_GFX
);
351 if (ip_block
->major
<= 7) {
352 /* gfx7 has no workaround */
354 } else if (ip_block
->major
== 8) {
355 if (adev
->gfx
.mec_fw_version
>= 673)
356 /* gfx8 is fixed in MEC firmware 673 */
365 * amdgpu_vm_flush - hardware flush the vm
367 * @ring: ring to use for flush
368 * @vm_id: vmid number to use
369 * @pd_addr: address of the page directory
371 * Emit a VM flush when it is necessary.
373 int amdgpu_vm_flush(struct amdgpu_ring
*ring
, struct amdgpu_job
*job
)
375 struct amdgpu_device
*adev
= ring
->adev
;
376 struct amdgpu_vm_id
*id
= &adev
->vm_manager
.ids
[job
->vm_id
];
377 bool gds_switch_needed
= ring
->funcs
->emit_gds_switch
&& (
378 id
->gds_base
!= job
->gds_base
||
379 id
->gds_size
!= job
->gds_size
||
380 id
->gws_base
!= job
->gws_base
||
381 id
->gws_size
!= job
->gws_size
||
382 id
->oa_base
!= job
->oa_base
||
383 id
->oa_size
!= job
->oa_size
);
386 if (ring
->funcs
->emit_pipeline_sync
&& (
387 job
->vm_needs_flush
|| gds_switch_needed
||
388 amdgpu_vm_ring_has_compute_vm_bug(ring
)))
389 amdgpu_ring_emit_pipeline_sync(ring
);
391 if (ring
->funcs
->emit_vm_flush
&& (job
->vm_needs_flush
||
392 amdgpu_vm_is_gpu_reset(adev
, id
))) {
395 trace_amdgpu_vm_flush(job
->vm_pd_addr
, ring
->idx
, job
->vm_id
);
396 amdgpu_ring_emit_vm_flush(ring
, job
->vm_id
, job
->vm_pd_addr
);
398 r
= amdgpu_fence_emit(ring
, &fence
);
402 mutex_lock(&adev
->vm_manager
.lock
);
403 fence_put(id
->last_flush
);
404 id
->last_flush
= fence
;
405 mutex_unlock(&adev
->vm_manager
.lock
);
408 if (gds_switch_needed
) {
409 id
->gds_base
= job
->gds_base
;
410 id
->gds_size
= job
->gds_size
;
411 id
->gws_base
= job
->gws_base
;
412 id
->gws_size
= job
->gws_size
;
413 id
->oa_base
= job
->oa_base
;
414 id
->oa_size
= job
->oa_size
;
415 amdgpu_ring_emit_gds_switch(ring
, job
->vm_id
,
416 job
->gds_base
, job
->gds_size
,
417 job
->gws_base
, job
->gws_size
,
418 job
->oa_base
, job
->oa_size
);
425 * amdgpu_vm_reset_id - reset VMID to zero
427 * @adev: amdgpu device structure
428 * @vm_id: vmid number to use
430 * Reset saved GDW, GWS and OA to force switch on next flush.
432 void amdgpu_vm_reset_id(struct amdgpu_device
*adev
, unsigned vm_id
)
434 struct amdgpu_vm_id
*id
= &adev
->vm_manager
.ids
[vm_id
];
445 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
448 * @bo: requested buffer object
450 * Find @bo inside the requested vm.
451 * Search inside the @bos vm list for the requested vm
452 * Returns the found bo_va or NULL if none is found
454 * Object has to be reserved!
456 struct amdgpu_bo_va
*amdgpu_vm_bo_find(struct amdgpu_vm
*vm
,
457 struct amdgpu_bo
*bo
)
459 struct amdgpu_bo_va
*bo_va
;
461 list_for_each_entry(bo_va
, &bo
->va
, bo_list
) {
462 if (bo_va
->vm
== vm
) {
470 * amdgpu_vm_update_pages - helper to call the right asic function
472 * @adev: amdgpu_device pointer
473 * @params: see amdgpu_pte_update_params definition
474 * @pe: addr of the page entry
475 * @addr: dst addr to write into pe
476 * @count: number of page entries to update
477 * @incr: increase next addr by incr bytes
478 * @flags: hw access flags
480 * Traces the parameters and calls the right asic functions
481 * to setup the page table using the DMA.
483 static void amdgpu_vm_update_pages(struct amdgpu_device
*adev
,
484 struct amdgpu_pte_update_params
*params
,
485 uint64_t pe
, uint64_t addr
,
486 unsigned count
, uint32_t incr
,
489 trace_amdgpu_vm_set_page(pe
, addr
, count
, incr
, flags
);
492 amdgpu_vm_copy_pte(adev
, params
->ib
,
493 pe
, (params
->src
+ (addr
>> 12) * 8), count
);
495 } else if (params
->pages_addr
) {
496 amdgpu_vm_write_pte(adev
, params
->ib
,
498 pe
, addr
, count
, incr
, flags
);
500 } else if (count
< 3) {
501 amdgpu_vm_write_pte(adev
, params
->ib
, NULL
, pe
, addr
,
505 amdgpu_vm_set_pte_pde(adev
, params
->ib
, pe
, addr
,
511 * amdgpu_vm_clear_bo - initially clear the page dir/table
513 * @adev: amdgpu_device pointer
516 * need to reserve bo first before calling it.
518 static int amdgpu_vm_clear_bo(struct amdgpu_device
*adev
,
519 struct amdgpu_vm
*vm
,
520 struct amdgpu_bo
*bo
)
522 struct amdgpu_ring
*ring
;
523 struct fence
*fence
= NULL
;
524 struct amdgpu_job
*job
;
525 struct amdgpu_pte_update_params params
;
530 memset(¶ms
, 0, sizeof(params
));
531 ring
= container_of(vm
->entity
.sched
, struct amdgpu_ring
, sched
);
533 r
= reservation_object_reserve_shared(bo
->tbo
.resv
);
537 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, true, false);
541 addr
= amdgpu_bo_gpu_offset(bo
);
542 entries
= amdgpu_bo_size(bo
) / 8;
544 r
= amdgpu_job_alloc_with_ib(adev
, 64, &job
);
548 params
.ib
= &job
->ibs
[0];
549 amdgpu_vm_update_pages(adev
, ¶ms
, addr
, 0, entries
,
551 amdgpu_ring_pad_ib(ring
, &job
->ibs
[0]);
553 WARN_ON(job
->ibs
[0].length_dw
> 64);
554 r
= amdgpu_job_submit(job
, ring
, &vm
->entity
,
555 AMDGPU_FENCE_OWNER_VM
, &fence
);
559 amdgpu_bo_fence(bo
, fence
, true);
564 amdgpu_job_free(job
);
571 * amdgpu_vm_map_gart - Resolve gart mapping of addr
573 * @pages_addr: optional DMA address to use for lookup
574 * @addr: the unmapped addr
576 * Look up the physical address of the page that the pte resolves
577 * to and return the pointer for the page table entry.
579 uint64_t amdgpu_vm_map_gart(const dma_addr_t
*pages_addr
, uint64_t addr
)
584 /* page table offset */
585 result
= pages_addr
[addr
>> PAGE_SHIFT
];
587 /* in case cpu page size != gpu page size*/
588 result
|= addr
& (~PAGE_MASK
);
591 /* No mapping required */
595 result
&= 0xFFFFFFFFFFFFF000ULL
;
601 * amdgpu_vm_update_pdes - make sure that page directory is valid
603 * @adev: amdgpu_device pointer
605 * @start: start of GPU address range
606 * @end: end of GPU address range
608 * Allocates new page tables if necessary
609 * and updates the page directory.
610 * Returns 0 for success, error for failure.
612 int amdgpu_vm_update_page_directory(struct amdgpu_device
*adev
,
613 struct amdgpu_vm
*vm
)
615 struct amdgpu_ring
*ring
;
616 struct amdgpu_bo
*pd
= vm
->page_directory
;
617 uint64_t pd_addr
= amdgpu_bo_gpu_offset(pd
);
618 uint32_t incr
= AMDGPU_VM_PTE_COUNT
* 8;
619 uint64_t last_pde
= ~0, last_pt
= ~0;
620 unsigned count
= 0, pt_idx
, ndw
;
621 struct amdgpu_job
*job
;
622 struct amdgpu_pte_update_params params
;
623 struct fence
*fence
= NULL
;
627 memset(¶ms
, 0, sizeof(params
));
628 ring
= container_of(vm
->entity
.sched
, struct amdgpu_ring
, sched
);
633 /* assume the worst case */
634 ndw
+= vm
->max_pde_used
* 6;
636 r
= amdgpu_job_alloc_with_ib(adev
, ndw
* 4, &job
);
640 params
.ib
= &job
->ibs
[0];
642 /* walk over the address space and update the page directory */
643 for (pt_idx
= 0; pt_idx
<= vm
->max_pde_used
; ++pt_idx
) {
644 struct amdgpu_bo
*bo
= vm
->page_tables
[pt_idx
].entry
.robj
;
650 pt
= amdgpu_bo_gpu_offset(bo
);
651 if (vm
->page_tables
[pt_idx
].addr
== pt
)
653 vm
->page_tables
[pt_idx
].addr
= pt
;
655 pde
= pd_addr
+ pt_idx
* 8;
656 if (((last_pde
+ 8 * count
) != pde
) ||
657 ((last_pt
+ incr
* count
) != pt
)) {
660 amdgpu_vm_update_pages(adev
, ¶ms
,
675 amdgpu_vm_update_pages(adev
, ¶ms
,
677 count
, incr
, AMDGPU_PTE_VALID
);
679 if (params
.ib
->length_dw
!= 0) {
680 amdgpu_ring_pad_ib(ring
, params
.ib
);
681 amdgpu_sync_resv(adev
, &job
->sync
, pd
->tbo
.resv
,
682 AMDGPU_FENCE_OWNER_VM
);
683 WARN_ON(params
.ib
->length_dw
> ndw
);
684 r
= amdgpu_job_submit(job
, ring
, &vm
->entity
,
685 AMDGPU_FENCE_OWNER_VM
, &fence
);
689 amdgpu_bo_fence(pd
, fence
, true);
690 fence_put(vm
->page_directory_fence
);
691 vm
->page_directory_fence
= fence_get(fence
);
695 amdgpu_job_free(job
);
701 amdgpu_job_free(job
);
706 * amdgpu_vm_frag_ptes - add fragment information to PTEs
708 * @adev: amdgpu_device pointer
709 * @params: see amdgpu_pte_update_params definition
710 * @pe_start: first PTE to handle
711 * @pe_end: last PTE to handle
712 * @addr: addr those PTEs should point to
713 * @flags: hw mapping flags
715 static void amdgpu_vm_frag_ptes(struct amdgpu_device
*adev
,
716 struct amdgpu_pte_update_params
*params
,
717 uint64_t pe_start
, uint64_t pe_end
,
718 uint64_t addr
, uint32_t flags
)
721 * The MC L1 TLB supports variable sized pages, based on a fragment
722 * field in the PTE. When this field is set to a non-zero value, page
723 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
724 * flags are considered valid for all PTEs within the fragment range
725 * and corresponding mappings are assumed to be physically contiguous.
727 * The L1 TLB can store a single PTE for the whole fragment,
728 * significantly increasing the space available for translation
729 * caching. This leads to large improvements in throughput when the
730 * TLB is under pressure.
732 * The L2 TLB distributes small and large fragments into two
733 * asymmetric partitions. The large fragment cache is significantly
734 * larger. Thus, we try to use large fragments wherever possible.
735 * Userspace can support this by aligning virtual base address and
736 * allocation size to the fragment size.
739 /* SI and newer are optimized for 64KB */
740 uint64_t frag_flags
= AMDGPU_PTE_FRAG(AMDGPU_LOG2_PAGES_PER_FRAG
);
741 uint64_t frag_align
= 0x80;
743 uint64_t frag_start
= ALIGN(pe_start
, frag_align
);
744 uint64_t frag_end
= pe_end
& ~(frag_align
- 1);
748 /* Abort early if there isn't anything to do */
749 if (pe_start
== pe_end
)
752 /* system pages are non continuously */
753 if (params
->src
|| params
->pages_addr
||
754 !(flags
& AMDGPU_PTE_VALID
) || (frag_start
>= frag_end
)) {
756 count
= (pe_end
- pe_start
) / 8;
757 amdgpu_vm_update_pages(adev
, params
, pe_start
,
758 addr
, count
, AMDGPU_GPU_PAGE_SIZE
,
763 /* handle the 4K area at the beginning */
764 if (pe_start
!= frag_start
) {
765 count
= (frag_start
- pe_start
) / 8;
766 amdgpu_vm_update_pages(adev
, params
, pe_start
, addr
,
767 count
, AMDGPU_GPU_PAGE_SIZE
, flags
);
768 addr
+= AMDGPU_GPU_PAGE_SIZE
* count
;
771 /* handle the area in the middle */
772 count
= (frag_end
- frag_start
) / 8;
773 amdgpu_vm_update_pages(adev
, params
, frag_start
, addr
, count
,
774 AMDGPU_GPU_PAGE_SIZE
, flags
| frag_flags
);
776 /* handle the 4K area at the end */
777 if (frag_end
!= pe_end
) {
778 addr
+= AMDGPU_GPU_PAGE_SIZE
* count
;
779 count
= (pe_end
- frag_end
) / 8;
780 amdgpu_vm_update_pages(adev
, params
, frag_end
, addr
,
781 count
, AMDGPU_GPU_PAGE_SIZE
, flags
);
786 * amdgpu_vm_update_ptes - make sure that page tables are valid
788 * @adev: amdgpu_device pointer
789 * @params: see amdgpu_pte_update_params definition
791 * @start: start of GPU address range
792 * @end: end of GPU address range
793 * @dst: destination address to map to, the next dst inside the function
794 * @flags: mapping flags
796 * Update the page tables in the range @start - @end.
798 static void amdgpu_vm_update_ptes(struct amdgpu_device
*adev
,
799 struct amdgpu_pte_update_params
*params
,
800 struct amdgpu_vm
*vm
,
801 uint64_t start
, uint64_t end
,
802 uint64_t dst
, uint32_t flags
)
804 const uint64_t mask
= AMDGPU_VM_PTE_COUNT
- 1;
806 uint64_t cur_pe_start
, cur_pe_end
, cur_dst
;
807 uint64_t addr
; /* next GPU address to be updated */
809 struct amdgpu_bo
*pt
;
810 unsigned nptes
; /* next number of ptes to be updated */
811 uint64_t next_pe_start
;
813 /* initialize the variables */
815 pt_idx
= addr
>> amdgpu_vm_block_size
;
816 pt
= vm
->page_tables
[pt_idx
].entry
.robj
;
818 if ((addr
& ~mask
) == (end
& ~mask
))
821 nptes
= AMDGPU_VM_PTE_COUNT
- (addr
& mask
);
823 cur_pe_start
= amdgpu_bo_gpu_offset(pt
);
824 cur_pe_start
+= (addr
& mask
) * 8;
825 cur_pe_end
= cur_pe_start
+ 8 * nptes
;
830 dst
+= nptes
* AMDGPU_GPU_PAGE_SIZE
;
832 /* walk over the address space and update the page tables */
834 pt_idx
= addr
>> amdgpu_vm_block_size
;
835 pt
= vm
->page_tables
[pt_idx
].entry
.robj
;
837 if ((addr
& ~mask
) == (end
& ~mask
))
840 nptes
= AMDGPU_VM_PTE_COUNT
- (addr
& mask
);
842 next_pe_start
= amdgpu_bo_gpu_offset(pt
);
843 next_pe_start
+= (addr
& mask
) * 8;
845 if (cur_pe_end
== next_pe_start
) {
846 /* The next ptb is consecutive to current ptb.
847 * Don't call amdgpu_vm_frag_ptes now.
848 * Will update two ptbs together in future.
850 cur_pe_end
+= 8 * nptes
;
852 amdgpu_vm_frag_ptes(adev
, params
,
853 cur_pe_start
, cur_pe_end
,
856 cur_pe_start
= next_pe_start
;
857 cur_pe_end
= next_pe_start
+ 8 * nptes
;
863 dst
+= nptes
* AMDGPU_GPU_PAGE_SIZE
;
866 amdgpu_vm_frag_ptes(adev
, params
, cur_pe_start
,
867 cur_pe_end
, cur_dst
, flags
);
871 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
873 * @adev: amdgpu_device pointer
874 * @exclusive: fence we need to sync to
875 * @src: address where to copy page table entries from
876 * @pages_addr: DMA addresses to use for mapping
878 * @start: start of mapped range
879 * @last: last mapped entry
880 * @flags: flags for the entries
881 * @addr: addr to set the area to
882 * @fence: optional resulting fence
884 * Fill in the page table entries between @start and @last.
885 * Returns 0 for success, -EINVAL for failure.
887 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device
*adev
,
888 struct fence
*exclusive
,
890 dma_addr_t
*pages_addr
,
891 struct amdgpu_vm
*vm
,
892 uint64_t start
, uint64_t last
,
893 uint32_t flags
, uint64_t addr
,
894 struct fence
**fence
)
896 struct amdgpu_ring
*ring
;
897 void *owner
= AMDGPU_FENCE_OWNER_VM
;
898 unsigned nptes
, ncmds
, ndw
;
899 struct amdgpu_job
*job
;
900 struct amdgpu_pte_update_params params
;
901 struct fence
*f
= NULL
;
904 ring
= container_of(vm
->entity
.sched
, struct amdgpu_ring
, sched
);
905 memset(¶ms
, 0, sizeof(params
));
907 params
.pages_addr
= pages_addr
;
909 /* sync to everything on unmapping */
910 if (!(flags
& AMDGPU_PTE_VALID
))
911 owner
= AMDGPU_FENCE_OWNER_UNDEFINED
;
913 nptes
= last
- start
+ 1;
916 * reserve space for one command every (1 << BLOCK_SIZE)
917 * entries or 2k dwords (whatever is smaller)
919 ncmds
= (nptes
>> min(amdgpu_vm_block_size
, 11)) + 1;
925 /* only copy commands needed */
928 } else if (params
.pages_addr
) {
929 /* header for write data commands */
932 /* body of write data command */
936 /* set page commands needed */
939 /* two extra commands for begin/end of fragment */
943 r
= amdgpu_job_alloc_with_ib(adev
, ndw
* 4, &job
);
947 params
.ib
= &job
->ibs
[0];
949 r
= amdgpu_sync_fence(adev
, &job
->sync
, exclusive
);
953 r
= amdgpu_sync_resv(adev
, &job
->sync
, vm
->page_directory
->tbo
.resv
,
958 r
= reservation_object_reserve_shared(vm
->page_directory
->tbo
.resv
);
962 amdgpu_vm_update_ptes(adev
, ¶ms
, vm
, start
,
963 last
+ 1, addr
, flags
);
965 amdgpu_ring_pad_ib(ring
, params
.ib
);
966 WARN_ON(params
.ib
->length_dw
> ndw
);
967 r
= amdgpu_job_submit(job
, ring
, &vm
->entity
,
968 AMDGPU_FENCE_OWNER_VM
, &f
);
972 amdgpu_bo_fence(vm
->page_directory
, f
, true);
975 *fence
= fence_get(f
);
981 amdgpu_job_free(job
);
986 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
988 * @adev: amdgpu_device pointer
989 * @exclusive: fence we need to sync to
990 * @gtt_flags: flags as they are used for GTT
991 * @pages_addr: DMA addresses to use for mapping
993 * @mapping: mapped range and flags to use for the update
994 * @addr: addr to set the area to
995 * @flags: HW flags for the mapping
996 * @fence: optional resulting fence
998 * Split the mapping into smaller chunks so that each update fits
1000 * Returns 0 for success, -EINVAL for failure.
1002 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device
*adev
,
1003 struct fence
*exclusive
,
1005 dma_addr_t
*pages_addr
,
1006 struct amdgpu_vm
*vm
,
1007 struct amdgpu_bo_va_mapping
*mapping
,
1008 uint32_t flags
, uint64_t addr
,
1009 struct fence
**fence
)
1011 const uint64_t max_size
= 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE
;
1013 uint64_t src
= 0, start
= mapping
->it
.start
;
1016 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1017 * but in case of something, we filter the flags in first place
1019 if (!(mapping
->flags
& AMDGPU_PTE_READABLE
))
1020 flags
&= ~AMDGPU_PTE_READABLE
;
1021 if (!(mapping
->flags
& AMDGPU_PTE_WRITEABLE
))
1022 flags
&= ~AMDGPU_PTE_WRITEABLE
;
1024 trace_amdgpu_vm_bo_update(mapping
);
1027 if (flags
== gtt_flags
)
1028 src
= adev
->gart
.table_addr
+ (addr
>> 12) * 8;
1031 addr
+= mapping
->offset
;
1033 if (!pages_addr
|| src
)
1034 return amdgpu_vm_bo_update_mapping(adev
, exclusive
,
1035 src
, pages_addr
, vm
,
1036 start
, mapping
->it
.last
,
1037 flags
, addr
, fence
);
1039 while (start
!= mapping
->it
.last
+ 1) {
1042 last
= min((uint64_t)mapping
->it
.last
, start
+ max_size
- 1);
1043 r
= amdgpu_vm_bo_update_mapping(adev
, exclusive
,
1044 src
, pages_addr
, vm
,
1045 start
, last
, flags
, addr
,
1051 addr
+= max_size
* AMDGPU_GPU_PAGE_SIZE
;
1058 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1060 * @adev: amdgpu_device pointer
1061 * @bo_va: requested BO and VM object
1064 * Fill in the page table entries for @bo_va.
1065 * Returns 0 for success, -EINVAL for failure.
1067 * Object have to be reserved and mutex must be locked!
1069 int amdgpu_vm_bo_update(struct amdgpu_device
*adev
,
1070 struct amdgpu_bo_va
*bo_va
,
1071 struct ttm_mem_reg
*mem
)
1073 struct amdgpu_vm
*vm
= bo_va
->vm
;
1074 struct amdgpu_bo_va_mapping
*mapping
;
1075 dma_addr_t
*pages_addr
= NULL
;
1076 uint32_t gtt_flags
, flags
;
1077 struct fence
*exclusive
;
1082 struct ttm_dma_tt
*ttm
;
1084 addr
= (u64
)mem
->start
<< PAGE_SHIFT
;
1085 switch (mem
->mem_type
) {
1087 ttm
= container_of(bo_va
->bo
->tbo
.ttm
, struct
1089 pages_addr
= ttm
->dma_address
;
1093 addr
+= adev
->vm_manager
.vram_base_offset
;
1100 exclusive
= reservation_object_get_excl(bo_va
->bo
->tbo
.resv
);
1106 flags
= amdgpu_ttm_tt_pte_flags(adev
, bo_va
->bo
->tbo
.ttm
, mem
);
1107 gtt_flags
= (adev
== bo_va
->bo
->adev
) ? flags
: 0;
1109 spin_lock(&vm
->status_lock
);
1110 if (!list_empty(&bo_va
->vm_status
))
1111 list_splice_init(&bo_va
->valids
, &bo_va
->invalids
);
1112 spin_unlock(&vm
->status_lock
);
1114 list_for_each_entry(mapping
, &bo_va
->invalids
, list
) {
1115 r
= amdgpu_vm_bo_split_mapping(adev
, exclusive
,
1116 gtt_flags
, pages_addr
, vm
,
1117 mapping
, flags
, addr
,
1118 &bo_va
->last_pt_update
);
1123 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1124 list_for_each_entry(mapping
, &bo_va
->valids
, list
)
1125 trace_amdgpu_vm_bo_mapping(mapping
);
1127 list_for_each_entry(mapping
, &bo_va
->invalids
, list
)
1128 trace_amdgpu_vm_bo_mapping(mapping
);
1131 spin_lock(&vm
->status_lock
);
1132 list_splice_init(&bo_va
->invalids
, &bo_va
->valids
);
1133 list_del_init(&bo_va
->vm_status
);
1135 list_add(&bo_va
->vm_status
, &vm
->cleared
);
1136 spin_unlock(&vm
->status_lock
);
1142 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1144 * @adev: amdgpu_device pointer
1147 * Make sure all freed BOs are cleared in the PT.
1148 * Returns 0 for success.
1150 * PTs have to be reserved and mutex must be locked!
1152 int amdgpu_vm_clear_freed(struct amdgpu_device
*adev
,
1153 struct amdgpu_vm
*vm
)
1155 struct amdgpu_bo_va_mapping
*mapping
;
1158 while (!list_empty(&vm
->freed
)) {
1159 mapping
= list_first_entry(&vm
->freed
,
1160 struct amdgpu_bo_va_mapping
, list
);
1161 list_del(&mapping
->list
);
1163 r
= amdgpu_vm_bo_split_mapping(adev
, NULL
, 0, NULL
, vm
, mapping
,
1175 * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
1177 * @adev: amdgpu_device pointer
1180 * Make sure all invalidated BOs are cleared in the PT.
1181 * Returns 0 for success.
1183 * PTs have to be reserved and mutex must be locked!
1185 int amdgpu_vm_clear_invalids(struct amdgpu_device
*adev
,
1186 struct amdgpu_vm
*vm
, struct amdgpu_sync
*sync
)
1188 struct amdgpu_bo_va
*bo_va
= NULL
;
1191 spin_lock(&vm
->status_lock
);
1192 while (!list_empty(&vm
->invalidated
)) {
1193 bo_va
= list_first_entry(&vm
->invalidated
,
1194 struct amdgpu_bo_va
, vm_status
);
1195 spin_unlock(&vm
->status_lock
);
1197 r
= amdgpu_vm_bo_update(adev
, bo_va
, NULL
);
1201 spin_lock(&vm
->status_lock
);
1203 spin_unlock(&vm
->status_lock
);
1206 r
= amdgpu_sync_fence(adev
, sync
, bo_va
->last_pt_update
);
1212 * amdgpu_vm_bo_add - add a bo to a specific vm
1214 * @adev: amdgpu_device pointer
1216 * @bo: amdgpu buffer object
1218 * Add @bo into the requested vm.
1219 * Add @bo to the list of bos associated with the vm
1220 * Returns newly added bo_va or NULL for failure
1222 * Object has to be reserved!
1224 struct amdgpu_bo_va
*amdgpu_vm_bo_add(struct amdgpu_device
*adev
,
1225 struct amdgpu_vm
*vm
,
1226 struct amdgpu_bo
*bo
)
1228 struct amdgpu_bo_va
*bo_va
;
1230 bo_va
= kzalloc(sizeof(struct amdgpu_bo_va
), GFP_KERNEL
);
1231 if (bo_va
== NULL
) {
1236 bo_va
->ref_count
= 1;
1237 INIT_LIST_HEAD(&bo_va
->bo_list
);
1238 INIT_LIST_HEAD(&bo_va
->valids
);
1239 INIT_LIST_HEAD(&bo_va
->invalids
);
1240 INIT_LIST_HEAD(&bo_va
->vm_status
);
1242 list_add_tail(&bo_va
->bo_list
, &bo
->va
);
1248 * amdgpu_vm_bo_map - map bo inside a vm
1250 * @adev: amdgpu_device pointer
1251 * @bo_va: bo_va to store the address
1252 * @saddr: where to map the BO
1253 * @offset: requested offset in the BO
1254 * @flags: attributes of pages (read/write/valid/etc.)
1256 * Add a mapping of the BO at the specefied addr into the VM.
1257 * Returns 0 for success, error for failure.
1259 * Object has to be reserved and unreserved outside!
1261 int amdgpu_vm_bo_map(struct amdgpu_device
*adev
,
1262 struct amdgpu_bo_va
*bo_va
,
1263 uint64_t saddr
, uint64_t offset
,
1264 uint64_t size
, uint32_t flags
)
1266 struct amdgpu_bo_va_mapping
*mapping
;
1267 struct amdgpu_vm
*vm
= bo_va
->vm
;
1268 struct interval_tree_node
*it
;
1269 unsigned last_pfn
, pt_idx
;
1273 /* validate the parameters */
1274 if (saddr
& AMDGPU_GPU_PAGE_MASK
|| offset
& AMDGPU_GPU_PAGE_MASK
||
1275 size
== 0 || size
& AMDGPU_GPU_PAGE_MASK
)
1278 /* make sure object fit at this offset */
1279 eaddr
= saddr
+ size
- 1;
1280 if ((saddr
>= eaddr
) || (offset
+ size
> amdgpu_bo_size(bo_va
->bo
)))
1283 last_pfn
= eaddr
/ AMDGPU_GPU_PAGE_SIZE
;
1284 if (last_pfn
>= adev
->vm_manager
.max_pfn
) {
1285 dev_err(adev
->dev
, "va above limit (0x%08X >= 0x%08X)\n",
1286 last_pfn
, adev
->vm_manager
.max_pfn
);
1290 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
1291 eaddr
/= AMDGPU_GPU_PAGE_SIZE
;
1293 it
= interval_tree_iter_first(&vm
->va
, saddr
, eaddr
);
1295 struct amdgpu_bo_va_mapping
*tmp
;
1296 tmp
= container_of(it
, struct amdgpu_bo_va_mapping
, it
);
1297 /* bo and tmp overlap, invalid addr */
1298 dev_err(adev
->dev
, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1299 "0x%010lx-0x%010lx\n", bo_va
->bo
, saddr
, eaddr
,
1300 tmp
->it
.start
, tmp
->it
.last
+ 1);
1305 mapping
= kmalloc(sizeof(*mapping
), GFP_KERNEL
);
1311 INIT_LIST_HEAD(&mapping
->list
);
1312 mapping
->it
.start
= saddr
;
1313 mapping
->it
.last
= eaddr
;
1314 mapping
->offset
= offset
;
1315 mapping
->flags
= flags
;
1317 list_add(&mapping
->list
, &bo_va
->invalids
);
1318 interval_tree_insert(&mapping
->it
, &vm
->va
);
1320 /* Make sure the page tables are allocated */
1321 saddr
>>= amdgpu_vm_block_size
;
1322 eaddr
>>= amdgpu_vm_block_size
;
1324 BUG_ON(eaddr
>= amdgpu_vm_num_pdes(adev
));
1326 if (eaddr
> vm
->max_pde_used
)
1327 vm
->max_pde_used
= eaddr
;
1329 /* walk over the address space and allocate the page tables */
1330 for (pt_idx
= saddr
; pt_idx
<= eaddr
; ++pt_idx
) {
1331 struct reservation_object
*resv
= vm
->page_directory
->tbo
.resv
;
1332 struct amdgpu_bo_list_entry
*entry
;
1333 struct amdgpu_bo
*pt
;
1335 entry
= &vm
->page_tables
[pt_idx
].entry
;
1339 r
= amdgpu_bo_create(adev
, AMDGPU_VM_PTE_COUNT
* 8,
1340 AMDGPU_GPU_PAGE_SIZE
, true,
1341 AMDGPU_GEM_DOMAIN_VRAM
,
1342 AMDGPU_GEM_CREATE_NO_CPU_ACCESS
,
1347 /* Keep a reference to the page table to avoid freeing
1348 * them up in the wrong order.
1350 pt
->parent
= amdgpu_bo_ref(vm
->page_directory
);
1352 r
= amdgpu_vm_clear_bo(adev
, vm
, pt
);
1354 amdgpu_bo_unref(&pt
);
1359 entry
->priority
= 0;
1360 entry
->tv
.bo
= &entry
->robj
->tbo
;
1361 entry
->tv
.shared
= true;
1362 entry
->user_pages
= NULL
;
1363 vm
->page_tables
[pt_idx
].addr
= 0;
1369 list_del(&mapping
->list
);
1370 interval_tree_remove(&mapping
->it
, &vm
->va
);
1371 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
1379 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1381 * @adev: amdgpu_device pointer
1382 * @bo_va: bo_va to remove the address from
1383 * @saddr: where to the BO is mapped
1385 * Remove a mapping of the BO at the specefied addr from the VM.
1386 * Returns 0 for success, error for failure.
1388 * Object has to be reserved and unreserved outside!
1390 int amdgpu_vm_bo_unmap(struct amdgpu_device
*adev
,
1391 struct amdgpu_bo_va
*bo_va
,
1394 struct amdgpu_bo_va_mapping
*mapping
;
1395 struct amdgpu_vm
*vm
= bo_va
->vm
;
1398 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
1400 list_for_each_entry(mapping
, &bo_va
->valids
, list
) {
1401 if (mapping
->it
.start
== saddr
)
1405 if (&mapping
->list
== &bo_va
->valids
) {
1408 list_for_each_entry(mapping
, &bo_va
->invalids
, list
) {
1409 if (mapping
->it
.start
== saddr
)
1413 if (&mapping
->list
== &bo_va
->invalids
)
1417 list_del(&mapping
->list
);
1418 interval_tree_remove(&mapping
->it
, &vm
->va
);
1419 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
1422 list_add(&mapping
->list
, &vm
->freed
);
1430 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
1432 * @adev: amdgpu_device pointer
1433 * @bo_va: requested bo_va
1435 * Remove @bo_va->bo from the requested vm.
1437 * Object have to be reserved!
1439 void amdgpu_vm_bo_rmv(struct amdgpu_device
*adev
,
1440 struct amdgpu_bo_va
*bo_va
)
1442 struct amdgpu_bo_va_mapping
*mapping
, *next
;
1443 struct amdgpu_vm
*vm
= bo_va
->vm
;
1445 list_del(&bo_va
->bo_list
);
1447 spin_lock(&vm
->status_lock
);
1448 list_del(&bo_va
->vm_status
);
1449 spin_unlock(&vm
->status_lock
);
1451 list_for_each_entry_safe(mapping
, next
, &bo_va
->valids
, list
) {
1452 list_del(&mapping
->list
);
1453 interval_tree_remove(&mapping
->it
, &vm
->va
);
1454 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
1455 list_add(&mapping
->list
, &vm
->freed
);
1457 list_for_each_entry_safe(mapping
, next
, &bo_va
->invalids
, list
) {
1458 list_del(&mapping
->list
);
1459 interval_tree_remove(&mapping
->it
, &vm
->va
);
1463 fence_put(bo_va
->last_pt_update
);
1468 * amdgpu_vm_bo_invalidate - mark the bo as invalid
1470 * @adev: amdgpu_device pointer
1472 * @bo: amdgpu buffer object
1474 * Mark @bo as invalid.
1476 void amdgpu_vm_bo_invalidate(struct amdgpu_device
*adev
,
1477 struct amdgpu_bo
*bo
)
1479 struct amdgpu_bo_va
*bo_va
;
1481 list_for_each_entry(bo_va
, &bo
->va
, bo_list
) {
1482 spin_lock(&bo_va
->vm
->status_lock
);
1483 if (list_empty(&bo_va
->vm_status
))
1484 list_add(&bo_va
->vm_status
, &bo_va
->vm
->invalidated
);
1485 spin_unlock(&bo_va
->vm
->status_lock
);
1490 * amdgpu_vm_init - initialize a vm instance
1492 * @adev: amdgpu_device pointer
1497 int amdgpu_vm_init(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
1499 const unsigned align
= min(AMDGPU_VM_PTB_ALIGN_SIZE
,
1500 AMDGPU_VM_PTE_COUNT
* 8);
1501 unsigned pd_size
, pd_entries
;
1502 unsigned ring_instance
;
1503 struct amdgpu_ring
*ring
;
1504 struct amd_sched_rq
*rq
;
1507 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
)
1510 vm
->client_id
= atomic64_inc_return(&adev
->vm_manager
.client_counter
);
1511 spin_lock_init(&vm
->status_lock
);
1512 INIT_LIST_HEAD(&vm
->invalidated
);
1513 INIT_LIST_HEAD(&vm
->cleared
);
1514 INIT_LIST_HEAD(&vm
->freed
);
1516 pd_size
= amdgpu_vm_directory_size(adev
);
1517 pd_entries
= amdgpu_vm_num_pdes(adev
);
1519 /* allocate page table array */
1520 vm
->page_tables
= drm_calloc_large(pd_entries
, sizeof(struct amdgpu_vm_pt
));
1521 if (vm
->page_tables
== NULL
) {
1522 DRM_ERROR("Cannot allocate memory for page table array\n");
1526 /* create scheduler entity for page table updates */
1528 ring_instance
= atomic_inc_return(&adev
->vm_manager
.vm_pte_next_ring
);
1529 ring_instance
%= adev
->vm_manager
.vm_pte_num_rings
;
1530 ring
= adev
->vm_manager
.vm_pte_rings
[ring_instance
];
1531 rq
= &ring
->sched
.sched_rq
[AMD_SCHED_PRIORITY_KERNEL
];
1532 r
= amd_sched_entity_init(&ring
->sched
, &vm
->entity
,
1533 rq
, amdgpu_sched_jobs
);
1537 vm
->page_directory_fence
= NULL
;
1539 r
= amdgpu_bo_create(adev
, pd_size
, align
, true,
1540 AMDGPU_GEM_DOMAIN_VRAM
,
1541 AMDGPU_GEM_CREATE_NO_CPU_ACCESS
,
1542 NULL
, NULL
, &vm
->page_directory
);
1544 goto error_free_sched_entity
;
1546 r
= amdgpu_bo_reserve(vm
->page_directory
, false);
1548 goto error_free_page_directory
;
1550 r
= amdgpu_vm_clear_bo(adev
, vm
, vm
->page_directory
);
1551 amdgpu_bo_unreserve(vm
->page_directory
);
1553 goto error_free_page_directory
;
1554 vm
->last_eviction_counter
= atomic64_read(&adev
->num_evictions
);
1558 error_free_page_directory
:
1559 amdgpu_bo_unref(&vm
->page_directory
);
1560 vm
->page_directory
= NULL
;
1562 error_free_sched_entity
:
1563 amd_sched_entity_fini(&ring
->sched
, &vm
->entity
);
1569 * amdgpu_vm_fini - tear down a vm instance
1571 * @adev: amdgpu_device pointer
1575 * Unbind the VM and remove all bos from the vm bo list
1577 void amdgpu_vm_fini(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
1579 struct amdgpu_bo_va_mapping
*mapping
, *tmp
;
1582 amd_sched_entity_fini(vm
->entity
.sched
, &vm
->entity
);
1584 if (!RB_EMPTY_ROOT(&vm
->va
)) {
1585 dev_err(adev
->dev
, "still active bo inside vm\n");
1587 rbtree_postorder_for_each_entry_safe(mapping
, tmp
, &vm
->va
, it
.rb
) {
1588 list_del(&mapping
->list
);
1589 interval_tree_remove(&mapping
->it
, &vm
->va
);
1592 list_for_each_entry_safe(mapping
, tmp
, &vm
->freed
, list
) {
1593 list_del(&mapping
->list
);
1597 for (i
= 0; i
< amdgpu_vm_num_pdes(adev
); i
++)
1598 amdgpu_bo_unref(&vm
->page_tables
[i
].entry
.robj
);
1599 drm_free_large(vm
->page_tables
);
1601 amdgpu_bo_unref(&vm
->page_directory
);
1602 fence_put(vm
->page_directory_fence
);
1606 * amdgpu_vm_manager_init - init the VM manager
1608 * @adev: amdgpu_device pointer
1610 * Initialize the VM manager structures
1612 void amdgpu_vm_manager_init(struct amdgpu_device
*adev
)
1616 INIT_LIST_HEAD(&adev
->vm_manager
.ids_lru
);
1618 /* skip over VMID 0, since it is the system VM */
1619 for (i
= 1; i
< adev
->vm_manager
.num_ids
; ++i
) {
1620 amdgpu_vm_reset_id(adev
, i
);
1621 amdgpu_sync_create(&adev
->vm_manager
.ids
[i
].active
);
1622 list_add_tail(&adev
->vm_manager
.ids
[i
].list
,
1623 &adev
->vm_manager
.ids_lru
);
1626 adev
->vm_manager
.fence_context
= fence_context_alloc(AMDGPU_MAX_RINGS
);
1627 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
)
1628 adev
->vm_manager
.seqno
[i
] = 0;
1630 atomic_set(&adev
->vm_manager
.vm_pte_next_ring
, 0);
1631 atomic64_set(&adev
->vm_manager
.client_counter
, 0);
1635 * amdgpu_vm_manager_fini - cleanup VM manager
1637 * @adev: amdgpu_device pointer
1639 * Cleanup the VM manager and free resources.
1641 void amdgpu_vm_manager_fini(struct amdgpu_device
*adev
)
1645 for (i
= 0; i
< AMDGPU_NUM_VM
; ++i
) {
1646 struct amdgpu_vm_id
*id
= &adev
->vm_manager
.ids
[i
];
1648 fence_put(adev
->vm_manager
.ids
[i
].first
);
1649 amdgpu_sync_free(&adev
->vm_manager
.ids
[i
].active
);
1650 fence_put(id
->flushed_updates
);