2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/dma-fence-array.h>
29 #include <linux/interval_tree_generic.h>
30 #include <linux/idr.h>
32 #include <drm/amdgpu_drm.h>
34 #include "amdgpu_trace.h"
35 #include "amdgpu_amdkfd.h"
36 #include "amdgpu_gmc.h"
37 #include "amdgpu_xgmi.h"
42 * GPUVM is similar to the legacy gart on older asics, however
43 * rather than there being a single global gart table
44 * for the entire GPU, there are multiple VM page tables active
45 * at any given time. The VM page tables can contain a mix
46 * vram pages and system memory pages and system memory pages
47 * can be mapped as snooped (cached system pages) or unsnooped
48 * (uncached system pages).
49 * Each VM has an ID associated with it and there is a page table
50 * associated with each VMID. When execting a command buffer,
51 * the kernel tells the the ring what VMID to use for that command
52 * buffer. VMIDs are allocated dynamically as commands are submitted.
53 * The userspace drivers maintain their own address space and the kernel
54 * sets up their pages tables accordingly when they submit their
55 * command buffers and a VMID is assigned.
56 * Cayman/Trinity support up to 8 active VMs at any given time;
60 #define START(node) ((node)->start)
61 #define LAST(node) ((node)->last)
63 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping
, rb
, uint64_t, __subtree_last
,
64 START
, LAST
, static, amdgpu_vm_it
)
70 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
72 struct amdgpu_prt_cb
{
75 * @adev: amdgpu device
77 struct amdgpu_device
*adev
;
82 struct dma_fence_cb cb
;
86 * amdgpu_vm_level_shift - return the addr shift for each level
88 * @adev: amdgpu_device pointer
92 * The number of bits the pfn needs to be right shifted for a level.
94 static unsigned amdgpu_vm_level_shift(struct amdgpu_device
*adev
,
97 unsigned shift
= 0xff;
103 shift
= 9 * (AMDGPU_VM_PDB0
- level
) +
104 adev
->vm_manager
.block_size
;
110 dev_err(adev
->dev
, "the level%d isn't supported.\n", level
);
117 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
119 * @adev: amdgpu_device pointer
123 * The number of entries in a page directory or page table.
125 static unsigned amdgpu_vm_num_entries(struct amdgpu_device
*adev
,
128 unsigned shift
= amdgpu_vm_level_shift(adev
,
129 adev
->vm_manager
.root_level
);
131 if (level
== adev
->vm_manager
.root_level
)
132 /* For the root directory */
133 return round_up(adev
->vm_manager
.max_pfn
, 1ULL << shift
) >> shift
;
134 else if (level
!= AMDGPU_VM_PTB
)
135 /* Everything in between */
138 /* For the page tables on the leaves */
139 return AMDGPU_VM_PTE_COUNT(adev
);
143 * amdgpu_vm_num_ats_entries - return the number of ATS entries in the root PD
145 * @adev: amdgpu_device pointer
148 * The number of entries in the root page directory which needs the ATS setting.
150 static unsigned amdgpu_vm_num_ats_entries(struct amdgpu_device
*adev
)
154 shift
= amdgpu_vm_level_shift(adev
, adev
->vm_manager
.root_level
);
155 return AMDGPU_GMC_HOLE_START
>> (shift
+ AMDGPU_GPU_PAGE_SHIFT
);
159 * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
161 * @adev: amdgpu_device pointer
165 * The mask to extract the entry number of a PD/PT from an address.
167 static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device
*adev
,
170 if (level
<= adev
->vm_manager
.root_level
)
172 else if (level
!= AMDGPU_VM_PTB
)
175 return AMDGPU_VM_PTE_COUNT(adev
) - 1;
179 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
181 * @adev: amdgpu_device pointer
185 * The size of the BO for a page directory or page table in bytes.
187 static unsigned amdgpu_vm_bo_size(struct amdgpu_device
*adev
, unsigned level
)
189 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev
, level
) * 8);
193 * amdgpu_vm_bo_evicted - vm_bo is evicted
195 * @vm_bo: vm_bo which is evicted
197 * State for PDs/PTs and per VM BOs which are not at the location they should
200 static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base
*vm_bo
)
202 struct amdgpu_vm
*vm
= vm_bo
->vm
;
203 struct amdgpu_bo
*bo
= vm_bo
->bo
;
206 if (bo
->tbo
.type
== ttm_bo_type_kernel
)
207 list_move(&vm_bo
->vm_status
, &vm
->evicted
);
209 list_move_tail(&vm_bo
->vm_status
, &vm
->evicted
);
213 * amdgpu_vm_bo_relocated - vm_bo is reloacted
215 * @vm_bo: vm_bo which is relocated
217 * State for PDs/PTs which needs to update their parent PD.
219 static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base
*vm_bo
)
221 list_move(&vm_bo
->vm_status
, &vm_bo
->vm
->relocated
);
225 * amdgpu_vm_bo_moved - vm_bo is moved
227 * @vm_bo: vm_bo which is moved
229 * State for per VM BOs which are moved, but that change is not yet reflected
230 * in the page tables.
232 static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base
*vm_bo
)
234 list_move(&vm_bo
->vm_status
, &vm_bo
->vm
->moved
);
238 * amdgpu_vm_bo_idle - vm_bo is idle
240 * @vm_bo: vm_bo which is now idle
242 * State for PDs/PTs and per VM BOs which have gone through the state machine
245 static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base
*vm_bo
)
247 list_move(&vm_bo
->vm_status
, &vm_bo
->vm
->idle
);
248 vm_bo
->moved
= false;
252 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
254 * @vm_bo: vm_bo which is now invalidated
256 * State for normal BOs which are invalidated and that change not yet reflected
259 static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base
*vm_bo
)
261 spin_lock(&vm_bo
->vm
->invalidated_lock
);
262 list_move(&vm_bo
->vm_status
, &vm_bo
->vm
->invalidated
);
263 spin_unlock(&vm_bo
->vm
->invalidated_lock
);
267 * amdgpu_vm_bo_done - vm_bo is done
269 * @vm_bo: vm_bo which is now done
271 * State for normal BOs which are invalidated and that change has been updated
274 static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base
*vm_bo
)
276 spin_lock(&vm_bo
->vm
->invalidated_lock
);
277 list_del_init(&vm_bo
->vm_status
);
278 spin_unlock(&vm_bo
->vm
->invalidated_lock
);
282 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
284 * @base: base structure for tracking BO usage in a VM
285 * @vm: vm to which bo is to be added
286 * @bo: amdgpu buffer object
288 * Initialize a bo_va_base structure and add it to the appropriate lists
291 static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base
*base
,
292 struct amdgpu_vm
*vm
,
293 struct amdgpu_bo
*bo
)
298 INIT_LIST_HEAD(&base
->vm_status
);
302 base
->next
= bo
->vm_bo
;
305 if (bo
->tbo
.resv
!= vm
->root
.base
.bo
->tbo
.resv
)
308 vm
->bulk_moveable
= false;
309 if (bo
->tbo
.type
== ttm_bo_type_kernel
)
310 amdgpu_vm_bo_relocated(base
);
312 amdgpu_vm_bo_idle(base
);
314 if (bo
->preferred_domains
&
315 amdgpu_mem_type_to_domain(bo
->tbo
.mem
.mem_type
))
319 * we checked all the prerequisites, but it looks like this per vm bo
320 * is currently evicted. add the bo to the evicted list to make sure it
321 * is validated on next vm use to avoid fault.
323 amdgpu_vm_bo_evicted(base
);
327 * amdgpu_vm_pt_parent - get the parent page directory
329 * @pt: child page table
331 * Helper to get the parent entry for the child page table. NULL if we are at
332 * the root page directory.
334 static struct amdgpu_vm_pt
*amdgpu_vm_pt_parent(struct amdgpu_vm_pt
*pt
)
336 struct amdgpu_bo
*parent
= pt
->base
.bo
->parent
;
341 return container_of(parent
->vm_bo
, struct amdgpu_vm_pt
, base
);
345 * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
347 struct amdgpu_vm_pt_cursor
{
349 struct amdgpu_vm_pt
*parent
;
350 struct amdgpu_vm_pt
*entry
;
355 * amdgpu_vm_pt_start - start PD/PT walk
357 * @adev: amdgpu_device pointer
358 * @vm: amdgpu_vm structure
359 * @start: start address of the walk
360 * @cursor: state to initialize
362 * Initialize a amdgpu_vm_pt_cursor to start a walk.
364 static void amdgpu_vm_pt_start(struct amdgpu_device
*adev
,
365 struct amdgpu_vm
*vm
, uint64_t start
,
366 struct amdgpu_vm_pt_cursor
*cursor
)
369 cursor
->parent
= NULL
;
370 cursor
->entry
= &vm
->root
;
371 cursor
->level
= adev
->vm_manager
.root_level
;
375 * amdgpu_vm_pt_descendant - go to child node
377 * @adev: amdgpu_device pointer
378 * @cursor: current state
380 * Walk to the child node of the current node.
382 * True if the walk was possible, false otherwise.
384 static bool amdgpu_vm_pt_descendant(struct amdgpu_device
*adev
,
385 struct amdgpu_vm_pt_cursor
*cursor
)
387 unsigned mask
, shift
, idx
;
389 if (!cursor
->entry
->entries
)
392 BUG_ON(!cursor
->entry
->base
.bo
);
393 mask
= amdgpu_vm_entries_mask(adev
, cursor
->level
);
394 shift
= amdgpu_vm_level_shift(adev
, cursor
->level
);
397 idx
= (cursor
->pfn
>> shift
) & mask
;
398 cursor
->parent
= cursor
->entry
;
399 cursor
->entry
= &cursor
->entry
->entries
[idx
];
404 * amdgpu_vm_pt_sibling - go to sibling node
406 * @adev: amdgpu_device pointer
407 * @cursor: current state
409 * Walk to the sibling node of the current node.
411 * True if the walk was possible, false otherwise.
413 static bool amdgpu_vm_pt_sibling(struct amdgpu_device
*adev
,
414 struct amdgpu_vm_pt_cursor
*cursor
)
416 unsigned shift
, num_entries
;
418 /* Root doesn't have a sibling */
422 /* Go to our parents and see if we got a sibling */
423 shift
= amdgpu_vm_level_shift(adev
, cursor
->level
- 1);
424 num_entries
= amdgpu_vm_num_entries(adev
, cursor
->level
- 1);
426 if (cursor
->entry
== &cursor
->parent
->entries
[num_entries
- 1])
429 cursor
->pfn
+= 1ULL << shift
;
430 cursor
->pfn
&= ~((1ULL << shift
) - 1);
436 * amdgpu_vm_pt_ancestor - go to parent node
438 * @cursor: current state
440 * Walk to the parent node of the current node.
442 * True if the walk was possible, false otherwise.
444 static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor
*cursor
)
450 cursor
->entry
= cursor
->parent
;
451 cursor
->parent
= amdgpu_vm_pt_parent(cursor
->parent
);
456 * amdgpu_vm_pt_next - get next PD/PT in hieratchy
458 * @adev: amdgpu_device pointer
459 * @cursor: current state
461 * Walk the PD/PT tree to the next node.
463 static void amdgpu_vm_pt_next(struct amdgpu_device
*adev
,
464 struct amdgpu_vm_pt_cursor
*cursor
)
466 /* First try a newborn child */
467 if (amdgpu_vm_pt_descendant(adev
, cursor
))
470 /* If that didn't worked try to find a sibling */
471 while (!amdgpu_vm_pt_sibling(adev
, cursor
)) {
472 /* No sibling, go to our parents and grandparents */
473 if (!amdgpu_vm_pt_ancestor(cursor
)) {
481 * amdgpu_vm_pt_first_dfs - start a deep first search
483 * @adev: amdgpu_device structure
484 * @vm: amdgpu_vm structure
485 * @cursor: state to initialize
487 * Starts a deep first traversal of the PD/PT tree.
489 static void amdgpu_vm_pt_first_dfs(struct amdgpu_device
*adev
,
490 struct amdgpu_vm
*vm
,
491 struct amdgpu_vm_pt_cursor
*start
,
492 struct amdgpu_vm_pt_cursor
*cursor
)
497 amdgpu_vm_pt_start(adev
, vm
, 0, cursor
);
498 while (amdgpu_vm_pt_descendant(adev
, cursor
));
502 * amdgpu_vm_pt_continue_dfs - check if the deep first search should continue
504 * @start: starting point for the search
505 * @entry: current entry
508 * True when the search should continue, false otherwise.
510 static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor
*start
,
511 struct amdgpu_vm_pt
*entry
)
513 return entry
&& (!start
|| entry
!= start
->entry
);
517 * amdgpu_vm_pt_next_dfs - get the next node for a deep first search
519 * @adev: amdgpu_device structure
520 * @cursor: current state
522 * Move the cursor to the next node in a deep first search.
524 static void amdgpu_vm_pt_next_dfs(struct amdgpu_device
*adev
,
525 struct amdgpu_vm_pt_cursor
*cursor
)
531 cursor
->entry
= NULL
;
532 else if (amdgpu_vm_pt_sibling(adev
, cursor
))
533 while (amdgpu_vm_pt_descendant(adev
, cursor
));
535 amdgpu_vm_pt_ancestor(cursor
);
539 * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs
541 #define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) \
542 for (amdgpu_vm_pt_first_dfs((adev), (vm), (start), &(cursor)), \
543 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\
544 amdgpu_vm_pt_continue_dfs((start), (entry)); \
545 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor)))
548 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
550 * @vm: vm providing the BOs
551 * @validated: head of validation list
552 * @entry: entry to add
554 * Add the page directory to the list of BOs to
555 * validate for command submission.
557 void amdgpu_vm_get_pd_bo(struct amdgpu_vm
*vm
,
558 struct list_head
*validated
,
559 struct amdgpu_bo_list_entry
*entry
)
562 entry
->tv
.bo
= &vm
->root
.base
.bo
->tbo
;
563 /* One for the VM updates, one for TTM and one for the CS job */
564 entry
->tv
.num_shared
= 3;
565 entry
->user_pages
= NULL
;
566 list_add(&entry
->tv
.head
, validated
);
569 void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object
*bo
)
571 struct amdgpu_bo
*abo
;
572 struct amdgpu_vm_bo_base
*bo_base
;
574 if (!amdgpu_bo_is_amdgpu_bo(bo
))
577 if (bo
->mem
.placement
& TTM_PL_FLAG_NO_EVICT
)
580 abo
= ttm_to_amdgpu_bo(bo
);
583 for (bo_base
= abo
->vm_bo
; bo_base
; bo_base
= bo_base
->next
) {
584 struct amdgpu_vm
*vm
= bo_base
->vm
;
586 if (abo
->tbo
.resv
== vm
->root
.base
.bo
->tbo
.resv
)
587 vm
->bulk_moveable
= false;
592 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
594 * @adev: amdgpu device pointer
595 * @vm: vm providing the BOs
597 * Move all BOs to the end of LRU and remember their positions to put them
600 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device
*adev
,
601 struct amdgpu_vm
*vm
)
603 struct ttm_bo_global
*glob
= adev
->mman
.bdev
.glob
;
604 struct amdgpu_vm_bo_base
*bo_base
;
606 if (vm
->bulk_moveable
) {
607 spin_lock(&glob
->lru_lock
);
608 ttm_bo_bulk_move_lru_tail(&vm
->lru_bulk_move
);
609 spin_unlock(&glob
->lru_lock
);
613 memset(&vm
->lru_bulk_move
, 0, sizeof(vm
->lru_bulk_move
));
615 spin_lock(&glob
->lru_lock
);
616 list_for_each_entry(bo_base
, &vm
->idle
, vm_status
) {
617 struct amdgpu_bo
*bo
= bo_base
->bo
;
622 ttm_bo_move_to_lru_tail(&bo
->tbo
, &vm
->lru_bulk_move
);
624 ttm_bo_move_to_lru_tail(&bo
->shadow
->tbo
,
627 spin_unlock(&glob
->lru_lock
);
629 vm
->bulk_moveable
= true;
633 * amdgpu_vm_validate_pt_bos - validate the page table BOs
635 * @adev: amdgpu device pointer
636 * @vm: vm providing the BOs
637 * @validate: callback to do the validation
638 * @param: parameter for the validation callback
640 * Validate the page table BOs on command submission if neccessary.
645 int amdgpu_vm_validate_pt_bos(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
646 int (*validate
)(void *p
, struct amdgpu_bo
*bo
),
649 struct amdgpu_vm_bo_base
*bo_base
, *tmp
;
652 list_for_each_entry_safe(bo_base
, tmp
, &vm
->evicted
, vm_status
) {
653 struct amdgpu_bo
*bo
= bo_base
->bo
;
655 r
= validate(param
, bo
);
659 if (bo
->tbo
.type
!= ttm_bo_type_kernel
) {
660 amdgpu_vm_bo_moved(bo_base
);
662 vm
->update_funcs
->map_table(bo
);
663 amdgpu_vm_bo_relocated(bo_base
);
671 * amdgpu_vm_ready - check VM is ready for updates
675 * Check if all VM PDs/PTs are ready for updates
678 * True if eviction list is empty.
680 bool amdgpu_vm_ready(struct amdgpu_vm
*vm
)
682 return list_empty(&vm
->evicted
);
686 * amdgpu_vm_clear_bo - initially clear the PDs/PTs
688 * @adev: amdgpu_device pointer
689 * @vm: VM to clear BO from
692 * Root PD needs to be reserved when calling this.
695 * 0 on success, errno otherwise.
697 static int amdgpu_vm_clear_bo(struct amdgpu_device
*adev
,
698 struct amdgpu_vm
*vm
,
699 struct amdgpu_bo
*bo
)
701 struct ttm_operation_ctx ctx
= { true, false };
702 unsigned level
= adev
->vm_manager
.root_level
;
703 struct amdgpu_vm_update_params params
;
704 struct amdgpu_bo
*ancestor
= bo
;
705 unsigned entries
, ats_entries
;
709 /* Figure out our place in the hierarchy */
710 if (ancestor
->parent
) {
712 while (ancestor
->parent
->parent
) {
714 ancestor
= ancestor
->parent
;
718 entries
= amdgpu_bo_size(bo
) / 8;
719 if (!vm
->pte_support_ats
) {
722 } else if (!bo
->parent
) {
723 ats_entries
= amdgpu_vm_num_ats_entries(adev
);
724 ats_entries
= min(ats_entries
, entries
);
725 entries
-= ats_entries
;
728 struct amdgpu_vm_pt
*pt
;
730 pt
= container_of(ancestor
->vm_bo
, struct amdgpu_vm_pt
, base
);
731 ats_entries
= amdgpu_vm_num_ats_entries(adev
);
732 if ((pt
- vm
->root
.entries
) >= ats_entries
) {
735 ats_entries
= entries
;
740 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, &ctx
);
745 r
= ttm_bo_validate(&bo
->shadow
->tbo
, &bo
->shadow
->placement
,
751 r
= vm
->update_funcs
->map_table(bo
);
755 memset(¶ms
, 0, sizeof(params
));
759 r
= vm
->update_funcs
->prepare(¶ms
, AMDGPU_FENCE_OWNER_KFD
, NULL
);
767 ats_value
= AMDGPU_PTE_DEFAULT_ATC
;
768 if (level
!= AMDGPU_VM_PTB
)
769 ats_value
|= AMDGPU_PDE_PTE
;
771 r
= vm
->update_funcs
->update(¶ms
, bo
, addr
, 0, ats_entries
,
776 addr
+= ats_entries
* 8;
782 /* Workaround for fault priority problem on GMC9 */
783 if (level
== AMDGPU_VM_PTB
&&
784 adev
->asic_type
>= CHIP_VEGA10
)
785 value
= AMDGPU_PTE_EXECUTABLE
;
787 r
= vm
->update_funcs
->update(¶ms
, bo
, addr
, 0, entries
,
793 return vm
->update_funcs
->commit(¶ms
, NULL
);
797 * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
799 * @adev: amdgpu_device pointer
801 * @bp: resulting BO allocation parameters
803 static void amdgpu_vm_bo_param(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
804 int level
, struct amdgpu_bo_param
*bp
)
806 memset(bp
, 0, sizeof(*bp
));
808 bp
->size
= amdgpu_vm_bo_size(adev
, level
);
809 bp
->byte_align
= AMDGPU_GPU_PAGE_SIZE
;
810 bp
->domain
= AMDGPU_GEM_DOMAIN_VRAM
;
811 bp
->domain
= amdgpu_bo_get_preferred_pin_domain(adev
, bp
->domain
);
812 bp
->flags
= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
|
813 AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
814 if (vm
->use_cpu_for_update
)
815 bp
->flags
|= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
;
816 else if (!vm
->root
.base
.bo
|| vm
->root
.base
.bo
->shadow
)
817 bp
->flags
|= AMDGPU_GEM_CREATE_SHADOW
;
818 bp
->type
= ttm_bo_type_kernel
;
819 if (vm
->root
.base
.bo
)
820 bp
->resv
= vm
->root
.base
.bo
->tbo
.resv
;
824 * amdgpu_vm_alloc_pts - Allocate a specific page table
826 * @adev: amdgpu_device pointer
827 * @vm: VM to allocate page tables for
828 * @cursor: Which page table to allocate
830 * Make sure a specific page table or directory is allocated.
833 * 1 if page table needed to be allocated, 0 if page table was already
834 * allocated, negative errno if an error occurred.
836 static int amdgpu_vm_alloc_pts(struct amdgpu_device
*adev
,
837 struct amdgpu_vm
*vm
,
838 struct amdgpu_vm_pt_cursor
*cursor
)
840 struct amdgpu_vm_pt
*entry
= cursor
->entry
;
841 struct amdgpu_bo_param bp
;
842 struct amdgpu_bo
*pt
;
845 if (cursor
->level
< AMDGPU_VM_PTB
&& !entry
->entries
) {
846 unsigned num_entries
;
848 num_entries
= amdgpu_vm_num_entries(adev
, cursor
->level
);
849 entry
->entries
= kvmalloc_array(num_entries
,
850 sizeof(*entry
->entries
),
851 GFP_KERNEL
| __GFP_ZERO
);
859 amdgpu_vm_bo_param(adev
, vm
, cursor
->level
, &bp
);
861 r
= amdgpu_bo_create(adev
, &bp
, &pt
);
865 /* Keep a reference to the root directory to avoid
866 * freeing them up in the wrong order.
868 pt
->parent
= amdgpu_bo_ref(cursor
->parent
->base
.bo
);
869 amdgpu_vm_bo_base_init(&entry
->base
, vm
, pt
);
871 r
= amdgpu_vm_clear_bo(adev
, vm
, pt
);
878 amdgpu_bo_unref(&pt
->shadow
);
879 amdgpu_bo_unref(&pt
);
884 * amdgpu_vm_free_table - fre one PD/PT
886 * @entry: PDE to free
888 static void amdgpu_vm_free_table(struct amdgpu_vm_pt
*entry
)
890 if (entry
->base
.bo
) {
891 entry
->base
.bo
->vm_bo
= NULL
;
892 list_del(&entry
->base
.vm_status
);
893 amdgpu_bo_unref(&entry
->base
.bo
->shadow
);
894 amdgpu_bo_unref(&entry
->base
.bo
);
896 kvfree(entry
->entries
);
897 entry
->entries
= NULL
;
901 * amdgpu_vm_free_pts - free PD/PT levels
903 * @adev: amdgpu device structure
904 * @vm: amdgpu vm structure
905 * @start: optional cursor where to start freeing PDs/PTs
907 * Free the page directory or page table level and all sub levels.
909 static void amdgpu_vm_free_pts(struct amdgpu_device
*adev
,
910 struct amdgpu_vm
*vm
,
911 struct amdgpu_vm_pt_cursor
*start
)
913 struct amdgpu_vm_pt_cursor cursor
;
914 struct amdgpu_vm_pt
*entry
;
916 vm
->bulk_moveable
= false;
918 for_each_amdgpu_vm_pt_dfs_safe(adev
, vm
, start
, cursor
, entry
)
919 amdgpu_vm_free_table(entry
);
922 amdgpu_vm_free_table(start
->entry
);
926 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
928 * @adev: amdgpu_device pointer
930 void amdgpu_vm_check_compute_bug(struct amdgpu_device
*adev
)
932 const struct amdgpu_ip_block
*ip_block
;
933 bool has_compute_vm_bug
;
934 struct amdgpu_ring
*ring
;
937 has_compute_vm_bug
= false;
939 ip_block
= amdgpu_device_ip_get_ip_block(adev
, AMD_IP_BLOCK_TYPE_GFX
);
941 /* Compute has a VM bug for GFX version < 7.
942 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
943 if (ip_block
->version
->major
<= 7)
944 has_compute_vm_bug
= true;
945 else if (ip_block
->version
->major
== 8)
946 if (adev
->gfx
.mec_fw_version
< 673)
947 has_compute_vm_bug
= true;
950 for (i
= 0; i
< adev
->num_rings
; i
++) {
951 ring
= adev
->rings
[i
];
952 if (ring
->funcs
->type
== AMDGPU_RING_TYPE_COMPUTE
)
953 /* only compute rings */
954 ring
->has_compute_vm_bug
= has_compute_vm_bug
;
956 ring
->has_compute_vm_bug
= false;
961 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
963 * @ring: ring on which the job will be submitted
964 * @job: job to submit
967 * True if sync is needed.
969 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring
*ring
,
970 struct amdgpu_job
*job
)
972 struct amdgpu_device
*adev
= ring
->adev
;
973 unsigned vmhub
= ring
->funcs
->vmhub
;
974 struct amdgpu_vmid_mgr
*id_mgr
= &adev
->vm_manager
.id_mgr
[vmhub
];
975 struct amdgpu_vmid
*id
;
976 bool gds_switch_needed
;
977 bool vm_flush_needed
= job
->vm_needs_flush
|| ring
->has_compute_vm_bug
;
981 id
= &id_mgr
->ids
[job
->vmid
];
982 gds_switch_needed
= ring
->funcs
->emit_gds_switch
&& (
983 id
->gds_base
!= job
->gds_base
||
984 id
->gds_size
!= job
->gds_size
||
985 id
->gws_base
!= job
->gws_base
||
986 id
->gws_size
!= job
->gws_size
||
987 id
->oa_base
!= job
->oa_base
||
988 id
->oa_size
!= job
->oa_size
);
990 if (amdgpu_vmid_had_gpu_reset(adev
, id
))
993 return vm_flush_needed
|| gds_switch_needed
;
997 * amdgpu_vm_flush - hardware flush the vm
999 * @ring: ring to use for flush
1001 * @need_pipe_sync: is pipe sync needed
1003 * Emit a VM flush when it is necessary.
1006 * 0 on success, errno otherwise.
1008 int amdgpu_vm_flush(struct amdgpu_ring
*ring
, struct amdgpu_job
*job
, bool need_pipe_sync
)
1010 struct amdgpu_device
*adev
= ring
->adev
;
1011 unsigned vmhub
= ring
->funcs
->vmhub
;
1012 struct amdgpu_vmid_mgr
*id_mgr
= &adev
->vm_manager
.id_mgr
[vmhub
];
1013 struct amdgpu_vmid
*id
= &id_mgr
->ids
[job
->vmid
];
1014 bool gds_switch_needed
= ring
->funcs
->emit_gds_switch
&& (
1015 id
->gds_base
!= job
->gds_base
||
1016 id
->gds_size
!= job
->gds_size
||
1017 id
->gws_base
!= job
->gws_base
||
1018 id
->gws_size
!= job
->gws_size
||
1019 id
->oa_base
!= job
->oa_base
||
1020 id
->oa_size
!= job
->oa_size
);
1021 bool vm_flush_needed
= job
->vm_needs_flush
;
1022 bool pasid_mapping_needed
= id
->pasid
!= job
->pasid
||
1023 !id
->pasid_mapping
||
1024 !dma_fence_is_signaled(id
->pasid_mapping
);
1025 struct dma_fence
*fence
= NULL
;
1026 unsigned patch_offset
= 0;
1029 if (amdgpu_vmid_had_gpu_reset(adev
, id
)) {
1030 gds_switch_needed
= true;
1031 vm_flush_needed
= true;
1032 pasid_mapping_needed
= true;
1035 gds_switch_needed
&= !!ring
->funcs
->emit_gds_switch
;
1036 vm_flush_needed
&= !!ring
->funcs
->emit_vm_flush
&&
1037 job
->vm_pd_addr
!= AMDGPU_BO_INVALID_OFFSET
;
1038 pasid_mapping_needed
&= adev
->gmc
.gmc_funcs
->emit_pasid_mapping
&&
1039 ring
->funcs
->emit_wreg
;
1041 if (!vm_flush_needed
&& !gds_switch_needed
&& !need_pipe_sync
)
1044 if (ring
->funcs
->init_cond_exec
)
1045 patch_offset
= amdgpu_ring_init_cond_exec(ring
);
1048 amdgpu_ring_emit_pipeline_sync(ring
);
1050 if (vm_flush_needed
) {
1051 trace_amdgpu_vm_flush(ring
, job
->vmid
, job
->vm_pd_addr
);
1052 amdgpu_ring_emit_vm_flush(ring
, job
->vmid
, job
->vm_pd_addr
);
1055 if (pasid_mapping_needed
)
1056 amdgpu_gmc_emit_pasid_mapping(ring
, job
->vmid
, job
->pasid
);
1058 if (vm_flush_needed
|| pasid_mapping_needed
) {
1059 r
= amdgpu_fence_emit(ring
, &fence
, 0);
1064 if (vm_flush_needed
) {
1065 mutex_lock(&id_mgr
->lock
);
1066 dma_fence_put(id
->last_flush
);
1067 id
->last_flush
= dma_fence_get(fence
);
1068 id
->current_gpu_reset_count
=
1069 atomic_read(&adev
->gpu_reset_counter
);
1070 mutex_unlock(&id_mgr
->lock
);
1073 if (pasid_mapping_needed
) {
1074 id
->pasid
= job
->pasid
;
1075 dma_fence_put(id
->pasid_mapping
);
1076 id
->pasid_mapping
= dma_fence_get(fence
);
1078 dma_fence_put(fence
);
1080 if (ring
->funcs
->emit_gds_switch
&& gds_switch_needed
) {
1081 id
->gds_base
= job
->gds_base
;
1082 id
->gds_size
= job
->gds_size
;
1083 id
->gws_base
= job
->gws_base
;
1084 id
->gws_size
= job
->gws_size
;
1085 id
->oa_base
= job
->oa_base
;
1086 id
->oa_size
= job
->oa_size
;
1087 amdgpu_ring_emit_gds_switch(ring
, job
->vmid
, job
->gds_base
,
1088 job
->gds_size
, job
->gws_base
,
1089 job
->gws_size
, job
->oa_base
,
1093 if (ring
->funcs
->patch_cond_exec
)
1094 amdgpu_ring_patch_cond_exec(ring
, patch_offset
);
1096 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
1097 if (ring
->funcs
->emit_switch_buffer
) {
1098 amdgpu_ring_emit_switch_buffer(ring
);
1099 amdgpu_ring_emit_switch_buffer(ring
);
1105 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
1108 * @bo: requested buffer object
1110 * Find @bo inside the requested vm.
1111 * Search inside the @bos vm list for the requested vm
1112 * Returns the found bo_va or NULL if none is found
1114 * Object has to be reserved!
1117 * Found bo_va or NULL.
1119 struct amdgpu_bo_va
*amdgpu_vm_bo_find(struct amdgpu_vm
*vm
,
1120 struct amdgpu_bo
*bo
)
1122 struct amdgpu_vm_bo_base
*base
;
1124 for (base
= bo
->vm_bo
; base
; base
= base
->next
) {
1128 return container_of(base
, struct amdgpu_bo_va
, base
);
1134 * amdgpu_vm_map_gart - Resolve gart mapping of addr
1136 * @pages_addr: optional DMA address to use for lookup
1137 * @addr: the unmapped addr
1139 * Look up the physical address of the page that the pte resolves
1143 * The pointer for the page table entry.
1145 uint64_t amdgpu_vm_map_gart(const dma_addr_t
*pages_addr
, uint64_t addr
)
1149 /* page table offset */
1150 result
= pages_addr
[addr
>> PAGE_SHIFT
];
1152 /* in case cpu page size != gpu page size*/
1153 result
|= addr
& (~PAGE_MASK
);
1155 result
&= 0xFFFFFFFFFFFFF000ULL
;
1161 * amdgpu_vm_update_pde - update a single level in the hierarchy
1163 * @param: parameters for the update
1165 * @parent: parent directory
1166 * @entry: entry to update
1168 * Makes sure the requested entry in parent is up to date.
1170 static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params
*params
,
1171 struct amdgpu_vm
*vm
,
1172 struct amdgpu_vm_pt
*parent
,
1173 struct amdgpu_vm_pt
*entry
)
1175 struct amdgpu_bo
*bo
= parent
->base
.bo
, *pbo
;
1176 uint64_t pde
, pt
, flags
;
1179 for (level
= 0, pbo
= bo
->parent
; pbo
; ++level
)
1182 level
+= params
->adev
->vm_manager
.root_level
;
1183 amdgpu_gmc_get_pde_for_bo(entry
->base
.bo
, level
, &pt
, &flags
);
1184 pde
= (entry
- parent
->entries
) * 8;
1185 return vm
->update_funcs
->update(params
, bo
, pde
, pt
, 1, 0, flags
);
1189 * amdgpu_vm_invalidate_pds - mark all PDs as invalid
1191 * @adev: amdgpu_device pointer
1194 * Mark all PD level as invalid after an error.
1196 static void amdgpu_vm_invalidate_pds(struct amdgpu_device
*adev
,
1197 struct amdgpu_vm
*vm
)
1199 struct amdgpu_vm_pt_cursor cursor
;
1200 struct amdgpu_vm_pt
*entry
;
1202 for_each_amdgpu_vm_pt_dfs_safe(adev
, vm
, NULL
, cursor
, entry
)
1203 if (entry
->base
.bo
&& !entry
->base
.moved
)
1204 amdgpu_vm_bo_relocated(&entry
->base
);
1208 * amdgpu_vm_update_directories - make sure that all directories are valid
1210 * @adev: amdgpu_device pointer
1213 * Makes sure all directories are up to date.
1216 * 0 for success, error for failure.
1218 int amdgpu_vm_update_directories(struct amdgpu_device
*adev
,
1219 struct amdgpu_vm
*vm
)
1221 struct amdgpu_vm_update_params params
;
1224 if (list_empty(&vm
->relocated
))
1227 memset(¶ms
, 0, sizeof(params
));
1231 r
= vm
->update_funcs
->prepare(¶ms
, AMDGPU_FENCE_OWNER_VM
, NULL
);
1235 while (!list_empty(&vm
->relocated
)) {
1236 struct amdgpu_vm_pt
*pt
, *entry
;
1238 entry
= list_first_entry(&vm
->relocated
, struct amdgpu_vm_pt
,
1240 amdgpu_vm_bo_idle(&entry
->base
);
1242 pt
= amdgpu_vm_pt_parent(entry
);
1246 r
= amdgpu_vm_update_pde(¶ms
, vm
, pt
, entry
);
1251 r
= vm
->update_funcs
->commit(¶ms
, &vm
->last_update
);
1257 amdgpu_vm_invalidate_pds(adev
, vm
);
1262 * amdgpu_vm_update_flags - figure out flags for PTE updates
1264 * Make sure to set the right flags for the PTEs at the desired level.
1266 static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params
*params
,
1267 struct amdgpu_bo
*bo
, unsigned level
,
1268 uint64_t pe
, uint64_t addr
,
1269 unsigned count
, uint32_t incr
,
1273 if (level
!= AMDGPU_VM_PTB
) {
1274 flags
|= AMDGPU_PDE_PTE
;
1275 amdgpu_gmc_get_vm_pde(params
->adev
, level
, &addr
, &flags
);
1277 } else if (params
->adev
->asic_type
>= CHIP_VEGA10
&&
1278 !(flags
& AMDGPU_PTE_VALID
) &&
1279 !(flags
& AMDGPU_PTE_PRT
)) {
1281 /* Workaround for fault priority problem on GMC9 */
1282 flags
|= AMDGPU_PTE_EXECUTABLE
;
1285 params
->vm
->update_funcs
->update(params
, bo
, pe
, addr
, count
, incr
,
1290 * amdgpu_vm_fragment - get fragment for PTEs
1292 * @params: see amdgpu_vm_update_params definition
1293 * @start: first PTE to handle
1294 * @end: last PTE to handle
1295 * @flags: hw mapping flags
1296 * @frag: resulting fragment size
1297 * @frag_end: end of this fragment
1299 * Returns the first possible fragment for the start and end address.
1301 static void amdgpu_vm_fragment(struct amdgpu_vm_update_params
*params
,
1302 uint64_t start
, uint64_t end
, uint64_t flags
,
1303 unsigned int *frag
, uint64_t *frag_end
)
1306 * The MC L1 TLB supports variable sized pages, based on a fragment
1307 * field in the PTE. When this field is set to a non-zero value, page
1308 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1309 * flags are considered valid for all PTEs within the fragment range
1310 * and corresponding mappings are assumed to be physically contiguous.
1312 * The L1 TLB can store a single PTE for the whole fragment,
1313 * significantly increasing the space available for translation
1314 * caching. This leads to large improvements in throughput when the
1315 * TLB is under pressure.
1317 * The L2 TLB distributes small and large fragments into two
1318 * asymmetric partitions. The large fragment cache is significantly
1319 * larger. Thus, we try to use large fragments wherever possible.
1320 * Userspace can support this by aligning virtual base address and
1321 * allocation size to the fragment size.
1323 * Starting with Vega10 the fragment size only controls the L1. The L2
1324 * is now directly feed with small/huge/giant pages from the walker.
1328 if (params
->adev
->asic_type
< CHIP_VEGA10
)
1329 max_frag
= params
->adev
->vm_manager
.fragment_size
;
1333 /* system pages are non continuously */
1334 if (params
->pages_addr
) {
1340 /* This intentionally wraps around if no bit is set */
1341 *frag
= min((unsigned)ffs(start
) - 1, (unsigned)fls64(end
- start
) - 1);
1342 if (*frag
>= max_frag
) {
1344 *frag_end
= end
& ~((1ULL << max_frag
) - 1);
1346 *frag_end
= start
+ (1 << *frag
);
1351 * amdgpu_vm_update_ptes - make sure that page tables are valid
1353 * @params: see amdgpu_vm_update_params definition
1354 * @start: start of GPU address range
1355 * @end: end of GPU address range
1356 * @dst: destination address to map to, the next dst inside the function
1357 * @flags: mapping flags
1359 * Update the page tables in the range @start - @end.
1362 * 0 for success, -EINVAL for failure.
1364 static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params
*params
,
1365 uint64_t start
, uint64_t end
,
1366 uint64_t dst
, uint64_t flags
)
1368 struct amdgpu_device
*adev
= params
->adev
;
1369 struct amdgpu_vm_pt_cursor cursor
;
1370 uint64_t frag_start
= start
, frag_end
;
1374 /* figure out the initial fragment */
1375 amdgpu_vm_fragment(params
, frag_start
, end
, flags
, &frag
, &frag_end
);
1377 /* walk over the address space and update the PTs */
1378 amdgpu_vm_pt_start(adev
, params
->vm
, start
, &cursor
);
1379 while (cursor
.pfn
< end
) {
1380 unsigned shift
, parent_shift
, mask
;
1381 uint64_t incr
, entry_end
, pe_start
;
1382 struct amdgpu_bo
*pt
;
1384 r
= amdgpu_vm_alloc_pts(params
->adev
, params
->vm
, &cursor
);
1388 pt
= cursor
.entry
->base
.bo
;
1390 /* The root level can't be a huge page */
1391 if (cursor
.level
== adev
->vm_manager
.root_level
) {
1392 if (!amdgpu_vm_pt_descendant(adev
, &cursor
))
1397 shift
= amdgpu_vm_level_shift(adev
, cursor
.level
);
1398 parent_shift
= amdgpu_vm_level_shift(adev
, cursor
.level
- 1);
1399 if (adev
->asic_type
< CHIP_VEGA10
&&
1400 (flags
& AMDGPU_PTE_VALID
)) {
1401 /* No huge page support before GMC v9 */
1402 if (cursor
.level
!= AMDGPU_VM_PTB
) {
1403 if (!amdgpu_vm_pt_descendant(adev
, &cursor
))
1407 } else if (frag
< shift
) {
1408 /* We can't use this level when the fragment size is
1409 * smaller than the address shift. Go to the next
1410 * child entry and try again.
1412 if (!amdgpu_vm_pt_descendant(adev
, &cursor
))
1415 } else if (frag
>= parent_shift
&&
1416 cursor
.level
- 1 != adev
->vm_manager
.root_level
) {
1417 /* If the fragment size is even larger than the parent
1418 * shift we should go up one level and check it again
1419 * unless one level up is the root level.
1421 if (!amdgpu_vm_pt_ancestor(&cursor
))
1426 /* Looks good so far, calculate parameters for the update */
1427 incr
= (uint64_t)AMDGPU_GPU_PAGE_SIZE
<< shift
;
1428 mask
= amdgpu_vm_entries_mask(adev
, cursor
.level
);
1429 pe_start
= ((cursor
.pfn
>> shift
) & mask
) * 8;
1430 entry_end
= (uint64_t)(mask
+ 1) << shift
;
1431 entry_end
+= cursor
.pfn
& ~(entry_end
- 1);
1432 entry_end
= min(entry_end
, end
);
1435 uint64_t upd_end
= min(entry_end
, frag_end
);
1436 unsigned nptes
= (upd_end
- frag_start
) >> shift
;
1438 amdgpu_vm_update_flags(params
, pt
, cursor
.level
,
1439 pe_start
, dst
, nptes
, incr
,
1440 flags
| AMDGPU_PTE_FRAG(frag
));
1442 pe_start
+= nptes
* 8;
1443 dst
+= (uint64_t)nptes
* AMDGPU_GPU_PAGE_SIZE
<< shift
;
1445 frag_start
= upd_end
;
1446 if (frag_start
>= frag_end
) {
1447 /* figure out the next fragment */
1448 amdgpu_vm_fragment(params
, frag_start
, end
,
1449 flags
, &frag
, &frag_end
);
1453 } while (frag_start
< entry_end
);
1455 if (amdgpu_vm_pt_descendant(adev
, &cursor
)) {
1456 /* Free all child entries */
1457 while (cursor
.pfn
< frag_start
) {
1458 amdgpu_vm_free_pts(adev
, params
->vm
, &cursor
);
1459 amdgpu_vm_pt_next(adev
, &cursor
);
1462 } else if (frag
>= shift
) {
1463 /* or just move on to the next on the same level. */
1464 amdgpu_vm_pt_next(adev
, &cursor
);
1472 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1474 * @adev: amdgpu_device pointer
1475 * @exclusive: fence we need to sync to
1476 * @pages_addr: DMA addresses to use for mapping
1478 * @start: start of mapped range
1479 * @last: last mapped entry
1480 * @flags: flags for the entries
1481 * @addr: addr to set the area to
1482 * @fence: optional resulting fence
1484 * Fill in the page table entries between @start and @last.
1487 * 0 for success, -EINVAL for failure.
1489 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device
*adev
,
1490 struct dma_fence
*exclusive
,
1491 dma_addr_t
*pages_addr
,
1492 struct amdgpu_vm
*vm
,
1493 uint64_t start
, uint64_t last
,
1494 uint64_t flags
, uint64_t addr
,
1495 struct dma_fence
**fence
)
1497 struct amdgpu_vm_update_params params
;
1498 void *owner
= AMDGPU_FENCE_OWNER_VM
;
1501 memset(¶ms
, 0, sizeof(params
));
1504 params
.pages_addr
= pages_addr
;
1506 /* sync to everything except eviction fences on unmapping */
1507 if (!(flags
& AMDGPU_PTE_VALID
))
1508 owner
= AMDGPU_FENCE_OWNER_KFD
;
1510 r
= vm
->update_funcs
->prepare(¶ms
, owner
, exclusive
);
1514 r
= amdgpu_vm_update_ptes(¶ms
, start
, last
+ 1, addr
, flags
);
1518 return vm
->update_funcs
->commit(¶ms
, fence
);
1522 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
1524 * @adev: amdgpu_device pointer
1525 * @exclusive: fence we need to sync to
1526 * @pages_addr: DMA addresses to use for mapping
1528 * @mapping: mapped range and flags to use for the update
1529 * @flags: HW flags for the mapping
1530 * @bo_adev: amdgpu_device pointer that bo actually been allocated
1531 * @nodes: array of drm_mm_nodes with the MC addresses
1532 * @fence: optional resulting fence
1534 * Split the mapping into smaller chunks so that each update fits
1538 * 0 for success, -EINVAL for failure.
1540 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device
*adev
,
1541 struct dma_fence
*exclusive
,
1542 dma_addr_t
*pages_addr
,
1543 struct amdgpu_vm
*vm
,
1544 struct amdgpu_bo_va_mapping
*mapping
,
1546 struct amdgpu_device
*bo_adev
,
1547 struct drm_mm_node
*nodes
,
1548 struct dma_fence
**fence
)
1550 unsigned min_linear_pages
= 1 << adev
->vm_manager
.fragment_size
;
1551 uint64_t pfn
, start
= mapping
->start
;
1554 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1555 * but in case of something, we filter the flags in first place
1557 if (!(mapping
->flags
& AMDGPU_PTE_READABLE
))
1558 flags
&= ~AMDGPU_PTE_READABLE
;
1559 if (!(mapping
->flags
& AMDGPU_PTE_WRITEABLE
))
1560 flags
&= ~AMDGPU_PTE_WRITEABLE
;
1562 flags
&= ~AMDGPU_PTE_EXECUTABLE
;
1563 flags
|= mapping
->flags
& AMDGPU_PTE_EXECUTABLE
;
1565 flags
&= ~AMDGPU_PTE_MTYPE_MASK
;
1566 flags
|= (mapping
->flags
& AMDGPU_PTE_MTYPE_MASK
);
1568 if ((mapping
->flags
& AMDGPU_PTE_PRT
) &&
1569 (adev
->asic_type
>= CHIP_VEGA10
)) {
1570 flags
|= AMDGPU_PTE_PRT
;
1571 flags
&= ~AMDGPU_PTE_VALID
;
1574 trace_amdgpu_vm_bo_update(mapping
);
1576 pfn
= mapping
->offset
>> PAGE_SHIFT
;
1578 while (pfn
>= nodes
->size
) {
1585 dma_addr_t
*dma_addr
= NULL
;
1586 uint64_t max_entries
;
1587 uint64_t addr
, last
;
1590 addr
= nodes
->start
<< PAGE_SHIFT
;
1591 max_entries
= (nodes
->size
- pfn
) *
1592 AMDGPU_GPU_PAGES_IN_CPU_PAGE
;
1595 max_entries
= S64_MAX
;
1602 count
< max_entries
/ AMDGPU_GPU_PAGES_IN_CPU_PAGE
;
1604 uint64_t idx
= pfn
+ count
;
1606 if (pages_addr
[idx
] !=
1607 (pages_addr
[idx
- 1] + PAGE_SIZE
))
1611 if (count
< min_linear_pages
) {
1612 addr
= pfn
<< PAGE_SHIFT
;
1613 dma_addr
= pages_addr
;
1615 addr
= pages_addr
[pfn
];
1616 max_entries
= count
* AMDGPU_GPU_PAGES_IN_CPU_PAGE
;
1619 } else if (flags
& AMDGPU_PTE_VALID
) {
1620 addr
+= bo_adev
->vm_manager
.vram_base_offset
;
1621 addr
+= pfn
<< PAGE_SHIFT
;
1624 last
= min((uint64_t)mapping
->last
, start
+ max_entries
- 1);
1625 r
= amdgpu_vm_bo_update_mapping(adev
, exclusive
, dma_addr
, vm
,
1626 start
, last
, flags
, addr
,
1631 pfn
+= (last
- start
+ 1) / AMDGPU_GPU_PAGES_IN_CPU_PAGE
;
1632 if (nodes
&& nodes
->size
== pfn
) {
1638 } while (unlikely(start
!= mapping
->last
+ 1));
1644 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1646 * @adev: amdgpu_device pointer
1647 * @bo_va: requested BO and VM object
1648 * @clear: if true clear the entries
1650 * Fill in the page table entries for @bo_va.
1653 * 0 for success, -EINVAL for failure.
1655 int amdgpu_vm_bo_update(struct amdgpu_device
*adev
,
1656 struct amdgpu_bo_va
*bo_va
,
1659 struct amdgpu_bo
*bo
= bo_va
->base
.bo
;
1660 struct amdgpu_vm
*vm
= bo_va
->base
.vm
;
1661 struct amdgpu_bo_va_mapping
*mapping
;
1662 dma_addr_t
*pages_addr
= NULL
;
1663 struct ttm_mem_reg
*mem
;
1664 struct drm_mm_node
*nodes
;
1665 struct dma_fence
*exclusive
, **last_update
;
1667 struct amdgpu_device
*bo_adev
= adev
;
1675 struct ttm_dma_tt
*ttm
;
1678 nodes
= mem
->mm_node
;
1679 if (mem
->mem_type
== TTM_PL_TT
) {
1680 ttm
= container_of(bo
->tbo
.ttm
, struct ttm_dma_tt
, ttm
);
1681 pages_addr
= ttm
->dma_address
;
1683 exclusive
= reservation_object_get_excl(bo
->tbo
.resv
);
1687 flags
= amdgpu_ttm_tt_pte_flags(adev
, bo
->tbo
.ttm
, mem
);
1688 bo_adev
= amdgpu_ttm_adev(bo
->tbo
.bdev
);
1693 if (clear
|| (bo
&& bo
->tbo
.resv
== vm
->root
.base
.bo
->tbo
.resv
))
1694 last_update
= &vm
->last_update
;
1696 last_update
= &bo_va
->last_pt_update
;
1698 if (!clear
&& bo_va
->base
.moved
) {
1699 bo_va
->base
.moved
= false;
1700 list_splice_init(&bo_va
->valids
, &bo_va
->invalids
);
1702 } else if (bo_va
->cleared
!= clear
) {
1703 list_splice_init(&bo_va
->valids
, &bo_va
->invalids
);
1706 list_for_each_entry(mapping
, &bo_va
->invalids
, list
) {
1707 r
= amdgpu_vm_bo_split_mapping(adev
, exclusive
, pages_addr
, vm
,
1708 mapping
, flags
, bo_adev
, nodes
,
1714 if (vm
->use_cpu_for_update
) {
1717 amdgpu_asic_flush_hdp(adev
, NULL
);
1720 /* If the BO is not in its preferred location add it back to
1721 * the evicted list so that it gets validated again on the
1722 * next command submission.
1724 if (bo
&& bo
->tbo
.resv
== vm
->root
.base
.bo
->tbo
.resv
) {
1725 uint32_t mem_type
= bo
->tbo
.mem
.mem_type
;
1727 if (!(bo
->preferred_domains
& amdgpu_mem_type_to_domain(mem_type
)))
1728 amdgpu_vm_bo_evicted(&bo_va
->base
);
1730 amdgpu_vm_bo_idle(&bo_va
->base
);
1732 amdgpu_vm_bo_done(&bo_va
->base
);
1735 list_splice_init(&bo_va
->invalids
, &bo_va
->valids
);
1736 bo_va
->cleared
= clear
;
1738 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1739 list_for_each_entry(mapping
, &bo_va
->valids
, list
)
1740 trace_amdgpu_vm_bo_mapping(mapping
);
1747 * amdgpu_vm_update_prt_state - update the global PRT state
1749 * @adev: amdgpu_device pointer
1751 static void amdgpu_vm_update_prt_state(struct amdgpu_device
*adev
)
1753 unsigned long flags
;
1756 spin_lock_irqsave(&adev
->vm_manager
.prt_lock
, flags
);
1757 enable
= !!atomic_read(&adev
->vm_manager
.num_prt_users
);
1758 adev
->gmc
.gmc_funcs
->set_prt(adev
, enable
);
1759 spin_unlock_irqrestore(&adev
->vm_manager
.prt_lock
, flags
);
1763 * amdgpu_vm_prt_get - add a PRT user
1765 * @adev: amdgpu_device pointer
1767 static void amdgpu_vm_prt_get(struct amdgpu_device
*adev
)
1769 if (!adev
->gmc
.gmc_funcs
->set_prt
)
1772 if (atomic_inc_return(&adev
->vm_manager
.num_prt_users
) == 1)
1773 amdgpu_vm_update_prt_state(adev
);
1777 * amdgpu_vm_prt_put - drop a PRT user
1779 * @adev: amdgpu_device pointer
1781 static void amdgpu_vm_prt_put(struct amdgpu_device
*adev
)
1783 if (atomic_dec_return(&adev
->vm_manager
.num_prt_users
) == 0)
1784 amdgpu_vm_update_prt_state(adev
);
1788 * amdgpu_vm_prt_cb - callback for updating the PRT status
1790 * @fence: fence for the callback
1791 * @_cb: the callback function
1793 static void amdgpu_vm_prt_cb(struct dma_fence
*fence
, struct dma_fence_cb
*_cb
)
1795 struct amdgpu_prt_cb
*cb
= container_of(_cb
, struct amdgpu_prt_cb
, cb
);
1797 amdgpu_vm_prt_put(cb
->adev
);
1802 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1804 * @adev: amdgpu_device pointer
1805 * @fence: fence for the callback
1807 static void amdgpu_vm_add_prt_cb(struct amdgpu_device
*adev
,
1808 struct dma_fence
*fence
)
1810 struct amdgpu_prt_cb
*cb
;
1812 if (!adev
->gmc
.gmc_funcs
->set_prt
)
1815 cb
= kmalloc(sizeof(struct amdgpu_prt_cb
), GFP_KERNEL
);
1817 /* Last resort when we are OOM */
1819 dma_fence_wait(fence
, false);
1821 amdgpu_vm_prt_put(adev
);
1824 if (!fence
|| dma_fence_add_callback(fence
, &cb
->cb
,
1826 amdgpu_vm_prt_cb(fence
, &cb
->cb
);
1831 * amdgpu_vm_free_mapping - free a mapping
1833 * @adev: amdgpu_device pointer
1835 * @mapping: mapping to be freed
1836 * @fence: fence of the unmap operation
1838 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1840 static void amdgpu_vm_free_mapping(struct amdgpu_device
*adev
,
1841 struct amdgpu_vm
*vm
,
1842 struct amdgpu_bo_va_mapping
*mapping
,
1843 struct dma_fence
*fence
)
1845 if (mapping
->flags
& AMDGPU_PTE_PRT
)
1846 amdgpu_vm_add_prt_cb(adev
, fence
);
1851 * amdgpu_vm_prt_fini - finish all prt mappings
1853 * @adev: amdgpu_device pointer
1856 * Register a cleanup callback to disable PRT support after VM dies.
1858 static void amdgpu_vm_prt_fini(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
1860 struct reservation_object
*resv
= vm
->root
.base
.bo
->tbo
.resv
;
1861 struct dma_fence
*excl
, **shared
;
1862 unsigned i
, shared_count
;
1865 r
= reservation_object_get_fences_rcu(resv
, &excl
,
1866 &shared_count
, &shared
);
1868 /* Not enough memory to grab the fence list, as last resort
1869 * block for all the fences to complete.
1871 reservation_object_wait_timeout_rcu(resv
, true, false,
1872 MAX_SCHEDULE_TIMEOUT
);
1876 /* Add a callback for each fence in the reservation object */
1877 amdgpu_vm_prt_get(adev
);
1878 amdgpu_vm_add_prt_cb(adev
, excl
);
1880 for (i
= 0; i
< shared_count
; ++i
) {
1881 amdgpu_vm_prt_get(adev
);
1882 amdgpu_vm_add_prt_cb(adev
, shared
[i
]);
1889 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1891 * @adev: amdgpu_device pointer
1893 * @fence: optional resulting fence (unchanged if no work needed to be done
1894 * or if an error occurred)
1896 * Make sure all freed BOs are cleared in the PT.
1897 * PTs have to be reserved and mutex must be locked!
1903 int amdgpu_vm_clear_freed(struct amdgpu_device
*adev
,
1904 struct amdgpu_vm
*vm
,
1905 struct dma_fence
**fence
)
1907 struct amdgpu_bo_va_mapping
*mapping
;
1908 uint64_t init_pte_value
= 0;
1909 struct dma_fence
*f
= NULL
;
1912 while (!list_empty(&vm
->freed
)) {
1913 mapping
= list_first_entry(&vm
->freed
,
1914 struct amdgpu_bo_va_mapping
, list
);
1915 list_del(&mapping
->list
);
1917 if (vm
->pte_support_ats
&&
1918 mapping
->start
< AMDGPU_GMC_HOLE_START
)
1919 init_pte_value
= AMDGPU_PTE_DEFAULT_ATC
;
1921 r
= amdgpu_vm_bo_update_mapping(adev
, NULL
, NULL
, vm
,
1922 mapping
->start
, mapping
->last
,
1923 init_pte_value
, 0, &f
);
1924 amdgpu_vm_free_mapping(adev
, vm
, mapping
, f
);
1932 dma_fence_put(*fence
);
1943 * amdgpu_vm_handle_moved - handle moved BOs in the PT
1945 * @adev: amdgpu_device pointer
1948 * Make sure all BOs which are moved are updated in the PTs.
1953 * PTs have to be reserved!
1955 int amdgpu_vm_handle_moved(struct amdgpu_device
*adev
,
1956 struct amdgpu_vm
*vm
)
1958 struct amdgpu_bo_va
*bo_va
, *tmp
;
1959 struct reservation_object
*resv
;
1963 list_for_each_entry_safe(bo_va
, tmp
, &vm
->moved
, base
.vm_status
) {
1964 /* Per VM BOs never need to bo cleared in the page tables */
1965 r
= amdgpu_vm_bo_update(adev
, bo_va
, false);
1970 spin_lock(&vm
->invalidated_lock
);
1971 while (!list_empty(&vm
->invalidated
)) {
1972 bo_va
= list_first_entry(&vm
->invalidated
, struct amdgpu_bo_va
,
1974 resv
= bo_va
->base
.bo
->tbo
.resv
;
1975 spin_unlock(&vm
->invalidated_lock
);
1977 /* Try to reserve the BO to avoid clearing its ptes */
1978 if (!amdgpu_vm_debug
&& reservation_object_trylock(resv
))
1980 /* Somebody else is using the BO right now */
1984 r
= amdgpu_vm_bo_update(adev
, bo_va
, clear
);
1989 reservation_object_unlock(resv
);
1990 spin_lock(&vm
->invalidated_lock
);
1992 spin_unlock(&vm
->invalidated_lock
);
1998 * amdgpu_vm_bo_add - add a bo to a specific vm
2000 * @adev: amdgpu_device pointer
2002 * @bo: amdgpu buffer object
2004 * Add @bo into the requested vm.
2005 * Add @bo to the list of bos associated with the vm
2008 * Newly added bo_va or NULL for failure
2010 * Object has to be reserved!
2012 struct amdgpu_bo_va
*amdgpu_vm_bo_add(struct amdgpu_device
*adev
,
2013 struct amdgpu_vm
*vm
,
2014 struct amdgpu_bo
*bo
)
2016 struct amdgpu_bo_va
*bo_va
;
2018 bo_va
= kzalloc(sizeof(struct amdgpu_bo_va
), GFP_KERNEL
);
2019 if (bo_va
== NULL
) {
2022 amdgpu_vm_bo_base_init(&bo_va
->base
, vm
, bo
);
2024 bo_va
->ref_count
= 1;
2025 INIT_LIST_HEAD(&bo_va
->valids
);
2026 INIT_LIST_HEAD(&bo_va
->invalids
);
2028 if (bo
&& amdgpu_xgmi_same_hive(adev
, amdgpu_ttm_adev(bo
->tbo
.bdev
))) {
2029 bo_va
->is_xgmi
= true;
2030 mutex_lock(&adev
->vm_manager
.lock_pstate
);
2031 /* Power up XGMI if it can be potentially used */
2032 if (++adev
->vm_manager
.xgmi_map_counter
== 1)
2033 amdgpu_xgmi_set_pstate(adev
, 1);
2034 mutex_unlock(&adev
->vm_manager
.lock_pstate
);
2042 * amdgpu_vm_bo_insert_mapping - insert a new mapping
2044 * @adev: amdgpu_device pointer
2045 * @bo_va: bo_va to store the address
2046 * @mapping: the mapping to insert
2048 * Insert a new mapping into all structures.
2050 static void amdgpu_vm_bo_insert_map(struct amdgpu_device
*adev
,
2051 struct amdgpu_bo_va
*bo_va
,
2052 struct amdgpu_bo_va_mapping
*mapping
)
2054 struct amdgpu_vm
*vm
= bo_va
->base
.vm
;
2055 struct amdgpu_bo
*bo
= bo_va
->base
.bo
;
2057 mapping
->bo_va
= bo_va
;
2058 list_add(&mapping
->list
, &bo_va
->invalids
);
2059 amdgpu_vm_it_insert(mapping
, &vm
->va
);
2061 if (mapping
->flags
& AMDGPU_PTE_PRT
)
2062 amdgpu_vm_prt_get(adev
);
2064 if (bo
&& bo
->tbo
.resv
== vm
->root
.base
.bo
->tbo
.resv
&&
2065 !bo_va
->base
.moved
) {
2066 list_move(&bo_va
->base
.vm_status
, &vm
->moved
);
2068 trace_amdgpu_vm_bo_map(bo_va
, mapping
);
2072 * amdgpu_vm_bo_map - map bo inside a vm
2074 * @adev: amdgpu_device pointer
2075 * @bo_va: bo_va to store the address
2076 * @saddr: where to map the BO
2077 * @offset: requested offset in the BO
2078 * @size: BO size in bytes
2079 * @flags: attributes of pages (read/write/valid/etc.)
2081 * Add a mapping of the BO at the specefied addr into the VM.
2084 * 0 for success, error for failure.
2086 * Object has to be reserved and unreserved outside!
2088 int amdgpu_vm_bo_map(struct amdgpu_device
*adev
,
2089 struct amdgpu_bo_va
*bo_va
,
2090 uint64_t saddr
, uint64_t offset
,
2091 uint64_t size
, uint64_t flags
)
2093 struct amdgpu_bo_va_mapping
*mapping
, *tmp
;
2094 struct amdgpu_bo
*bo
= bo_va
->base
.bo
;
2095 struct amdgpu_vm
*vm
= bo_va
->base
.vm
;
2098 /* validate the parameters */
2099 if (saddr
& AMDGPU_GPU_PAGE_MASK
|| offset
& AMDGPU_GPU_PAGE_MASK
||
2100 size
== 0 || size
& AMDGPU_GPU_PAGE_MASK
)
2103 /* make sure object fit at this offset */
2104 eaddr
= saddr
+ size
- 1;
2105 if (saddr
>= eaddr
||
2106 (bo
&& offset
+ size
> amdgpu_bo_size(bo
)))
2109 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
2110 eaddr
/= AMDGPU_GPU_PAGE_SIZE
;
2112 tmp
= amdgpu_vm_it_iter_first(&vm
->va
, saddr
, eaddr
);
2114 /* bo and tmp overlap, invalid addr */
2115 dev_err(adev
->dev
, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2116 "0x%010Lx-0x%010Lx\n", bo
, saddr
, eaddr
,
2117 tmp
->start
, tmp
->last
+ 1);
2121 mapping
= kmalloc(sizeof(*mapping
), GFP_KERNEL
);
2125 mapping
->start
= saddr
;
2126 mapping
->last
= eaddr
;
2127 mapping
->offset
= offset
;
2128 mapping
->flags
= flags
;
2130 amdgpu_vm_bo_insert_map(adev
, bo_va
, mapping
);
2136 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
2138 * @adev: amdgpu_device pointer
2139 * @bo_va: bo_va to store the address
2140 * @saddr: where to map the BO
2141 * @offset: requested offset in the BO
2142 * @size: BO size in bytes
2143 * @flags: attributes of pages (read/write/valid/etc.)
2145 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
2146 * mappings as we do so.
2149 * 0 for success, error for failure.
2151 * Object has to be reserved and unreserved outside!
2153 int amdgpu_vm_bo_replace_map(struct amdgpu_device
*adev
,
2154 struct amdgpu_bo_va
*bo_va
,
2155 uint64_t saddr
, uint64_t offset
,
2156 uint64_t size
, uint64_t flags
)
2158 struct amdgpu_bo_va_mapping
*mapping
;
2159 struct amdgpu_bo
*bo
= bo_va
->base
.bo
;
2163 /* validate the parameters */
2164 if (saddr
& AMDGPU_GPU_PAGE_MASK
|| offset
& AMDGPU_GPU_PAGE_MASK
||
2165 size
== 0 || size
& AMDGPU_GPU_PAGE_MASK
)
2168 /* make sure object fit at this offset */
2169 eaddr
= saddr
+ size
- 1;
2170 if (saddr
>= eaddr
||
2171 (bo
&& offset
+ size
> amdgpu_bo_size(bo
)))
2174 /* Allocate all the needed memory */
2175 mapping
= kmalloc(sizeof(*mapping
), GFP_KERNEL
);
2179 r
= amdgpu_vm_bo_clear_mappings(adev
, bo_va
->base
.vm
, saddr
, size
);
2185 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
2186 eaddr
/= AMDGPU_GPU_PAGE_SIZE
;
2188 mapping
->start
= saddr
;
2189 mapping
->last
= eaddr
;
2190 mapping
->offset
= offset
;
2191 mapping
->flags
= flags
;
2193 amdgpu_vm_bo_insert_map(adev
, bo_va
, mapping
);
2199 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2201 * @adev: amdgpu_device pointer
2202 * @bo_va: bo_va to remove the address from
2203 * @saddr: where to the BO is mapped
2205 * Remove a mapping of the BO at the specefied addr from the VM.
2208 * 0 for success, error for failure.
2210 * Object has to be reserved and unreserved outside!
2212 int amdgpu_vm_bo_unmap(struct amdgpu_device
*adev
,
2213 struct amdgpu_bo_va
*bo_va
,
2216 struct amdgpu_bo_va_mapping
*mapping
;
2217 struct amdgpu_vm
*vm
= bo_va
->base
.vm
;
2220 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
2222 list_for_each_entry(mapping
, &bo_va
->valids
, list
) {
2223 if (mapping
->start
== saddr
)
2227 if (&mapping
->list
== &bo_va
->valids
) {
2230 list_for_each_entry(mapping
, &bo_va
->invalids
, list
) {
2231 if (mapping
->start
== saddr
)
2235 if (&mapping
->list
== &bo_va
->invalids
)
2239 list_del(&mapping
->list
);
2240 amdgpu_vm_it_remove(mapping
, &vm
->va
);
2241 mapping
->bo_va
= NULL
;
2242 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
2245 list_add(&mapping
->list
, &vm
->freed
);
2247 amdgpu_vm_free_mapping(adev
, vm
, mapping
,
2248 bo_va
->last_pt_update
);
2254 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2256 * @adev: amdgpu_device pointer
2257 * @vm: VM structure to use
2258 * @saddr: start of the range
2259 * @size: size of the range
2261 * Remove all mappings in a range, split them as appropriate.
2264 * 0 for success, error for failure.
2266 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device
*adev
,
2267 struct amdgpu_vm
*vm
,
2268 uint64_t saddr
, uint64_t size
)
2270 struct amdgpu_bo_va_mapping
*before
, *after
, *tmp
, *next
;
2274 eaddr
= saddr
+ size
- 1;
2275 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
2276 eaddr
/= AMDGPU_GPU_PAGE_SIZE
;
2278 /* Allocate all the needed memory */
2279 before
= kzalloc(sizeof(*before
), GFP_KERNEL
);
2282 INIT_LIST_HEAD(&before
->list
);
2284 after
= kzalloc(sizeof(*after
), GFP_KERNEL
);
2289 INIT_LIST_HEAD(&after
->list
);
2291 /* Now gather all removed mappings */
2292 tmp
= amdgpu_vm_it_iter_first(&vm
->va
, saddr
, eaddr
);
2294 /* Remember mapping split at the start */
2295 if (tmp
->start
< saddr
) {
2296 before
->start
= tmp
->start
;
2297 before
->last
= saddr
- 1;
2298 before
->offset
= tmp
->offset
;
2299 before
->flags
= tmp
->flags
;
2300 before
->bo_va
= tmp
->bo_va
;
2301 list_add(&before
->list
, &tmp
->bo_va
->invalids
);
2304 /* Remember mapping split at the end */
2305 if (tmp
->last
> eaddr
) {
2306 after
->start
= eaddr
+ 1;
2307 after
->last
= tmp
->last
;
2308 after
->offset
= tmp
->offset
;
2309 after
->offset
+= after
->start
- tmp
->start
;
2310 after
->flags
= tmp
->flags
;
2311 after
->bo_va
= tmp
->bo_va
;
2312 list_add(&after
->list
, &tmp
->bo_va
->invalids
);
2315 list_del(&tmp
->list
);
2316 list_add(&tmp
->list
, &removed
);
2318 tmp
= amdgpu_vm_it_iter_next(tmp
, saddr
, eaddr
);
2321 /* And free them up */
2322 list_for_each_entry_safe(tmp
, next
, &removed
, list
) {
2323 amdgpu_vm_it_remove(tmp
, &vm
->va
);
2324 list_del(&tmp
->list
);
2326 if (tmp
->start
< saddr
)
2328 if (tmp
->last
> eaddr
)
2332 list_add(&tmp
->list
, &vm
->freed
);
2333 trace_amdgpu_vm_bo_unmap(NULL
, tmp
);
2336 /* Insert partial mapping before the range */
2337 if (!list_empty(&before
->list
)) {
2338 amdgpu_vm_it_insert(before
, &vm
->va
);
2339 if (before
->flags
& AMDGPU_PTE_PRT
)
2340 amdgpu_vm_prt_get(adev
);
2345 /* Insert partial mapping after the range */
2346 if (!list_empty(&after
->list
)) {
2347 amdgpu_vm_it_insert(after
, &vm
->va
);
2348 if (after
->flags
& AMDGPU_PTE_PRT
)
2349 amdgpu_vm_prt_get(adev
);
2358 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2360 * @vm: the requested VM
2361 * @addr: the address
2363 * Find a mapping by it's address.
2366 * The amdgpu_bo_va_mapping matching for addr or NULL
2369 struct amdgpu_bo_va_mapping
*amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm
*vm
,
2372 return amdgpu_vm_it_iter_first(&vm
->va
, addr
, addr
);
2376 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
2378 * @vm: the requested vm
2379 * @ticket: CS ticket
2381 * Trace all mappings of BOs reserved during a command submission.
2383 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm
*vm
, struct ww_acquire_ctx
*ticket
)
2385 struct amdgpu_bo_va_mapping
*mapping
;
2387 if (!trace_amdgpu_vm_bo_cs_enabled())
2390 for (mapping
= amdgpu_vm_it_iter_first(&vm
->va
, 0, U64_MAX
); mapping
;
2391 mapping
= amdgpu_vm_it_iter_next(mapping
, 0, U64_MAX
)) {
2392 if (mapping
->bo_va
&& mapping
->bo_va
->base
.bo
) {
2393 struct amdgpu_bo
*bo
;
2395 bo
= mapping
->bo_va
->base
.bo
;
2396 if (READ_ONCE(bo
->tbo
.resv
->lock
.ctx
) != ticket
)
2400 trace_amdgpu_vm_bo_cs(mapping
);
2405 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2407 * @adev: amdgpu_device pointer
2408 * @bo_va: requested bo_va
2410 * Remove @bo_va->bo from the requested vm.
2412 * Object have to be reserved!
2414 void amdgpu_vm_bo_rmv(struct amdgpu_device
*adev
,
2415 struct amdgpu_bo_va
*bo_va
)
2417 struct amdgpu_bo_va_mapping
*mapping
, *next
;
2418 struct amdgpu_bo
*bo
= bo_va
->base
.bo
;
2419 struct amdgpu_vm
*vm
= bo_va
->base
.vm
;
2420 struct amdgpu_vm_bo_base
**base
;
2423 if (bo
->tbo
.resv
== vm
->root
.base
.bo
->tbo
.resv
)
2424 vm
->bulk_moveable
= false;
2426 for (base
= &bo_va
->base
.bo
->vm_bo
; *base
;
2427 base
= &(*base
)->next
) {
2428 if (*base
!= &bo_va
->base
)
2431 *base
= bo_va
->base
.next
;
2436 spin_lock(&vm
->invalidated_lock
);
2437 list_del(&bo_va
->base
.vm_status
);
2438 spin_unlock(&vm
->invalidated_lock
);
2440 list_for_each_entry_safe(mapping
, next
, &bo_va
->valids
, list
) {
2441 list_del(&mapping
->list
);
2442 amdgpu_vm_it_remove(mapping
, &vm
->va
);
2443 mapping
->bo_va
= NULL
;
2444 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
2445 list_add(&mapping
->list
, &vm
->freed
);
2447 list_for_each_entry_safe(mapping
, next
, &bo_va
->invalids
, list
) {
2448 list_del(&mapping
->list
);
2449 amdgpu_vm_it_remove(mapping
, &vm
->va
);
2450 amdgpu_vm_free_mapping(adev
, vm
, mapping
,
2451 bo_va
->last_pt_update
);
2454 dma_fence_put(bo_va
->last_pt_update
);
2456 if (bo
&& bo_va
->is_xgmi
) {
2457 mutex_lock(&adev
->vm_manager
.lock_pstate
);
2458 if (--adev
->vm_manager
.xgmi_map_counter
== 0)
2459 amdgpu_xgmi_set_pstate(adev
, 0);
2460 mutex_unlock(&adev
->vm_manager
.lock_pstate
);
2467 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2469 * @adev: amdgpu_device pointer
2470 * @bo: amdgpu buffer object
2471 * @evicted: is the BO evicted
2473 * Mark @bo as invalid.
2475 void amdgpu_vm_bo_invalidate(struct amdgpu_device
*adev
,
2476 struct amdgpu_bo
*bo
, bool evicted
)
2478 struct amdgpu_vm_bo_base
*bo_base
;
2480 /* shadow bo doesn't have bo base, its validation needs its parent */
2481 if (bo
->parent
&& bo
->parent
->shadow
== bo
)
2484 for (bo_base
= bo
->vm_bo
; bo_base
; bo_base
= bo_base
->next
) {
2485 struct amdgpu_vm
*vm
= bo_base
->vm
;
2487 if (evicted
&& bo
->tbo
.resv
== vm
->root
.base
.bo
->tbo
.resv
) {
2488 amdgpu_vm_bo_evicted(bo_base
);
2494 bo_base
->moved
= true;
2496 if (bo
->tbo
.type
== ttm_bo_type_kernel
)
2497 amdgpu_vm_bo_relocated(bo_base
);
2498 else if (bo
->tbo
.resv
== vm
->root
.base
.bo
->tbo
.resv
)
2499 amdgpu_vm_bo_moved(bo_base
);
2501 amdgpu_vm_bo_invalidated(bo_base
);
2506 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2511 * VM page table as power of two
2513 static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size
)
2515 /* Total bits covered by PD + PTs */
2516 unsigned bits
= ilog2(vm_size
) + 18;
2518 /* Make sure the PD is 4K in size up to 8GB address space.
2519 Above that split equal between PD and PTs */
2523 return ((bits
+ 3) / 2);
2527 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2529 * @adev: amdgpu_device pointer
2530 * @min_vm_size: the minimum vm size in GB if it's set auto
2531 * @fragment_size_default: Default PTE fragment size
2532 * @max_level: max VMPT level
2533 * @max_bits: max address space size in bits
2536 void amdgpu_vm_adjust_size(struct amdgpu_device
*adev
, uint32_t min_vm_size
,
2537 uint32_t fragment_size_default
, unsigned max_level
,
2540 unsigned int max_size
= 1 << (max_bits
- 30);
2541 unsigned int vm_size
;
2544 /* adjust vm size first */
2545 if (amdgpu_vm_size
!= -1) {
2546 vm_size
= amdgpu_vm_size
;
2547 if (vm_size
> max_size
) {
2548 dev_warn(adev
->dev
, "VM size (%d) too large, max is %u GB\n",
2549 amdgpu_vm_size
, max_size
);
2554 unsigned int phys_ram_gb
;
2556 /* Optimal VM size depends on the amount of physical
2557 * RAM available. Underlying requirements and
2560 * - Need to map system memory and VRAM from all GPUs
2561 * - VRAM from other GPUs not known here
2562 * - Assume VRAM <= system memory
2563 * - On GFX8 and older, VM space can be segmented for
2565 * - Need to allow room for fragmentation, guard pages etc.
2567 * This adds up to a rough guess of system memory x3.
2568 * Round up to power of two to maximize the available
2569 * VM size with the given page table size.
2572 phys_ram_gb
= ((uint64_t)si
.totalram
* si
.mem_unit
+
2573 (1 << 30) - 1) >> 30;
2574 vm_size
= roundup_pow_of_two(
2575 min(max(phys_ram_gb
* 3, min_vm_size
), max_size
));
2578 adev
->vm_manager
.max_pfn
= (uint64_t)vm_size
<< 18;
2580 tmp
= roundup_pow_of_two(adev
->vm_manager
.max_pfn
);
2581 if (amdgpu_vm_block_size
!= -1)
2582 tmp
>>= amdgpu_vm_block_size
- 9;
2583 tmp
= DIV_ROUND_UP(fls64(tmp
) - 1, 9) - 1;
2584 adev
->vm_manager
.num_level
= min(max_level
, (unsigned)tmp
);
2585 switch (adev
->vm_manager
.num_level
) {
2587 adev
->vm_manager
.root_level
= AMDGPU_VM_PDB2
;
2590 adev
->vm_manager
.root_level
= AMDGPU_VM_PDB1
;
2593 adev
->vm_manager
.root_level
= AMDGPU_VM_PDB0
;
2596 dev_err(adev
->dev
, "VMPT only supports 2~4+1 levels\n");
2598 /* block size depends on vm size and hw setup*/
2599 if (amdgpu_vm_block_size
!= -1)
2600 adev
->vm_manager
.block_size
=
2601 min((unsigned)amdgpu_vm_block_size
, max_bits
2602 - AMDGPU_GPU_PAGE_SHIFT
2603 - 9 * adev
->vm_manager
.num_level
);
2604 else if (adev
->vm_manager
.num_level
> 1)
2605 adev
->vm_manager
.block_size
= 9;
2607 adev
->vm_manager
.block_size
= amdgpu_vm_get_block_size(tmp
);
2609 if (amdgpu_vm_fragment_size
== -1)
2610 adev
->vm_manager
.fragment_size
= fragment_size_default
;
2612 adev
->vm_manager
.fragment_size
= amdgpu_vm_fragment_size
;
2614 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2615 vm_size
, adev
->vm_manager
.num_level
+ 1,
2616 adev
->vm_manager
.block_size
,
2617 adev
->vm_manager
.fragment_size
);
2621 * amdgpu_vm_wait_idle - wait for the VM to become idle
2623 * @vm: VM object to wait for
2624 * @timeout: timeout to wait for VM to become idle
2626 long amdgpu_vm_wait_idle(struct amdgpu_vm
*vm
, long timeout
)
2628 return reservation_object_wait_timeout_rcu(vm
->root
.base
.bo
->tbo
.resv
,
2629 true, true, timeout
);
2633 * amdgpu_vm_init - initialize a vm instance
2635 * @adev: amdgpu_device pointer
2637 * @vm_context: Indicates if it GFX or Compute context
2638 * @pasid: Process address space identifier
2643 * 0 for success, error for failure.
2645 int amdgpu_vm_init(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
2646 int vm_context
, unsigned int pasid
)
2648 struct amdgpu_bo_param bp
;
2649 struct amdgpu_bo
*root
;
2652 vm
->va
= RB_ROOT_CACHED
;
2653 for (i
= 0; i
< AMDGPU_MAX_VMHUBS
; i
++)
2654 vm
->reserved_vmid
[i
] = NULL
;
2655 INIT_LIST_HEAD(&vm
->evicted
);
2656 INIT_LIST_HEAD(&vm
->relocated
);
2657 INIT_LIST_HEAD(&vm
->moved
);
2658 INIT_LIST_HEAD(&vm
->idle
);
2659 INIT_LIST_HEAD(&vm
->invalidated
);
2660 spin_lock_init(&vm
->invalidated_lock
);
2661 INIT_LIST_HEAD(&vm
->freed
);
2663 /* create scheduler entity for page table updates */
2664 r
= drm_sched_entity_init(&vm
->entity
, adev
->vm_manager
.vm_pte_rqs
,
2665 adev
->vm_manager
.vm_pte_num_rqs
, NULL
);
2669 vm
->pte_support_ats
= false;
2671 if (vm_context
== AMDGPU_VM_CONTEXT_COMPUTE
) {
2672 vm
->use_cpu_for_update
= !!(adev
->vm_manager
.vm_update_mode
&
2673 AMDGPU_VM_USE_CPU_FOR_COMPUTE
);
2675 if (adev
->asic_type
== CHIP_RAVEN
)
2676 vm
->pte_support_ats
= true;
2678 vm
->use_cpu_for_update
= !!(adev
->vm_manager
.vm_update_mode
&
2679 AMDGPU_VM_USE_CPU_FOR_GFX
);
2681 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2682 vm
->use_cpu_for_update
? "CPU" : "SDMA");
2683 WARN_ONCE((vm
->use_cpu_for_update
&& !amdgpu_gmc_vram_full_visible(&adev
->gmc
)),
2684 "CPU update of VM recommended only for large BAR system\n");
2686 if (vm
->use_cpu_for_update
)
2687 vm
->update_funcs
= &amdgpu_vm_cpu_funcs
;
2689 vm
->update_funcs
= &amdgpu_vm_sdma_funcs
;
2690 vm
->last_update
= NULL
;
2692 amdgpu_vm_bo_param(adev
, vm
, adev
->vm_manager
.root_level
, &bp
);
2693 if (vm_context
== AMDGPU_VM_CONTEXT_COMPUTE
)
2694 bp
.flags
&= ~AMDGPU_GEM_CREATE_SHADOW
;
2695 r
= amdgpu_bo_create(adev
, &bp
, &root
);
2697 goto error_free_sched_entity
;
2699 r
= amdgpu_bo_reserve(root
, true);
2701 goto error_free_root
;
2703 r
= reservation_object_reserve_shared(root
->tbo
.resv
, 1);
2705 goto error_unreserve
;
2707 amdgpu_vm_bo_base_init(&vm
->root
.base
, vm
, root
);
2709 r
= amdgpu_vm_clear_bo(adev
, vm
, root
);
2711 goto error_unreserve
;
2713 amdgpu_bo_unreserve(vm
->root
.base
.bo
);
2716 unsigned long flags
;
2718 spin_lock_irqsave(&adev
->vm_manager
.pasid_lock
, flags
);
2719 r
= idr_alloc(&adev
->vm_manager
.pasid_idr
, vm
, pasid
, pasid
+ 1,
2721 spin_unlock_irqrestore(&adev
->vm_manager
.pasid_lock
, flags
);
2723 goto error_free_root
;
2728 INIT_KFIFO(vm
->faults
);
2733 amdgpu_bo_unreserve(vm
->root
.base
.bo
);
2736 amdgpu_bo_unref(&vm
->root
.base
.bo
->shadow
);
2737 amdgpu_bo_unref(&vm
->root
.base
.bo
);
2738 vm
->root
.base
.bo
= NULL
;
2740 error_free_sched_entity
:
2741 drm_sched_entity_destroy(&vm
->entity
);
2747 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2749 * @adev: amdgpu_device pointer
2752 * This only works on GFX VMs that don't have any BOs added and no
2753 * page tables allocated yet.
2755 * Changes the following VM parameters:
2756 * - use_cpu_for_update
2757 * - pte_supports_ats
2758 * - pasid (old PASID is released, because compute manages its own PASIDs)
2760 * Reinitializes the page directory to reflect the changed ATS
2764 * 0 for success, -errno for errors.
2766 int amdgpu_vm_make_compute(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
, unsigned int pasid
)
2768 bool pte_support_ats
= (adev
->asic_type
== CHIP_RAVEN
);
2771 r
= amdgpu_bo_reserve(vm
->root
.base
.bo
, true);
2776 if (!RB_EMPTY_ROOT(&vm
->va
.rb_root
) || vm
->root
.entries
) {
2782 unsigned long flags
;
2784 spin_lock_irqsave(&adev
->vm_manager
.pasid_lock
, flags
);
2785 r
= idr_alloc(&adev
->vm_manager
.pasid_idr
, vm
, pasid
, pasid
+ 1,
2787 spin_unlock_irqrestore(&adev
->vm_manager
.pasid_lock
, flags
);
2794 /* Check if PD needs to be reinitialized and do it before
2795 * changing any other state, in case it fails.
2797 if (pte_support_ats
!= vm
->pte_support_ats
) {
2798 vm
->pte_support_ats
= pte_support_ats
;
2799 r
= amdgpu_vm_clear_bo(adev
, vm
, vm
->root
.base
.bo
);
2804 /* Update VM state */
2805 vm
->use_cpu_for_update
= !!(adev
->vm_manager
.vm_update_mode
&
2806 AMDGPU_VM_USE_CPU_FOR_COMPUTE
);
2807 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2808 vm
->use_cpu_for_update
? "CPU" : "SDMA");
2809 WARN_ONCE((vm
->use_cpu_for_update
&& !amdgpu_gmc_vram_full_visible(&adev
->gmc
)),
2810 "CPU update of VM recommended only for large BAR system\n");
2813 unsigned long flags
;
2815 spin_lock_irqsave(&adev
->vm_manager
.pasid_lock
, flags
);
2816 idr_remove(&adev
->vm_manager
.pasid_idr
, vm
->pasid
);
2817 spin_unlock_irqrestore(&adev
->vm_manager
.pasid_lock
, flags
);
2819 /* Free the original amdgpu allocated pasid
2820 * Will be replaced with kfd allocated pasid
2822 amdgpu_pasid_free(vm
->pasid
);
2826 /* Free the shadow bo for compute VM */
2827 amdgpu_bo_unref(&vm
->root
.base
.bo
->shadow
);
2836 unsigned long flags
;
2838 spin_lock_irqsave(&adev
->vm_manager
.pasid_lock
, flags
);
2839 idr_remove(&adev
->vm_manager
.pasid_idr
, pasid
);
2840 spin_unlock_irqrestore(&adev
->vm_manager
.pasid_lock
, flags
);
2843 amdgpu_bo_unreserve(vm
->root
.base
.bo
);
2848 * amdgpu_vm_release_compute - release a compute vm
2849 * @adev: amdgpu_device pointer
2850 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
2852 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
2853 * pasid from vm. Compute should stop use of vm after this call.
2855 void amdgpu_vm_release_compute(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
2858 unsigned long flags
;
2860 spin_lock_irqsave(&adev
->vm_manager
.pasid_lock
, flags
);
2861 idr_remove(&adev
->vm_manager
.pasid_idr
, vm
->pasid
);
2862 spin_unlock_irqrestore(&adev
->vm_manager
.pasid_lock
, flags
);
2868 * amdgpu_vm_fini - tear down a vm instance
2870 * @adev: amdgpu_device pointer
2874 * Unbind the VM and remove all bos from the vm bo list
2876 void amdgpu_vm_fini(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
2878 struct amdgpu_bo_va_mapping
*mapping
, *tmp
;
2879 bool prt_fini_needed
= !!adev
->gmc
.gmc_funcs
->set_prt
;
2880 struct amdgpu_bo
*root
;
2883 amdgpu_amdkfd_gpuvm_destroy_cb(adev
, vm
);
2886 unsigned long flags
;
2888 spin_lock_irqsave(&adev
->vm_manager
.pasid_lock
, flags
);
2889 idr_remove(&adev
->vm_manager
.pasid_idr
, vm
->pasid
);
2890 spin_unlock_irqrestore(&adev
->vm_manager
.pasid_lock
, flags
);
2893 drm_sched_entity_destroy(&vm
->entity
);
2895 if (!RB_EMPTY_ROOT(&vm
->va
.rb_root
)) {
2896 dev_err(adev
->dev
, "still active bo inside vm\n");
2898 rbtree_postorder_for_each_entry_safe(mapping
, tmp
,
2899 &vm
->va
.rb_root
, rb
) {
2900 /* Don't remove the mapping here, we don't want to trigger a
2901 * rebalance and the tree is about to be destroyed anyway.
2903 list_del(&mapping
->list
);
2906 list_for_each_entry_safe(mapping
, tmp
, &vm
->freed
, list
) {
2907 if (mapping
->flags
& AMDGPU_PTE_PRT
&& prt_fini_needed
) {
2908 amdgpu_vm_prt_fini(adev
, vm
);
2909 prt_fini_needed
= false;
2912 list_del(&mapping
->list
);
2913 amdgpu_vm_free_mapping(adev
, vm
, mapping
, NULL
);
2916 root
= amdgpu_bo_ref(vm
->root
.base
.bo
);
2917 r
= amdgpu_bo_reserve(root
, true);
2919 dev_err(adev
->dev
, "Leaking page tables because BO reservation failed\n");
2921 amdgpu_vm_free_pts(adev
, vm
, NULL
);
2922 amdgpu_bo_unreserve(root
);
2924 amdgpu_bo_unref(&root
);
2925 WARN_ON(vm
->root
.base
.bo
);
2926 dma_fence_put(vm
->last_update
);
2927 for (i
= 0; i
< AMDGPU_MAX_VMHUBS
; i
++)
2928 amdgpu_vmid_free_reserved(adev
, vm
, i
);
2932 * amdgpu_vm_manager_init - init the VM manager
2934 * @adev: amdgpu_device pointer
2936 * Initialize the VM manager structures
2938 void amdgpu_vm_manager_init(struct amdgpu_device
*adev
)
2942 amdgpu_vmid_mgr_init(adev
);
2944 adev
->vm_manager
.fence_context
=
2945 dma_fence_context_alloc(AMDGPU_MAX_RINGS
);
2946 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
)
2947 adev
->vm_manager
.seqno
[i
] = 0;
2949 spin_lock_init(&adev
->vm_manager
.prt_lock
);
2950 atomic_set(&adev
->vm_manager
.num_prt_users
, 0);
2952 /* If not overridden by the user, by default, only in large BAR systems
2953 * Compute VM tables will be updated by CPU
2955 #ifdef CONFIG_X86_64
2956 if (amdgpu_vm_update_mode
== -1) {
2957 if (amdgpu_gmc_vram_full_visible(&adev
->gmc
))
2958 adev
->vm_manager
.vm_update_mode
=
2959 AMDGPU_VM_USE_CPU_FOR_COMPUTE
;
2961 adev
->vm_manager
.vm_update_mode
= 0;
2963 adev
->vm_manager
.vm_update_mode
= amdgpu_vm_update_mode
;
2965 adev
->vm_manager
.vm_update_mode
= 0;
2968 idr_init(&adev
->vm_manager
.pasid_idr
);
2969 spin_lock_init(&adev
->vm_manager
.pasid_lock
);
2971 adev
->vm_manager
.xgmi_map_counter
= 0;
2972 mutex_init(&adev
->vm_manager
.lock_pstate
);
2976 * amdgpu_vm_manager_fini - cleanup VM manager
2978 * @adev: amdgpu_device pointer
2980 * Cleanup the VM manager and free resources.
2982 void amdgpu_vm_manager_fini(struct amdgpu_device
*adev
)
2984 WARN_ON(!idr_is_empty(&adev
->vm_manager
.pasid_idr
));
2985 idr_destroy(&adev
->vm_manager
.pasid_idr
);
2987 amdgpu_vmid_mgr_fini(adev
);
2991 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
2993 * @dev: drm device pointer
2994 * @data: drm_amdgpu_vm
2995 * @filp: drm file pointer
2998 * 0 for success, -errno for errors.
3000 int amdgpu_vm_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
)
3002 union drm_amdgpu_vm
*args
= data
;
3003 struct amdgpu_device
*adev
= dev
->dev_private
;
3004 struct amdgpu_fpriv
*fpriv
= filp
->driver_priv
;
3007 switch (args
->in
.op
) {
3008 case AMDGPU_VM_OP_RESERVE_VMID
:
3009 /* current, we only have requirement to reserve vmid from gfxhub */
3010 r
= amdgpu_vmid_alloc_reserved(adev
, &fpriv
->vm
, AMDGPU_GFXHUB
);
3014 case AMDGPU_VM_OP_UNRESERVE_VMID
:
3015 amdgpu_vmid_free_reserved(adev
, &fpriv
->vm
, AMDGPU_GFXHUB
);
3025 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
3027 * @adev: drm device pointer
3028 * @pasid: PASID identifier for VM
3029 * @task_info: task_info to fill.
3031 void amdgpu_vm_get_task_info(struct amdgpu_device
*adev
, unsigned int pasid
,
3032 struct amdgpu_task_info
*task_info
)
3034 struct amdgpu_vm
*vm
;
3035 unsigned long flags
;
3037 spin_lock_irqsave(&adev
->vm_manager
.pasid_lock
, flags
);
3039 vm
= idr_find(&adev
->vm_manager
.pasid_idr
, pasid
);
3041 *task_info
= vm
->task_info
;
3043 spin_unlock_irqrestore(&adev
->vm_manager
.pasid_lock
, flags
);
3047 * amdgpu_vm_set_task_info - Sets VMs task info.
3049 * @vm: vm for which to set the info
3051 void amdgpu_vm_set_task_info(struct amdgpu_vm
*vm
)
3053 if (!vm
->task_info
.pid
) {
3054 vm
->task_info
.pid
= current
->pid
;
3055 get_task_comm(vm
->task_info
.task_name
, current
);
3057 if (current
->group_leader
->mm
== current
->mm
) {
3058 vm
->task_info
.tgid
= current
->group_leader
->pid
;
3059 get_task_comm(vm
->task_info
.process_name
, current
->group_leader
);