drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König
  23  */
  24 #ifndef __AMDGPU_VM_H__
  25 #define __AMDGPU_VM_H__
  26
  27 #include <linux/rbtree.h>
  28 #include <linux/idr.h>
  29
  30 #include "gpu_scheduler.h"
  31 #include "amdgpu_sync.h"
  32 #include "amdgpu_ring.h"
  33
  34 struct amdgpu_bo_va;
  35 struct amdgpu_job;
  36 struct amdgpu_bo_list_entry;
  37
  38 /*
  39  * GPUVM handling
  40  */
  41
  42 /* maximum number of VMIDs */
  43 #define AMDGPU_NUM_VM   16
  44
  45 /* Maximum number of PTEs the hardware can write with one command */
  46 #define AMDGPU_VM_MAX_UPDATE_SIZE       0x3FFFF
  47
  48 /* number of entries in page table */
  49 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
  50
  51 /* PTBs (Page Table Blocks) need to be aligned to 32K */
  52 #define AMDGPU_VM_PTB_ALIGN_SIZE   32768
  53
  54 #define AMDGPU_PTE_VALID        (1ULL << 0)
  55 #define AMDGPU_PTE_SYSTEM       (1ULL << 1)
  56 #define AMDGPU_PTE_SNOOPED      (1ULL << 2)
  57
  58 /* VI only */
  59 #define AMDGPU_PTE_EXECUTABLE   (1ULL << 4)
  60
  61 #define AMDGPU_PTE_READABLE     (1ULL << 5)
  62 #define AMDGPU_PTE_WRITEABLE    (1ULL << 6)
  63
  64 #define AMDGPU_PTE_FRAG(x)      ((x & 0x1fULL) << 7)
  65
  66 /* TILED for VEGA10, reserved for older ASICs  */
  67 #define AMDGPU_PTE_PRT          (1ULL << 51)
  68
  69 /* PDE is handled as PTE for VEGA10 */
  70 #define AMDGPU_PDE_PTE          (1ULL << 54)
  71
  72 /* VEGA10 only */
  73 #define AMDGPU_PTE_MTYPE(a)    ((uint64_t)a << 57)
  74 #define AMDGPU_PTE_MTYPE_MASK   AMDGPU_PTE_MTYPE(3ULL)
  75
  76 /* How to programm VM fault handling */
  77 #define AMDGPU_VM_FAULT_STOP_NEVER      0
  78 #define AMDGPU_VM_FAULT_STOP_FIRST      1
  79 #define AMDGPU_VM_FAULT_STOP_ALWAYS     2
  80
  81 /* max number of VMHUB */
  82 #define AMDGPU_MAX_VMHUBS                       2
  83 #define AMDGPU_GFXHUB                           0
  84 #define AMDGPU_MMHUB                            1
  85
  86 /* hardcode that limit for now */
  87 #define AMDGPU_VA_RESERVED_SIZE                 (8 << 20)
  88 /* max vmids dedicated for process */
  89 #define AMDGPU_VM_MAX_RESERVED_VMID     1
  90
  91 #define AMDGPU_VM_CONTEXT_GFX 0
  92 #define AMDGPU_VM_CONTEXT_COMPUTE 1
  93
  94 /* See vm_update_mode */
  95 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
  96 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
  97
  98 /* base structure for tracking BO usage in a VM */
  99 struct amdgpu_vm_bo_base {
 100         /* constant after initialization */
 101         struct amdgpu_vm                *vm;
 102         struct amdgpu_bo                *bo;
 103
 104         /* protected by bo being reserved */
 105         struct list_head                bo_list;
 106
 107         /* protected by spinlock */
 108         struct list_head                vm_status;
 109
 110         /* protected by the BO being reserved */
 111         bool                            moved;
 112 };
 113
 114 struct amdgpu_vm_pt {
 115         struct amdgpu_vm_bo_base        base;
 116         uint64_t                        addr;
 117
 118         /* array of page tables, one for each directory entry */
 119         struct amdgpu_vm_pt             *entries;
 120         unsigned                        last_entry_used;
 121 };
 122
 123 #define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) | (addr))
 124 #define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48)
 125 #define AMDGPU_VM_FAULT_ADDR(fault)  ((u64)(fault) & 0xfffffffff000ULL)
 126
 127 struct amdgpu_vm {
 128         /* tree of virtual addresses mapped */
 129         struct rb_root_cached   va;
 130
 131         /* protecting invalidated */
 132         spinlock_t              status_lock;
 133
 134         /* BOs who needs a validation */
 135         struct list_head        evicted;
 136
 137         /* PT BOs which relocated and their parent need an update */
 138         struct list_head        relocated;
 139
 140         /* BOs moved, but not yet updated in the PT */
 141         struct list_head        moved;
 142
 143         /* BO mappings freed, but not yet updated in the PT */
 144         struct list_head        freed;
 145
 146         /* contains the page directory */
 147         struct amdgpu_vm_pt     root;
 148         struct dma_fence        *last_update;
 149
 150         /* protecting freed */
 151         spinlock_t              freed_lock;
 152
 153         /* Scheduler entity for page table updates */
 154         struct amd_sched_entity entity;
 155
 156         /* client id and PASID (TODO: replace client_id with PASID) */
 157         u64                     client_id;
 158         unsigned int            pasid;
 159         /* dedicated to vm */
 160         struct amdgpu_vm_id     *reserved_vmid[AMDGPU_MAX_VMHUBS];
 161
 162         /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
 163         bool                    use_cpu_for_update;
 164
 165         /* Flag to indicate ATS support from PTE for GFX9 */
 166         bool                    pte_support_ats;
 167
 168         /* Up to 128 pending page faults */
 169         DECLARE_KFIFO(faults, u64, 128);
 170 };
 171
 172 struct amdgpu_vm_id {
 173         struct list_head        list;
 174         struct amdgpu_sync      active;
 175         struct dma_fence                *last_flush;
 176         atomic64_t              owner;
 177
 178         uint64_t                pd_gpu_addr;
 179         /* last flushed PD/PT update */
 180         struct dma_fence                *flushed_updates;
 181
 182         uint32_t                current_gpu_reset_count;
 183
 184         uint32_t                gds_base;
 185         uint32_t                gds_size;
 186         uint32_t                gws_base;
 187         uint32_t                gws_size;
 188         uint32_t                oa_base;
 189         uint32_t                oa_size;
 190 };
 191
 192 struct amdgpu_vm_id_manager {
 193         struct mutex            lock;
 194         unsigned                num_ids;
 195         struct list_head        ids_lru;
 196         struct amdgpu_vm_id     ids[AMDGPU_NUM_VM];
 197         atomic_t                reserved_vmid_num;
 198 };
 199
 200 struct amdgpu_vm_manager {
 201         /* Handling of VMIDs */
 202         struct amdgpu_vm_id_manager             id_mgr[AMDGPU_MAX_VMHUBS];
 203
 204         /* Handling of VM fences */
 205         u64                                     fence_context;
 206         unsigned                                seqno[AMDGPU_MAX_RINGS];
 207
 208         uint64_t                                max_pfn;
 209         uint32_t                                num_level;
 210         uint64_t                                vm_size;
 211         uint32_t                                block_size;
 212         uint32_t                                fragment_size;
 213         /* vram base address for page table entry  */
 214         u64                                     vram_base_offset;
 215         /* vm pte handling */
 216         const struct amdgpu_vm_pte_funcs        *vm_pte_funcs;
 217         struct amdgpu_ring                      *vm_pte_rings[AMDGPU_MAX_RINGS];
 218         unsigned                                vm_pte_num_rings;
 219         atomic_t                                vm_pte_next_ring;
 220         /* client id counter */
 221         atomic64_t                              client_counter;
 222
 223         /* partial resident texture handling */
 224         spinlock_t                              prt_lock;
 225         atomic_t                                num_prt_users;
 226
 227         /* controls how VM page tables are updated for Graphics and Compute.
 228          * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU
 229          * BIT1[= 0] Compute updated by SDMA [= 1] by CPU
 230          */
 231         int                                     vm_update_mode;
 232
 233         /* PASID to VM mapping, will be used in interrupt context to
 234          * look up VM of a page fault
 235          */
 236         struct idr                              pasid_idr;
 237         spinlock_t                              pasid_lock;
 238 };
 239
 240 int amdgpu_vm_alloc_pasid(unsigned int bits);
 241 void amdgpu_vm_free_pasid(unsigned int pasid);
 242 void amdgpu_vm_manager_init(struct amdgpu_device *adev);
 243 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
 244 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 245                    int vm_context, unsigned int pasid);
 246 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
 247 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
 248                          struct list_head *validated,
 249                          struct amdgpu_bo_list_entry *entry);
 250 bool amdgpu_vm_ready(struct amdgpu_vm *vm);
 251 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 252                               int (*callback)(void *p, struct amdgpu_bo *bo),
 253                               void *param);
 254 int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
 255                         struct amdgpu_vm *vm,
 256                         uint64_t saddr, uint64_t size);
 257 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 258                       struct amdgpu_sync *sync, struct dma_fence *fence,
 259                       struct amdgpu_job *job);
 260 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
 261 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub,
 262                         unsigned vmid);
 263 void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev);
 264 int amdgpu_vm_update_directories(struct amdgpu_device *adev,
 265                                  struct amdgpu_vm *vm);
 266 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
 267                           struct amdgpu_vm *vm,
 268                           struct dma_fence **fence);
 269 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
 270                            struct amdgpu_vm *vm);
 271 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 272                         struct amdgpu_bo_va *bo_va,
 273                         bool clear);
 274 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
 275                              struct amdgpu_bo *bo, bool evicted);
 276 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
 277                                        struct amdgpu_bo *bo);
 278 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
 279                                       struct amdgpu_vm *vm,
 280                                       struct amdgpu_bo *bo);
 281 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
 282                      struct amdgpu_bo_va *bo_va,
 283                      uint64_t addr, uint64_t offset,
 284                      uint64_t size, uint64_t flags);
 285 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
 286                              struct amdgpu_bo_va *bo_va,
 287                              uint64_t addr, uint64_t offset,
 288                              uint64_t size, uint64_t flags);
 289 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
 290                        struct amdgpu_bo_va *bo_va,
 291                        uint64_t addr);
 292 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
 293                                 struct amdgpu_vm *vm,
 294                                 uint64_t saddr, uint64_t size);
 295 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
 296                                                          uint64_t addr);
 297 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
 298                       struct amdgpu_bo_va *bo_va);
 299 void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
 300                                 uint32_t fragment_size_default);
 301 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size,
 302                                 uint32_t fragment_size_default);
 303 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
 304 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
 305                                   struct amdgpu_job *job);
 306 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
 307
 308 #endif