2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/amdgpu_drm.h>
30 #include "amdgpu_connectors.h"
32 #include "atombios_encoders.h"
33 #include "atombios_dp.h"
34 #include <linux/backlight.h>
35 #include "bif/bif_4_1_d.h"
38 amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device
*adev
)
43 bios_2_scratch
= RREG32(mmBIOS_SCRATCH_2
);
45 backlight_level
= ((bios_2_scratch
& ATOM_S2_CURRENT_BL_LEVEL_MASK
) >>
46 ATOM_S2_CURRENT_BL_LEVEL_SHIFT
);
48 return backlight_level
;
52 amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device
*adev
,
57 bios_2_scratch
= RREG32(mmBIOS_SCRATCH_2
);
59 bios_2_scratch
&= ~ATOM_S2_CURRENT_BL_LEVEL_MASK
;
60 bios_2_scratch
|= ((backlight_level
<< ATOM_S2_CURRENT_BL_LEVEL_SHIFT
) &
61 ATOM_S2_CURRENT_BL_LEVEL_MASK
);
63 WREG32(mmBIOS_SCRATCH_2
, bios_2_scratch
);
67 amdgpu_atombios_encoder_get_backlight_level(struct amdgpu_encoder
*amdgpu_encoder
)
69 struct drm_device
*dev
= amdgpu_encoder
->base
.dev
;
70 struct amdgpu_device
*adev
= dev
->dev_private
;
72 if (!(adev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
75 return amdgpu_atombios_encoder_get_backlight_level_from_reg(adev
);
79 amdgpu_atombios_encoder_set_backlight_level(struct amdgpu_encoder
*amdgpu_encoder
,
82 struct drm_encoder
*encoder
= &amdgpu_encoder
->base
;
83 struct drm_device
*dev
= amdgpu_encoder
->base
.dev
;
84 struct amdgpu_device
*adev
= dev
->dev_private
;
85 struct amdgpu_encoder_atom_dig
*dig
;
87 if (!(adev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
90 if ((amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) &&
91 amdgpu_encoder
->enc_priv
) {
92 dig
= amdgpu_encoder
->enc_priv
;
93 dig
->backlight_level
= level
;
94 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev
, dig
->backlight_level
);
96 switch (amdgpu_encoder
->encoder_id
) {
97 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
98 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
99 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
100 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
101 if (dig
->backlight_level
== 0)
102 amdgpu_atombios_encoder_setup_dig_transmitter(encoder
,
103 ATOM_TRANSMITTER_ACTION_LCD_BLOFF
, 0, 0);
105 amdgpu_atombios_encoder_setup_dig_transmitter(encoder
,
106 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL
, 0, 0);
107 amdgpu_atombios_encoder_setup_dig_transmitter(encoder
,
108 ATOM_TRANSMITTER_ACTION_LCD_BLON
, 0, 0);
117 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
119 static u8
amdgpu_atombios_encoder_backlight_level(struct backlight_device
*bd
)
123 /* Convert brightness to hardware level */
124 if (bd
->props
.brightness
< 0)
126 else if (bd
->props
.brightness
> AMDGPU_MAX_BL_LEVEL
)
127 level
= AMDGPU_MAX_BL_LEVEL
;
129 level
= bd
->props
.brightness
;
134 static int amdgpu_atombios_encoder_update_backlight_status(struct backlight_device
*bd
)
136 struct amdgpu_backlight_privdata
*pdata
= bl_get_data(bd
);
137 struct amdgpu_encoder
*amdgpu_encoder
= pdata
->encoder
;
139 amdgpu_atombios_encoder_set_backlight_level(amdgpu_encoder
,
140 amdgpu_atombios_encoder_backlight_level(bd
));
146 amdgpu_atombios_encoder_get_backlight_brightness(struct backlight_device
*bd
)
148 struct amdgpu_backlight_privdata
*pdata
= bl_get_data(bd
);
149 struct amdgpu_encoder
*amdgpu_encoder
= pdata
->encoder
;
150 struct drm_device
*dev
= amdgpu_encoder
->base
.dev
;
151 struct amdgpu_device
*adev
= dev
->dev_private
;
153 return amdgpu_atombios_encoder_get_backlight_level_from_reg(adev
);
156 static const struct backlight_ops amdgpu_atombios_encoder_backlight_ops
= {
157 .get_brightness
= amdgpu_atombios_encoder_get_backlight_brightness
,
158 .update_status
= amdgpu_atombios_encoder_update_backlight_status
,
161 void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder
*amdgpu_encoder
,
162 struct drm_connector
*drm_connector
)
164 struct drm_device
*dev
= amdgpu_encoder
->base
.dev
;
165 struct amdgpu_device
*adev
= dev
->dev_private
;
166 struct backlight_device
*bd
;
167 struct backlight_properties props
;
168 struct amdgpu_backlight_privdata
*pdata
;
169 struct amdgpu_encoder_atom_dig
*dig
;
173 /* Mac laptops with multiple GPUs use the gmux driver for backlight
174 * so don't register a backlight device
176 if ((adev
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_APPLE
) &&
177 (adev
->pdev
->device
== 0x6741))
180 if (!amdgpu_encoder
->enc_priv
)
183 if (!adev
->is_atom_bios
)
186 if (!(adev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
189 pdata
= kmalloc(sizeof(struct amdgpu_backlight_privdata
), GFP_KERNEL
);
191 DRM_ERROR("Memory allocation failed\n");
195 memset(&props
, 0, sizeof(props
));
196 props
.max_brightness
= AMDGPU_MAX_BL_LEVEL
;
197 props
.type
= BACKLIGHT_RAW
;
198 snprintf(bl_name
, sizeof(bl_name
),
199 "amdgpu_bl%d", dev
->primary
->index
);
200 bd
= backlight_device_register(bl_name
, drm_connector
->kdev
,
201 pdata
, &amdgpu_atombios_encoder_backlight_ops
, &props
);
203 DRM_ERROR("Backlight registration failed\n");
207 pdata
->encoder
= amdgpu_encoder
;
209 backlight_level
= amdgpu_atombios_encoder_get_backlight_level_from_reg(adev
);
211 dig
= amdgpu_encoder
->enc_priv
;
214 bd
->props
.brightness
= amdgpu_atombios_encoder_get_backlight_brightness(bd
);
215 bd
->props
.power
= FB_BLANK_UNBLANK
;
216 backlight_update_status(bd
);
218 DRM_INFO("amdgpu atom DIG backlight initialized\n");
228 amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder
*amdgpu_encoder
)
230 struct drm_device
*dev
= amdgpu_encoder
->base
.dev
;
231 struct amdgpu_device
*adev
= dev
->dev_private
;
232 struct backlight_device
*bd
= NULL
;
233 struct amdgpu_encoder_atom_dig
*dig
;
235 if (!amdgpu_encoder
->enc_priv
)
238 if (!adev
->is_atom_bios
)
241 if (!(adev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
244 dig
= amdgpu_encoder
->enc_priv
;
249 struct amdgpu_legacy_backlight_privdata
*pdata
;
251 pdata
= bl_get_data(bd
);
252 backlight_device_unregister(bd
);
255 DRM_INFO("amdgpu atom LVDS backlight unloaded\n");
259 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
261 void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder
*encoder
)
265 void amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder
*encoder
)
271 bool amdgpu_atombios_encoder_is_digital(struct drm_encoder
*encoder
)
273 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
274 switch (amdgpu_encoder
->encoder_id
) {
275 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
276 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
277 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
278 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
279 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
286 bool amdgpu_atombios_encoder_mode_fixup(struct drm_encoder
*encoder
,
287 const struct drm_display_mode
*mode
,
288 struct drm_display_mode
*adjusted_mode
)
290 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
292 /* set the active encoder to connector routing */
293 amdgpu_encoder_set_active_device(encoder
);
294 drm_mode_set_crtcinfo(adjusted_mode
, 0);
297 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
298 && (mode
->crtc_vsync_start
< (mode
->crtc_vdisplay
+ 2)))
299 adjusted_mode
->crtc_vsync_start
= adjusted_mode
->crtc_vdisplay
+ 2;
301 /* vertical FP must be at least 1 */
302 if (mode
->crtc_vsync_start
== mode
->crtc_vdisplay
)
303 adjusted_mode
->crtc_vsync_start
++;
305 /* get the native mode for scaling */
306 if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_LCD_SUPPORT
))
307 amdgpu_panel_mode_fixup(encoder
, adjusted_mode
);
308 else if (amdgpu_encoder
->rmx_type
!= RMX_OFF
)
309 amdgpu_panel_mode_fixup(encoder
, adjusted_mode
);
311 if ((amdgpu_encoder
->active_device
& (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
312 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
)) {
313 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
314 amdgpu_atombios_dp_set_link_config(connector
, adjusted_mode
);
321 amdgpu_atombios_encoder_setup_dac(struct drm_encoder
*encoder
, int action
)
323 struct drm_device
*dev
= encoder
->dev
;
324 struct amdgpu_device
*adev
= dev
->dev_private
;
325 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
326 DAC_ENCODER_CONTROL_PS_ALLOCATION args
;
329 memset(&args
, 0, sizeof(args
));
331 switch (amdgpu_encoder
->encoder_id
) {
332 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
333 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
334 index
= GetIndexIntoMasterTable(COMMAND
, DAC1EncoderControl
);
336 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
337 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
338 index
= GetIndexIntoMasterTable(COMMAND
, DAC2EncoderControl
);
342 args
.ucAction
= action
;
343 args
.ucDacStandard
= ATOM_DAC1_PS2
;
344 args
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
346 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
350 static u8
amdgpu_atombios_encoder_get_bpc(struct drm_encoder
*encoder
)
355 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
356 bpc
= amdgpu_crtc
->bpc
;
361 return PANEL_BPC_UNDEFINE
;
363 return PANEL_6BIT_PER_COLOR
;
366 return PANEL_8BIT_PER_COLOR
;
368 return PANEL_10BIT_PER_COLOR
;
370 return PANEL_12BIT_PER_COLOR
;
372 return PANEL_16BIT_PER_COLOR
;
376 union dvo_encoder_control
{
377 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds
;
378 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo
;
379 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3
;
380 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4
;
384 amdgpu_atombios_encoder_setup_dvo(struct drm_encoder
*encoder
, int action
)
386 struct drm_device
*dev
= encoder
->dev
;
387 struct amdgpu_device
*adev
= dev
->dev_private
;
388 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
389 union dvo_encoder_control args
;
390 int index
= GetIndexIntoMasterTable(COMMAND
, DVOEncoderControl
);
393 memset(&args
, 0, sizeof(args
));
395 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
403 args
.ext_tmds
.sXTmdsEncoder
.ucEnable
= action
;
405 if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
406 args
.ext_tmds
.sXTmdsEncoder
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
408 args
.ext_tmds
.sXTmdsEncoder
.ucMisc
|= ATOM_PANEL_MISC_888RGB
;
412 args
.dvo
.sDVOEncoder
.ucAction
= action
;
413 args
.dvo
.sDVOEncoder
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
414 /* DFP1, CRT1, TV1 depending on the type of port */
415 args
.dvo
.sDVOEncoder
.ucDeviceType
= ATOM_DEVICE_DFP1_INDEX
;
417 if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
418 args
.dvo
.sDVOEncoder
.usDevAttr
.sDigAttrib
.ucAttribute
|= PANEL_ENCODER_MISC_DUAL
;
422 args
.dvo_v3
.ucAction
= action
;
423 args
.dvo_v3
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
424 args
.dvo_v3
.ucDVOConfig
= 0; /* XXX */
428 args
.dvo_v4
.ucAction
= action
;
429 args
.dvo_v4
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
430 args
.dvo_v4
.ucDVOConfig
= 0; /* XXX */
431 args
.dvo_v4
.ucBitPerColor
= amdgpu_atombios_encoder_get_bpc(encoder
);
434 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
439 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
443 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
446 int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder
*encoder
)
448 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
449 struct drm_connector
*connector
;
450 struct amdgpu_connector
*amdgpu_connector
;
451 struct amdgpu_connector_atom_dig
*dig_connector
;
453 /* dp bridges are always DP */
454 if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
)
455 return ATOM_ENCODER_MODE_DP
;
457 /* DVO is always DVO */
458 if ((amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DVO1
) ||
459 (amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
))
460 return ATOM_ENCODER_MODE_DVO
;
462 connector
= amdgpu_get_connector_for_encoder(encoder
);
463 /* if we don't have an active device yet, just use one of
464 * the connectors tied to the encoder.
467 connector
= amdgpu_get_connector_for_encoder_init(encoder
);
468 amdgpu_connector
= to_amdgpu_connector(connector
);
470 switch (connector
->connector_type
) {
471 case DRM_MODE_CONNECTOR_DVII
:
472 case DRM_MODE_CONNECTOR_HDMIB
: /* HDMI-B is basically DL-DVI; analog works fine */
473 if (amdgpu_audio
!= 0) {
474 if (amdgpu_connector
->use_digital
&&
475 (amdgpu_connector
->audio
== AMDGPU_AUDIO_ENABLE
))
476 return ATOM_ENCODER_MODE_HDMI
;
477 else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector
)) &&
478 (amdgpu_connector
->audio
== AMDGPU_AUDIO_AUTO
))
479 return ATOM_ENCODER_MODE_HDMI
;
480 else if (amdgpu_connector
->use_digital
)
481 return ATOM_ENCODER_MODE_DVI
;
483 return ATOM_ENCODER_MODE_CRT
;
484 } else if (amdgpu_connector
->use_digital
) {
485 return ATOM_ENCODER_MODE_DVI
;
487 return ATOM_ENCODER_MODE_CRT
;
490 case DRM_MODE_CONNECTOR_DVID
:
491 case DRM_MODE_CONNECTOR_HDMIA
:
493 if (amdgpu_audio
!= 0) {
494 if (amdgpu_connector
->audio
== AMDGPU_AUDIO_ENABLE
)
495 return ATOM_ENCODER_MODE_HDMI
;
496 else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector
)) &&
497 (amdgpu_connector
->audio
== AMDGPU_AUDIO_AUTO
))
498 return ATOM_ENCODER_MODE_HDMI
;
500 return ATOM_ENCODER_MODE_DVI
;
502 return ATOM_ENCODER_MODE_DVI
;
505 case DRM_MODE_CONNECTOR_LVDS
:
506 return ATOM_ENCODER_MODE_LVDS
;
508 case DRM_MODE_CONNECTOR_DisplayPort
:
509 dig_connector
= amdgpu_connector
->con_priv
;
510 if ((dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_DISPLAYPORT
) ||
511 (dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_eDP
)) {
512 return ATOM_ENCODER_MODE_DP
;
513 } else if (amdgpu_audio
!= 0) {
514 if (amdgpu_connector
->audio
== AMDGPU_AUDIO_ENABLE
)
515 return ATOM_ENCODER_MODE_HDMI
;
516 else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector
)) &&
517 (amdgpu_connector
->audio
== AMDGPU_AUDIO_AUTO
))
518 return ATOM_ENCODER_MODE_HDMI
;
520 return ATOM_ENCODER_MODE_DVI
;
522 return ATOM_ENCODER_MODE_DVI
;
525 case DRM_MODE_CONNECTOR_eDP
:
526 return ATOM_ENCODER_MODE_DP
;
527 case DRM_MODE_CONNECTOR_DVIA
:
528 case DRM_MODE_CONNECTOR_VGA
:
529 return ATOM_ENCODER_MODE_CRT
;
531 case DRM_MODE_CONNECTOR_Composite
:
532 case DRM_MODE_CONNECTOR_SVIDEO
:
533 case DRM_MODE_CONNECTOR_9PinDIN
:
535 return ATOM_ENCODER_MODE_TV
;
536 /*return ATOM_ENCODER_MODE_CV;*/
542 * DIG Encoder/Transmitter Setup
545 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
546 * Supports up to 6 digital outputs
547 * - 6 DIG encoder blocks.
548 * - DIG to PHY mapping is hardcoded
549 * DIG1 drives UNIPHY0 link A, A+B
550 * DIG2 drives UNIPHY0 link B
551 * DIG3 drives UNIPHY1 link A, A+B
552 * DIG4 drives UNIPHY1 link B
553 * DIG5 drives UNIPHY2 link A, A+B
554 * DIG6 drives UNIPHY2 link B
557 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
559 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
560 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
561 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
562 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
565 union dig_encoder_control
{
566 DIG_ENCODER_CONTROL_PS_ALLOCATION v1
;
567 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2
;
568 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3
;
569 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4
;
573 amdgpu_atombios_encoder_setup_dig_encoder(struct drm_encoder
*encoder
,
574 int action
, int panel_mode
)
576 struct drm_device
*dev
= encoder
->dev
;
577 struct amdgpu_device
*adev
= dev
->dev_private
;
578 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
579 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
580 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
581 union dig_encoder_control args
;
582 int index
= GetIndexIntoMasterTable(COMMAND
, DIGxEncoderControl
);
585 int dp_lane_count
= 0;
586 int hpd_id
= AMDGPU_HPD_NONE
;
589 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
590 struct amdgpu_connector_atom_dig
*dig_connector
=
591 amdgpu_connector
->con_priv
;
593 dp_clock
= dig_connector
->dp_clock
;
594 dp_lane_count
= dig_connector
->dp_lane_count
;
595 hpd_id
= amdgpu_connector
->hpd
.hpd
;
598 /* no dig encoder assigned */
599 if (dig
->dig_encoder
== -1)
602 memset(&args
, 0, sizeof(args
));
604 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
611 args
.v1
.ucAction
= action
;
612 args
.v1
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
613 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
614 args
.v3
.ucPanelMode
= panel_mode
;
616 args
.v1
.ucEncoderMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
618 if (ENCODER_MODE_IS_DP(args
.v1
.ucEncoderMode
))
619 args
.v1
.ucLaneNum
= dp_lane_count
;
620 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
621 args
.v1
.ucLaneNum
= 8;
623 args
.v1
.ucLaneNum
= 4;
625 if (ENCODER_MODE_IS_DP(args
.v1
.ucEncoderMode
) && (dp_clock
== 270000))
626 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ
;
627 switch (amdgpu_encoder
->encoder_id
) {
628 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
629 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER1
;
631 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
632 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
633 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER2
;
635 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
636 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER3
;
640 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKB
;
642 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKA
;
646 args
.v3
.ucAction
= action
;
647 args
.v3
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
648 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
649 args
.v3
.ucPanelMode
= panel_mode
;
651 args
.v3
.ucEncoderMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
653 if (ENCODER_MODE_IS_DP(args
.v3
.ucEncoderMode
))
654 args
.v3
.ucLaneNum
= dp_lane_count
;
655 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
656 args
.v3
.ucLaneNum
= 8;
658 args
.v3
.ucLaneNum
= 4;
660 if (ENCODER_MODE_IS_DP(args
.v3
.ucEncoderMode
) && (dp_clock
== 270000))
661 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ
;
662 args
.v3
.acConfig
.ucDigSel
= dig
->dig_encoder
;
663 args
.v3
.ucBitPerColor
= amdgpu_atombios_encoder_get_bpc(encoder
);
666 args
.v4
.ucAction
= action
;
667 args
.v4
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
668 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
669 args
.v4
.ucPanelMode
= panel_mode
;
671 args
.v4
.ucEncoderMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
673 if (ENCODER_MODE_IS_DP(args
.v4
.ucEncoderMode
))
674 args
.v4
.ucLaneNum
= dp_lane_count
;
675 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
676 args
.v4
.ucLaneNum
= 8;
678 args
.v4
.ucLaneNum
= 4;
680 if (ENCODER_MODE_IS_DP(args
.v4
.ucEncoderMode
)) {
681 if (dp_clock
== 540000)
682 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ
;
683 else if (dp_clock
== 324000)
684 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ
;
685 else if (dp_clock
== 270000)
686 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ
;
688 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ
;
690 args
.v4
.acConfig
.ucDigSel
= dig
->dig_encoder
;
691 args
.v4
.ucBitPerColor
= amdgpu_atombios_encoder_get_bpc(encoder
);
692 if (hpd_id
== AMDGPU_HPD_NONE
)
693 args
.v4
.ucHPD_ID
= 0;
695 args
.v4
.ucHPD_ID
= hpd_id
+ 1;
698 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
703 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
707 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
711 union dig_transmitter_control
{
712 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1
;
713 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2
;
714 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3
;
715 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4
;
716 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5
;
720 amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder
*encoder
, int action
,
721 uint8_t lane_num
, uint8_t lane_set
)
723 struct drm_device
*dev
= encoder
->dev
;
724 struct amdgpu_device
*adev
= dev
->dev_private
;
725 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
726 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
727 struct drm_connector
*connector
;
728 union dig_transmitter_control args
;
734 int dp_lane_count
= 0;
735 int connector_object_id
= 0;
736 int igp_lane_info
= 0;
737 int dig_encoder
= dig
->dig_encoder
;
738 int hpd_id
= AMDGPU_HPD_NONE
;
740 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
741 connector
= amdgpu_get_connector_for_encoder_init(encoder
);
742 /* just needed to avoid bailing in the encoder check. the encoder
743 * isn't used for init
747 connector
= amdgpu_get_connector_for_encoder(encoder
);
750 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
751 struct amdgpu_connector_atom_dig
*dig_connector
=
752 amdgpu_connector
->con_priv
;
754 hpd_id
= amdgpu_connector
->hpd
.hpd
;
755 dp_clock
= dig_connector
->dp_clock
;
756 dp_lane_count
= dig_connector
->dp_lane_count
;
757 connector_object_id
=
758 (amdgpu_connector
->connector_object_id
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
762 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
763 pll_id
= amdgpu_crtc
->pll_id
;
766 /* no dig encoder assigned */
767 if (dig_encoder
== -1)
770 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder
)))
773 memset(&args
, 0, sizeof(args
));
775 switch (amdgpu_encoder
->encoder_id
) {
776 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
777 index
= GetIndexIntoMasterTable(COMMAND
, DVOOutputControl
);
779 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
780 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
781 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
782 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
783 index
= GetIndexIntoMasterTable(COMMAND
, UNIPHYTransmitterControl
);
785 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
786 index
= GetIndexIntoMasterTable(COMMAND
, LVTMATransmitterControl
);
790 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
797 args
.v1
.ucAction
= action
;
798 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
799 args
.v1
.usInitInfo
= cpu_to_le16(connector_object_id
);
800 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
801 args
.v1
.asMode
.ucLaneSel
= lane_num
;
802 args
.v1
.asMode
.ucLaneSet
= lane_set
;
805 args
.v1
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
806 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
807 args
.v1
.usPixelClock
= cpu_to_le16((amdgpu_encoder
->pixel_clock
/ 2) / 10);
809 args
.v1
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
812 args
.v1
.ucConfig
= ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL
;
815 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER
;
817 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER
;
819 if ((adev
->flags
& AMD_IS_APU
) &&
820 (amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_UNIPHY
)) {
822 !amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
)) {
823 if (igp_lane_info
& 0x1)
824 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_3
;
825 else if (igp_lane_info
& 0x2)
826 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_4_7
;
827 else if (igp_lane_info
& 0x4)
828 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_11
;
829 else if (igp_lane_info
& 0x8)
830 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_12_15
;
832 if (igp_lane_info
& 0x3)
833 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_7
;
834 else if (igp_lane_info
& 0xc)
835 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_15
;
840 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKB
;
842 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKA
;
845 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_COHERENT
;
846 else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
847 if (dig
->coherent_mode
)
848 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_COHERENT
;
849 if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
850 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_8LANE_LINK
;
854 args
.v2
.ucAction
= action
;
855 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
856 args
.v2
.usInitInfo
= cpu_to_le16(connector_object_id
);
857 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
858 args
.v2
.asMode
.ucLaneSel
= lane_num
;
859 args
.v2
.asMode
.ucLaneSet
= lane_set
;
862 args
.v2
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
863 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
864 args
.v2
.usPixelClock
= cpu_to_le16((amdgpu_encoder
->pixel_clock
/ 2) / 10);
866 args
.v2
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
869 args
.v2
.acConfig
.ucEncoderSel
= dig_encoder
;
871 args
.v2
.acConfig
.ucLinkSel
= 1;
873 switch (amdgpu_encoder
->encoder_id
) {
874 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
875 args
.v2
.acConfig
.ucTransmitterSel
= 0;
877 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
878 args
.v2
.acConfig
.ucTransmitterSel
= 1;
880 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
881 args
.v2
.acConfig
.ucTransmitterSel
= 2;
886 args
.v2
.acConfig
.fCoherentMode
= 1;
887 args
.v2
.acConfig
.fDPConnector
= 1;
888 } else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
889 if (dig
->coherent_mode
)
890 args
.v2
.acConfig
.fCoherentMode
= 1;
891 if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
892 args
.v2
.acConfig
.fDualLinkConnector
= 1;
896 args
.v3
.ucAction
= action
;
897 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
898 args
.v3
.usInitInfo
= cpu_to_le16(connector_object_id
);
899 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
900 args
.v3
.asMode
.ucLaneSel
= lane_num
;
901 args
.v3
.asMode
.ucLaneSet
= lane_set
;
904 args
.v3
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
905 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
906 args
.v3
.usPixelClock
= cpu_to_le16((amdgpu_encoder
->pixel_clock
/ 2) / 10);
908 args
.v3
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
912 args
.v3
.ucLaneNum
= dp_lane_count
;
913 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
914 args
.v3
.ucLaneNum
= 8;
916 args
.v3
.ucLaneNum
= 4;
919 args
.v3
.acConfig
.ucLinkSel
= 1;
921 args
.v3
.acConfig
.ucEncoderSel
= 1;
923 /* Select the PLL for the PHY
924 * DP PHY should be clocked from external src if there is
927 /* On DCE4, if there is an external clock, it generates the DP ref clock */
928 if (is_dp
&& adev
->clock
.dp_extclk
)
929 args
.v3
.acConfig
.ucRefClkSource
= 2; /* external src */
931 args
.v3
.acConfig
.ucRefClkSource
= pll_id
;
933 switch (amdgpu_encoder
->encoder_id
) {
934 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
935 args
.v3
.acConfig
.ucTransmitterSel
= 0;
937 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
938 args
.v3
.acConfig
.ucTransmitterSel
= 1;
940 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
941 args
.v3
.acConfig
.ucTransmitterSel
= 2;
946 args
.v3
.acConfig
.fCoherentMode
= 1; /* DP requires coherent */
947 else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
948 if (dig
->coherent_mode
)
949 args
.v3
.acConfig
.fCoherentMode
= 1;
950 if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
951 args
.v3
.acConfig
.fDualLinkConnector
= 1;
955 args
.v4
.ucAction
= action
;
956 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
957 args
.v4
.usInitInfo
= cpu_to_le16(connector_object_id
);
958 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
959 args
.v4
.asMode
.ucLaneSel
= lane_num
;
960 args
.v4
.asMode
.ucLaneSet
= lane_set
;
963 args
.v4
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
964 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
965 args
.v4
.usPixelClock
= cpu_to_le16((amdgpu_encoder
->pixel_clock
/ 2) / 10);
967 args
.v4
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
971 args
.v4
.ucLaneNum
= dp_lane_count
;
972 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
973 args
.v4
.ucLaneNum
= 8;
975 args
.v4
.ucLaneNum
= 4;
978 args
.v4
.acConfig
.ucLinkSel
= 1;
980 args
.v4
.acConfig
.ucEncoderSel
= 1;
982 /* Select the PLL for the PHY
983 * DP PHY should be clocked from external src if there is
986 /* On DCE5 DCPLL usually generates the DP ref clock */
988 if (adev
->clock
.dp_extclk
)
989 args
.v4
.acConfig
.ucRefClkSource
= ENCODER_REFCLK_SRC_EXTCLK
;
991 args
.v4
.acConfig
.ucRefClkSource
= ENCODER_REFCLK_SRC_DCPLL
;
993 args
.v4
.acConfig
.ucRefClkSource
= pll_id
;
995 switch (amdgpu_encoder
->encoder_id
) {
996 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
997 args
.v4
.acConfig
.ucTransmitterSel
= 0;
999 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1000 args
.v4
.acConfig
.ucTransmitterSel
= 1;
1002 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1003 args
.v4
.acConfig
.ucTransmitterSel
= 2;
1008 args
.v4
.acConfig
.fCoherentMode
= 1; /* DP requires coherent */
1009 else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1010 if (dig
->coherent_mode
)
1011 args
.v4
.acConfig
.fCoherentMode
= 1;
1012 if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
1013 args
.v4
.acConfig
.fDualLinkConnector
= 1;
1017 args
.v5
.ucAction
= action
;
1019 args
.v5
.usSymClock
= cpu_to_le16(dp_clock
/ 10);
1021 args
.v5
.usSymClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
1023 switch (amdgpu_encoder
->encoder_id
) {
1024 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1026 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYB
;
1028 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYA
;
1030 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1032 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYD
;
1034 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYC
;
1036 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1038 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYF
;
1040 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYE
;
1042 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1043 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYG
;
1047 args
.v5
.ucLaneNum
= dp_lane_count
;
1048 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
1049 args
.v5
.ucLaneNum
= 8;
1051 args
.v5
.ucLaneNum
= 4;
1052 args
.v5
.ucConnObjId
= connector_object_id
;
1053 args
.v5
.ucDigMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1055 if (is_dp
&& adev
->clock
.dp_extclk
)
1056 args
.v5
.asConfig
.ucPhyClkSrcId
= ENCODER_REFCLK_SRC_EXTCLK
;
1058 args
.v5
.asConfig
.ucPhyClkSrcId
= pll_id
;
1061 args
.v5
.asConfig
.ucCoherentMode
= 1; /* DP requires coherent */
1062 else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1063 if (dig
->coherent_mode
)
1064 args
.v5
.asConfig
.ucCoherentMode
= 1;
1066 if (hpd_id
== AMDGPU_HPD_NONE
)
1067 args
.v5
.asConfig
.ucHPDSel
= 0;
1069 args
.v5
.asConfig
.ucHPDSel
= hpd_id
+ 1;
1070 args
.v5
.ucDigEncoderSel
= 1 << dig_encoder
;
1071 args
.v5
.ucDPLaneSet
= lane_set
;
1074 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1079 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1083 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1087 amdgpu_atombios_encoder_set_edp_panel_power(struct drm_connector
*connector
,
1090 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
1091 struct drm_device
*dev
= amdgpu_connector
->base
.dev
;
1092 struct amdgpu_device
*adev
= dev
->dev_private
;
1093 union dig_transmitter_control args
;
1094 int index
= GetIndexIntoMasterTable(COMMAND
, UNIPHYTransmitterControl
);
1097 if (connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
1100 if ((action
!= ATOM_TRANSMITTER_ACTION_POWER_ON
) &&
1101 (action
!= ATOM_TRANSMITTER_ACTION_POWER_OFF
))
1104 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1107 memset(&args
, 0, sizeof(args
));
1109 args
.v1
.ucAction
= action
;
1111 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1113 /* wait for the panel to power up */
1114 if (action
== ATOM_TRANSMITTER_ACTION_POWER_ON
) {
1117 for (i
= 0; i
< 300; i
++) {
1118 if (amdgpu_display_hpd_sense(adev
, amdgpu_connector
->hpd
.hpd
))
1128 union external_encoder_control
{
1129 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1
;
1130 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3
;
1134 amdgpu_atombios_encoder_setup_external_encoder(struct drm_encoder
*encoder
,
1135 struct drm_encoder
*ext_encoder
,
1138 struct drm_device
*dev
= encoder
->dev
;
1139 struct amdgpu_device
*adev
= dev
->dev_private
;
1140 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1141 struct amdgpu_encoder
*ext_amdgpu_encoder
= to_amdgpu_encoder(ext_encoder
);
1142 union external_encoder_control args
;
1143 struct drm_connector
*connector
;
1144 int index
= GetIndexIntoMasterTable(COMMAND
, ExternalEncoderControl
);
1147 int dp_lane_count
= 0;
1148 int connector_object_id
= 0;
1149 u32 ext_enum
= (ext_amdgpu_encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
1151 if (action
== EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
)
1152 connector
= amdgpu_get_connector_for_encoder_init(encoder
);
1154 connector
= amdgpu_get_connector_for_encoder(encoder
);
1157 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
1158 struct amdgpu_connector_atom_dig
*dig_connector
=
1159 amdgpu_connector
->con_priv
;
1161 dp_clock
= dig_connector
->dp_clock
;
1162 dp_lane_count
= dig_connector
->dp_lane_count
;
1163 connector_object_id
=
1164 (amdgpu_connector
->connector_object_id
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
1167 memset(&args
, 0, sizeof(args
));
1169 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1174 /* no params on frev 1 */
1180 args
.v1
.sDigEncoder
.ucAction
= action
;
1181 args
.v1
.sDigEncoder
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
1182 args
.v1
.sDigEncoder
.ucEncoderMode
=
1183 amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1185 if (ENCODER_MODE_IS_DP(args
.v1
.sDigEncoder
.ucEncoderMode
)) {
1186 if (dp_clock
== 270000)
1187 args
.v1
.sDigEncoder
.ucConfig
|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ
;
1188 args
.v1
.sDigEncoder
.ucLaneNum
= dp_lane_count
;
1189 } else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
1190 args
.v1
.sDigEncoder
.ucLaneNum
= 8;
1192 args
.v1
.sDigEncoder
.ucLaneNum
= 4;
1195 args
.v3
.sExtEncoder
.ucAction
= action
;
1196 if (action
== EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
)
1197 args
.v3
.sExtEncoder
.usConnectorId
= cpu_to_le16(connector_object_id
);
1199 args
.v3
.sExtEncoder
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
1200 args
.v3
.sExtEncoder
.ucEncoderMode
=
1201 amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1203 if (ENCODER_MODE_IS_DP(args
.v3
.sExtEncoder
.ucEncoderMode
)) {
1204 if (dp_clock
== 270000)
1205 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ
;
1206 else if (dp_clock
== 540000)
1207 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ
;
1208 args
.v3
.sExtEncoder
.ucLaneNum
= dp_lane_count
;
1209 } else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
1210 args
.v3
.sExtEncoder
.ucLaneNum
= 8;
1212 args
.v3
.sExtEncoder
.ucLaneNum
= 4;
1214 case GRAPH_OBJECT_ENUM_ID1
:
1215 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1
;
1217 case GRAPH_OBJECT_ENUM_ID2
:
1218 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2
;
1220 case GRAPH_OBJECT_ENUM_ID3
:
1221 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3
;
1224 args
.v3
.sExtEncoder
.ucBitPerColor
= amdgpu_atombios_encoder_get_bpc(encoder
);
1227 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1232 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1235 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1239 amdgpu_atombios_encoder_setup_dig(struct drm_encoder
*encoder
, int action
)
1241 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1242 struct drm_encoder
*ext_encoder
= amdgpu_get_external_encoder(encoder
);
1243 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1244 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
1245 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1246 struct amdgpu_connector_atom_dig
*amdgpu_dig_connector
= NULL
;
1249 amdgpu_connector
= to_amdgpu_connector(connector
);
1250 amdgpu_dig_connector
= amdgpu_connector
->con_priv
;
1253 if (action
== ATOM_ENABLE
) {
1255 dig
->panel_mode
= DP_PANEL_MODE_EXTERNAL_DP_MODE
;
1257 dig
->panel_mode
= amdgpu_atombios_dp_get_panel_mode(encoder
, connector
);
1259 /* setup and enable the encoder */
1260 amdgpu_atombios_encoder_setup_dig_encoder(encoder
, ATOM_ENCODER_CMD_SETUP
, 0);
1261 amdgpu_atombios_encoder_setup_dig_encoder(encoder
,
1262 ATOM_ENCODER_CMD_SETUP_PANEL_MODE
,
1265 amdgpu_atombios_encoder_setup_external_encoder(encoder
, ext_encoder
,
1266 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP
);
1267 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder
)) &&
1269 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) {
1270 amdgpu_atombios_encoder_set_edp_panel_power(connector
,
1271 ATOM_TRANSMITTER_ACTION_POWER_ON
);
1272 amdgpu_dig_connector
->edp_on
= true;
1275 /* enable the transmitter */
1276 amdgpu_atombios_encoder_setup_dig_transmitter(encoder
,
1277 ATOM_TRANSMITTER_ACTION_ENABLE
,
1279 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder
)) &&
1281 /* DP_SET_POWER_D0 is set in amdgpu_atombios_dp_link_train */
1282 amdgpu_atombios_dp_link_train(encoder
, connector
);
1283 amdgpu_atombios_encoder_setup_dig_encoder(encoder
, ATOM_ENCODER_CMD_DP_VIDEO_ON
, 0);
1285 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1286 amdgpu_atombios_encoder_set_backlight_level(amdgpu_encoder
, dig
->backlight_level
);
1288 amdgpu_atombios_encoder_setup_external_encoder(encoder
, ext_encoder
, ATOM_ENABLE
);
1290 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder
)) &&
1292 amdgpu_atombios_encoder_setup_dig_encoder(encoder
,
1293 ATOM_ENCODER_CMD_DP_VIDEO_OFF
, 0);
1295 amdgpu_atombios_encoder_setup_external_encoder(encoder
, ext_encoder
, ATOM_DISABLE
);
1296 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1297 amdgpu_atombios_encoder_setup_dig_transmitter(encoder
,
1298 ATOM_TRANSMITTER_ACTION_LCD_BLOFF
, 0, 0);
1300 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder
)) &&
1302 amdgpu_atombios_dp_set_rx_power_state(connector
, DP_SET_POWER_D3
);
1303 /* disable the transmitter */
1304 amdgpu_atombios_encoder_setup_dig_transmitter(encoder
,
1305 ATOM_TRANSMITTER_ACTION_DISABLE
, 0, 0);
1306 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder
)) &&
1308 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) {
1309 amdgpu_atombios_encoder_set_edp_panel_power(connector
,
1310 ATOM_TRANSMITTER_ACTION_POWER_OFF
);
1311 amdgpu_dig_connector
->edp_on
= false;
1318 amdgpu_atombios_encoder_dpms(struct drm_encoder
*encoder
, int mode
)
1320 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1322 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1323 amdgpu_encoder
->encoder_id
, mode
, amdgpu_encoder
->devices
,
1324 amdgpu_encoder
->active_device
);
1325 switch (amdgpu_encoder
->encoder_id
) {
1326 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1327 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1328 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1329 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1331 case DRM_MODE_DPMS_ON
:
1332 amdgpu_atombios_encoder_setup_dig(encoder
, ATOM_ENABLE
);
1334 case DRM_MODE_DPMS_STANDBY
:
1335 case DRM_MODE_DPMS_SUSPEND
:
1336 case DRM_MODE_DPMS_OFF
:
1337 amdgpu_atombios_encoder_setup_dig(encoder
, ATOM_DISABLE
);
1341 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1343 case DRM_MODE_DPMS_ON
:
1344 amdgpu_atombios_encoder_setup_dvo(encoder
, ATOM_ENABLE
);
1346 case DRM_MODE_DPMS_STANDBY
:
1347 case DRM_MODE_DPMS_SUSPEND
:
1348 case DRM_MODE_DPMS_OFF
:
1349 amdgpu_atombios_encoder_setup_dvo(encoder
, ATOM_DISABLE
);
1353 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1355 case DRM_MODE_DPMS_ON
:
1356 amdgpu_atombios_encoder_setup_dac(encoder
, ATOM_ENABLE
);
1358 case DRM_MODE_DPMS_STANDBY
:
1359 case DRM_MODE_DPMS_SUSPEND
:
1360 case DRM_MODE_DPMS_OFF
:
1361 amdgpu_atombios_encoder_setup_dac(encoder
, ATOM_DISABLE
);
1370 union crtc_source_param
{
1371 SELECT_CRTC_SOURCE_PS_ALLOCATION v1
;
1372 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2
;
1373 SELECT_CRTC_SOURCE_PARAMETERS_V3 v3
;
1377 amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder
*encoder
)
1379 struct drm_device
*dev
= encoder
->dev
;
1380 struct amdgpu_device
*adev
= dev
->dev_private
;
1381 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1382 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
1383 union crtc_source_param args
;
1384 int index
= GetIndexIntoMasterTable(COMMAND
, SelectCRTC_Source
);
1386 struct amdgpu_encoder_atom_dig
*dig
;
1388 memset(&args
, 0, sizeof(args
));
1390 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1398 args
.v1
.ucCRTC
= amdgpu_crtc
->crtc_id
;
1399 switch (amdgpu_encoder
->encoder_id
) {
1400 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1401 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1402 args
.v1
.ucDevice
= ATOM_DEVICE_DFP1_INDEX
;
1404 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1405 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1406 if (amdgpu_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)
1407 args
.v1
.ucDevice
= ATOM_DEVICE_LCD1_INDEX
;
1409 args
.v1
.ucDevice
= ATOM_DEVICE_DFP3_INDEX
;
1411 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1412 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1413 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1414 args
.v1
.ucDevice
= ATOM_DEVICE_DFP2_INDEX
;
1416 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1417 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1418 if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1419 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1420 else if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1421 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1423 args
.v1
.ucDevice
= ATOM_DEVICE_CRT1_INDEX
;
1425 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1426 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1427 if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1428 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1429 else if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1430 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1432 args
.v1
.ucDevice
= ATOM_DEVICE_CRT2_INDEX
;
1437 args
.v2
.ucCRTC
= amdgpu_crtc
->crtc_id
;
1438 if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
) {
1439 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
1441 if (connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
)
1442 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_LVDS
;
1443 else if (connector
->connector_type
== DRM_MODE_CONNECTOR_VGA
)
1444 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_CRT
;
1446 args
.v2
.ucEncodeMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1447 } else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1448 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_LVDS
;
1450 args
.v2
.ucEncodeMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1452 switch (amdgpu_encoder
->encoder_id
) {
1453 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1454 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1455 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1456 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1457 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1458 dig
= amdgpu_encoder
->enc_priv
;
1459 switch (dig
->dig_encoder
) {
1461 args
.v2
.ucEncoderID
= ASIC_INT_DIG1_ENCODER_ID
;
1464 args
.v2
.ucEncoderID
= ASIC_INT_DIG2_ENCODER_ID
;
1467 args
.v2
.ucEncoderID
= ASIC_INT_DIG3_ENCODER_ID
;
1470 args
.v2
.ucEncoderID
= ASIC_INT_DIG4_ENCODER_ID
;
1473 args
.v2
.ucEncoderID
= ASIC_INT_DIG5_ENCODER_ID
;
1476 args
.v2
.ucEncoderID
= ASIC_INT_DIG6_ENCODER_ID
;
1479 args
.v2
.ucEncoderID
= ASIC_INT_DIG7_ENCODER_ID
;
1483 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1484 args
.v2
.ucEncoderID
= ASIC_INT_DVO_ENCODER_ID
;
1486 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1487 if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1488 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1489 else if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1490 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1492 args
.v2
.ucEncoderID
= ASIC_INT_DAC1_ENCODER_ID
;
1494 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1495 if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1496 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1497 else if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1498 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1500 args
.v2
.ucEncoderID
= ASIC_INT_DAC2_ENCODER_ID
;
1505 args
.v3
.ucCRTC
= amdgpu_crtc
->crtc_id
;
1506 if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
) {
1507 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
1509 if (connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
)
1510 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_LVDS
;
1511 else if (connector
->connector_type
== DRM_MODE_CONNECTOR_VGA
)
1512 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_CRT
;
1514 args
.v2
.ucEncodeMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1515 } else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1516 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_LVDS
;
1518 args
.v2
.ucEncodeMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1520 args
.v3
.ucDstBpc
= amdgpu_atombios_encoder_get_bpc(encoder
);
1521 switch (amdgpu_encoder
->encoder_id
) {
1522 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1523 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1524 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1525 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1526 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1527 dig
= amdgpu_encoder
->enc_priv
;
1528 switch (dig
->dig_encoder
) {
1530 args
.v3
.ucEncoderID
= ASIC_INT_DIG1_ENCODER_ID
;
1533 args
.v3
.ucEncoderID
= ASIC_INT_DIG2_ENCODER_ID
;
1536 args
.v3
.ucEncoderID
= ASIC_INT_DIG3_ENCODER_ID
;
1539 args
.v3
.ucEncoderID
= ASIC_INT_DIG4_ENCODER_ID
;
1542 args
.v3
.ucEncoderID
= ASIC_INT_DIG5_ENCODER_ID
;
1545 args
.v3
.ucEncoderID
= ASIC_INT_DIG6_ENCODER_ID
;
1548 args
.v3
.ucEncoderID
= ASIC_INT_DIG7_ENCODER_ID
;
1552 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1553 args
.v3
.ucEncoderID
= ASIC_INT_DVO_ENCODER_ID
;
1555 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1556 if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1557 args
.v3
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1558 else if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1559 args
.v3
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1561 args
.v3
.ucEncoderID
= ASIC_INT_DAC1_ENCODER_ID
;
1563 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1564 if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1565 args
.v3
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1566 else if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1567 args
.v3
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1569 args
.v3
.ucEncoderID
= ASIC_INT_DAC2_ENCODER_ID
;
1576 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1580 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1583 /* This only needs to be called once at startup */
1585 amdgpu_atombios_encoder_init_dig(struct amdgpu_device
*adev
)
1587 struct drm_device
*dev
= adev
->ddev
;
1588 struct drm_encoder
*encoder
;
1590 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
1591 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1592 struct drm_encoder
*ext_encoder
= amdgpu_get_external_encoder(encoder
);
1594 switch (amdgpu_encoder
->encoder_id
) {
1595 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1596 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1597 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1598 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1599 amdgpu_atombios_encoder_setup_dig_transmitter(encoder
, ATOM_TRANSMITTER_ACTION_INIT
,
1605 amdgpu_atombios_encoder_setup_external_encoder(encoder
, ext_encoder
,
1606 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
);
1611 amdgpu_atombios_encoder_dac_load_detect(struct drm_encoder
*encoder
,
1612 struct drm_connector
*connector
)
1614 struct drm_device
*dev
= encoder
->dev
;
1615 struct amdgpu_device
*adev
= dev
->dev_private
;
1616 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1617 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
1619 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
|
1620 ATOM_DEVICE_CV_SUPPORT
|
1621 ATOM_DEVICE_CRT_SUPPORT
)) {
1622 DAC_LOAD_DETECTION_PS_ALLOCATION args
;
1623 int index
= GetIndexIntoMasterTable(COMMAND
, DAC_LoadDetection
);
1626 memset(&args
, 0, sizeof(args
));
1628 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1631 args
.sDacload
.ucMisc
= 0;
1633 if ((amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DAC1
) ||
1634 (amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
))
1635 args
.sDacload
.ucDacType
= ATOM_DAC_A
;
1637 args
.sDacload
.ucDacType
= ATOM_DAC_B
;
1639 if (amdgpu_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)
1640 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT
);
1641 else if (amdgpu_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)
1642 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT
);
1643 else if (amdgpu_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1644 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CV_SUPPORT
);
1646 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
1647 } else if (amdgpu_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1648 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT
);
1650 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
1653 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1660 enum drm_connector_status
1661 amdgpu_atombios_encoder_dac_detect(struct drm_encoder
*encoder
,
1662 struct drm_connector
*connector
)
1664 struct drm_device
*dev
= encoder
->dev
;
1665 struct amdgpu_device
*adev
= dev
->dev_private
;
1666 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1667 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
1668 uint32_t bios_0_scratch
;
1670 if (!amdgpu_atombios_encoder_dac_load_detect(encoder
, connector
)) {
1671 DRM_DEBUG_KMS("detect returned false \n");
1672 return connector_status_unknown
;
1675 bios_0_scratch
= RREG32(mmBIOS_SCRATCH_0
);
1677 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch
, amdgpu_encoder
->devices
);
1678 if (amdgpu_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
1679 if (bios_0_scratch
& ATOM_S0_CRT1_MASK
)
1680 return connector_status_connected
;
1682 if (amdgpu_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
1683 if (bios_0_scratch
& ATOM_S0_CRT2_MASK
)
1684 return connector_status_connected
;
1686 if (amdgpu_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1687 if (bios_0_scratch
& (ATOM_S0_CV_MASK
|ATOM_S0_CV_MASK_A
))
1688 return connector_status_connected
;
1690 if (amdgpu_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1691 if (bios_0_scratch
& (ATOM_S0_TV1_COMPOSITE
| ATOM_S0_TV1_COMPOSITE_A
))
1692 return connector_status_connected
; /* CTV */
1693 else if (bios_0_scratch
& (ATOM_S0_TV1_SVIDEO
| ATOM_S0_TV1_SVIDEO_A
))
1694 return connector_status_connected
; /* STV */
1696 return connector_status_disconnected
;
1699 enum drm_connector_status
1700 amdgpu_atombios_encoder_dig_detect(struct drm_encoder
*encoder
,
1701 struct drm_connector
*connector
)
1703 struct drm_device
*dev
= encoder
->dev
;
1704 struct amdgpu_device
*adev
= dev
->dev_private
;
1705 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1706 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
1707 struct drm_encoder
*ext_encoder
= amdgpu_get_external_encoder(encoder
);
1711 return connector_status_unknown
;
1713 if ((amdgpu_connector
->devices
& ATOM_DEVICE_CRT_SUPPORT
) == 0)
1714 return connector_status_unknown
;
1716 /* load detect on the dp bridge */
1717 amdgpu_atombios_encoder_setup_external_encoder(encoder
, ext_encoder
,
1718 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION
);
1720 bios_0_scratch
= RREG32(mmBIOS_SCRATCH_0
);
1722 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch
, amdgpu_encoder
->devices
);
1723 if (amdgpu_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
1724 if (bios_0_scratch
& ATOM_S0_CRT1_MASK
)
1725 return connector_status_connected
;
1727 if (amdgpu_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
1728 if (bios_0_scratch
& ATOM_S0_CRT2_MASK
)
1729 return connector_status_connected
;
1731 if (amdgpu_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1732 if (bios_0_scratch
& (ATOM_S0_CV_MASK
|ATOM_S0_CV_MASK_A
))
1733 return connector_status_connected
;
1735 if (amdgpu_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1736 if (bios_0_scratch
& (ATOM_S0_TV1_COMPOSITE
| ATOM_S0_TV1_COMPOSITE_A
))
1737 return connector_status_connected
; /* CTV */
1738 else if (bios_0_scratch
& (ATOM_S0_TV1_SVIDEO
| ATOM_S0_TV1_SVIDEO_A
))
1739 return connector_status_connected
; /* STV */
1741 return connector_status_disconnected
;
1745 amdgpu_atombios_encoder_setup_ext_encoder_ddc(struct drm_encoder
*encoder
)
1747 struct drm_encoder
*ext_encoder
= amdgpu_get_external_encoder(encoder
);
1750 /* ddc_setup on the dp bridge */
1751 amdgpu_atombios_encoder_setup_external_encoder(encoder
, ext_encoder
,
1752 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP
);
1757 amdgpu_atombios_encoder_set_bios_scratch_regs(struct drm_connector
*connector
,
1758 struct drm_encoder
*encoder
,
1761 struct drm_device
*dev
= connector
->dev
;
1762 struct amdgpu_device
*adev
= dev
->dev_private
;
1763 struct amdgpu_connector
*amdgpu_connector
=
1764 to_amdgpu_connector(connector
);
1765 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1766 uint32_t bios_0_scratch
, bios_3_scratch
, bios_6_scratch
;
1768 bios_0_scratch
= RREG32(mmBIOS_SCRATCH_0
);
1769 bios_3_scratch
= RREG32(mmBIOS_SCRATCH_3
);
1770 bios_6_scratch
= RREG32(mmBIOS_SCRATCH_6
);
1772 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) &&
1773 (amdgpu_connector
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)) {
1775 DRM_DEBUG_KMS("LCD1 connected\n");
1776 bios_0_scratch
|= ATOM_S0_LCD1
;
1777 bios_3_scratch
|= ATOM_S3_LCD1_ACTIVE
;
1778 bios_6_scratch
|= ATOM_S6_ACC_REQ_LCD1
;
1780 DRM_DEBUG_KMS("LCD1 disconnected\n");
1781 bios_0_scratch
&= ~ATOM_S0_LCD1
;
1782 bios_3_scratch
&= ~ATOM_S3_LCD1_ACTIVE
;
1783 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_LCD1
;
1786 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) &&
1787 (amdgpu_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)) {
1789 DRM_DEBUG_KMS("CRT1 connected\n");
1790 bios_0_scratch
|= ATOM_S0_CRT1_COLOR
;
1791 bios_3_scratch
|= ATOM_S3_CRT1_ACTIVE
;
1792 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT1
;
1794 DRM_DEBUG_KMS("CRT1 disconnected\n");
1795 bios_0_scratch
&= ~ATOM_S0_CRT1_MASK
;
1796 bios_3_scratch
&= ~ATOM_S3_CRT1_ACTIVE
;
1797 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT1
;
1800 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) &&
1801 (amdgpu_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)) {
1803 DRM_DEBUG_KMS("CRT2 connected\n");
1804 bios_0_scratch
|= ATOM_S0_CRT2_COLOR
;
1805 bios_3_scratch
|= ATOM_S3_CRT2_ACTIVE
;
1806 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT2
;
1808 DRM_DEBUG_KMS("CRT2 disconnected\n");
1809 bios_0_scratch
&= ~ATOM_S0_CRT2_MASK
;
1810 bios_3_scratch
&= ~ATOM_S3_CRT2_ACTIVE
;
1811 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT2
;
1814 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) &&
1815 (amdgpu_connector
->devices
& ATOM_DEVICE_DFP1_SUPPORT
)) {
1817 DRM_DEBUG_KMS("DFP1 connected\n");
1818 bios_0_scratch
|= ATOM_S0_DFP1
;
1819 bios_3_scratch
|= ATOM_S3_DFP1_ACTIVE
;
1820 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP1
;
1822 DRM_DEBUG_KMS("DFP1 disconnected\n");
1823 bios_0_scratch
&= ~ATOM_S0_DFP1
;
1824 bios_3_scratch
&= ~ATOM_S3_DFP1_ACTIVE
;
1825 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP1
;
1828 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) &&
1829 (amdgpu_connector
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
1831 DRM_DEBUG_KMS("DFP2 connected\n");
1832 bios_0_scratch
|= ATOM_S0_DFP2
;
1833 bios_3_scratch
|= ATOM_S3_DFP2_ACTIVE
;
1834 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP2
;
1836 DRM_DEBUG_KMS("DFP2 disconnected\n");
1837 bios_0_scratch
&= ~ATOM_S0_DFP2
;
1838 bios_3_scratch
&= ~ATOM_S3_DFP2_ACTIVE
;
1839 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP2
;
1842 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) &&
1843 (amdgpu_connector
->devices
& ATOM_DEVICE_DFP3_SUPPORT
)) {
1845 DRM_DEBUG_KMS("DFP3 connected\n");
1846 bios_0_scratch
|= ATOM_S0_DFP3
;
1847 bios_3_scratch
|= ATOM_S3_DFP3_ACTIVE
;
1848 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP3
;
1850 DRM_DEBUG_KMS("DFP3 disconnected\n");
1851 bios_0_scratch
&= ~ATOM_S0_DFP3
;
1852 bios_3_scratch
&= ~ATOM_S3_DFP3_ACTIVE
;
1853 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP3
;
1856 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) &&
1857 (amdgpu_connector
->devices
& ATOM_DEVICE_DFP4_SUPPORT
)) {
1859 DRM_DEBUG_KMS("DFP4 connected\n");
1860 bios_0_scratch
|= ATOM_S0_DFP4
;
1861 bios_3_scratch
|= ATOM_S3_DFP4_ACTIVE
;
1862 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP4
;
1864 DRM_DEBUG_KMS("DFP4 disconnected\n");
1865 bios_0_scratch
&= ~ATOM_S0_DFP4
;
1866 bios_3_scratch
&= ~ATOM_S3_DFP4_ACTIVE
;
1867 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP4
;
1870 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) &&
1871 (amdgpu_connector
->devices
& ATOM_DEVICE_DFP5_SUPPORT
)) {
1873 DRM_DEBUG_KMS("DFP5 connected\n");
1874 bios_0_scratch
|= ATOM_S0_DFP5
;
1875 bios_3_scratch
|= ATOM_S3_DFP5_ACTIVE
;
1876 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP5
;
1878 DRM_DEBUG_KMS("DFP5 disconnected\n");
1879 bios_0_scratch
&= ~ATOM_S0_DFP5
;
1880 bios_3_scratch
&= ~ATOM_S3_DFP5_ACTIVE
;
1881 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP5
;
1884 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_DFP6_SUPPORT
) &&
1885 (amdgpu_connector
->devices
& ATOM_DEVICE_DFP6_SUPPORT
)) {
1887 DRM_DEBUG_KMS("DFP6 connected\n");
1888 bios_0_scratch
|= ATOM_S0_DFP6
;
1889 bios_3_scratch
|= ATOM_S3_DFP6_ACTIVE
;
1890 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP6
;
1892 DRM_DEBUG_KMS("DFP6 disconnected\n");
1893 bios_0_scratch
&= ~ATOM_S0_DFP6
;
1894 bios_3_scratch
&= ~ATOM_S3_DFP6_ACTIVE
;
1895 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP6
;
1899 WREG32(mmBIOS_SCRATCH_0
, bios_0_scratch
);
1900 WREG32(mmBIOS_SCRATCH_3
, bios_3_scratch
);
1901 WREG32(mmBIOS_SCRATCH_6
, bios_6_scratch
);
1905 struct _ATOM_LVDS_INFO info
;
1906 struct _ATOM_LVDS_INFO_V12 info_12
;
1909 struct amdgpu_encoder_atom_dig
*
1910 amdgpu_atombios_encoder_get_lcd_info(struct amdgpu_encoder
*encoder
)
1912 struct drm_device
*dev
= encoder
->base
.dev
;
1913 struct amdgpu_device
*adev
= dev
->dev_private
;
1914 struct amdgpu_mode_info
*mode_info
= &adev
->mode_info
;
1915 int index
= GetIndexIntoMasterTable(DATA
, LVDS_Info
);
1916 uint16_t data_offset
, misc
;
1917 union lvds_info
*lvds_info
;
1919 struct amdgpu_encoder_atom_dig
*lvds
= NULL
;
1920 int encoder_enum
= (encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
1922 if (amdgpu_atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1923 &frev
, &crev
, &data_offset
)) {
1925 (union lvds_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
1927 kzalloc(sizeof(struct amdgpu_encoder_atom_dig
), GFP_KERNEL
);
1932 lvds
->native_mode
.clock
=
1933 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usPixClk
) * 10;
1934 lvds
->native_mode
.hdisplay
=
1935 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHActive
);
1936 lvds
->native_mode
.vdisplay
=
1937 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVActive
);
1938 lvds
->native_mode
.htotal
= lvds
->native_mode
.hdisplay
+
1939 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHBlanking_Time
);
1940 lvds
->native_mode
.hsync_start
= lvds
->native_mode
.hdisplay
+
1941 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncOffset
);
1942 lvds
->native_mode
.hsync_end
= lvds
->native_mode
.hsync_start
+
1943 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncWidth
);
1944 lvds
->native_mode
.vtotal
= lvds
->native_mode
.vdisplay
+
1945 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVBlanking_Time
);
1946 lvds
->native_mode
.vsync_start
= lvds
->native_mode
.vdisplay
+
1947 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncOffset
);
1948 lvds
->native_mode
.vsync_end
= lvds
->native_mode
.vsync_start
+
1949 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncWidth
);
1950 lvds
->panel_pwr_delay
=
1951 le16_to_cpu(lvds_info
->info
.usOffDelayInMs
);
1952 lvds
->lcd_misc
= lvds_info
->info
.ucLVDS_Misc
;
1954 misc
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.susModeMiscInfo
.usAccess
);
1955 if (misc
& ATOM_VSYNC_POLARITY
)
1956 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
1957 if (misc
& ATOM_HSYNC_POLARITY
)
1958 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
1959 if (misc
& ATOM_COMPOSITESYNC
)
1960 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_CSYNC
;
1961 if (misc
& ATOM_INTERLACE
)
1962 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
1963 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1964 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_DBLSCAN
;
1966 lvds
->native_mode
.width_mm
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.usImageHSize
);
1967 lvds
->native_mode
.height_mm
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.usImageVSize
);
1969 /* set crtc values */
1970 drm_mode_set_crtcinfo(&lvds
->native_mode
, CRTC_INTERLACE_HALVE_V
);
1972 lvds
->lcd_ss_id
= lvds_info
->info
.ucSS_Id
;
1974 encoder
->native_mode
= lvds
->native_mode
;
1976 if (encoder_enum
== 2)
1979 lvds
->linkb
= false;
1981 /* parse the lcd record table */
1982 if (le16_to_cpu(lvds_info
->info
.usModePatchTableOffset
)) {
1983 ATOM_FAKE_EDID_PATCH_RECORD
*fake_edid_record
;
1984 ATOM_PANEL_RESOLUTION_PATCH_RECORD
*panel_res_record
;
1985 bool bad_record
= false;
1988 if ((frev
== 1) && (crev
< 2))
1990 record
= (u8
*)(mode_info
->atom_context
->bios
+
1991 le16_to_cpu(lvds_info
->info
.usModePatchTableOffset
));
1994 record
= (u8
*)(mode_info
->atom_context
->bios
+
1996 le16_to_cpu(lvds_info
->info
.usModePatchTableOffset
));
1997 while (*record
!= ATOM_RECORD_END_TYPE
) {
1999 case LCD_MODE_PATCH_RECORD_MODE_TYPE
:
2000 record
+= sizeof(ATOM_PATCH_RECORD_MODE
);
2002 case LCD_RTS_RECORD_TYPE
:
2003 record
+= sizeof(ATOM_LCD_RTS_RECORD
);
2005 case LCD_CAP_RECORD_TYPE
:
2006 record
+= sizeof(ATOM_LCD_MODE_CONTROL_CAP
);
2008 case LCD_FAKE_EDID_PATCH_RECORD_TYPE
:
2009 fake_edid_record
= (ATOM_FAKE_EDID_PATCH_RECORD
*)record
;
2010 if (fake_edid_record
->ucFakeEDIDLength
) {
2013 max((int)EDID_LENGTH
, (int)fake_edid_record
->ucFakeEDIDLength
);
2014 edid
= kmalloc(edid_size
, GFP_KERNEL
);
2016 memcpy((u8
*)edid
, (u8
*)&fake_edid_record
->ucFakeEDIDString
[0],
2017 fake_edid_record
->ucFakeEDIDLength
);
2019 if (drm_edid_is_valid(edid
)) {
2020 adev
->mode_info
.bios_hardcoded_edid
= edid
;
2021 adev
->mode_info
.bios_hardcoded_edid_size
= edid_size
;
2026 record
+= fake_edid_record
->ucFakeEDIDLength
?
2027 fake_edid_record
->ucFakeEDIDLength
+ 2 :
2028 sizeof(ATOM_FAKE_EDID_PATCH_RECORD
);
2030 case LCD_PANEL_RESOLUTION_RECORD_TYPE
:
2031 panel_res_record
= (ATOM_PANEL_RESOLUTION_PATCH_RECORD
*)record
;
2032 lvds
->native_mode
.width_mm
= panel_res_record
->usHSize
;
2033 lvds
->native_mode
.height_mm
= panel_res_record
->usVSize
;
2034 record
+= sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD
);
2037 DRM_ERROR("Bad LCD record %d\n", *record
);
2049 struct amdgpu_encoder_atom_dig
*
2050 amdgpu_atombios_encoder_get_dig_info(struct amdgpu_encoder
*amdgpu_encoder
)
2052 int encoder_enum
= (amdgpu_encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
2053 struct amdgpu_encoder_atom_dig
*dig
= kzalloc(sizeof(struct amdgpu_encoder_atom_dig
), GFP_KERNEL
);
2058 /* coherent mode by default */
2059 dig
->coherent_mode
= true;
2060 dig
->dig_encoder
= -1;
2062 if (encoder_enum
== 2)