2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/amdgpu_drm.h>
30 #include "amdgpu_connectors.h"
32 #include "atombios_encoders.h"
33 #include "atombios_dp.h"
34 #include <linux/backlight.h>
35 #include "bif/bif_4_1_d.h"
38 amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device
*adev
)
43 bios_2_scratch
= RREG32(mmBIOS_SCRATCH_2
);
45 backlight_level
= ((bios_2_scratch
& ATOM_S2_CURRENT_BL_LEVEL_MASK
) >>
46 ATOM_S2_CURRENT_BL_LEVEL_SHIFT
);
48 return backlight_level
;
52 amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device
*adev
,
57 bios_2_scratch
= RREG32(mmBIOS_SCRATCH_2
);
59 bios_2_scratch
&= ~ATOM_S2_CURRENT_BL_LEVEL_MASK
;
60 bios_2_scratch
|= ((backlight_level
<< ATOM_S2_CURRENT_BL_LEVEL_SHIFT
) &
61 ATOM_S2_CURRENT_BL_LEVEL_MASK
);
63 WREG32(mmBIOS_SCRATCH_2
, bios_2_scratch
);
67 amdgpu_atombios_encoder_get_backlight_level(struct amdgpu_encoder
*amdgpu_encoder
)
69 struct drm_device
*dev
= amdgpu_encoder
->base
.dev
;
70 struct amdgpu_device
*adev
= dev
->dev_private
;
72 if (!(adev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
75 return amdgpu_atombios_encoder_get_backlight_level_from_reg(adev
);
79 amdgpu_atombios_encoder_set_backlight_level(struct amdgpu_encoder
*amdgpu_encoder
,
82 struct drm_encoder
*encoder
= &amdgpu_encoder
->base
;
83 struct drm_device
*dev
= amdgpu_encoder
->base
.dev
;
84 struct amdgpu_device
*adev
= dev
->dev_private
;
85 struct amdgpu_encoder_atom_dig
*dig
;
87 if (!(adev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
90 if ((amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) &&
91 amdgpu_encoder
->enc_priv
) {
92 dig
= amdgpu_encoder
->enc_priv
;
93 dig
->backlight_level
= level
;
94 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev
, dig
->backlight_level
);
96 switch (amdgpu_encoder
->encoder_id
) {
97 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
98 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
99 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
100 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
101 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
102 if (dig
->backlight_level
== 0)
103 amdgpu_atombios_encoder_setup_dig_transmitter(encoder
,
104 ATOM_TRANSMITTER_ACTION_LCD_BLOFF
, 0, 0);
106 amdgpu_atombios_encoder_setup_dig_transmitter(encoder
,
107 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL
, 0, 0);
108 amdgpu_atombios_encoder_setup_dig_transmitter(encoder
,
109 ATOM_TRANSMITTER_ACTION_LCD_BLON
, 0, 0);
118 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
120 static u8
amdgpu_atombios_encoder_backlight_level(struct backlight_device
*bd
)
124 /* Convert brightness to hardware level */
125 if (bd
->props
.brightness
< 0)
127 else if (bd
->props
.brightness
> AMDGPU_MAX_BL_LEVEL
)
128 level
= AMDGPU_MAX_BL_LEVEL
;
130 level
= bd
->props
.brightness
;
135 static int amdgpu_atombios_encoder_update_backlight_status(struct backlight_device
*bd
)
137 struct amdgpu_backlight_privdata
*pdata
= bl_get_data(bd
);
138 struct amdgpu_encoder
*amdgpu_encoder
= pdata
->encoder
;
140 amdgpu_atombios_encoder_set_backlight_level(amdgpu_encoder
,
141 amdgpu_atombios_encoder_backlight_level(bd
));
147 amdgpu_atombios_encoder_get_backlight_brightness(struct backlight_device
*bd
)
149 struct amdgpu_backlight_privdata
*pdata
= bl_get_data(bd
);
150 struct amdgpu_encoder
*amdgpu_encoder
= pdata
->encoder
;
151 struct drm_device
*dev
= amdgpu_encoder
->base
.dev
;
152 struct amdgpu_device
*adev
= dev
->dev_private
;
154 return amdgpu_atombios_encoder_get_backlight_level_from_reg(adev
);
157 static const struct backlight_ops amdgpu_atombios_encoder_backlight_ops
= {
158 .get_brightness
= amdgpu_atombios_encoder_get_backlight_brightness
,
159 .update_status
= amdgpu_atombios_encoder_update_backlight_status
,
162 void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder
*amdgpu_encoder
,
163 struct drm_connector
*drm_connector
)
165 struct drm_device
*dev
= amdgpu_encoder
->base
.dev
;
166 struct amdgpu_device
*adev
= dev
->dev_private
;
167 struct backlight_device
*bd
;
168 struct backlight_properties props
;
169 struct amdgpu_backlight_privdata
*pdata
;
170 struct amdgpu_encoder_atom_dig
*dig
;
174 /* Mac laptops with multiple GPUs use the gmux driver for backlight
175 * so don't register a backlight device
177 if ((adev
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_APPLE
) &&
178 (adev
->pdev
->device
== 0x6741))
181 if (!amdgpu_encoder
->enc_priv
)
184 if (!(adev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
187 pdata
= kmalloc(sizeof(struct amdgpu_backlight_privdata
), GFP_KERNEL
);
189 DRM_ERROR("Memory allocation failed\n");
193 memset(&props
, 0, sizeof(props
));
194 props
.max_brightness
= AMDGPU_MAX_BL_LEVEL
;
195 props
.type
= BACKLIGHT_RAW
;
196 snprintf(bl_name
, sizeof(bl_name
),
197 "amdgpu_bl%d", dev
->primary
->index
);
198 bd
= backlight_device_register(bl_name
, drm_connector
->kdev
,
199 pdata
, &amdgpu_atombios_encoder_backlight_ops
, &props
);
201 DRM_ERROR("Backlight registration failed\n");
205 pdata
->encoder
= amdgpu_encoder
;
207 backlight_level
= amdgpu_atombios_encoder_get_backlight_level_from_reg(adev
);
209 dig
= amdgpu_encoder
->enc_priv
;
212 bd
->props
.brightness
= amdgpu_atombios_encoder_get_backlight_brightness(bd
);
213 bd
->props
.power
= FB_BLANK_UNBLANK
;
214 backlight_update_status(bd
);
216 DRM_INFO("amdgpu atom DIG backlight initialized\n");
226 amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder
*amdgpu_encoder
)
228 struct drm_device
*dev
= amdgpu_encoder
->base
.dev
;
229 struct amdgpu_device
*adev
= dev
->dev_private
;
230 struct backlight_device
*bd
= NULL
;
231 struct amdgpu_encoder_atom_dig
*dig
;
233 if (!amdgpu_encoder
->enc_priv
)
236 if (!(adev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
239 dig
= amdgpu_encoder
->enc_priv
;
244 struct amdgpu_legacy_backlight_privdata
*pdata
;
246 pdata
= bl_get_data(bd
);
247 backlight_device_unregister(bd
);
250 DRM_INFO("amdgpu atom LVDS backlight unloaded\n");
254 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
256 void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder
*encoder
)
260 void amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder
*encoder
)
266 bool amdgpu_atombios_encoder_is_digital(struct drm_encoder
*encoder
)
268 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
269 switch (amdgpu_encoder
->encoder_id
) {
270 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
271 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
272 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
273 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
274 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
281 bool amdgpu_atombios_encoder_mode_fixup(struct drm_encoder
*encoder
,
282 const struct drm_display_mode
*mode
,
283 struct drm_display_mode
*adjusted_mode
)
285 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
287 /* set the active encoder to connector routing */
288 amdgpu_encoder_set_active_device(encoder
);
289 drm_mode_set_crtcinfo(adjusted_mode
, 0);
292 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
293 && (mode
->crtc_vsync_start
< (mode
->crtc_vdisplay
+ 2)))
294 adjusted_mode
->crtc_vsync_start
= adjusted_mode
->crtc_vdisplay
+ 2;
296 /* vertical FP must be at least 1 */
297 if (mode
->crtc_vsync_start
== mode
->crtc_vdisplay
)
298 adjusted_mode
->crtc_vsync_start
++;
300 /* get the native mode for scaling */
301 if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_LCD_SUPPORT
))
302 amdgpu_panel_mode_fixup(encoder
, adjusted_mode
);
303 else if (amdgpu_encoder
->rmx_type
!= RMX_OFF
)
304 amdgpu_panel_mode_fixup(encoder
, adjusted_mode
);
306 if ((amdgpu_encoder
->active_device
& (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
307 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
)) {
308 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
309 amdgpu_atombios_dp_set_link_config(connector
, adjusted_mode
);
316 amdgpu_atombios_encoder_setup_dac(struct drm_encoder
*encoder
, int action
)
318 struct drm_device
*dev
= encoder
->dev
;
319 struct amdgpu_device
*adev
= dev
->dev_private
;
320 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
321 DAC_ENCODER_CONTROL_PS_ALLOCATION args
;
324 memset(&args
, 0, sizeof(args
));
326 switch (amdgpu_encoder
->encoder_id
) {
327 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
328 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
329 index
= GetIndexIntoMasterTable(COMMAND
, DAC1EncoderControl
);
331 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
332 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
333 index
= GetIndexIntoMasterTable(COMMAND
, DAC2EncoderControl
);
337 args
.ucAction
= action
;
338 args
.ucDacStandard
= ATOM_DAC1_PS2
;
339 args
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
341 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
345 static u8
amdgpu_atombios_encoder_get_bpc(struct drm_encoder
*encoder
)
350 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
351 bpc
= amdgpu_crtc
->bpc
;
356 return PANEL_BPC_UNDEFINE
;
358 return PANEL_6BIT_PER_COLOR
;
361 return PANEL_8BIT_PER_COLOR
;
363 return PANEL_10BIT_PER_COLOR
;
365 return PANEL_12BIT_PER_COLOR
;
367 return PANEL_16BIT_PER_COLOR
;
371 union dvo_encoder_control
{
372 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds
;
373 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo
;
374 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3
;
375 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4
;
379 amdgpu_atombios_encoder_setup_dvo(struct drm_encoder
*encoder
, int action
)
381 struct drm_device
*dev
= encoder
->dev
;
382 struct amdgpu_device
*adev
= dev
->dev_private
;
383 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
384 union dvo_encoder_control args
;
385 int index
= GetIndexIntoMasterTable(COMMAND
, DVOEncoderControl
);
388 memset(&args
, 0, sizeof(args
));
390 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
398 args
.ext_tmds
.sXTmdsEncoder
.ucEnable
= action
;
400 if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
401 args
.ext_tmds
.sXTmdsEncoder
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
403 args
.ext_tmds
.sXTmdsEncoder
.ucMisc
|= ATOM_PANEL_MISC_888RGB
;
407 args
.dvo
.sDVOEncoder
.ucAction
= action
;
408 args
.dvo
.sDVOEncoder
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
409 /* DFP1, CRT1, TV1 depending on the type of port */
410 args
.dvo
.sDVOEncoder
.ucDeviceType
= ATOM_DEVICE_DFP1_INDEX
;
412 if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
413 args
.dvo
.sDVOEncoder
.usDevAttr
.sDigAttrib
.ucAttribute
|= PANEL_ENCODER_MISC_DUAL
;
417 args
.dvo_v3
.ucAction
= action
;
418 args
.dvo_v3
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
419 args
.dvo_v3
.ucDVOConfig
= 0; /* XXX */
423 args
.dvo_v4
.ucAction
= action
;
424 args
.dvo_v4
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
425 args
.dvo_v4
.ucDVOConfig
= 0; /* XXX */
426 args
.dvo_v4
.ucBitPerColor
= amdgpu_atombios_encoder_get_bpc(encoder
);
429 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
434 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
438 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
441 int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder
*encoder
)
443 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
444 struct drm_connector
*connector
;
445 struct amdgpu_connector
*amdgpu_connector
;
446 struct amdgpu_connector_atom_dig
*dig_connector
;
448 /* dp bridges are always DP */
449 if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
)
450 return ATOM_ENCODER_MODE_DP
;
452 /* DVO is always DVO */
453 if ((amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DVO1
) ||
454 (amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
))
455 return ATOM_ENCODER_MODE_DVO
;
457 connector
= amdgpu_get_connector_for_encoder(encoder
);
458 /* if we don't have an active device yet, just use one of
459 * the connectors tied to the encoder.
462 connector
= amdgpu_get_connector_for_encoder_init(encoder
);
463 amdgpu_connector
= to_amdgpu_connector(connector
);
465 switch (connector
->connector_type
) {
466 case DRM_MODE_CONNECTOR_DVII
:
467 case DRM_MODE_CONNECTOR_HDMIB
: /* HDMI-B is basically DL-DVI; analog works fine */
468 if (amdgpu_audio
!= 0) {
469 if (amdgpu_connector
->use_digital
&&
470 (amdgpu_connector
->audio
== AMDGPU_AUDIO_ENABLE
))
471 return ATOM_ENCODER_MODE_HDMI
;
472 else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector
)) &&
473 (amdgpu_connector
->audio
== AMDGPU_AUDIO_AUTO
))
474 return ATOM_ENCODER_MODE_HDMI
;
475 else if (amdgpu_connector
->use_digital
)
476 return ATOM_ENCODER_MODE_DVI
;
478 return ATOM_ENCODER_MODE_CRT
;
479 } else if (amdgpu_connector
->use_digital
) {
480 return ATOM_ENCODER_MODE_DVI
;
482 return ATOM_ENCODER_MODE_CRT
;
485 case DRM_MODE_CONNECTOR_DVID
:
486 case DRM_MODE_CONNECTOR_HDMIA
:
488 if (amdgpu_audio
!= 0) {
489 if (amdgpu_connector
->audio
== AMDGPU_AUDIO_ENABLE
)
490 return ATOM_ENCODER_MODE_HDMI
;
491 else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector
)) &&
492 (amdgpu_connector
->audio
== AMDGPU_AUDIO_AUTO
))
493 return ATOM_ENCODER_MODE_HDMI
;
495 return ATOM_ENCODER_MODE_DVI
;
497 return ATOM_ENCODER_MODE_DVI
;
500 case DRM_MODE_CONNECTOR_LVDS
:
501 return ATOM_ENCODER_MODE_LVDS
;
503 case DRM_MODE_CONNECTOR_DisplayPort
:
504 dig_connector
= amdgpu_connector
->con_priv
;
505 if ((dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_DISPLAYPORT
) ||
506 (dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_eDP
)) {
507 return ATOM_ENCODER_MODE_DP
;
508 } else if (amdgpu_audio
!= 0) {
509 if (amdgpu_connector
->audio
== AMDGPU_AUDIO_ENABLE
)
510 return ATOM_ENCODER_MODE_HDMI
;
511 else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector
)) &&
512 (amdgpu_connector
->audio
== AMDGPU_AUDIO_AUTO
))
513 return ATOM_ENCODER_MODE_HDMI
;
515 return ATOM_ENCODER_MODE_DVI
;
517 return ATOM_ENCODER_MODE_DVI
;
520 case DRM_MODE_CONNECTOR_eDP
:
521 return ATOM_ENCODER_MODE_DP
;
522 case DRM_MODE_CONNECTOR_DVIA
:
523 case DRM_MODE_CONNECTOR_VGA
:
524 return ATOM_ENCODER_MODE_CRT
;
526 case DRM_MODE_CONNECTOR_Composite
:
527 case DRM_MODE_CONNECTOR_SVIDEO
:
528 case DRM_MODE_CONNECTOR_9PinDIN
:
530 return ATOM_ENCODER_MODE_TV
;
531 /*return ATOM_ENCODER_MODE_CV;*/
537 * DIG Encoder/Transmitter Setup
540 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
541 * Supports up to 6 digital outputs
542 * - 6 DIG encoder blocks.
543 * - DIG to PHY mapping is hardcoded
544 * DIG1 drives UNIPHY0 link A, A+B
545 * DIG2 drives UNIPHY0 link B
546 * DIG3 drives UNIPHY1 link A, A+B
547 * DIG4 drives UNIPHY1 link B
548 * DIG5 drives UNIPHY2 link A, A+B
549 * DIG6 drives UNIPHY2 link B
552 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
554 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
555 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
556 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
557 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
560 union dig_encoder_control
{
561 DIG_ENCODER_CONTROL_PS_ALLOCATION v1
;
562 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2
;
563 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3
;
564 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4
;
565 DIG_ENCODER_CONTROL_PARAMETERS_V5 v5
;
569 amdgpu_atombios_encoder_setup_dig_encoder(struct drm_encoder
*encoder
,
570 int action
, int panel_mode
)
572 struct drm_device
*dev
= encoder
->dev
;
573 struct amdgpu_device
*adev
= dev
->dev_private
;
574 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
575 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
576 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
577 union dig_encoder_control args
;
578 int index
= GetIndexIntoMasterTable(COMMAND
, DIGxEncoderControl
);
581 int dp_lane_count
= 0;
582 int hpd_id
= AMDGPU_HPD_NONE
;
585 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
586 struct amdgpu_connector_atom_dig
*dig_connector
=
587 amdgpu_connector
->con_priv
;
589 dp_clock
= dig_connector
->dp_clock
;
590 dp_lane_count
= dig_connector
->dp_lane_count
;
591 hpd_id
= amdgpu_connector
->hpd
.hpd
;
594 /* no dig encoder assigned */
595 if (dig
->dig_encoder
== -1)
598 memset(&args
, 0, sizeof(args
));
600 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
607 args
.v1
.ucAction
= action
;
608 args
.v1
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
609 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
610 args
.v3
.ucPanelMode
= panel_mode
;
612 args
.v1
.ucEncoderMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
614 if (ENCODER_MODE_IS_DP(args
.v1
.ucEncoderMode
))
615 args
.v1
.ucLaneNum
= dp_lane_count
;
616 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
617 args
.v1
.ucLaneNum
= 8;
619 args
.v1
.ucLaneNum
= 4;
621 if (ENCODER_MODE_IS_DP(args
.v1
.ucEncoderMode
) && (dp_clock
== 270000))
622 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ
;
623 switch (amdgpu_encoder
->encoder_id
) {
624 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
625 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER1
;
627 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
628 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
629 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER2
;
631 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
632 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER3
;
636 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKB
;
638 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKA
;
642 args
.v3
.ucAction
= action
;
643 args
.v3
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
644 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
645 args
.v3
.ucPanelMode
= panel_mode
;
647 args
.v3
.ucEncoderMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
649 if (ENCODER_MODE_IS_DP(args
.v3
.ucEncoderMode
))
650 args
.v3
.ucLaneNum
= dp_lane_count
;
651 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
652 args
.v3
.ucLaneNum
= 8;
654 args
.v3
.ucLaneNum
= 4;
656 if (ENCODER_MODE_IS_DP(args
.v3
.ucEncoderMode
) && (dp_clock
== 270000))
657 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ
;
658 args
.v3
.acConfig
.ucDigSel
= dig
->dig_encoder
;
659 args
.v3
.ucBitPerColor
= amdgpu_atombios_encoder_get_bpc(encoder
);
662 args
.v4
.ucAction
= action
;
663 args
.v4
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
664 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
665 args
.v4
.ucPanelMode
= panel_mode
;
667 args
.v4
.ucEncoderMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
669 if (ENCODER_MODE_IS_DP(args
.v4
.ucEncoderMode
))
670 args
.v4
.ucLaneNum
= dp_lane_count
;
671 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
672 args
.v4
.ucLaneNum
= 8;
674 args
.v4
.ucLaneNum
= 4;
676 if (ENCODER_MODE_IS_DP(args
.v4
.ucEncoderMode
)) {
677 if (dp_clock
== 540000)
678 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ
;
679 else if (dp_clock
== 324000)
680 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ
;
681 else if (dp_clock
== 270000)
682 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ
;
684 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ
;
686 args
.v4
.acConfig
.ucDigSel
= dig
->dig_encoder
;
687 args
.v4
.ucBitPerColor
= amdgpu_atombios_encoder_get_bpc(encoder
);
688 if (hpd_id
== AMDGPU_HPD_NONE
)
689 args
.v4
.ucHPD_ID
= 0;
691 args
.v4
.ucHPD_ID
= hpd_id
+ 1;
695 case ATOM_ENCODER_CMD_SETUP_PANEL_MODE
:
696 args
.v5
.asDPPanelModeParam
.ucAction
= action
;
697 args
.v5
.asDPPanelModeParam
.ucPanelMode
= panel_mode
;
698 args
.v5
.asDPPanelModeParam
.ucDigId
= dig
->dig_encoder
;
700 case ATOM_ENCODER_CMD_STREAM_SETUP
:
701 args
.v5
.asStreamParam
.ucAction
= action
;
702 args
.v5
.asStreamParam
.ucDigId
= dig
->dig_encoder
;
703 args
.v5
.asStreamParam
.ucDigMode
=
704 amdgpu_atombios_encoder_get_encoder_mode(encoder
);
705 if (ENCODER_MODE_IS_DP(args
.v5
.asStreamParam
.ucDigMode
))
706 args
.v5
.asStreamParam
.ucLaneNum
= dp_lane_count
;
707 else if (amdgpu_dig_monitor_is_duallink(encoder
,
708 amdgpu_encoder
->pixel_clock
))
709 args
.v5
.asStreamParam
.ucLaneNum
= 8;
711 args
.v5
.asStreamParam
.ucLaneNum
= 4;
712 args
.v5
.asStreamParam
.ulPixelClock
=
713 cpu_to_le32(amdgpu_encoder
->pixel_clock
/ 10);
714 args
.v5
.asStreamParam
.ucBitPerColor
=
715 amdgpu_atombios_encoder_get_bpc(encoder
);
716 args
.v5
.asStreamParam
.ucLinkRateIn270Mhz
= dp_clock
/ 27000;
718 case ATOM_ENCODER_CMD_DP_LINK_TRAINING_START
:
719 case ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1
:
720 case ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2
:
721 case ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3
:
722 case ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4
:
723 case ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE
:
724 case ATOM_ENCODER_CMD_DP_VIDEO_OFF
:
725 case ATOM_ENCODER_CMD_DP_VIDEO_ON
:
726 args
.v5
.asCmdParam
.ucAction
= action
;
727 args
.v5
.asCmdParam
.ucDigId
= dig
->dig_encoder
;
730 DRM_ERROR("Unsupported action 0x%x\n", action
);
735 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
740 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
744 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
748 union dig_transmitter_control
{
749 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1
;
750 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2
;
751 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3
;
752 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4
;
753 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5
;
754 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6 v6
;
758 amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder
*encoder
, int action
,
759 uint8_t lane_num
, uint8_t lane_set
)
761 struct drm_device
*dev
= encoder
->dev
;
762 struct amdgpu_device
*adev
= dev
->dev_private
;
763 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
764 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
765 struct drm_connector
*connector
;
766 union dig_transmitter_control args
;
772 int dp_lane_count
= 0;
773 int connector_object_id
= 0;
774 int igp_lane_info
= 0;
775 int dig_encoder
= dig
->dig_encoder
;
776 int hpd_id
= AMDGPU_HPD_NONE
;
778 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
779 connector
= amdgpu_get_connector_for_encoder_init(encoder
);
780 /* just needed to avoid bailing in the encoder check. the encoder
781 * isn't used for init
785 connector
= amdgpu_get_connector_for_encoder(encoder
);
788 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
789 struct amdgpu_connector_atom_dig
*dig_connector
=
790 amdgpu_connector
->con_priv
;
792 hpd_id
= amdgpu_connector
->hpd
.hpd
;
793 dp_clock
= dig_connector
->dp_clock
;
794 dp_lane_count
= dig_connector
->dp_lane_count
;
795 connector_object_id
=
796 (amdgpu_connector
->connector_object_id
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
800 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
801 pll_id
= amdgpu_crtc
->pll_id
;
804 /* no dig encoder assigned */
805 if (dig_encoder
== -1)
808 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder
)))
811 memset(&args
, 0, sizeof(args
));
813 switch (amdgpu_encoder
->encoder_id
) {
814 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
815 index
= GetIndexIntoMasterTable(COMMAND
, DVOOutputControl
);
817 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
818 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
819 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
820 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
821 index
= GetIndexIntoMasterTable(COMMAND
, UNIPHYTransmitterControl
);
823 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
824 index
= GetIndexIntoMasterTable(COMMAND
, LVTMATransmitterControl
);
828 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
835 args
.v1
.ucAction
= action
;
836 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
837 args
.v1
.usInitInfo
= cpu_to_le16(connector_object_id
);
838 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
839 args
.v1
.asMode
.ucLaneSel
= lane_num
;
840 args
.v1
.asMode
.ucLaneSet
= lane_set
;
843 args
.v1
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
844 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
845 args
.v1
.usPixelClock
= cpu_to_le16((amdgpu_encoder
->pixel_clock
/ 2) / 10);
847 args
.v1
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
850 args
.v1
.ucConfig
= ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL
;
853 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER
;
855 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER
;
857 if ((adev
->flags
& AMD_IS_APU
) &&
858 (amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_UNIPHY
)) {
860 !amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
)) {
861 if (igp_lane_info
& 0x1)
862 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_3
;
863 else if (igp_lane_info
& 0x2)
864 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_4_7
;
865 else if (igp_lane_info
& 0x4)
866 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_11
;
867 else if (igp_lane_info
& 0x8)
868 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_12_15
;
870 if (igp_lane_info
& 0x3)
871 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_7
;
872 else if (igp_lane_info
& 0xc)
873 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_15
;
878 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKB
;
880 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKA
;
883 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_COHERENT
;
884 else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
885 if (dig
->coherent_mode
)
886 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_COHERENT
;
887 if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
888 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_8LANE_LINK
;
892 args
.v2
.ucAction
= action
;
893 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
894 args
.v2
.usInitInfo
= cpu_to_le16(connector_object_id
);
895 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
896 args
.v2
.asMode
.ucLaneSel
= lane_num
;
897 args
.v2
.asMode
.ucLaneSet
= lane_set
;
900 args
.v2
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
901 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
902 args
.v2
.usPixelClock
= cpu_to_le16((amdgpu_encoder
->pixel_clock
/ 2) / 10);
904 args
.v2
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
907 args
.v2
.acConfig
.ucEncoderSel
= dig_encoder
;
909 args
.v2
.acConfig
.ucLinkSel
= 1;
911 switch (amdgpu_encoder
->encoder_id
) {
912 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
913 args
.v2
.acConfig
.ucTransmitterSel
= 0;
915 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
916 args
.v2
.acConfig
.ucTransmitterSel
= 1;
918 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
919 args
.v2
.acConfig
.ucTransmitterSel
= 2;
924 args
.v2
.acConfig
.fCoherentMode
= 1;
925 args
.v2
.acConfig
.fDPConnector
= 1;
926 } else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
927 if (dig
->coherent_mode
)
928 args
.v2
.acConfig
.fCoherentMode
= 1;
929 if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
930 args
.v2
.acConfig
.fDualLinkConnector
= 1;
934 args
.v3
.ucAction
= action
;
935 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
936 args
.v3
.usInitInfo
= cpu_to_le16(connector_object_id
);
937 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
938 args
.v3
.asMode
.ucLaneSel
= lane_num
;
939 args
.v3
.asMode
.ucLaneSet
= lane_set
;
942 args
.v3
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
943 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
944 args
.v3
.usPixelClock
= cpu_to_le16((amdgpu_encoder
->pixel_clock
/ 2) / 10);
946 args
.v3
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
950 args
.v3
.ucLaneNum
= dp_lane_count
;
951 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
952 args
.v3
.ucLaneNum
= 8;
954 args
.v3
.ucLaneNum
= 4;
957 args
.v3
.acConfig
.ucLinkSel
= 1;
959 args
.v3
.acConfig
.ucEncoderSel
= 1;
961 /* Select the PLL for the PHY
962 * DP PHY should be clocked from external src if there is
965 /* On DCE4, if there is an external clock, it generates the DP ref clock */
966 if (is_dp
&& adev
->clock
.dp_extclk
)
967 args
.v3
.acConfig
.ucRefClkSource
= 2; /* external src */
969 args
.v3
.acConfig
.ucRefClkSource
= pll_id
;
971 switch (amdgpu_encoder
->encoder_id
) {
972 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
973 args
.v3
.acConfig
.ucTransmitterSel
= 0;
975 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
976 args
.v3
.acConfig
.ucTransmitterSel
= 1;
978 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
979 args
.v3
.acConfig
.ucTransmitterSel
= 2;
984 args
.v3
.acConfig
.fCoherentMode
= 1; /* DP requires coherent */
985 else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
986 if (dig
->coherent_mode
)
987 args
.v3
.acConfig
.fCoherentMode
= 1;
988 if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
989 args
.v3
.acConfig
.fDualLinkConnector
= 1;
993 args
.v4
.ucAction
= action
;
994 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
995 args
.v4
.usInitInfo
= cpu_to_le16(connector_object_id
);
996 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
997 args
.v4
.asMode
.ucLaneSel
= lane_num
;
998 args
.v4
.asMode
.ucLaneSet
= lane_set
;
1001 args
.v4
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1002 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
1003 args
.v4
.usPixelClock
= cpu_to_le16((amdgpu_encoder
->pixel_clock
/ 2) / 10);
1005 args
.v4
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
1009 args
.v4
.ucLaneNum
= dp_lane_count
;
1010 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
1011 args
.v4
.ucLaneNum
= 8;
1013 args
.v4
.ucLaneNum
= 4;
1016 args
.v4
.acConfig
.ucLinkSel
= 1;
1017 if (dig_encoder
& 1)
1018 args
.v4
.acConfig
.ucEncoderSel
= 1;
1020 /* Select the PLL for the PHY
1021 * DP PHY should be clocked from external src if there is
1024 /* On DCE5 DCPLL usually generates the DP ref clock */
1026 if (adev
->clock
.dp_extclk
)
1027 args
.v4
.acConfig
.ucRefClkSource
= ENCODER_REFCLK_SRC_EXTCLK
;
1029 args
.v4
.acConfig
.ucRefClkSource
= ENCODER_REFCLK_SRC_DCPLL
;
1031 args
.v4
.acConfig
.ucRefClkSource
= pll_id
;
1033 switch (amdgpu_encoder
->encoder_id
) {
1034 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1035 args
.v4
.acConfig
.ucTransmitterSel
= 0;
1037 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1038 args
.v4
.acConfig
.ucTransmitterSel
= 1;
1040 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1041 args
.v4
.acConfig
.ucTransmitterSel
= 2;
1046 args
.v4
.acConfig
.fCoherentMode
= 1; /* DP requires coherent */
1047 else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1048 if (dig
->coherent_mode
)
1049 args
.v4
.acConfig
.fCoherentMode
= 1;
1050 if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
1051 args
.v4
.acConfig
.fDualLinkConnector
= 1;
1055 args
.v5
.ucAction
= action
;
1057 args
.v5
.usSymClock
= cpu_to_le16(dp_clock
/ 10);
1059 args
.v5
.usSymClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
1061 switch (amdgpu_encoder
->encoder_id
) {
1062 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1064 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYB
;
1066 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYA
;
1068 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1070 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYD
;
1072 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYC
;
1074 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1076 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYF
;
1078 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYE
;
1080 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1081 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYG
;
1085 args
.v5
.ucLaneNum
= dp_lane_count
;
1086 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
1087 args
.v5
.ucLaneNum
= 8;
1089 args
.v5
.ucLaneNum
= 4;
1090 args
.v5
.ucConnObjId
= connector_object_id
;
1091 args
.v5
.ucDigMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1093 if (is_dp
&& adev
->clock
.dp_extclk
)
1094 args
.v5
.asConfig
.ucPhyClkSrcId
= ENCODER_REFCLK_SRC_EXTCLK
;
1096 args
.v5
.asConfig
.ucPhyClkSrcId
= pll_id
;
1099 args
.v5
.asConfig
.ucCoherentMode
= 1; /* DP requires coherent */
1100 else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1101 if (dig
->coherent_mode
)
1102 args
.v5
.asConfig
.ucCoherentMode
= 1;
1104 if (hpd_id
== AMDGPU_HPD_NONE
)
1105 args
.v5
.asConfig
.ucHPDSel
= 0;
1107 args
.v5
.asConfig
.ucHPDSel
= hpd_id
+ 1;
1108 args
.v5
.ucDigEncoderSel
= 1 << dig_encoder
;
1109 args
.v5
.ucDPLaneSet
= lane_set
;
1112 args
.v6
.ucAction
= action
;
1114 args
.v6
.ulSymClock
= cpu_to_le32(dp_clock
/ 10);
1116 args
.v6
.ulSymClock
= cpu_to_le32(amdgpu_encoder
->pixel_clock
/ 10);
1118 switch (amdgpu_encoder
->encoder_id
) {
1119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1121 args
.v6
.ucPhyId
= ATOM_PHY_ID_UNIPHYB
;
1123 args
.v6
.ucPhyId
= ATOM_PHY_ID_UNIPHYA
;
1125 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1127 args
.v6
.ucPhyId
= ATOM_PHY_ID_UNIPHYD
;
1129 args
.v6
.ucPhyId
= ATOM_PHY_ID_UNIPHYC
;
1131 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1133 args
.v6
.ucPhyId
= ATOM_PHY_ID_UNIPHYF
;
1135 args
.v6
.ucPhyId
= ATOM_PHY_ID_UNIPHYE
;
1137 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1138 args
.v6
.ucPhyId
= ATOM_PHY_ID_UNIPHYG
;
1142 args
.v6
.ucLaneNum
= dp_lane_count
;
1143 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
1144 args
.v6
.ucLaneNum
= 8;
1146 args
.v6
.ucLaneNum
= 4;
1147 args
.v6
.ucConnObjId
= connector_object_id
;
1148 if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
)
1149 args
.v6
.ucDPLaneSet
= lane_set
;
1151 args
.v6
.ucDigMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1153 if (hpd_id
== AMDGPU_HPD_NONE
)
1154 args
.v6
.ucHPDSel
= 0;
1156 args
.v6
.ucHPDSel
= hpd_id
+ 1;
1157 args
.v6
.ucDigEncoderSel
= 1 << dig_encoder
;
1160 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1165 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1169 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1173 amdgpu_atombios_encoder_set_edp_panel_power(struct drm_connector
*connector
,
1176 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
1177 struct drm_device
*dev
= amdgpu_connector
->base
.dev
;
1178 struct amdgpu_device
*adev
= dev
->dev_private
;
1179 union dig_transmitter_control args
;
1180 int index
= GetIndexIntoMasterTable(COMMAND
, UNIPHYTransmitterControl
);
1183 if (connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
1186 if ((action
!= ATOM_TRANSMITTER_ACTION_POWER_ON
) &&
1187 (action
!= ATOM_TRANSMITTER_ACTION_POWER_OFF
))
1190 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1193 memset(&args
, 0, sizeof(args
));
1195 args
.v1
.ucAction
= action
;
1197 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1199 /* wait for the panel to power up */
1200 if (action
== ATOM_TRANSMITTER_ACTION_POWER_ON
) {
1203 for (i
= 0; i
< 300; i
++) {
1204 if (amdgpu_display_hpd_sense(adev
, amdgpu_connector
->hpd
.hpd
))
1214 union external_encoder_control
{
1215 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1
;
1216 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3
;
1220 amdgpu_atombios_encoder_setup_external_encoder(struct drm_encoder
*encoder
,
1221 struct drm_encoder
*ext_encoder
,
1224 struct drm_device
*dev
= encoder
->dev
;
1225 struct amdgpu_device
*adev
= dev
->dev_private
;
1226 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1227 struct amdgpu_encoder
*ext_amdgpu_encoder
= to_amdgpu_encoder(ext_encoder
);
1228 union external_encoder_control args
;
1229 struct drm_connector
*connector
;
1230 int index
= GetIndexIntoMasterTable(COMMAND
, ExternalEncoderControl
);
1233 int dp_lane_count
= 0;
1234 int connector_object_id
= 0;
1235 u32 ext_enum
= (ext_amdgpu_encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
1237 if (action
== EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
)
1238 connector
= amdgpu_get_connector_for_encoder_init(encoder
);
1240 connector
= amdgpu_get_connector_for_encoder(encoder
);
1243 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
1244 struct amdgpu_connector_atom_dig
*dig_connector
=
1245 amdgpu_connector
->con_priv
;
1247 dp_clock
= dig_connector
->dp_clock
;
1248 dp_lane_count
= dig_connector
->dp_lane_count
;
1249 connector_object_id
=
1250 (amdgpu_connector
->connector_object_id
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
1253 memset(&args
, 0, sizeof(args
));
1255 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1260 /* no params on frev 1 */
1266 args
.v1
.sDigEncoder
.ucAction
= action
;
1267 args
.v1
.sDigEncoder
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
1268 args
.v1
.sDigEncoder
.ucEncoderMode
=
1269 amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1271 if (ENCODER_MODE_IS_DP(args
.v1
.sDigEncoder
.ucEncoderMode
)) {
1272 if (dp_clock
== 270000)
1273 args
.v1
.sDigEncoder
.ucConfig
|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ
;
1274 args
.v1
.sDigEncoder
.ucLaneNum
= dp_lane_count
;
1275 } else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
1276 args
.v1
.sDigEncoder
.ucLaneNum
= 8;
1278 args
.v1
.sDigEncoder
.ucLaneNum
= 4;
1281 args
.v3
.sExtEncoder
.ucAction
= action
;
1282 if (action
== EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
)
1283 args
.v3
.sExtEncoder
.usConnectorId
= cpu_to_le16(connector_object_id
);
1285 args
.v3
.sExtEncoder
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
1286 args
.v3
.sExtEncoder
.ucEncoderMode
=
1287 amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1289 if (ENCODER_MODE_IS_DP(args
.v3
.sExtEncoder
.ucEncoderMode
)) {
1290 if (dp_clock
== 270000)
1291 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ
;
1292 else if (dp_clock
== 540000)
1293 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ
;
1294 args
.v3
.sExtEncoder
.ucLaneNum
= dp_lane_count
;
1295 } else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
1296 args
.v3
.sExtEncoder
.ucLaneNum
= 8;
1298 args
.v3
.sExtEncoder
.ucLaneNum
= 4;
1300 case GRAPH_OBJECT_ENUM_ID1
:
1301 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1
;
1303 case GRAPH_OBJECT_ENUM_ID2
:
1304 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2
;
1306 case GRAPH_OBJECT_ENUM_ID3
:
1307 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3
;
1310 args
.v3
.sExtEncoder
.ucBitPerColor
= amdgpu_atombios_encoder_get_bpc(encoder
);
1313 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1318 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1321 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1325 amdgpu_atombios_encoder_setup_dig(struct drm_encoder
*encoder
, int action
)
1327 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1328 struct drm_encoder
*ext_encoder
= amdgpu_get_external_encoder(encoder
);
1329 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1330 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
1331 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1332 struct amdgpu_connector_atom_dig
*amdgpu_dig_connector
= NULL
;
1335 amdgpu_connector
= to_amdgpu_connector(connector
);
1336 amdgpu_dig_connector
= amdgpu_connector
->con_priv
;
1339 if (action
== ATOM_ENABLE
) {
1341 dig
->panel_mode
= DP_PANEL_MODE_EXTERNAL_DP_MODE
;
1343 dig
->panel_mode
= amdgpu_atombios_dp_get_panel_mode(encoder
, connector
);
1345 /* setup and enable the encoder */
1346 amdgpu_atombios_encoder_setup_dig_encoder(encoder
, ATOM_ENCODER_CMD_SETUP
, 0);
1347 amdgpu_atombios_encoder_setup_dig_encoder(encoder
,
1348 ATOM_ENCODER_CMD_SETUP_PANEL_MODE
,
1351 amdgpu_atombios_encoder_setup_external_encoder(encoder
, ext_encoder
,
1352 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP
);
1353 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder
)) &&
1355 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) {
1356 amdgpu_atombios_encoder_set_edp_panel_power(connector
,
1357 ATOM_TRANSMITTER_ACTION_POWER_ON
);
1358 amdgpu_dig_connector
->edp_on
= true;
1361 /* enable the transmitter */
1362 amdgpu_atombios_encoder_setup_dig_transmitter(encoder
,
1363 ATOM_TRANSMITTER_ACTION_ENABLE
,
1365 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder
)) &&
1367 /* DP_SET_POWER_D0 is set in amdgpu_atombios_dp_link_train */
1368 amdgpu_atombios_dp_link_train(encoder
, connector
);
1369 amdgpu_atombios_encoder_setup_dig_encoder(encoder
, ATOM_ENCODER_CMD_DP_VIDEO_ON
, 0);
1371 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1372 amdgpu_atombios_encoder_set_backlight_level(amdgpu_encoder
, dig
->backlight_level
);
1374 amdgpu_atombios_encoder_setup_external_encoder(encoder
, ext_encoder
, ATOM_ENABLE
);
1376 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder
)) &&
1378 amdgpu_atombios_encoder_setup_dig_encoder(encoder
,
1379 ATOM_ENCODER_CMD_DP_VIDEO_OFF
, 0);
1381 amdgpu_atombios_encoder_setup_external_encoder(encoder
, ext_encoder
, ATOM_DISABLE
);
1382 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1383 amdgpu_atombios_encoder_setup_dig_transmitter(encoder
,
1384 ATOM_TRANSMITTER_ACTION_LCD_BLOFF
, 0, 0);
1386 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder
)) &&
1388 amdgpu_atombios_dp_set_rx_power_state(connector
, DP_SET_POWER_D3
);
1389 /* disable the transmitter */
1390 amdgpu_atombios_encoder_setup_dig_transmitter(encoder
,
1391 ATOM_TRANSMITTER_ACTION_DISABLE
, 0, 0);
1392 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder
)) &&
1394 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) {
1395 amdgpu_atombios_encoder_set_edp_panel_power(connector
,
1396 ATOM_TRANSMITTER_ACTION_POWER_OFF
);
1397 amdgpu_dig_connector
->edp_on
= false;
1404 amdgpu_atombios_encoder_dpms(struct drm_encoder
*encoder
, int mode
)
1406 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1408 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1409 amdgpu_encoder
->encoder_id
, mode
, amdgpu_encoder
->devices
,
1410 amdgpu_encoder
->active_device
);
1411 switch (amdgpu_encoder
->encoder_id
) {
1412 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1413 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1414 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1415 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1417 case DRM_MODE_DPMS_ON
:
1418 amdgpu_atombios_encoder_setup_dig(encoder
, ATOM_ENABLE
);
1420 case DRM_MODE_DPMS_STANDBY
:
1421 case DRM_MODE_DPMS_SUSPEND
:
1422 case DRM_MODE_DPMS_OFF
:
1423 amdgpu_atombios_encoder_setup_dig(encoder
, ATOM_DISABLE
);
1427 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1429 case DRM_MODE_DPMS_ON
:
1430 amdgpu_atombios_encoder_setup_dvo(encoder
, ATOM_ENABLE
);
1432 case DRM_MODE_DPMS_STANDBY
:
1433 case DRM_MODE_DPMS_SUSPEND
:
1434 case DRM_MODE_DPMS_OFF
:
1435 amdgpu_atombios_encoder_setup_dvo(encoder
, ATOM_DISABLE
);
1439 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1441 case DRM_MODE_DPMS_ON
:
1442 amdgpu_atombios_encoder_setup_dac(encoder
, ATOM_ENABLE
);
1444 case DRM_MODE_DPMS_STANDBY
:
1445 case DRM_MODE_DPMS_SUSPEND
:
1446 case DRM_MODE_DPMS_OFF
:
1447 amdgpu_atombios_encoder_setup_dac(encoder
, ATOM_DISABLE
);
1456 union crtc_source_param
{
1457 SELECT_CRTC_SOURCE_PS_ALLOCATION v1
;
1458 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2
;
1459 SELECT_CRTC_SOURCE_PARAMETERS_V3 v3
;
1463 amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder
*encoder
)
1465 struct drm_device
*dev
= encoder
->dev
;
1466 struct amdgpu_device
*adev
= dev
->dev_private
;
1467 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1468 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
1469 union crtc_source_param args
;
1470 int index
= GetIndexIntoMasterTable(COMMAND
, SelectCRTC_Source
);
1472 struct amdgpu_encoder_atom_dig
*dig
;
1474 memset(&args
, 0, sizeof(args
));
1476 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1484 args
.v1
.ucCRTC
= amdgpu_crtc
->crtc_id
;
1485 switch (amdgpu_encoder
->encoder_id
) {
1486 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1487 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1488 args
.v1
.ucDevice
= ATOM_DEVICE_DFP1_INDEX
;
1490 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1491 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1492 if (amdgpu_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)
1493 args
.v1
.ucDevice
= ATOM_DEVICE_LCD1_INDEX
;
1495 args
.v1
.ucDevice
= ATOM_DEVICE_DFP3_INDEX
;
1497 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1498 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1499 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1500 args
.v1
.ucDevice
= ATOM_DEVICE_DFP2_INDEX
;
1502 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1503 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1504 if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1505 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1506 else if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1507 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1509 args
.v1
.ucDevice
= ATOM_DEVICE_CRT1_INDEX
;
1511 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1512 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1513 if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1514 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1515 else if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1516 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1518 args
.v1
.ucDevice
= ATOM_DEVICE_CRT2_INDEX
;
1523 args
.v2
.ucCRTC
= amdgpu_crtc
->crtc_id
;
1524 if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
) {
1525 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
1527 if (connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
)
1528 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_LVDS
;
1529 else if (connector
->connector_type
== DRM_MODE_CONNECTOR_VGA
)
1530 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_CRT
;
1532 args
.v2
.ucEncodeMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1533 } else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1534 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_LVDS
;
1536 args
.v2
.ucEncodeMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1538 switch (amdgpu_encoder
->encoder_id
) {
1539 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1540 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1541 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1542 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1543 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1544 dig
= amdgpu_encoder
->enc_priv
;
1545 switch (dig
->dig_encoder
) {
1547 args
.v2
.ucEncoderID
= ASIC_INT_DIG1_ENCODER_ID
;
1550 args
.v2
.ucEncoderID
= ASIC_INT_DIG2_ENCODER_ID
;
1553 args
.v2
.ucEncoderID
= ASIC_INT_DIG3_ENCODER_ID
;
1556 args
.v2
.ucEncoderID
= ASIC_INT_DIG4_ENCODER_ID
;
1559 args
.v2
.ucEncoderID
= ASIC_INT_DIG5_ENCODER_ID
;
1562 args
.v2
.ucEncoderID
= ASIC_INT_DIG6_ENCODER_ID
;
1565 args
.v2
.ucEncoderID
= ASIC_INT_DIG7_ENCODER_ID
;
1569 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1570 args
.v2
.ucEncoderID
= ASIC_INT_DVO_ENCODER_ID
;
1572 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1573 if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1574 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1575 else if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1576 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1578 args
.v2
.ucEncoderID
= ASIC_INT_DAC1_ENCODER_ID
;
1580 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1581 if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1582 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1583 else if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1584 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1586 args
.v2
.ucEncoderID
= ASIC_INT_DAC2_ENCODER_ID
;
1591 args
.v3
.ucCRTC
= amdgpu_crtc
->crtc_id
;
1592 if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
) {
1593 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
1595 if (connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
)
1596 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_LVDS
;
1597 else if (connector
->connector_type
== DRM_MODE_CONNECTOR_VGA
)
1598 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_CRT
;
1600 args
.v2
.ucEncodeMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1601 } else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1602 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_LVDS
;
1604 args
.v2
.ucEncodeMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1606 args
.v3
.ucDstBpc
= amdgpu_atombios_encoder_get_bpc(encoder
);
1607 switch (amdgpu_encoder
->encoder_id
) {
1608 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1609 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1610 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1611 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1612 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1613 dig
= amdgpu_encoder
->enc_priv
;
1614 switch (dig
->dig_encoder
) {
1616 args
.v3
.ucEncoderID
= ASIC_INT_DIG1_ENCODER_ID
;
1619 args
.v3
.ucEncoderID
= ASIC_INT_DIG2_ENCODER_ID
;
1622 args
.v3
.ucEncoderID
= ASIC_INT_DIG3_ENCODER_ID
;
1625 args
.v3
.ucEncoderID
= ASIC_INT_DIG4_ENCODER_ID
;
1628 args
.v3
.ucEncoderID
= ASIC_INT_DIG5_ENCODER_ID
;
1631 args
.v3
.ucEncoderID
= ASIC_INT_DIG6_ENCODER_ID
;
1634 args
.v3
.ucEncoderID
= ASIC_INT_DIG7_ENCODER_ID
;
1638 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1639 args
.v3
.ucEncoderID
= ASIC_INT_DVO_ENCODER_ID
;
1641 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1642 if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1643 args
.v3
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1644 else if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1645 args
.v3
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1647 args
.v3
.ucEncoderID
= ASIC_INT_DAC1_ENCODER_ID
;
1649 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1650 if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1651 args
.v3
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1652 else if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1653 args
.v3
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1655 args
.v3
.ucEncoderID
= ASIC_INT_DAC2_ENCODER_ID
;
1662 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1666 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1669 /* This only needs to be called once at startup */
1671 amdgpu_atombios_encoder_init_dig(struct amdgpu_device
*adev
)
1673 struct drm_device
*dev
= adev
->ddev
;
1674 struct drm_encoder
*encoder
;
1676 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
1677 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1678 struct drm_encoder
*ext_encoder
= amdgpu_get_external_encoder(encoder
);
1680 switch (amdgpu_encoder
->encoder_id
) {
1681 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1682 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1683 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1684 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1685 amdgpu_atombios_encoder_setup_dig_transmitter(encoder
, ATOM_TRANSMITTER_ACTION_INIT
,
1691 amdgpu_atombios_encoder_setup_external_encoder(encoder
, ext_encoder
,
1692 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
);
1697 amdgpu_atombios_encoder_dac_load_detect(struct drm_encoder
*encoder
,
1698 struct drm_connector
*connector
)
1700 struct drm_device
*dev
= encoder
->dev
;
1701 struct amdgpu_device
*adev
= dev
->dev_private
;
1702 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1703 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
1705 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
|
1706 ATOM_DEVICE_CV_SUPPORT
|
1707 ATOM_DEVICE_CRT_SUPPORT
)) {
1708 DAC_LOAD_DETECTION_PS_ALLOCATION args
;
1709 int index
= GetIndexIntoMasterTable(COMMAND
, DAC_LoadDetection
);
1712 memset(&args
, 0, sizeof(args
));
1714 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1717 args
.sDacload
.ucMisc
= 0;
1719 if ((amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DAC1
) ||
1720 (amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
))
1721 args
.sDacload
.ucDacType
= ATOM_DAC_A
;
1723 args
.sDacload
.ucDacType
= ATOM_DAC_B
;
1725 if (amdgpu_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)
1726 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT
);
1727 else if (amdgpu_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)
1728 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT
);
1729 else if (amdgpu_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1730 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CV_SUPPORT
);
1732 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
1733 } else if (amdgpu_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1734 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT
);
1736 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
1739 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1746 enum drm_connector_status
1747 amdgpu_atombios_encoder_dac_detect(struct drm_encoder
*encoder
,
1748 struct drm_connector
*connector
)
1750 struct drm_device
*dev
= encoder
->dev
;
1751 struct amdgpu_device
*adev
= dev
->dev_private
;
1752 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1753 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
1754 uint32_t bios_0_scratch
;
1756 if (!amdgpu_atombios_encoder_dac_load_detect(encoder
, connector
)) {
1757 DRM_DEBUG_KMS("detect returned false \n");
1758 return connector_status_unknown
;
1761 bios_0_scratch
= RREG32(mmBIOS_SCRATCH_0
);
1763 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch
, amdgpu_encoder
->devices
);
1764 if (amdgpu_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
1765 if (bios_0_scratch
& ATOM_S0_CRT1_MASK
)
1766 return connector_status_connected
;
1768 if (amdgpu_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
1769 if (bios_0_scratch
& ATOM_S0_CRT2_MASK
)
1770 return connector_status_connected
;
1772 if (amdgpu_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1773 if (bios_0_scratch
& (ATOM_S0_CV_MASK
|ATOM_S0_CV_MASK_A
))
1774 return connector_status_connected
;
1776 if (amdgpu_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1777 if (bios_0_scratch
& (ATOM_S0_TV1_COMPOSITE
| ATOM_S0_TV1_COMPOSITE_A
))
1778 return connector_status_connected
; /* CTV */
1779 else if (bios_0_scratch
& (ATOM_S0_TV1_SVIDEO
| ATOM_S0_TV1_SVIDEO_A
))
1780 return connector_status_connected
; /* STV */
1782 return connector_status_disconnected
;
1785 enum drm_connector_status
1786 amdgpu_atombios_encoder_dig_detect(struct drm_encoder
*encoder
,
1787 struct drm_connector
*connector
)
1789 struct drm_device
*dev
= encoder
->dev
;
1790 struct amdgpu_device
*adev
= dev
->dev_private
;
1791 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1792 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
1793 struct drm_encoder
*ext_encoder
= amdgpu_get_external_encoder(encoder
);
1797 return connector_status_unknown
;
1799 if ((amdgpu_connector
->devices
& ATOM_DEVICE_CRT_SUPPORT
) == 0)
1800 return connector_status_unknown
;
1802 /* load detect on the dp bridge */
1803 amdgpu_atombios_encoder_setup_external_encoder(encoder
, ext_encoder
,
1804 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION
);
1806 bios_0_scratch
= RREG32(mmBIOS_SCRATCH_0
);
1808 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch
, amdgpu_encoder
->devices
);
1809 if (amdgpu_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
1810 if (bios_0_scratch
& ATOM_S0_CRT1_MASK
)
1811 return connector_status_connected
;
1813 if (amdgpu_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
1814 if (bios_0_scratch
& ATOM_S0_CRT2_MASK
)
1815 return connector_status_connected
;
1817 if (amdgpu_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1818 if (bios_0_scratch
& (ATOM_S0_CV_MASK
|ATOM_S0_CV_MASK_A
))
1819 return connector_status_connected
;
1821 if (amdgpu_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1822 if (bios_0_scratch
& (ATOM_S0_TV1_COMPOSITE
| ATOM_S0_TV1_COMPOSITE_A
))
1823 return connector_status_connected
; /* CTV */
1824 else if (bios_0_scratch
& (ATOM_S0_TV1_SVIDEO
| ATOM_S0_TV1_SVIDEO_A
))
1825 return connector_status_connected
; /* STV */
1827 return connector_status_disconnected
;
1831 amdgpu_atombios_encoder_setup_ext_encoder_ddc(struct drm_encoder
*encoder
)
1833 struct drm_encoder
*ext_encoder
= amdgpu_get_external_encoder(encoder
);
1836 /* ddc_setup on the dp bridge */
1837 amdgpu_atombios_encoder_setup_external_encoder(encoder
, ext_encoder
,
1838 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP
);
1843 amdgpu_atombios_encoder_set_bios_scratch_regs(struct drm_connector
*connector
,
1844 struct drm_encoder
*encoder
,
1847 struct drm_device
*dev
= connector
->dev
;
1848 struct amdgpu_device
*adev
= dev
->dev_private
;
1849 struct amdgpu_connector
*amdgpu_connector
=
1850 to_amdgpu_connector(connector
);
1851 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1852 uint32_t bios_0_scratch
, bios_3_scratch
, bios_6_scratch
;
1854 bios_0_scratch
= RREG32(mmBIOS_SCRATCH_0
);
1855 bios_3_scratch
= RREG32(mmBIOS_SCRATCH_3
);
1856 bios_6_scratch
= RREG32(mmBIOS_SCRATCH_6
);
1858 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) &&
1859 (amdgpu_connector
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)) {
1861 DRM_DEBUG_KMS("LCD1 connected\n");
1862 bios_0_scratch
|= ATOM_S0_LCD1
;
1863 bios_3_scratch
|= ATOM_S3_LCD1_ACTIVE
;
1864 bios_6_scratch
|= ATOM_S6_ACC_REQ_LCD1
;
1866 DRM_DEBUG_KMS("LCD1 disconnected\n");
1867 bios_0_scratch
&= ~ATOM_S0_LCD1
;
1868 bios_3_scratch
&= ~ATOM_S3_LCD1_ACTIVE
;
1869 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_LCD1
;
1872 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) &&
1873 (amdgpu_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)) {
1875 DRM_DEBUG_KMS("CRT1 connected\n");
1876 bios_0_scratch
|= ATOM_S0_CRT1_COLOR
;
1877 bios_3_scratch
|= ATOM_S3_CRT1_ACTIVE
;
1878 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT1
;
1880 DRM_DEBUG_KMS("CRT1 disconnected\n");
1881 bios_0_scratch
&= ~ATOM_S0_CRT1_MASK
;
1882 bios_3_scratch
&= ~ATOM_S3_CRT1_ACTIVE
;
1883 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT1
;
1886 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) &&
1887 (amdgpu_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)) {
1889 DRM_DEBUG_KMS("CRT2 connected\n");
1890 bios_0_scratch
|= ATOM_S0_CRT2_COLOR
;
1891 bios_3_scratch
|= ATOM_S3_CRT2_ACTIVE
;
1892 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT2
;
1894 DRM_DEBUG_KMS("CRT2 disconnected\n");
1895 bios_0_scratch
&= ~ATOM_S0_CRT2_MASK
;
1896 bios_3_scratch
&= ~ATOM_S3_CRT2_ACTIVE
;
1897 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT2
;
1900 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) &&
1901 (amdgpu_connector
->devices
& ATOM_DEVICE_DFP1_SUPPORT
)) {
1903 DRM_DEBUG_KMS("DFP1 connected\n");
1904 bios_0_scratch
|= ATOM_S0_DFP1
;
1905 bios_3_scratch
|= ATOM_S3_DFP1_ACTIVE
;
1906 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP1
;
1908 DRM_DEBUG_KMS("DFP1 disconnected\n");
1909 bios_0_scratch
&= ~ATOM_S0_DFP1
;
1910 bios_3_scratch
&= ~ATOM_S3_DFP1_ACTIVE
;
1911 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP1
;
1914 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) &&
1915 (amdgpu_connector
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
1917 DRM_DEBUG_KMS("DFP2 connected\n");
1918 bios_0_scratch
|= ATOM_S0_DFP2
;
1919 bios_3_scratch
|= ATOM_S3_DFP2_ACTIVE
;
1920 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP2
;
1922 DRM_DEBUG_KMS("DFP2 disconnected\n");
1923 bios_0_scratch
&= ~ATOM_S0_DFP2
;
1924 bios_3_scratch
&= ~ATOM_S3_DFP2_ACTIVE
;
1925 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP2
;
1928 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) &&
1929 (amdgpu_connector
->devices
& ATOM_DEVICE_DFP3_SUPPORT
)) {
1931 DRM_DEBUG_KMS("DFP3 connected\n");
1932 bios_0_scratch
|= ATOM_S0_DFP3
;
1933 bios_3_scratch
|= ATOM_S3_DFP3_ACTIVE
;
1934 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP3
;
1936 DRM_DEBUG_KMS("DFP3 disconnected\n");
1937 bios_0_scratch
&= ~ATOM_S0_DFP3
;
1938 bios_3_scratch
&= ~ATOM_S3_DFP3_ACTIVE
;
1939 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP3
;
1942 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) &&
1943 (amdgpu_connector
->devices
& ATOM_DEVICE_DFP4_SUPPORT
)) {
1945 DRM_DEBUG_KMS("DFP4 connected\n");
1946 bios_0_scratch
|= ATOM_S0_DFP4
;
1947 bios_3_scratch
|= ATOM_S3_DFP4_ACTIVE
;
1948 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP4
;
1950 DRM_DEBUG_KMS("DFP4 disconnected\n");
1951 bios_0_scratch
&= ~ATOM_S0_DFP4
;
1952 bios_3_scratch
&= ~ATOM_S3_DFP4_ACTIVE
;
1953 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP4
;
1956 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) &&
1957 (amdgpu_connector
->devices
& ATOM_DEVICE_DFP5_SUPPORT
)) {
1959 DRM_DEBUG_KMS("DFP5 connected\n");
1960 bios_0_scratch
|= ATOM_S0_DFP5
;
1961 bios_3_scratch
|= ATOM_S3_DFP5_ACTIVE
;
1962 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP5
;
1964 DRM_DEBUG_KMS("DFP5 disconnected\n");
1965 bios_0_scratch
&= ~ATOM_S0_DFP5
;
1966 bios_3_scratch
&= ~ATOM_S3_DFP5_ACTIVE
;
1967 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP5
;
1970 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_DFP6_SUPPORT
) &&
1971 (amdgpu_connector
->devices
& ATOM_DEVICE_DFP6_SUPPORT
)) {
1973 DRM_DEBUG_KMS("DFP6 connected\n");
1974 bios_0_scratch
|= ATOM_S0_DFP6
;
1975 bios_3_scratch
|= ATOM_S3_DFP6_ACTIVE
;
1976 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP6
;
1978 DRM_DEBUG_KMS("DFP6 disconnected\n");
1979 bios_0_scratch
&= ~ATOM_S0_DFP6
;
1980 bios_3_scratch
&= ~ATOM_S3_DFP6_ACTIVE
;
1981 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP6
;
1985 WREG32(mmBIOS_SCRATCH_0
, bios_0_scratch
);
1986 WREG32(mmBIOS_SCRATCH_3
, bios_3_scratch
);
1987 WREG32(mmBIOS_SCRATCH_6
, bios_6_scratch
);
1991 struct _ATOM_LVDS_INFO info
;
1992 struct _ATOM_LVDS_INFO_V12 info_12
;
1995 struct amdgpu_encoder_atom_dig
*
1996 amdgpu_atombios_encoder_get_lcd_info(struct amdgpu_encoder
*encoder
)
1998 struct drm_device
*dev
= encoder
->base
.dev
;
1999 struct amdgpu_device
*adev
= dev
->dev_private
;
2000 struct amdgpu_mode_info
*mode_info
= &adev
->mode_info
;
2001 int index
= GetIndexIntoMasterTable(DATA
, LVDS_Info
);
2002 uint16_t data_offset
, misc
;
2003 union lvds_info
*lvds_info
;
2005 struct amdgpu_encoder_atom_dig
*lvds
= NULL
;
2006 int encoder_enum
= (encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
2008 if (amdgpu_atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2009 &frev
, &crev
, &data_offset
)) {
2011 (union lvds_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
2013 kzalloc(sizeof(struct amdgpu_encoder_atom_dig
), GFP_KERNEL
);
2018 lvds
->native_mode
.clock
=
2019 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usPixClk
) * 10;
2020 lvds
->native_mode
.hdisplay
=
2021 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHActive
);
2022 lvds
->native_mode
.vdisplay
=
2023 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVActive
);
2024 lvds
->native_mode
.htotal
= lvds
->native_mode
.hdisplay
+
2025 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHBlanking_Time
);
2026 lvds
->native_mode
.hsync_start
= lvds
->native_mode
.hdisplay
+
2027 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncOffset
);
2028 lvds
->native_mode
.hsync_end
= lvds
->native_mode
.hsync_start
+
2029 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncWidth
);
2030 lvds
->native_mode
.vtotal
= lvds
->native_mode
.vdisplay
+
2031 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVBlanking_Time
);
2032 lvds
->native_mode
.vsync_start
= lvds
->native_mode
.vdisplay
+
2033 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncOffset
);
2034 lvds
->native_mode
.vsync_end
= lvds
->native_mode
.vsync_start
+
2035 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncWidth
);
2036 lvds
->panel_pwr_delay
=
2037 le16_to_cpu(lvds_info
->info
.usOffDelayInMs
);
2038 lvds
->lcd_misc
= lvds_info
->info
.ucLVDS_Misc
;
2040 misc
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.susModeMiscInfo
.usAccess
);
2041 if (misc
& ATOM_VSYNC_POLARITY
)
2042 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
2043 if (misc
& ATOM_HSYNC_POLARITY
)
2044 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
2045 if (misc
& ATOM_COMPOSITESYNC
)
2046 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_CSYNC
;
2047 if (misc
& ATOM_INTERLACE
)
2048 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
2049 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
2050 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_DBLSCAN
;
2052 lvds
->native_mode
.width_mm
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.usImageHSize
);
2053 lvds
->native_mode
.height_mm
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.usImageVSize
);
2055 /* set crtc values */
2056 drm_mode_set_crtcinfo(&lvds
->native_mode
, CRTC_INTERLACE_HALVE_V
);
2058 lvds
->lcd_ss_id
= lvds_info
->info
.ucSS_Id
;
2060 encoder
->native_mode
= lvds
->native_mode
;
2062 if (encoder_enum
== 2)
2065 lvds
->linkb
= false;
2067 /* parse the lcd record table */
2068 if (le16_to_cpu(lvds_info
->info
.usModePatchTableOffset
)) {
2069 ATOM_FAKE_EDID_PATCH_RECORD
*fake_edid_record
;
2070 ATOM_PANEL_RESOLUTION_PATCH_RECORD
*panel_res_record
;
2071 bool bad_record
= false;
2074 if ((frev
== 1) && (crev
< 2))
2076 record
= (u8
*)(mode_info
->atom_context
->bios
+
2077 le16_to_cpu(lvds_info
->info
.usModePatchTableOffset
));
2080 record
= (u8
*)(mode_info
->atom_context
->bios
+
2082 le16_to_cpu(lvds_info
->info
.usModePatchTableOffset
));
2083 while (*record
!= ATOM_RECORD_END_TYPE
) {
2085 case LCD_MODE_PATCH_RECORD_MODE_TYPE
:
2086 record
+= sizeof(ATOM_PATCH_RECORD_MODE
);
2088 case LCD_RTS_RECORD_TYPE
:
2089 record
+= sizeof(ATOM_LCD_RTS_RECORD
);
2091 case LCD_CAP_RECORD_TYPE
:
2092 record
+= sizeof(ATOM_LCD_MODE_CONTROL_CAP
);
2094 case LCD_FAKE_EDID_PATCH_RECORD_TYPE
:
2095 fake_edid_record
= (ATOM_FAKE_EDID_PATCH_RECORD
*)record
;
2096 if (fake_edid_record
->ucFakeEDIDLength
) {
2099 max((int)EDID_LENGTH
, (int)fake_edid_record
->ucFakeEDIDLength
);
2100 edid
= kmalloc(edid_size
, GFP_KERNEL
);
2102 memcpy((u8
*)edid
, (u8
*)&fake_edid_record
->ucFakeEDIDString
[0],
2103 fake_edid_record
->ucFakeEDIDLength
);
2105 if (drm_edid_is_valid(edid
)) {
2106 adev
->mode_info
.bios_hardcoded_edid
= edid
;
2107 adev
->mode_info
.bios_hardcoded_edid_size
= edid_size
;
2112 record
+= fake_edid_record
->ucFakeEDIDLength
?
2113 fake_edid_record
->ucFakeEDIDLength
+ 2 :
2114 sizeof(ATOM_FAKE_EDID_PATCH_RECORD
);
2116 case LCD_PANEL_RESOLUTION_RECORD_TYPE
:
2117 panel_res_record
= (ATOM_PANEL_RESOLUTION_PATCH_RECORD
*)record
;
2118 lvds
->native_mode
.width_mm
= panel_res_record
->usHSize
;
2119 lvds
->native_mode
.height_mm
= panel_res_record
->usVSize
;
2120 record
+= sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD
);
2123 DRM_ERROR("Bad LCD record %d\n", *record
);
2135 struct amdgpu_encoder_atom_dig
*
2136 amdgpu_atombios_encoder_get_dig_info(struct amdgpu_encoder
*amdgpu_encoder
)
2138 int encoder_enum
= (amdgpu_encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
2139 struct amdgpu_encoder_atom_dig
*dig
= kzalloc(sizeof(struct amdgpu_encoder_atom_dig
), GFP_KERNEL
);
2144 /* coherent mode by default */
2145 dig
->coherent_mode
= true;
2146 dig
->dig_encoder
= -1;
2148 if (encoder_enum
== 2)