2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
27 #include "amdgpu_pm.h"
28 #include "amdgpu_ucode.h"
30 #include "amdgpu_dpm.h"
35 #include <linux/seq_file.h>
37 #include "smu/smu_7_0_1_d.h"
38 #include "smu/smu_7_0_1_sh_mask.h"
40 #include "dce/dce_8_0_d.h"
41 #include "dce/dce_8_0_sh_mask.h"
43 #include "bif/bif_4_1_d.h"
44 #include "bif/bif_4_1_sh_mask.h"
46 #include "gca/gfx_7_2_d.h"
47 #include "gca/gfx_7_2_sh_mask.h"
49 #include "gmc/gmc_7_1_d.h"
50 #include "gmc/gmc_7_1_sh_mask.h"
52 MODULE_FIRMWARE("radeon/bonaire_smc.bin");
53 MODULE_FIRMWARE("radeon/bonaire_k_smc.bin");
54 MODULE_FIRMWARE("radeon/hawaii_smc.bin");
55 MODULE_FIRMWARE("radeon/hawaii_k_smc.bin");
57 #define MC_CG_ARB_FREQ_F0 0x0a
58 #define MC_CG_ARB_FREQ_F1 0x0b
59 #define MC_CG_ARB_FREQ_F2 0x0c
60 #define MC_CG_ARB_FREQ_F3 0x0d
62 #define SMC_RAM_END 0x40000
64 #define VOLTAGE_SCALE 4
65 #define VOLTAGE_VID_OFFSET_SCALE1 625
66 #define VOLTAGE_VID_OFFSET_SCALE2 100
68 static const struct ci_pt_defaults defaults_hawaii_xt
=
70 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
71 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
72 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
75 static const struct ci_pt_defaults defaults_hawaii_pro
=
77 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
78 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
79 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
82 static const struct ci_pt_defaults defaults_bonaire_xt
=
84 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
85 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
86 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
90 static const struct ci_pt_defaults defaults_bonaire_pro
=
92 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
93 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F },
94 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
98 static const struct ci_pt_defaults defaults_saturn_xt
=
100 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
101 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D },
102 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
106 static const struct ci_pt_defaults defaults_saturn_pro
=
108 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
109 { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A },
110 { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
114 static const struct ci_pt_config_reg didt_config_ci
[] =
116 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
117 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
118 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
119 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
120 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
121 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
122 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
123 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
124 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
125 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
126 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
127 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
128 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND
},
129 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND
},
130 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND
},
131 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND
},
132 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND
},
133 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
134 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
135 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
136 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
137 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
138 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
139 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
140 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
141 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
142 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
143 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
144 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
145 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
146 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND
},
147 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND
},
148 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND
},
149 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND
},
150 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND
},
151 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
152 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
153 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
154 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
155 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
156 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
157 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
158 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
159 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
160 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
161 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
162 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
163 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
164 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND
},
165 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND
},
166 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND
},
167 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND
},
168 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND
},
169 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
170 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
171 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
172 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
173 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
174 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
175 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
176 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
177 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
178 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
179 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
180 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
181 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
182 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND
},
183 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND
},
184 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND
},
185 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND
},
186 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND
},
187 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND
},
191 static u8
ci_get_memory_module_index(struct amdgpu_device
*adev
)
193 return (u8
) ((RREG32(mmBIOS_SCRATCH_4
) >> 16) & 0xff);
196 #define MC_CG_ARB_FREQ_F0 0x0a
197 #define MC_CG_ARB_FREQ_F1 0x0b
198 #define MC_CG_ARB_FREQ_F2 0x0c
199 #define MC_CG_ARB_FREQ_F3 0x0d
201 static int ci_copy_and_switch_arb_sets(struct amdgpu_device
*adev
,
202 u32 arb_freq_src
, u32 arb_freq_dest
)
204 u32 mc_arb_dram_timing
;
205 u32 mc_arb_dram_timing2
;
209 switch (arb_freq_src
) {
210 case MC_CG_ARB_FREQ_F0
:
211 mc_arb_dram_timing
= RREG32(mmMC_ARB_DRAM_TIMING
);
212 mc_arb_dram_timing2
= RREG32(mmMC_ARB_DRAM_TIMING2
);
213 burst_time
= (RREG32(mmMC_ARB_BURST_TIME
) & MC_ARB_BURST_TIME__STATE0_MASK
) >>
214 MC_ARB_BURST_TIME__STATE0__SHIFT
;
216 case MC_CG_ARB_FREQ_F1
:
217 mc_arb_dram_timing
= RREG32(mmMC_ARB_DRAM_TIMING_1
);
218 mc_arb_dram_timing2
= RREG32(mmMC_ARB_DRAM_TIMING2_1
);
219 burst_time
= (RREG32(mmMC_ARB_BURST_TIME
) & MC_ARB_BURST_TIME__STATE1_MASK
) >>
220 MC_ARB_BURST_TIME__STATE1__SHIFT
;
226 switch (arb_freq_dest
) {
227 case MC_CG_ARB_FREQ_F0
:
228 WREG32(mmMC_ARB_DRAM_TIMING
, mc_arb_dram_timing
);
229 WREG32(mmMC_ARB_DRAM_TIMING2
, mc_arb_dram_timing2
);
230 WREG32_P(mmMC_ARB_BURST_TIME
, (burst_time
<< MC_ARB_BURST_TIME__STATE0__SHIFT
),
231 ~MC_ARB_BURST_TIME__STATE0_MASK
);
233 case MC_CG_ARB_FREQ_F1
:
234 WREG32(mmMC_ARB_DRAM_TIMING_1
, mc_arb_dram_timing
);
235 WREG32(mmMC_ARB_DRAM_TIMING2_1
, mc_arb_dram_timing2
);
236 WREG32_P(mmMC_ARB_BURST_TIME
, (burst_time
<< MC_ARB_BURST_TIME__STATE1__SHIFT
),
237 ~MC_ARB_BURST_TIME__STATE1_MASK
);
243 mc_cg_config
= RREG32(mmMC_CG_CONFIG
) | 0x0000000F;
244 WREG32(mmMC_CG_CONFIG
, mc_cg_config
);
245 WREG32_P(mmMC_ARB_CG
, (arb_freq_dest
) << MC_ARB_CG__CG_ARB_REQ__SHIFT
,
246 ~MC_ARB_CG__CG_ARB_REQ_MASK
);
251 static u8
ci_get_ddr3_mclk_frequency_ratio(u32 memory_clock
)
255 if (memory_clock
< 10000)
257 else if (memory_clock
>= 80000)
258 mc_para_index
= 0x0f;
260 mc_para_index
= (u8
)((memory_clock
- 10000) / 5000 + 1);
261 return mc_para_index
;
264 static u8
ci_get_mclk_frequency_ratio(u32 memory_clock
, bool strobe_mode
)
269 if (memory_clock
< 12500)
270 mc_para_index
= 0x00;
271 else if (memory_clock
> 47500)
272 mc_para_index
= 0x0f;
274 mc_para_index
= (u8
)((memory_clock
- 10000) / 2500);
276 if (memory_clock
< 65000)
277 mc_para_index
= 0x00;
278 else if (memory_clock
> 135000)
279 mc_para_index
= 0x0f;
281 mc_para_index
= (u8
)((memory_clock
- 60000) / 5000);
283 return mc_para_index
;
286 static void ci_trim_voltage_table_to_fit_state_table(struct amdgpu_device
*adev
,
287 u32 max_voltage_steps
,
288 struct atom_voltage_table
*voltage_table
)
290 unsigned int i
, diff
;
292 if (voltage_table
->count
<= max_voltage_steps
)
295 diff
= voltage_table
->count
- max_voltage_steps
;
297 for (i
= 0; i
< max_voltage_steps
; i
++)
298 voltage_table
->entries
[i
] = voltage_table
->entries
[i
+ diff
];
300 voltage_table
->count
= max_voltage_steps
;
303 static int ci_get_std_voltage_value_sidd(struct amdgpu_device
*adev
,
304 struct atom_voltage_table_entry
*voltage_table
,
305 u16
*std_voltage_hi_sidd
, u16
*std_voltage_lo_sidd
);
306 static int ci_set_power_limit(struct amdgpu_device
*adev
, u32 n
);
307 static int ci_set_overdrive_target_tdp(struct amdgpu_device
*adev
,
309 static int ci_update_uvd_dpm(struct amdgpu_device
*adev
, bool gate
);
310 static void ci_dpm_set_dpm_funcs(struct amdgpu_device
*adev
);
311 static void ci_dpm_set_irq_funcs(struct amdgpu_device
*adev
);
313 static PPSMC_Result
amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device
*adev
,
314 PPSMC_Msg msg
, u32 parameter
);
315 static void ci_thermal_start_smc_fan_control(struct amdgpu_device
*adev
);
316 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device
*adev
);
318 static struct ci_power_info
*ci_get_pi(struct amdgpu_device
*adev
)
320 struct ci_power_info
*pi
= adev
->pm
.dpm
.priv
;
325 static struct ci_ps
*ci_get_ps(struct amdgpu_ps
*rps
)
327 struct ci_ps
*ps
= rps
->ps_priv
;
332 static void ci_initialize_powertune_defaults(struct amdgpu_device
*adev
)
334 struct ci_power_info
*pi
= ci_get_pi(adev
);
336 switch (adev
->pdev
->device
) {
344 pi
->powertune_defaults
= &defaults_bonaire_xt
;
350 pi
->powertune_defaults
= &defaults_saturn_xt
;
354 pi
->powertune_defaults
= &defaults_hawaii_xt
;
358 pi
->powertune_defaults
= &defaults_hawaii_pro
;
368 pi
->powertune_defaults
= &defaults_bonaire_xt
;
372 pi
->dte_tj_offset
= 0;
374 pi
->caps_power_containment
= true;
375 pi
->caps_cac
= false;
376 pi
->caps_sq_ramping
= false;
377 pi
->caps_db_ramping
= false;
378 pi
->caps_td_ramping
= false;
379 pi
->caps_tcp_ramping
= false;
381 if (pi
->caps_power_containment
) {
383 if (adev
->asic_type
== CHIP_HAWAII
)
384 pi
->enable_bapm_feature
= false;
386 pi
->enable_bapm_feature
= true;
387 pi
->enable_tdc_limit_feature
= true;
388 pi
->enable_pkg_pwr_tracking_feature
= true;
392 static u8
ci_convert_to_vid(u16 vddc
)
394 return (6200 - (vddc
* VOLTAGE_SCALE
)) / 25;
397 static int ci_populate_bapm_vddc_vid_sidd(struct amdgpu_device
*adev
)
399 struct ci_power_info
*pi
= ci_get_pi(adev
);
400 u8
*hi_vid
= pi
->smc_powertune_table
.BapmVddCVidHiSidd
;
401 u8
*lo_vid
= pi
->smc_powertune_table
.BapmVddCVidLoSidd
;
402 u8
*hi2_vid
= pi
->smc_powertune_table
.BapmVddCVidHiSidd2
;
405 if (adev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
== NULL
)
407 if (adev
->pm
.dpm
.dyn_state
.cac_leakage_table
.count
> 8)
409 if (adev
->pm
.dpm
.dyn_state
.cac_leakage_table
.count
!=
410 adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.count
)
413 for (i
= 0; i
< adev
->pm
.dpm
.dyn_state
.cac_leakage_table
.count
; i
++) {
414 if (adev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_EVV
) {
415 lo_vid
[i
] = ci_convert_to_vid(adev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[i
].vddc1
);
416 hi_vid
[i
] = ci_convert_to_vid(adev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[i
].vddc2
);
417 hi2_vid
[i
] = ci_convert_to_vid(adev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[i
].vddc3
);
419 lo_vid
[i
] = ci_convert_to_vid(adev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[i
].vddc
);
420 hi_vid
[i
] = ci_convert_to_vid((u16
)adev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[i
].leakage
);
426 static int ci_populate_vddc_vid(struct amdgpu_device
*adev
)
428 struct ci_power_info
*pi
= ci_get_pi(adev
);
429 u8
*vid
= pi
->smc_powertune_table
.VddCVid
;
432 if (pi
->vddc_voltage_table
.count
> 8)
435 for (i
= 0; i
< pi
->vddc_voltage_table
.count
; i
++)
436 vid
[i
] = ci_convert_to_vid(pi
->vddc_voltage_table
.entries
[i
].value
);
441 static int ci_populate_svi_load_line(struct amdgpu_device
*adev
)
443 struct ci_power_info
*pi
= ci_get_pi(adev
);
444 const struct ci_pt_defaults
*pt_defaults
= pi
->powertune_defaults
;
446 pi
->smc_powertune_table
.SviLoadLineEn
= pt_defaults
->svi_load_line_en
;
447 pi
->smc_powertune_table
.SviLoadLineVddC
= pt_defaults
->svi_load_line_vddc
;
448 pi
->smc_powertune_table
.SviLoadLineTrimVddC
= 3;
449 pi
->smc_powertune_table
.SviLoadLineOffsetVddC
= 0;
454 static int ci_populate_tdc_limit(struct amdgpu_device
*adev
)
456 struct ci_power_info
*pi
= ci_get_pi(adev
);
457 const struct ci_pt_defaults
*pt_defaults
= pi
->powertune_defaults
;
460 tdc_limit
= adev
->pm
.dpm
.dyn_state
.cac_tdp_table
->tdc
* 256;
461 pi
->smc_powertune_table
.TDC_VDDC_PkgLimit
= cpu_to_be16(tdc_limit
);
462 pi
->smc_powertune_table
.TDC_VDDC_ThrottleReleaseLimitPerc
=
463 pt_defaults
->tdc_vddc_throttle_release_limit_perc
;
464 pi
->smc_powertune_table
.TDC_MAWt
= pt_defaults
->tdc_mawt
;
469 static int ci_populate_dw8(struct amdgpu_device
*adev
)
471 struct ci_power_info
*pi
= ci_get_pi(adev
);
472 const struct ci_pt_defaults
*pt_defaults
= pi
->powertune_defaults
;
475 ret
= amdgpu_ci_read_smc_sram_dword(adev
,
476 SMU7_FIRMWARE_HEADER_LOCATION
+
477 offsetof(SMU7_Firmware_Header
, PmFuseTable
) +
478 offsetof(SMU7_Discrete_PmFuses
, TdcWaterfallCtl
),
479 (u32
*)&pi
->smc_powertune_table
.TdcWaterfallCtl
,
484 pi
->smc_powertune_table
.TdcWaterfallCtl
= pt_defaults
->tdc_waterfall_ctl
;
489 static int ci_populate_fuzzy_fan(struct amdgpu_device
*adev
)
491 struct ci_power_info
*pi
= ci_get_pi(adev
);
493 if ((adev
->pm
.dpm
.fan
.fan_output_sensitivity
& (1 << 15)) ||
494 (adev
->pm
.dpm
.fan
.fan_output_sensitivity
== 0))
495 adev
->pm
.dpm
.fan
.fan_output_sensitivity
=
496 adev
->pm
.dpm
.fan
.default_fan_output_sensitivity
;
498 pi
->smc_powertune_table
.FuzzyFan_PwmSetDelta
=
499 cpu_to_be16(adev
->pm
.dpm
.fan
.fan_output_sensitivity
);
504 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct amdgpu_device
*adev
)
506 struct ci_power_info
*pi
= ci_get_pi(adev
);
507 u8
*hi_vid
= pi
->smc_powertune_table
.BapmVddCVidHiSidd
;
508 u8
*lo_vid
= pi
->smc_powertune_table
.BapmVddCVidLoSidd
;
511 min
= max
= hi_vid
[0];
512 for (i
= 0; i
< 8; i
++) {
513 if (0 != hi_vid
[i
]) {
520 if (0 != lo_vid
[i
]) {
528 if ((min
== 0) || (max
== 0))
530 pi
->smc_powertune_table
.GnbLPMLMaxVid
= (u8
)max
;
531 pi
->smc_powertune_table
.GnbLPMLMinVid
= (u8
)min
;
536 static int ci_populate_bapm_vddc_base_leakage_sidd(struct amdgpu_device
*adev
)
538 struct ci_power_info
*pi
= ci_get_pi(adev
);
539 u16 hi_sidd
= pi
->smc_powertune_table
.BapmVddCBaseLeakageHiSidd
;
540 u16 lo_sidd
= pi
->smc_powertune_table
.BapmVddCBaseLeakageLoSidd
;
541 struct amdgpu_cac_tdp_table
*cac_tdp_table
=
542 adev
->pm
.dpm
.dyn_state
.cac_tdp_table
;
544 hi_sidd
= cac_tdp_table
->high_cac_leakage
/ 100 * 256;
545 lo_sidd
= cac_tdp_table
->low_cac_leakage
/ 100 * 256;
547 pi
->smc_powertune_table
.BapmVddCBaseLeakageHiSidd
= cpu_to_be16(hi_sidd
);
548 pi
->smc_powertune_table
.BapmVddCBaseLeakageLoSidd
= cpu_to_be16(lo_sidd
);
553 static int ci_populate_bapm_parameters_in_dpm_table(struct amdgpu_device
*adev
)
555 struct ci_power_info
*pi
= ci_get_pi(adev
);
556 const struct ci_pt_defaults
*pt_defaults
= pi
->powertune_defaults
;
557 SMU7_Discrete_DpmTable
*dpm_table
= &pi
->smc_state_table
;
558 struct amdgpu_cac_tdp_table
*cac_tdp_table
=
559 adev
->pm
.dpm
.dyn_state
.cac_tdp_table
;
560 struct amdgpu_ppm_table
*ppm
= adev
->pm
.dpm
.dyn_state
.ppm_table
;
565 dpm_table
->DefaultTdp
= cac_tdp_table
->tdp
* 256;
566 dpm_table
->TargetTdp
= cac_tdp_table
->configurable_tdp
* 256;
568 dpm_table
->DTETjOffset
= (u8
)pi
->dte_tj_offset
;
569 dpm_table
->GpuTjMax
=
570 (u8
)(pi
->thermal_temp_setting
.temperature_high
/ 1000);
571 dpm_table
->GpuTjHyst
= 8;
573 dpm_table
->DTEAmbientTempBase
= pt_defaults
->dte_ambient_temp_base
;
576 dpm_table
->PPM_PkgPwrLimit
= cpu_to_be16((u16
)ppm
->dgpu_tdp
* 256 / 1000);
577 dpm_table
->PPM_TemperatureLimit
= cpu_to_be16((u16
)ppm
->tj_max
* 256);
579 dpm_table
->PPM_PkgPwrLimit
= cpu_to_be16(0);
580 dpm_table
->PPM_TemperatureLimit
= cpu_to_be16(0);
583 dpm_table
->BAPM_TEMP_GRADIENT
= cpu_to_be32(pt_defaults
->bapm_temp_gradient
);
584 def1
= pt_defaults
->bapmti_r
;
585 def2
= pt_defaults
->bapmti_rc
;
587 for (i
= 0; i
< SMU7_DTE_ITERATIONS
; i
++) {
588 for (j
= 0; j
< SMU7_DTE_SOURCES
; j
++) {
589 for (k
= 0; k
< SMU7_DTE_SINKS
; k
++) {
590 dpm_table
->BAPMTI_R
[i
][j
][k
] = cpu_to_be16(*def1
);
591 dpm_table
->BAPMTI_RC
[i
][j
][k
] = cpu_to_be16(*def2
);
601 static int ci_populate_pm_base(struct amdgpu_device
*adev
)
603 struct ci_power_info
*pi
= ci_get_pi(adev
);
604 u32 pm_fuse_table_offset
;
607 if (pi
->caps_power_containment
) {
608 ret
= amdgpu_ci_read_smc_sram_dword(adev
,
609 SMU7_FIRMWARE_HEADER_LOCATION
+
610 offsetof(SMU7_Firmware_Header
, PmFuseTable
),
611 &pm_fuse_table_offset
, pi
->sram_end
);
614 ret
= ci_populate_bapm_vddc_vid_sidd(adev
);
617 ret
= ci_populate_vddc_vid(adev
);
620 ret
= ci_populate_svi_load_line(adev
);
623 ret
= ci_populate_tdc_limit(adev
);
626 ret
= ci_populate_dw8(adev
);
629 ret
= ci_populate_fuzzy_fan(adev
);
632 ret
= ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(adev
);
635 ret
= ci_populate_bapm_vddc_base_leakage_sidd(adev
);
638 ret
= amdgpu_ci_copy_bytes_to_smc(adev
, pm_fuse_table_offset
,
639 (u8
*)&pi
->smc_powertune_table
,
640 sizeof(SMU7_Discrete_PmFuses
), pi
->sram_end
);
648 static void ci_do_enable_didt(struct amdgpu_device
*adev
, const bool enable
)
650 struct ci_power_info
*pi
= ci_get_pi(adev
);
653 if (pi
->caps_sq_ramping
) {
654 data
= RREG32_DIDT(ixDIDT_SQ_CTRL0
);
656 data
|= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK
;
658 data
&= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK
;
659 WREG32_DIDT(ixDIDT_SQ_CTRL0
, data
);
662 if (pi
->caps_db_ramping
) {
663 data
= RREG32_DIDT(ixDIDT_DB_CTRL0
);
665 data
|= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK
;
667 data
&= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK
;
668 WREG32_DIDT(ixDIDT_DB_CTRL0
, data
);
671 if (pi
->caps_td_ramping
) {
672 data
= RREG32_DIDT(ixDIDT_TD_CTRL0
);
674 data
|= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK
;
676 data
&= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK
;
677 WREG32_DIDT(ixDIDT_TD_CTRL0
, data
);
680 if (pi
->caps_tcp_ramping
) {
681 data
= RREG32_DIDT(ixDIDT_TCP_CTRL0
);
683 data
|= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK
;
685 data
&= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK
;
686 WREG32_DIDT(ixDIDT_TCP_CTRL0
, data
);
690 static int ci_program_pt_config_registers(struct amdgpu_device
*adev
,
691 const struct ci_pt_config_reg
*cac_config_regs
)
693 const struct ci_pt_config_reg
*config_regs
= cac_config_regs
;
697 if (config_regs
== NULL
)
700 while (config_regs
->offset
!= 0xFFFFFFFF) {
701 if (config_regs
->type
== CISLANDS_CONFIGREG_CACHE
) {
702 cache
|= ((config_regs
->value
<< config_regs
->shift
) & config_regs
->mask
);
704 switch (config_regs
->type
) {
705 case CISLANDS_CONFIGREG_SMC_IND
:
706 data
= RREG32_SMC(config_regs
->offset
);
708 case CISLANDS_CONFIGREG_DIDT_IND
:
709 data
= RREG32_DIDT(config_regs
->offset
);
712 data
= RREG32(config_regs
->offset
);
716 data
&= ~config_regs
->mask
;
717 data
|= ((config_regs
->value
<< config_regs
->shift
) & config_regs
->mask
);
720 switch (config_regs
->type
) {
721 case CISLANDS_CONFIGREG_SMC_IND
:
722 WREG32_SMC(config_regs
->offset
, data
);
724 case CISLANDS_CONFIGREG_DIDT_IND
:
725 WREG32_DIDT(config_regs
->offset
, data
);
728 WREG32(config_regs
->offset
, data
);
738 static int ci_enable_didt(struct amdgpu_device
*adev
, bool enable
)
740 struct ci_power_info
*pi
= ci_get_pi(adev
);
743 if (pi
->caps_sq_ramping
|| pi
->caps_db_ramping
||
744 pi
->caps_td_ramping
|| pi
->caps_tcp_ramping
) {
745 adev
->gfx
.rlc
.funcs
->enter_safe_mode(adev
);
748 ret
= ci_program_pt_config_registers(adev
, didt_config_ci
);
750 adev
->gfx
.rlc
.funcs
->exit_safe_mode(adev
);
755 ci_do_enable_didt(adev
, enable
);
757 adev
->gfx
.rlc
.funcs
->exit_safe_mode(adev
);
763 static int ci_enable_power_containment(struct amdgpu_device
*adev
, bool enable
)
765 struct ci_power_info
*pi
= ci_get_pi(adev
);
766 PPSMC_Result smc_result
;
770 pi
->power_containment_features
= 0;
771 if (pi
->caps_power_containment
) {
772 if (pi
->enable_bapm_feature
) {
773 smc_result
= amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_EnableDTE
);
774 if (smc_result
!= PPSMC_Result_OK
)
777 pi
->power_containment_features
|= POWERCONTAINMENT_FEATURE_BAPM
;
780 if (pi
->enable_tdc_limit_feature
) {
781 smc_result
= amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_TDCLimitEnable
);
782 if (smc_result
!= PPSMC_Result_OK
)
785 pi
->power_containment_features
|= POWERCONTAINMENT_FEATURE_TDCLimit
;
788 if (pi
->enable_pkg_pwr_tracking_feature
) {
789 smc_result
= amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_PkgPwrLimitEnable
);
790 if (smc_result
!= PPSMC_Result_OK
) {
793 struct amdgpu_cac_tdp_table
*cac_tdp_table
=
794 adev
->pm
.dpm
.dyn_state
.cac_tdp_table
;
795 u32 default_pwr_limit
=
796 (u32
)(cac_tdp_table
->maximum_power_delivery_limit
* 256);
798 pi
->power_containment_features
|= POWERCONTAINMENT_FEATURE_PkgPwrLimit
;
800 ci_set_power_limit(adev
, default_pwr_limit
);
805 if (pi
->caps_power_containment
&& pi
->power_containment_features
) {
806 if (pi
->power_containment_features
& POWERCONTAINMENT_FEATURE_TDCLimit
)
807 amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_TDCLimitDisable
);
809 if (pi
->power_containment_features
& POWERCONTAINMENT_FEATURE_BAPM
)
810 amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_DisableDTE
);
812 if (pi
->power_containment_features
& POWERCONTAINMENT_FEATURE_PkgPwrLimit
)
813 amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_PkgPwrLimitDisable
);
814 pi
->power_containment_features
= 0;
821 static int ci_enable_smc_cac(struct amdgpu_device
*adev
, bool enable
)
823 struct ci_power_info
*pi
= ci_get_pi(adev
);
824 PPSMC_Result smc_result
;
829 smc_result
= amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_EnableCac
);
830 if (smc_result
!= PPSMC_Result_OK
) {
832 pi
->cac_enabled
= false;
834 pi
->cac_enabled
= true;
836 } else if (pi
->cac_enabled
) {
837 amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_DisableCac
);
838 pi
->cac_enabled
= false;
845 static int ci_enable_thermal_based_sclk_dpm(struct amdgpu_device
*adev
,
848 struct ci_power_info
*pi
= ci_get_pi(adev
);
849 PPSMC_Result smc_result
= PPSMC_Result_OK
;
851 if (pi
->thermal_sclk_dpm_enabled
) {
853 smc_result
= amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_ENABLE_THERMAL_DPM
);
855 smc_result
= amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_DISABLE_THERMAL_DPM
);
858 if (smc_result
== PPSMC_Result_OK
)
864 static int ci_power_control_set_level(struct amdgpu_device
*adev
)
866 struct ci_power_info
*pi
= ci_get_pi(adev
);
867 struct amdgpu_cac_tdp_table
*cac_tdp_table
=
868 adev
->pm
.dpm
.dyn_state
.cac_tdp_table
;
872 bool adjust_polarity
= false; /* ??? */
874 if (pi
->caps_power_containment
) {
875 adjust_percent
= adjust_polarity
?
876 adev
->pm
.dpm
.tdp_adjustment
: (-1 * adev
->pm
.dpm
.tdp_adjustment
);
877 target_tdp
= ((100 + adjust_percent
) *
878 (s32
)cac_tdp_table
->configurable_tdp
) / 100;
880 ret
= ci_set_overdrive_target_tdp(adev
, (u32
)target_tdp
);
886 static void ci_dpm_powergate_uvd(struct amdgpu_device
*adev
, bool gate
)
888 struct ci_power_info
*pi
= ci_get_pi(adev
);
890 pi
->uvd_power_gated
= gate
;
893 /* stop the UVD block */
894 amdgpu_set_powergating_state(adev
, AMD_IP_BLOCK_TYPE_UVD
,
896 ci_update_uvd_dpm(adev
, gate
);
898 amdgpu_set_powergating_state(adev
, AMD_IP_BLOCK_TYPE_UVD
,
899 AMD_PG_STATE_UNGATE
);
900 ci_update_uvd_dpm(adev
, gate
);
904 static bool ci_dpm_vblank_too_short(struct amdgpu_device
*adev
)
906 u32 vblank_time
= amdgpu_dpm_get_vblank_time(adev
);
907 u32 switch_limit
= adev
->mc
.vram_type
== AMDGPU_VRAM_TYPE_GDDR5
? 450 : 300;
909 /* disable mclk switching if the refresh is >120Hz, even if the
910 * blanking period would allow it
912 if (amdgpu_dpm_get_vrefresh(adev
) > 120)
915 if (vblank_time
< switch_limit
)
922 static void ci_apply_state_adjust_rules(struct amdgpu_device
*adev
,
923 struct amdgpu_ps
*rps
)
925 struct ci_ps
*ps
= ci_get_ps(rps
);
926 struct ci_power_info
*pi
= ci_get_pi(adev
);
927 struct amdgpu_clock_and_voltage_limits
*max_limits
;
928 bool disable_mclk_switching
;
932 if (rps
->vce_active
) {
933 rps
->evclk
= adev
->pm
.dpm
.vce_states
[adev
->pm
.dpm
.vce_level
].evclk
;
934 rps
->ecclk
= adev
->pm
.dpm
.vce_states
[adev
->pm
.dpm
.vce_level
].ecclk
;
940 if ((adev
->pm
.dpm
.new_active_crtc_count
> 1) ||
941 ci_dpm_vblank_too_short(adev
))
942 disable_mclk_switching
= true;
944 disable_mclk_switching
= false;
946 if ((rps
->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK
) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
)
947 pi
->battery_state
= true;
949 pi
->battery_state
= false;
951 if (adev
->pm
.dpm
.ac_power
)
952 max_limits
= &adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
;
954 max_limits
= &adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_dc
;
956 if (adev
->pm
.dpm
.ac_power
== false) {
957 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
958 if (ps
->performance_levels
[i
].mclk
> max_limits
->mclk
)
959 ps
->performance_levels
[i
].mclk
= max_limits
->mclk
;
960 if (ps
->performance_levels
[i
].sclk
> max_limits
->sclk
)
961 ps
->performance_levels
[i
].sclk
= max_limits
->sclk
;
965 /* XXX validate the min clocks required for display */
967 if (disable_mclk_switching
) {
968 mclk
= ps
->performance_levels
[ps
->performance_level_count
- 1].mclk
;
969 sclk
= ps
->performance_levels
[0].sclk
;
971 mclk
= ps
->performance_levels
[0].mclk
;
972 sclk
= ps
->performance_levels
[0].sclk
;
975 if (adev
->pm
.pm_display_cfg
.min_core_set_clock
> sclk
)
976 sclk
= adev
->pm
.pm_display_cfg
.min_core_set_clock
;
978 if (adev
->pm
.pm_display_cfg
.min_mem_set_clock
> mclk
)
979 mclk
= adev
->pm
.pm_display_cfg
.min_mem_set_clock
;
981 if (rps
->vce_active
) {
982 if (sclk
< adev
->pm
.dpm
.vce_states
[adev
->pm
.dpm
.vce_level
].sclk
)
983 sclk
= adev
->pm
.dpm
.vce_states
[adev
->pm
.dpm
.vce_level
].sclk
;
984 if (mclk
< adev
->pm
.dpm
.vce_states
[adev
->pm
.dpm
.vce_level
].mclk
)
985 mclk
= adev
->pm
.dpm
.vce_states
[adev
->pm
.dpm
.vce_level
].mclk
;
988 ps
->performance_levels
[0].sclk
= sclk
;
989 ps
->performance_levels
[0].mclk
= mclk
;
991 if (ps
->performance_levels
[1].sclk
< ps
->performance_levels
[0].sclk
)
992 ps
->performance_levels
[1].sclk
= ps
->performance_levels
[0].sclk
;
994 if (disable_mclk_switching
) {
995 if (ps
->performance_levels
[0].mclk
< ps
->performance_levels
[1].mclk
)
996 ps
->performance_levels
[0].mclk
= ps
->performance_levels
[1].mclk
;
998 if (ps
->performance_levels
[1].mclk
< ps
->performance_levels
[0].mclk
)
999 ps
->performance_levels
[1].mclk
= ps
->performance_levels
[0].mclk
;
1003 static int ci_thermal_set_temperature_range(struct amdgpu_device
*adev
,
1004 int min_temp
, int max_temp
)
1006 int low_temp
= 0 * 1000;
1007 int high_temp
= 255 * 1000;
1010 if (low_temp
< min_temp
)
1011 low_temp
= min_temp
;
1012 if (high_temp
> max_temp
)
1013 high_temp
= max_temp
;
1014 if (high_temp
< low_temp
) {
1015 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp
, high_temp
);
1019 tmp
= RREG32_SMC(ixCG_THERMAL_INT
);
1020 tmp
&= ~(CG_THERMAL_INT__DIG_THERM_INTH_MASK
| CG_THERMAL_INT__DIG_THERM_INTL_MASK
);
1021 tmp
|= ((high_temp
/ 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT
) |
1022 ((low_temp
/ 1000)) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT
;
1023 WREG32_SMC(ixCG_THERMAL_INT
, tmp
);
1026 /* XXX: need to figure out how to handle this properly */
1027 tmp
= RREG32_SMC(ixCG_THERMAL_CTRL
);
1028 tmp
&= DIG_THERM_DPM_MASK
;
1029 tmp
|= DIG_THERM_DPM(high_temp
/ 1000);
1030 WREG32_SMC(ixCG_THERMAL_CTRL
, tmp
);
1033 adev
->pm
.dpm
.thermal
.min_temp
= low_temp
;
1034 adev
->pm
.dpm
.thermal
.max_temp
= high_temp
;
1038 static int ci_thermal_enable_alert(struct amdgpu_device
*adev
,
1041 u32 thermal_int
= RREG32_SMC(ixCG_THERMAL_INT
);
1042 PPSMC_Result result
;
1045 thermal_int
&= ~(CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK
|
1046 CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK
);
1047 WREG32_SMC(ixCG_THERMAL_INT
, thermal_int
);
1048 result
= amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_Thermal_Cntl_Enable
);
1049 if (result
!= PPSMC_Result_OK
) {
1050 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
1054 thermal_int
|= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK
|
1055 CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK
;
1056 WREG32_SMC(ixCG_THERMAL_INT
, thermal_int
);
1057 result
= amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_Thermal_Cntl_Disable
);
1058 if (result
!= PPSMC_Result_OK
) {
1059 DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
1067 static void ci_fan_ctrl_set_static_mode(struct amdgpu_device
*adev
, u32 mode
)
1069 struct ci_power_info
*pi
= ci_get_pi(adev
);
1072 if (pi
->fan_ctrl_is_in_default_mode
) {
1073 tmp
= (RREG32_SMC(ixCG_FDO_CTRL2
) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK
)
1074 >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT
;
1075 pi
->fan_ctrl_default_mode
= tmp
;
1076 tmp
= (RREG32_SMC(ixCG_FDO_CTRL2
) & CG_FDO_CTRL2__TMIN_MASK
)
1077 >> CG_FDO_CTRL2__TMIN__SHIFT
;
1079 pi
->fan_ctrl_is_in_default_mode
= false;
1082 tmp
= RREG32_SMC(ixCG_FDO_CTRL2
) & ~CG_FDO_CTRL2__TMIN_MASK
;
1083 tmp
|= 0 << CG_FDO_CTRL2__TMIN__SHIFT
;
1084 WREG32_SMC(ixCG_FDO_CTRL2
, tmp
);
1086 tmp
= RREG32_SMC(ixCG_FDO_CTRL2
) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK
;
1087 tmp
|= mode
<< CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT
;
1088 WREG32_SMC(ixCG_FDO_CTRL2
, tmp
);
1091 static int ci_thermal_setup_fan_table(struct amdgpu_device
*adev
)
1093 struct ci_power_info
*pi
= ci_get_pi(adev
);
1094 SMU7_Discrete_FanTable fan_table
= { FDO_MODE_HARDWARE
};
1096 u32 t_diff1
, t_diff2
, pwm_diff1
, pwm_diff2
;
1097 u16 fdo_min
, slope1
, slope2
;
1098 u32 reference_clock
, tmp
;
1102 if (!pi
->fan_table_start
) {
1103 adev
->pm
.dpm
.fan
.ucode_fan_control
= false;
1107 duty100
= (RREG32_SMC(ixCG_FDO_CTRL1
) & CG_FDO_CTRL1__FMAX_DUTY100_MASK
)
1108 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT
;
1111 adev
->pm
.dpm
.fan
.ucode_fan_control
= false;
1115 tmp64
= (u64
)adev
->pm
.dpm
.fan
.pwm_min
* duty100
;
1116 do_div(tmp64
, 10000);
1117 fdo_min
= (u16
)tmp64
;
1119 t_diff1
= adev
->pm
.dpm
.fan
.t_med
- adev
->pm
.dpm
.fan
.t_min
;
1120 t_diff2
= adev
->pm
.dpm
.fan
.t_high
- adev
->pm
.dpm
.fan
.t_med
;
1122 pwm_diff1
= adev
->pm
.dpm
.fan
.pwm_med
- adev
->pm
.dpm
.fan
.pwm_min
;
1123 pwm_diff2
= adev
->pm
.dpm
.fan
.pwm_high
- adev
->pm
.dpm
.fan
.pwm_med
;
1125 slope1
= (u16
)((50 + ((16 * duty100
* pwm_diff1
) / t_diff1
)) / 100);
1126 slope2
= (u16
)((50 + ((16 * duty100
* pwm_diff2
) / t_diff2
)) / 100);
1128 fan_table
.TempMin
= cpu_to_be16((50 + adev
->pm
.dpm
.fan
.t_min
) / 100);
1129 fan_table
.TempMed
= cpu_to_be16((50 + adev
->pm
.dpm
.fan
.t_med
) / 100);
1130 fan_table
.TempMax
= cpu_to_be16((50 + adev
->pm
.dpm
.fan
.t_max
) / 100);
1132 fan_table
.Slope1
= cpu_to_be16(slope1
);
1133 fan_table
.Slope2
= cpu_to_be16(slope2
);
1135 fan_table
.FdoMin
= cpu_to_be16(fdo_min
);
1137 fan_table
.HystDown
= cpu_to_be16(adev
->pm
.dpm
.fan
.t_hyst
);
1139 fan_table
.HystUp
= cpu_to_be16(1);
1141 fan_table
.HystSlope
= cpu_to_be16(1);
1143 fan_table
.TempRespLim
= cpu_to_be16(5);
1145 reference_clock
= amdgpu_asic_get_xclk(adev
);
1147 fan_table
.RefreshPeriod
= cpu_to_be32((adev
->pm
.dpm
.fan
.cycle_delay
*
1148 reference_clock
) / 1600);
1150 fan_table
.FdoMax
= cpu_to_be16((u16
)duty100
);
1152 tmp
= (RREG32_SMC(ixCG_MULT_THERMAL_CTRL
) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK
)
1153 >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT
;
1154 fan_table
.TempSrc
= (uint8_t)tmp
;
1156 ret
= amdgpu_ci_copy_bytes_to_smc(adev
,
1157 pi
->fan_table_start
,
1163 DRM_ERROR("Failed to load fan table to the SMC.");
1164 adev
->pm
.dpm
.fan
.ucode_fan_control
= false;
1170 static int ci_fan_ctrl_start_smc_fan_control(struct amdgpu_device
*adev
)
1172 struct ci_power_info
*pi
= ci_get_pi(adev
);
1175 if (pi
->caps_od_fuzzy_fan_control_support
) {
1176 ret
= amdgpu_ci_send_msg_to_smc_with_parameter(adev
,
1177 PPSMC_StartFanControl
,
1179 if (ret
!= PPSMC_Result_OK
)
1181 ret
= amdgpu_ci_send_msg_to_smc_with_parameter(adev
,
1182 PPSMC_MSG_SetFanPwmMax
,
1183 adev
->pm
.dpm
.fan
.default_max_fan_pwm
);
1184 if (ret
!= PPSMC_Result_OK
)
1187 ret
= amdgpu_ci_send_msg_to_smc_with_parameter(adev
,
1188 PPSMC_StartFanControl
,
1190 if (ret
!= PPSMC_Result_OK
)
1194 pi
->fan_is_controlled_by_smc
= true;
1199 static int ci_fan_ctrl_stop_smc_fan_control(struct amdgpu_device
*adev
)
1202 struct ci_power_info
*pi
= ci_get_pi(adev
);
1204 ret
= amdgpu_ci_send_msg_to_smc(adev
, PPSMC_StopFanControl
);
1205 if (ret
== PPSMC_Result_OK
) {
1206 pi
->fan_is_controlled_by_smc
= false;
1213 static int ci_dpm_get_fan_speed_percent(struct amdgpu_device
*adev
,
1219 if (adev
->pm
.no_fan
)
1222 duty100
= (RREG32_SMC(ixCG_FDO_CTRL1
) & CG_FDO_CTRL1__FMAX_DUTY100_MASK
)
1223 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT
;
1224 duty
= (RREG32_SMC(ixCG_THERMAL_STATUS
) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK
)
1225 >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT
;
1230 tmp64
= (u64
)duty
* 100;
1231 do_div(tmp64
, duty100
);
1232 *speed
= (u32
)tmp64
;
1240 static int ci_dpm_set_fan_speed_percent(struct amdgpu_device
*adev
,
1246 struct ci_power_info
*pi
= ci_get_pi(adev
);
1248 if (adev
->pm
.no_fan
)
1251 if (pi
->fan_is_controlled_by_smc
)
1257 duty100
= (RREG32_SMC(ixCG_FDO_CTRL1
) & CG_FDO_CTRL1__FMAX_DUTY100_MASK
)
1258 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT
;
1263 tmp64
= (u64
)speed
* duty100
;
1267 tmp
= RREG32_SMC(ixCG_FDO_CTRL0
) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK
;
1268 tmp
|= duty
<< CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT
;
1269 WREG32_SMC(ixCG_FDO_CTRL0
, tmp
);
1274 static void ci_dpm_set_fan_control_mode(struct amdgpu_device
*adev
, u32 mode
)
1277 case AMD_FAN_CTRL_NONE
:
1278 if (adev
->pm
.dpm
.fan
.ucode_fan_control
)
1279 ci_fan_ctrl_stop_smc_fan_control(adev
);
1280 ci_dpm_set_fan_speed_percent(adev
, 100);
1282 case AMD_FAN_CTRL_MANUAL
:
1283 if (adev
->pm
.dpm
.fan
.ucode_fan_control
)
1284 ci_fan_ctrl_stop_smc_fan_control(adev
);
1286 case AMD_FAN_CTRL_AUTO
:
1287 if (adev
->pm
.dpm
.fan
.ucode_fan_control
)
1288 ci_thermal_start_smc_fan_control(adev
);
1295 static u32
ci_dpm_get_fan_control_mode(struct amdgpu_device
*adev
)
1297 struct ci_power_info
*pi
= ci_get_pi(adev
);
1299 if (pi
->fan_is_controlled_by_smc
)
1300 return AMD_FAN_CTRL_AUTO
;
1302 return AMD_FAN_CTRL_MANUAL
;
1306 static int ci_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device
*adev
,
1310 u32 xclk
= amdgpu_asic_get_xclk(adev
);
1312 if (adev
->pm
.no_fan
)
1315 if (adev
->pm
.fan_pulses_per_revolution
== 0)
1318 tach_period
= (RREG32_SMC(ixCG_TACH_STATUS
) & CG_TACH_STATUS__TACH_PERIOD_MASK
)
1319 >> CG_TACH_STATUS__TACH_PERIOD__SHIFT
;
1320 if (tach_period
== 0)
1323 *speed
= 60 * xclk
* 10000 / tach_period
;
1328 static int ci_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device
*adev
,
1331 u32 tach_period
, tmp
;
1332 u32 xclk
= amdgpu_asic_get_xclk(adev
);
1334 if (adev
->pm
.no_fan
)
1337 if (adev
->pm
.fan_pulses_per_revolution
== 0)
1340 if ((speed
< adev
->pm
.fan_min_rpm
) ||
1341 (speed
> adev
->pm
.fan_max_rpm
))
1344 if (adev
->pm
.dpm
.fan
.ucode_fan_control
)
1345 ci_fan_ctrl_stop_smc_fan_control(adev
);
1347 tach_period
= 60 * xclk
* 10000 / (8 * speed
);
1348 tmp
= RREG32_SMC(ixCG_TACH_CTRL
) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK
;
1349 tmp
|= tach_period
<< CG_TACH_CTRL__TARGET_PERIOD__SHIFT
;
1350 WREG32_SMC(CG_TACH_CTRL
, tmp
);
1352 ci_fan_ctrl_set_static_mode(adev
, FDO_PWM_MODE_STATIC_RPM
);
1358 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device
*adev
)
1360 struct ci_power_info
*pi
= ci_get_pi(adev
);
1363 if (!pi
->fan_ctrl_is_in_default_mode
) {
1364 tmp
= RREG32_SMC(ixCG_FDO_CTRL2
) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK
;
1365 tmp
|= pi
->fan_ctrl_default_mode
<< CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT
;
1366 WREG32_SMC(ixCG_FDO_CTRL2
, tmp
);
1368 tmp
= RREG32_SMC(ixCG_FDO_CTRL2
) & ~CG_FDO_CTRL2__TMIN_MASK
;
1369 tmp
|= pi
->t_min
<< CG_FDO_CTRL2__TMIN__SHIFT
;
1370 WREG32_SMC(ixCG_FDO_CTRL2
, tmp
);
1371 pi
->fan_ctrl_is_in_default_mode
= true;
1375 static void ci_thermal_start_smc_fan_control(struct amdgpu_device
*adev
)
1377 if (adev
->pm
.dpm
.fan
.ucode_fan_control
) {
1378 ci_fan_ctrl_start_smc_fan_control(adev
);
1379 ci_fan_ctrl_set_static_mode(adev
, FDO_PWM_MODE_STATIC
);
1383 static void ci_thermal_initialize(struct amdgpu_device
*adev
)
1387 if (adev
->pm
.fan_pulses_per_revolution
) {
1388 tmp
= RREG32_SMC(ixCG_TACH_CTRL
) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK
;
1389 tmp
|= (adev
->pm
.fan_pulses_per_revolution
- 1)
1390 << CG_TACH_CTRL__EDGE_PER_REV__SHIFT
;
1391 WREG32_SMC(ixCG_TACH_CTRL
, tmp
);
1394 tmp
= RREG32_SMC(ixCG_FDO_CTRL2
) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK
;
1395 tmp
|= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT
;
1396 WREG32_SMC(ixCG_FDO_CTRL2
, tmp
);
1399 static int ci_thermal_start_thermal_controller(struct amdgpu_device
*adev
)
1403 ci_thermal_initialize(adev
);
1404 ret
= ci_thermal_set_temperature_range(adev
, CISLANDS_TEMP_RANGE_MIN
, CISLANDS_TEMP_RANGE_MAX
);
1407 ret
= ci_thermal_enable_alert(adev
, true);
1410 if (adev
->pm
.dpm
.fan
.ucode_fan_control
) {
1411 ret
= ci_thermal_setup_fan_table(adev
);
1414 ci_thermal_start_smc_fan_control(adev
);
1420 static void ci_thermal_stop_thermal_controller(struct amdgpu_device
*adev
)
1422 if (!adev
->pm
.no_fan
)
1423 ci_fan_ctrl_set_default_mode(adev
);
1426 static int ci_read_smc_soft_register(struct amdgpu_device
*adev
,
1427 u16 reg_offset
, u32
*value
)
1429 struct ci_power_info
*pi
= ci_get_pi(adev
);
1431 return amdgpu_ci_read_smc_sram_dword(adev
,
1432 pi
->soft_regs_start
+ reg_offset
,
1433 value
, pi
->sram_end
);
1436 static int ci_write_smc_soft_register(struct amdgpu_device
*adev
,
1437 u16 reg_offset
, u32 value
)
1439 struct ci_power_info
*pi
= ci_get_pi(adev
);
1441 return amdgpu_ci_write_smc_sram_dword(adev
,
1442 pi
->soft_regs_start
+ reg_offset
,
1443 value
, pi
->sram_end
);
1446 static void ci_init_fps_limits(struct amdgpu_device
*adev
)
1448 struct ci_power_info
*pi
= ci_get_pi(adev
);
1449 SMU7_Discrete_DpmTable
*table
= &pi
->smc_state_table
;
1455 table
->FpsHighT
= cpu_to_be16(tmp
);
1458 table
->FpsLowT
= cpu_to_be16(tmp
);
1462 static int ci_update_sclk_t(struct amdgpu_device
*adev
)
1464 struct ci_power_info
*pi
= ci_get_pi(adev
);
1466 u32 low_sclk_interrupt_t
= 0;
1468 if (pi
->caps_sclk_throttle_low_notification
) {
1469 low_sclk_interrupt_t
= cpu_to_be32(pi
->low_sclk_interrupt_t
);
1471 ret
= amdgpu_ci_copy_bytes_to_smc(adev
,
1472 pi
->dpm_table_start
+
1473 offsetof(SMU7_Discrete_DpmTable
, LowSclkInterruptT
),
1474 (u8
*)&low_sclk_interrupt_t
,
1475 sizeof(u32
), pi
->sram_end
);
1482 static void ci_get_leakage_voltages(struct amdgpu_device
*adev
)
1484 struct ci_power_info
*pi
= ci_get_pi(adev
);
1485 u16 leakage_id
, virtual_voltage_id
;
1489 pi
->vddc_leakage
.count
= 0;
1490 pi
->vddci_leakage
.count
= 0;
1492 if (adev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_EVV
) {
1493 for (i
= 0; i
< CISLANDS_MAX_LEAKAGE_COUNT
; i
++) {
1494 virtual_voltage_id
= ATOM_VIRTUAL_VOLTAGE_ID0
+ i
;
1495 if (amdgpu_atombios_get_voltage_evv(adev
, virtual_voltage_id
, &vddc
) != 0)
1497 if (vddc
!= 0 && vddc
!= virtual_voltage_id
) {
1498 pi
->vddc_leakage
.actual_voltage
[pi
->vddc_leakage
.count
] = vddc
;
1499 pi
->vddc_leakage
.leakage_id
[pi
->vddc_leakage
.count
] = virtual_voltage_id
;
1500 pi
->vddc_leakage
.count
++;
1503 } else if (amdgpu_atombios_get_leakage_id_from_vbios(adev
, &leakage_id
) == 0) {
1504 for (i
= 0; i
< CISLANDS_MAX_LEAKAGE_COUNT
; i
++) {
1505 virtual_voltage_id
= ATOM_VIRTUAL_VOLTAGE_ID0
+ i
;
1506 if (amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(adev
, &vddc
, &vddci
,
1509 if (vddc
!= 0 && vddc
!= virtual_voltage_id
) {
1510 pi
->vddc_leakage
.actual_voltage
[pi
->vddc_leakage
.count
] = vddc
;
1511 pi
->vddc_leakage
.leakage_id
[pi
->vddc_leakage
.count
] = virtual_voltage_id
;
1512 pi
->vddc_leakage
.count
++;
1514 if (vddci
!= 0 && vddci
!= virtual_voltage_id
) {
1515 pi
->vddci_leakage
.actual_voltage
[pi
->vddci_leakage
.count
] = vddci
;
1516 pi
->vddci_leakage
.leakage_id
[pi
->vddci_leakage
.count
] = virtual_voltage_id
;
1517 pi
->vddci_leakage
.count
++;
1524 static void ci_set_dpm_event_sources(struct amdgpu_device
*adev
, u32 sources
)
1526 struct ci_power_info
*pi
= ci_get_pi(adev
);
1527 bool want_thermal_protection
;
1528 enum amdgpu_dpm_event_src dpm_event_src
;
1534 want_thermal_protection
= false;
1536 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL
):
1537 want_thermal_protection
= true;
1538 dpm_event_src
= AMDGPU_DPM_EVENT_SRC_DIGITAL
;
1540 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
):
1541 want_thermal_protection
= true;
1542 dpm_event_src
= AMDGPU_DPM_EVENT_SRC_EXTERNAL
;
1544 case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
) |
1545 (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL
)):
1546 want_thermal_protection
= true;
1547 dpm_event_src
= AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL
;
1551 if (want_thermal_protection
) {
1553 /* XXX: need to figure out how to handle this properly */
1554 tmp
= RREG32_SMC(ixCG_THERMAL_CTRL
);
1555 tmp
&= DPM_EVENT_SRC_MASK
;
1556 tmp
|= DPM_EVENT_SRC(dpm_event_src
);
1557 WREG32_SMC(ixCG_THERMAL_CTRL
, tmp
);
1560 tmp
= RREG32_SMC(ixGENERAL_PWRMGT
);
1561 if (pi
->thermal_protection
)
1562 tmp
&= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK
;
1564 tmp
|= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK
;
1565 WREG32_SMC(ixGENERAL_PWRMGT
, tmp
);
1567 tmp
= RREG32_SMC(ixGENERAL_PWRMGT
);
1568 tmp
|= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK
;
1569 WREG32_SMC(ixGENERAL_PWRMGT
, tmp
);
1573 static void ci_enable_auto_throttle_source(struct amdgpu_device
*adev
,
1574 enum amdgpu_dpm_auto_throttle_src source
,
1577 struct ci_power_info
*pi
= ci_get_pi(adev
);
1580 if (!(pi
->active_auto_throttle_sources
& (1 << source
))) {
1581 pi
->active_auto_throttle_sources
|= 1 << source
;
1582 ci_set_dpm_event_sources(adev
, pi
->active_auto_throttle_sources
);
1585 if (pi
->active_auto_throttle_sources
& (1 << source
)) {
1586 pi
->active_auto_throttle_sources
&= ~(1 << source
);
1587 ci_set_dpm_event_sources(adev
, pi
->active_auto_throttle_sources
);
1592 static void ci_enable_vr_hot_gpio_interrupt(struct amdgpu_device
*adev
)
1594 if (adev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_REGULATOR_HOT
)
1595 amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_EnableVRHotGPIOInterrupt
);
1598 static int ci_unfreeze_sclk_mclk_dpm(struct amdgpu_device
*adev
)
1600 struct ci_power_info
*pi
= ci_get_pi(adev
);
1601 PPSMC_Result smc_result
;
1603 if (!pi
->need_update_smu7_dpm_table
)
1606 if ((!pi
->sclk_dpm_key_disabled
) &&
1607 (pi
->need_update_smu7_dpm_table
& (DPMTABLE_OD_UPDATE_SCLK
| DPMTABLE_UPDATE_SCLK
))) {
1608 smc_result
= amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_SCLKDPM_UnfreezeLevel
);
1609 if (smc_result
!= PPSMC_Result_OK
)
1613 if ((!pi
->mclk_dpm_key_disabled
) &&
1614 (pi
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_MCLK
)) {
1615 smc_result
= amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_MCLKDPM_UnfreezeLevel
);
1616 if (smc_result
!= PPSMC_Result_OK
)
1620 pi
->need_update_smu7_dpm_table
= 0;
1624 static int ci_enable_sclk_mclk_dpm(struct amdgpu_device
*adev
, bool enable
)
1626 struct ci_power_info
*pi
= ci_get_pi(adev
);
1627 PPSMC_Result smc_result
;
1630 if (!pi
->sclk_dpm_key_disabled
) {
1631 smc_result
= amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_DPM_Enable
);
1632 if (smc_result
!= PPSMC_Result_OK
)
1636 if (!pi
->mclk_dpm_key_disabled
) {
1637 smc_result
= amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_MCLKDPM_Enable
);
1638 if (smc_result
!= PPSMC_Result_OK
)
1641 WREG32_P(mmMC_SEQ_CNTL_3
, MC_SEQ_CNTL_3__CAC_EN_MASK
,
1642 ~MC_SEQ_CNTL_3__CAC_EN_MASK
);
1644 WREG32_SMC(ixLCAC_MC0_CNTL
, 0x05);
1645 WREG32_SMC(ixLCAC_MC1_CNTL
, 0x05);
1646 WREG32_SMC(ixLCAC_CPL_CNTL
, 0x100005);
1650 WREG32_SMC(ixLCAC_MC0_CNTL
, 0x400005);
1651 WREG32_SMC(ixLCAC_MC1_CNTL
, 0x400005);
1652 WREG32_SMC(ixLCAC_CPL_CNTL
, 0x500005);
1655 if (!pi
->sclk_dpm_key_disabled
) {
1656 smc_result
= amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_DPM_Disable
);
1657 if (smc_result
!= PPSMC_Result_OK
)
1661 if (!pi
->mclk_dpm_key_disabled
) {
1662 smc_result
= amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_MCLKDPM_Disable
);
1663 if (smc_result
!= PPSMC_Result_OK
)
1671 static int ci_start_dpm(struct amdgpu_device
*adev
)
1673 struct ci_power_info
*pi
= ci_get_pi(adev
);
1674 PPSMC_Result smc_result
;
1678 tmp
= RREG32_SMC(ixGENERAL_PWRMGT
);
1679 tmp
|= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK
;
1680 WREG32_SMC(ixGENERAL_PWRMGT
, tmp
);
1682 tmp
= RREG32_SMC(ixSCLK_PWRMGT_CNTL
);
1683 tmp
|= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK
;
1684 WREG32_SMC(ixSCLK_PWRMGT_CNTL
, tmp
);
1686 ci_write_smc_soft_register(adev
, offsetof(SMU7_SoftRegisters
, VoltageChangeTimeout
), 0x1000);
1688 WREG32_P(mmBIF_LNCNT_RESET
, 0, ~BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK
);
1690 smc_result
= amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_Voltage_Cntl_Enable
);
1691 if (smc_result
!= PPSMC_Result_OK
)
1694 ret
= ci_enable_sclk_mclk_dpm(adev
, true);
1698 if (!pi
->pcie_dpm_key_disabled
) {
1699 smc_result
= amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_PCIeDPM_Enable
);
1700 if (smc_result
!= PPSMC_Result_OK
)
1707 static int ci_freeze_sclk_mclk_dpm(struct amdgpu_device
*adev
)
1709 struct ci_power_info
*pi
= ci_get_pi(adev
);
1710 PPSMC_Result smc_result
;
1712 if (!pi
->need_update_smu7_dpm_table
)
1715 if ((!pi
->sclk_dpm_key_disabled
) &&
1716 (pi
->need_update_smu7_dpm_table
& (DPMTABLE_OD_UPDATE_SCLK
| DPMTABLE_UPDATE_SCLK
))) {
1717 smc_result
= amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_SCLKDPM_FreezeLevel
);
1718 if (smc_result
!= PPSMC_Result_OK
)
1722 if ((!pi
->mclk_dpm_key_disabled
) &&
1723 (pi
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_MCLK
)) {
1724 smc_result
= amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_MCLKDPM_FreezeLevel
);
1725 if (smc_result
!= PPSMC_Result_OK
)
1732 static int ci_stop_dpm(struct amdgpu_device
*adev
)
1734 struct ci_power_info
*pi
= ci_get_pi(adev
);
1735 PPSMC_Result smc_result
;
1739 tmp
= RREG32_SMC(ixGENERAL_PWRMGT
);
1740 tmp
&= ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK
;
1741 WREG32_SMC(ixGENERAL_PWRMGT
, tmp
);
1743 tmp
= RREG32_SMC(ixSCLK_PWRMGT_CNTL
);
1744 tmp
&= ~SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK
;
1745 WREG32_SMC(ixSCLK_PWRMGT_CNTL
, tmp
);
1747 if (!pi
->pcie_dpm_key_disabled
) {
1748 smc_result
= amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_PCIeDPM_Disable
);
1749 if (smc_result
!= PPSMC_Result_OK
)
1753 ret
= ci_enable_sclk_mclk_dpm(adev
, false);
1757 smc_result
= amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_Voltage_Cntl_Disable
);
1758 if (smc_result
!= PPSMC_Result_OK
)
1764 static void ci_enable_sclk_control(struct amdgpu_device
*adev
, bool enable
)
1766 u32 tmp
= RREG32_SMC(ixSCLK_PWRMGT_CNTL
);
1769 tmp
&= ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK
;
1771 tmp
|= SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK
;
1772 WREG32_SMC(ixSCLK_PWRMGT_CNTL
, tmp
);
1776 static int ci_notify_hw_of_power_source(struct amdgpu_device
*adev
,
1779 struct ci_power_info
*pi
= ci_get_pi(adev
);
1780 struct amdgpu_cac_tdp_table
*cac_tdp_table
=
1781 adev
->pm
.dpm
.dyn_state
.cac_tdp_table
;
1785 power_limit
= (u32
)(cac_tdp_table
->maximum_power_delivery_limit
* 256);
1787 power_limit
= (u32
)(cac_tdp_table
->battery_power_limit
* 256);
1789 ci_set_power_limit(adev
, power_limit
);
1791 if (pi
->caps_automatic_dc_transition
) {
1793 amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_RunningOnAC
);
1795 amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_Remove_DC_Clamp
);
1802 static PPSMC_Result
amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device
*adev
,
1803 PPSMC_Msg msg
, u32 parameter
)
1805 WREG32(mmSMC_MSG_ARG_0
, parameter
);
1806 return amdgpu_ci_send_msg_to_smc(adev
, msg
);
1809 static PPSMC_Result
amdgpu_ci_send_msg_to_smc_return_parameter(struct amdgpu_device
*adev
,
1810 PPSMC_Msg msg
, u32
*parameter
)
1812 PPSMC_Result smc_result
;
1814 smc_result
= amdgpu_ci_send_msg_to_smc(adev
, msg
);
1816 if ((smc_result
== PPSMC_Result_OK
) && parameter
)
1817 *parameter
= RREG32(mmSMC_MSG_ARG_0
);
1822 static int ci_dpm_force_state_sclk(struct amdgpu_device
*adev
, u32 n
)
1824 struct ci_power_info
*pi
= ci_get_pi(adev
);
1826 if (!pi
->sclk_dpm_key_disabled
) {
1827 PPSMC_Result smc_result
=
1828 amdgpu_ci_send_msg_to_smc_with_parameter(adev
, PPSMC_MSG_SCLKDPM_SetEnabledMask
, 1 << n
);
1829 if (smc_result
!= PPSMC_Result_OK
)
1836 static int ci_dpm_force_state_mclk(struct amdgpu_device
*adev
, u32 n
)
1838 struct ci_power_info
*pi
= ci_get_pi(adev
);
1840 if (!pi
->mclk_dpm_key_disabled
) {
1841 PPSMC_Result smc_result
=
1842 amdgpu_ci_send_msg_to_smc_with_parameter(adev
, PPSMC_MSG_MCLKDPM_SetEnabledMask
, 1 << n
);
1843 if (smc_result
!= PPSMC_Result_OK
)
1850 static int ci_dpm_force_state_pcie(struct amdgpu_device
*adev
, u32 n
)
1852 struct ci_power_info
*pi
= ci_get_pi(adev
);
1854 if (!pi
->pcie_dpm_key_disabled
) {
1855 PPSMC_Result smc_result
=
1856 amdgpu_ci_send_msg_to_smc_with_parameter(adev
, PPSMC_MSG_PCIeDPM_ForceLevel
, n
);
1857 if (smc_result
!= PPSMC_Result_OK
)
1864 static int ci_set_power_limit(struct amdgpu_device
*adev
, u32 n
)
1866 struct ci_power_info
*pi
= ci_get_pi(adev
);
1868 if (pi
->power_containment_features
& POWERCONTAINMENT_FEATURE_PkgPwrLimit
) {
1869 PPSMC_Result smc_result
=
1870 amdgpu_ci_send_msg_to_smc_with_parameter(adev
, PPSMC_MSG_PkgPwrSetLimit
, n
);
1871 if (smc_result
!= PPSMC_Result_OK
)
1878 static int ci_set_overdrive_target_tdp(struct amdgpu_device
*adev
,
1881 PPSMC_Result smc_result
=
1882 amdgpu_ci_send_msg_to_smc_with_parameter(adev
, PPSMC_MSG_OverDriveSetTargetTdp
, target_tdp
);
1883 if (smc_result
!= PPSMC_Result_OK
)
1889 static int ci_set_boot_state(struct amdgpu_device
*adev
)
1891 return ci_enable_sclk_mclk_dpm(adev
, false);
1895 static u32
ci_get_average_sclk_freq(struct amdgpu_device
*adev
)
1898 PPSMC_Result smc_result
=
1899 amdgpu_ci_send_msg_to_smc_return_parameter(adev
,
1900 PPSMC_MSG_API_GetSclkFrequency
,
1902 if (smc_result
!= PPSMC_Result_OK
)
1908 static u32
ci_get_average_mclk_freq(struct amdgpu_device
*adev
)
1911 PPSMC_Result smc_result
=
1912 amdgpu_ci_send_msg_to_smc_return_parameter(adev
,
1913 PPSMC_MSG_API_GetMclkFrequency
,
1915 if (smc_result
!= PPSMC_Result_OK
)
1921 static void ci_dpm_start_smc(struct amdgpu_device
*adev
)
1925 amdgpu_ci_program_jump_on_start(adev
);
1926 amdgpu_ci_start_smc_clock(adev
);
1927 amdgpu_ci_start_smc(adev
);
1928 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
1929 if (RREG32_SMC(ixFIRMWARE_FLAGS
) & FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK
)
1934 static void ci_dpm_stop_smc(struct amdgpu_device
*adev
)
1936 amdgpu_ci_reset_smc(adev
);
1937 amdgpu_ci_stop_smc_clock(adev
);
1940 static int ci_process_firmware_header(struct amdgpu_device
*adev
)
1942 struct ci_power_info
*pi
= ci_get_pi(adev
);
1946 ret
= amdgpu_ci_read_smc_sram_dword(adev
,
1947 SMU7_FIRMWARE_HEADER_LOCATION
+
1948 offsetof(SMU7_Firmware_Header
, DpmTable
),
1949 &tmp
, pi
->sram_end
);
1953 pi
->dpm_table_start
= tmp
;
1955 ret
= amdgpu_ci_read_smc_sram_dword(adev
,
1956 SMU7_FIRMWARE_HEADER_LOCATION
+
1957 offsetof(SMU7_Firmware_Header
, SoftRegisters
),
1958 &tmp
, pi
->sram_end
);
1962 pi
->soft_regs_start
= tmp
;
1964 ret
= amdgpu_ci_read_smc_sram_dword(adev
,
1965 SMU7_FIRMWARE_HEADER_LOCATION
+
1966 offsetof(SMU7_Firmware_Header
, mcRegisterTable
),
1967 &tmp
, pi
->sram_end
);
1971 pi
->mc_reg_table_start
= tmp
;
1973 ret
= amdgpu_ci_read_smc_sram_dword(adev
,
1974 SMU7_FIRMWARE_HEADER_LOCATION
+
1975 offsetof(SMU7_Firmware_Header
, FanTable
),
1976 &tmp
, pi
->sram_end
);
1980 pi
->fan_table_start
= tmp
;
1982 ret
= amdgpu_ci_read_smc_sram_dword(adev
,
1983 SMU7_FIRMWARE_HEADER_LOCATION
+
1984 offsetof(SMU7_Firmware_Header
, mcArbDramTimingTable
),
1985 &tmp
, pi
->sram_end
);
1989 pi
->arb_table_start
= tmp
;
1994 static void ci_read_clock_registers(struct amdgpu_device
*adev
)
1996 struct ci_power_info
*pi
= ci_get_pi(adev
);
1998 pi
->clock_registers
.cg_spll_func_cntl
=
1999 RREG32_SMC(ixCG_SPLL_FUNC_CNTL
);
2000 pi
->clock_registers
.cg_spll_func_cntl_2
=
2001 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2
);
2002 pi
->clock_registers
.cg_spll_func_cntl_3
=
2003 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3
);
2004 pi
->clock_registers
.cg_spll_func_cntl_4
=
2005 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4
);
2006 pi
->clock_registers
.cg_spll_spread_spectrum
=
2007 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM
);
2008 pi
->clock_registers
.cg_spll_spread_spectrum_2
=
2009 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2
);
2010 pi
->clock_registers
.dll_cntl
= RREG32(mmDLL_CNTL
);
2011 pi
->clock_registers
.mclk_pwrmgt_cntl
= RREG32(mmMCLK_PWRMGT_CNTL
);
2012 pi
->clock_registers
.mpll_ad_func_cntl
= RREG32(mmMPLL_AD_FUNC_CNTL
);
2013 pi
->clock_registers
.mpll_dq_func_cntl
= RREG32(mmMPLL_DQ_FUNC_CNTL
);
2014 pi
->clock_registers
.mpll_func_cntl
= RREG32(mmMPLL_FUNC_CNTL
);
2015 pi
->clock_registers
.mpll_func_cntl_1
= RREG32(mmMPLL_FUNC_CNTL_1
);
2016 pi
->clock_registers
.mpll_func_cntl_2
= RREG32(mmMPLL_FUNC_CNTL_2
);
2017 pi
->clock_registers
.mpll_ss1
= RREG32(mmMPLL_SS1
);
2018 pi
->clock_registers
.mpll_ss2
= RREG32(mmMPLL_SS2
);
2021 static void ci_init_sclk_t(struct amdgpu_device
*adev
)
2023 struct ci_power_info
*pi
= ci_get_pi(adev
);
2025 pi
->low_sclk_interrupt_t
= 0;
2028 static void ci_enable_thermal_protection(struct amdgpu_device
*adev
,
2031 u32 tmp
= RREG32_SMC(ixGENERAL_PWRMGT
);
2034 tmp
&= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK
;
2036 tmp
|= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK
;
2037 WREG32_SMC(ixGENERAL_PWRMGT
, tmp
);
2040 static void ci_enable_acpi_power_management(struct amdgpu_device
*adev
)
2042 u32 tmp
= RREG32_SMC(ixGENERAL_PWRMGT
);
2044 tmp
|= GENERAL_PWRMGT__STATIC_PM_EN_MASK
;
2046 WREG32_SMC(ixGENERAL_PWRMGT
, tmp
);
2050 static int ci_enter_ulp_state(struct amdgpu_device
*adev
)
2053 WREG32(mmSMC_MESSAGE_0
, PPSMC_MSG_SwitchToMinimumPower
);
2060 static int ci_exit_ulp_state(struct amdgpu_device
*adev
)
2064 WREG32(mmSMC_MESSAGE_0
, PPSMC_MSG_ResumeFromMinimumPower
);
2068 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
2069 if (RREG32(mmSMC_RESP_0
) == 1)
2078 static int ci_notify_smc_display_change(struct amdgpu_device
*adev
,
2081 PPSMC_Msg msg
= has_display
? PPSMC_MSG_HasDisplay
: PPSMC_MSG_NoDisplay
;
2083 return (amdgpu_ci_send_msg_to_smc(adev
, msg
) == PPSMC_Result_OK
) ? 0 : -EINVAL
;
2086 static int ci_enable_ds_master_switch(struct amdgpu_device
*adev
,
2089 struct ci_power_info
*pi
= ci_get_pi(adev
);
2092 if (pi
->caps_sclk_ds
) {
2093 if (amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_MASTER_DeepSleep_ON
) != PPSMC_Result_OK
)
2096 if (amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_MASTER_DeepSleep_OFF
) != PPSMC_Result_OK
)
2100 if (pi
->caps_sclk_ds
) {
2101 if (amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_MASTER_DeepSleep_OFF
) != PPSMC_Result_OK
)
2109 static void ci_program_display_gap(struct amdgpu_device
*adev
)
2111 u32 tmp
= RREG32_SMC(ixCG_DISPLAY_GAP_CNTL
);
2112 u32 pre_vbi_time_in_us
;
2113 u32 frame_time_in_us
;
2114 u32 ref_clock
= adev
->clock
.spll
.reference_freq
;
2115 u32 refresh_rate
= amdgpu_dpm_get_vrefresh(adev
);
2116 u32 vblank_time
= amdgpu_dpm_get_vblank_time(adev
);
2118 tmp
&= ~CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK
;
2119 if (adev
->pm
.dpm
.new_active_crtc_count
> 0)
2120 tmp
|= (AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM
<< CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT
);
2122 tmp
|= (AMDGPU_PM_DISPLAY_GAP_IGNORE
<< CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT
);
2123 WREG32_SMC(ixCG_DISPLAY_GAP_CNTL
, tmp
);
2125 if (refresh_rate
== 0)
2127 if (vblank_time
== 0xffffffff)
2129 frame_time_in_us
= 1000000 / refresh_rate
;
2130 pre_vbi_time_in_us
=
2131 frame_time_in_us
- 200 - vblank_time
;
2132 tmp
= pre_vbi_time_in_us
* (ref_clock
/ 100);
2134 WREG32_SMC(ixCG_DISPLAY_GAP_CNTL2
, tmp
);
2135 ci_write_smc_soft_register(adev
, offsetof(SMU7_SoftRegisters
, PreVBlankGap
), 0x64);
2136 ci_write_smc_soft_register(adev
, offsetof(SMU7_SoftRegisters
, VBlankTimeout
), (frame_time_in_us
- pre_vbi_time_in_us
));
2139 ci_notify_smc_display_change(adev
, (adev
->pm
.dpm
.new_active_crtc_count
== 1));
2143 static void ci_enable_spread_spectrum(struct amdgpu_device
*adev
, bool enable
)
2145 struct ci_power_info
*pi
= ci_get_pi(adev
);
2149 if (pi
->caps_sclk_ss_support
) {
2150 tmp
= RREG32_SMC(ixGENERAL_PWRMGT
);
2151 tmp
|= GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK
;
2152 WREG32_SMC(ixGENERAL_PWRMGT
, tmp
);
2155 tmp
= RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM
);
2156 tmp
&= ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK
;
2157 WREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM
, tmp
);
2159 tmp
= RREG32_SMC(ixGENERAL_PWRMGT
);
2160 tmp
&= ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK
;
2161 WREG32_SMC(ixGENERAL_PWRMGT
, tmp
);
2165 static void ci_program_sstp(struct amdgpu_device
*adev
)
2167 WREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER
,
2168 ((CISLANDS_SSTU_DFLT
<< CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT
) |
2169 (CISLANDS_SST_DFLT
<< CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT
)));
2172 static void ci_enable_display_gap(struct amdgpu_device
*adev
)
2174 u32 tmp
= RREG32_SMC(ixCG_DISPLAY_GAP_CNTL
);
2176 tmp
&= ~(CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK
|
2177 CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK
);
2178 tmp
|= ((AMDGPU_PM_DISPLAY_GAP_IGNORE
<< CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT
) |
2179 (AMDGPU_PM_DISPLAY_GAP_VBLANK
<< CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT
));
2181 WREG32_SMC(ixCG_DISPLAY_GAP_CNTL
, tmp
);
2184 static void ci_program_vc(struct amdgpu_device
*adev
)
2188 tmp
= RREG32_SMC(ixSCLK_PWRMGT_CNTL
);
2189 tmp
&= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK
| SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK
);
2190 WREG32_SMC(ixSCLK_PWRMGT_CNTL
, tmp
);
2192 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0
, CISLANDS_VRC_DFLT0
);
2193 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1
, CISLANDS_VRC_DFLT1
);
2194 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2
, CISLANDS_VRC_DFLT2
);
2195 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3
, CISLANDS_VRC_DFLT3
);
2196 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4
, CISLANDS_VRC_DFLT4
);
2197 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5
, CISLANDS_VRC_DFLT5
);
2198 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6
, CISLANDS_VRC_DFLT6
);
2199 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7
, CISLANDS_VRC_DFLT7
);
2202 static void ci_clear_vc(struct amdgpu_device
*adev
)
2206 tmp
= RREG32_SMC(ixSCLK_PWRMGT_CNTL
);
2207 tmp
|= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK
| SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK
);
2208 WREG32_SMC(ixSCLK_PWRMGT_CNTL
, tmp
);
2210 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0
, 0);
2211 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1
, 0);
2212 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2
, 0);
2213 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3
, 0);
2214 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4
, 0);
2215 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5
, 0);
2216 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6
, 0);
2217 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7
, 0);
2220 static int ci_upload_firmware(struct amdgpu_device
*adev
)
2224 if (amdgpu_ci_is_smc_running(adev
)) {
2225 DRM_INFO("smc is running, no need to load smc firmware\n");
2229 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
2230 if (RREG32_SMC(ixRCU_UC_EVENTS
) & RCU_UC_EVENTS__boot_seq_done_MASK
)
2233 WREG32_SMC(ixSMC_SYSCON_MISC_CNTL
, 1);
2235 amdgpu_ci_stop_smc_clock(adev
);
2236 amdgpu_ci_reset_smc(adev
);
2238 ret
= amdgpu_ci_load_smc_ucode(adev
, SMC_RAM_END
);
2244 static int ci_get_svi2_voltage_table(struct amdgpu_device
*adev
,
2245 struct amdgpu_clock_voltage_dependency_table
*voltage_dependency_table
,
2246 struct atom_voltage_table
*voltage_table
)
2250 if (voltage_dependency_table
== NULL
)
2253 voltage_table
->mask_low
= 0;
2254 voltage_table
->phase_delay
= 0;
2256 voltage_table
->count
= voltage_dependency_table
->count
;
2257 for (i
= 0; i
< voltage_table
->count
; i
++) {
2258 voltage_table
->entries
[i
].value
= voltage_dependency_table
->entries
[i
].v
;
2259 voltage_table
->entries
[i
].smio_low
= 0;
2265 static int ci_construct_voltage_tables(struct amdgpu_device
*adev
)
2267 struct ci_power_info
*pi
= ci_get_pi(adev
);
2270 if (pi
->voltage_control
== CISLANDS_VOLTAGE_CONTROL_BY_GPIO
) {
2271 ret
= amdgpu_atombios_get_voltage_table(adev
, VOLTAGE_TYPE_VDDC
,
2272 VOLTAGE_OBJ_GPIO_LUT
,
2273 &pi
->vddc_voltage_table
);
2276 } else if (pi
->voltage_control
== CISLANDS_VOLTAGE_CONTROL_BY_SVID2
) {
2277 ret
= ci_get_svi2_voltage_table(adev
,
2278 &adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_mclk
,
2279 &pi
->vddc_voltage_table
);
2284 if (pi
->vddc_voltage_table
.count
> SMU7_MAX_LEVELS_VDDC
)
2285 ci_trim_voltage_table_to_fit_state_table(adev
, SMU7_MAX_LEVELS_VDDC
,
2286 &pi
->vddc_voltage_table
);
2288 if (pi
->vddci_control
== CISLANDS_VOLTAGE_CONTROL_BY_GPIO
) {
2289 ret
= amdgpu_atombios_get_voltage_table(adev
, VOLTAGE_TYPE_VDDCI
,
2290 VOLTAGE_OBJ_GPIO_LUT
,
2291 &pi
->vddci_voltage_table
);
2294 } else if (pi
->vddci_control
== CISLANDS_VOLTAGE_CONTROL_BY_SVID2
) {
2295 ret
= ci_get_svi2_voltage_table(adev
,
2296 &adev
->pm
.dpm
.dyn_state
.vddci_dependency_on_mclk
,
2297 &pi
->vddci_voltage_table
);
2302 if (pi
->vddci_voltage_table
.count
> SMU7_MAX_LEVELS_VDDCI
)
2303 ci_trim_voltage_table_to_fit_state_table(adev
, SMU7_MAX_LEVELS_VDDCI
,
2304 &pi
->vddci_voltage_table
);
2306 if (pi
->mvdd_control
== CISLANDS_VOLTAGE_CONTROL_BY_GPIO
) {
2307 ret
= amdgpu_atombios_get_voltage_table(adev
, VOLTAGE_TYPE_MVDDC
,
2308 VOLTAGE_OBJ_GPIO_LUT
,
2309 &pi
->mvdd_voltage_table
);
2312 } else if (pi
->mvdd_control
== CISLANDS_VOLTAGE_CONTROL_BY_SVID2
) {
2313 ret
= ci_get_svi2_voltage_table(adev
,
2314 &adev
->pm
.dpm
.dyn_state
.mvdd_dependency_on_mclk
,
2315 &pi
->mvdd_voltage_table
);
2320 if (pi
->mvdd_voltage_table
.count
> SMU7_MAX_LEVELS_MVDD
)
2321 ci_trim_voltage_table_to_fit_state_table(adev
, SMU7_MAX_LEVELS_MVDD
,
2322 &pi
->mvdd_voltage_table
);
2327 static void ci_populate_smc_voltage_table(struct amdgpu_device
*adev
,
2328 struct atom_voltage_table_entry
*voltage_table
,
2329 SMU7_Discrete_VoltageLevel
*smc_voltage_table
)
2333 ret
= ci_get_std_voltage_value_sidd(adev
, voltage_table
,
2334 &smc_voltage_table
->StdVoltageHiSidd
,
2335 &smc_voltage_table
->StdVoltageLoSidd
);
2338 smc_voltage_table
->StdVoltageHiSidd
= voltage_table
->value
* VOLTAGE_SCALE
;
2339 smc_voltage_table
->StdVoltageLoSidd
= voltage_table
->value
* VOLTAGE_SCALE
;
2342 smc_voltage_table
->Voltage
= cpu_to_be16(voltage_table
->value
* VOLTAGE_SCALE
);
2343 smc_voltage_table
->StdVoltageHiSidd
=
2344 cpu_to_be16(smc_voltage_table
->StdVoltageHiSidd
);
2345 smc_voltage_table
->StdVoltageLoSidd
=
2346 cpu_to_be16(smc_voltage_table
->StdVoltageLoSidd
);
2349 static int ci_populate_smc_vddc_table(struct amdgpu_device
*adev
,
2350 SMU7_Discrete_DpmTable
*table
)
2352 struct ci_power_info
*pi
= ci_get_pi(adev
);
2355 table
->VddcLevelCount
= pi
->vddc_voltage_table
.count
;
2356 for (count
= 0; count
< table
->VddcLevelCount
; count
++) {
2357 ci_populate_smc_voltage_table(adev
,
2358 &pi
->vddc_voltage_table
.entries
[count
],
2359 &table
->VddcLevel
[count
]);
2361 if (pi
->voltage_control
== CISLANDS_VOLTAGE_CONTROL_BY_GPIO
)
2362 table
->VddcLevel
[count
].Smio
|=
2363 pi
->vddc_voltage_table
.entries
[count
].smio_low
;
2365 table
->VddcLevel
[count
].Smio
= 0;
2367 table
->VddcLevelCount
= cpu_to_be32(table
->VddcLevelCount
);
2372 static int ci_populate_smc_vddci_table(struct amdgpu_device
*adev
,
2373 SMU7_Discrete_DpmTable
*table
)
2376 struct ci_power_info
*pi
= ci_get_pi(adev
);
2378 table
->VddciLevelCount
= pi
->vddci_voltage_table
.count
;
2379 for (count
= 0; count
< table
->VddciLevelCount
; count
++) {
2380 ci_populate_smc_voltage_table(adev
,
2381 &pi
->vddci_voltage_table
.entries
[count
],
2382 &table
->VddciLevel
[count
]);
2384 if (pi
->vddci_control
== CISLANDS_VOLTAGE_CONTROL_BY_GPIO
)
2385 table
->VddciLevel
[count
].Smio
|=
2386 pi
->vddci_voltage_table
.entries
[count
].smio_low
;
2388 table
->VddciLevel
[count
].Smio
= 0;
2390 table
->VddciLevelCount
= cpu_to_be32(table
->VddciLevelCount
);
2395 static int ci_populate_smc_mvdd_table(struct amdgpu_device
*adev
,
2396 SMU7_Discrete_DpmTable
*table
)
2398 struct ci_power_info
*pi
= ci_get_pi(adev
);
2401 table
->MvddLevelCount
= pi
->mvdd_voltage_table
.count
;
2402 for (count
= 0; count
< table
->MvddLevelCount
; count
++) {
2403 ci_populate_smc_voltage_table(adev
,
2404 &pi
->mvdd_voltage_table
.entries
[count
],
2405 &table
->MvddLevel
[count
]);
2407 if (pi
->mvdd_control
== CISLANDS_VOLTAGE_CONTROL_BY_GPIO
)
2408 table
->MvddLevel
[count
].Smio
|=
2409 pi
->mvdd_voltage_table
.entries
[count
].smio_low
;
2411 table
->MvddLevel
[count
].Smio
= 0;
2413 table
->MvddLevelCount
= cpu_to_be32(table
->MvddLevelCount
);
2418 static int ci_populate_smc_voltage_tables(struct amdgpu_device
*adev
,
2419 SMU7_Discrete_DpmTable
*table
)
2423 ret
= ci_populate_smc_vddc_table(adev
, table
);
2427 ret
= ci_populate_smc_vddci_table(adev
, table
);
2431 ret
= ci_populate_smc_mvdd_table(adev
, table
);
2438 static int ci_populate_mvdd_value(struct amdgpu_device
*adev
, u32 mclk
,
2439 SMU7_Discrete_VoltageLevel
*voltage
)
2441 struct ci_power_info
*pi
= ci_get_pi(adev
);
2444 if (pi
->mvdd_control
!= CISLANDS_VOLTAGE_CONTROL_NONE
) {
2445 for (i
= 0; i
< adev
->pm
.dpm
.dyn_state
.mvdd_dependency_on_mclk
.count
; i
++) {
2446 if (mclk
<= adev
->pm
.dpm
.dyn_state
.mvdd_dependency_on_mclk
.entries
[i
].clk
) {
2447 voltage
->Voltage
= pi
->mvdd_voltage_table
.entries
[i
].value
;
2452 if (i
>= adev
->pm
.dpm
.dyn_state
.mvdd_dependency_on_mclk
.count
)
2459 static int ci_get_std_voltage_value_sidd(struct amdgpu_device
*adev
,
2460 struct atom_voltage_table_entry
*voltage_table
,
2461 u16
*std_voltage_hi_sidd
, u16
*std_voltage_lo_sidd
)
2464 bool voltage_found
= false;
2465 *std_voltage_hi_sidd
= voltage_table
->value
* VOLTAGE_SCALE
;
2466 *std_voltage_lo_sidd
= voltage_table
->value
* VOLTAGE_SCALE
;
2468 if (adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
== NULL
)
2471 if (adev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
) {
2472 for (v_index
= 0; (u32
)v_index
< adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.count
; v_index
++) {
2473 if (voltage_table
->value
==
2474 adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
[v_index
].v
) {
2475 voltage_found
= true;
2476 if ((u32
)v_index
< adev
->pm
.dpm
.dyn_state
.cac_leakage_table
.count
)
2479 idx
= adev
->pm
.dpm
.dyn_state
.cac_leakage_table
.count
- 1;
2480 *std_voltage_lo_sidd
=
2481 adev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[idx
].vddc
* VOLTAGE_SCALE
;
2482 *std_voltage_hi_sidd
=
2483 adev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[idx
].leakage
* VOLTAGE_SCALE
;
2488 if (!voltage_found
) {
2489 for (v_index
= 0; (u32
)v_index
< adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.count
; v_index
++) {
2490 if (voltage_table
->value
<=
2491 adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
[v_index
].v
) {
2492 voltage_found
= true;
2493 if ((u32
)v_index
< adev
->pm
.dpm
.dyn_state
.cac_leakage_table
.count
)
2496 idx
= adev
->pm
.dpm
.dyn_state
.cac_leakage_table
.count
- 1;
2497 *std_voltage_lo_sidd
=
2498 adev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[idx
].vddc
* VOLTAGE_SCALE
;
2499 *std_voltage_hi_sidd
=
2500 adev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[idx
].leakage
* VOLTAGE_SCALE
;
2510 static void ci_populate_phase_value_based_on_sclk(struct amdgpu_device
*adev
,
2511 const struct amdgpu_phase_shedding_limits_table
*limits
,
2513 u32
*phase_shedding
)
2517 *phase_shedding
= 1;
2519 for (i
= 0; i
< limits
->count
; i
++) {
2520 if (sclk
< limits
->entries
[i
].sclk
) {
2521 *phase_shedding
= i
;
2527 static void ci_populate_phase_value_based_on_mclk(struct amdgpu_device
*adev
,
2528 const struct amdgpu_phase_shedding_limits_table
*limits
,
2530 u32
*phase_shedding
)
2534 *phase_shedding
= 1;
2536 for (i
= 0; i
< limits
->count
; i
++) {
2537 if (mclk
< limits
->entries
[i
].mclk
) {
2538 *phase_shedding
= i
;
2544 static int ci_init_arb_table_index(struct amdgpu_device
*adev
)
2546 struct ci_power_info
*pi
= ci_get_pi(adev
);
2550 ret
= amdgpu_ci_read_smc_sram_dword(adev
, pi
->arb_table_start
,
2551 &tmp
, pi
->sram_end
);
2556 tmp
|= MC_CG_ARB_FREQ_F1
<< 24;
2558 return amdgpu_ci_write_smc_sram_dword(adev
, pi
->arb_table_start
,
2562 static int ci_get_dependency_volt_by_clk(struct amdgpu_device
*adev
,
2563 struct amdgpu_clock_voltage_dependency_table
*allowed_clock_voltage_table
,
2564 u32 clock
, u32
*voltage
)
2568 if (allowed_clock_voltage_table
->count
== 0)
2571 for (i
= 0; i
< allowed_clock_voltage_table
->count
; i
++) {
2572 if (allowed_clock_voltage_table
->entries
[i
].clk
>= clock
) {
2573 *voltage
= allowed_clock_voltage_table
->entries
[i
].v
;
2578 *voltage
= allowed_clock_voltage_table
->entries
[i
-1].v
;
2583 static u8
ci_get_sleep_divider_id_from_clock(u32 sclk
, u32 min_sclk_in_sr
)
2587 u32 min
= max(min_sclk_in_sr
, (u32
)CISLAND_MINIMUM_ENGINE_CLOCK
);
2592 for (i
= CISLAND_MAX_DEEPSLEEP_DIVIDER_ID
; ; i
--) {
2594 if (tmp
>= min
|| i
== 0)
2601 static int ci_initial_switch_from_arb_f0_to_f1(struct amdgpu_device
*adev
)
2603 return ci_copy_and_switch_arb_sets(adev
, MC_CG_ARB_FREQ_F0
, MC_CG_ARB_FREQ_F1
);
2606 static int ci_reset_to_default(struct amdgpu_device
*adev
)
2608 return (amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_ResetToDefaults
) == PPSMC_Result_OK
) ?
2612 static int ci_force_switch_to_arb_f0(struct amdgpu_device
*adev
)
2616 tmp
= (RREG32_SMC(ixSMC_SCRATCH9
) & 0x0000ff00) >> 8;
2618 if (tmp
== MC_CG_ARB_FREQ_F0
)
2621 return ci_copy_and_switch_arb_sets(adev
, tmp
, MC_CG_ARB_FREQ_F0
);
2624 static void ci_register_patching_mc_arb(struct amdgpu_device
*adev
,
2625 const u32 engine_clock
,
2626 const u32 memory_clock
,
2632 tmp
= RREG32(mmMC_SEQ_MISC0
);
2633 patch
= ((tmp
& 0x0000f00) == 0x300) ? true : false;
2636 ((adev
->pdev
->device
== 0x67B0) ||
2637 (adev
->pdev
->device
== 0x67B1))) {
2638 if ((memory_clock
> 100000) && (memory_clock
<= 125000)) {
2639 tmp2
= (((0x31 * engine_clock
) / 125000) - 1) & 0xff;
2640 *dram_timimg2
&= ~0x00ff0000;
2641 *dram_timimg2
|= tmp2
<< 16;
2642 } else if ((memory_clock
> 125000) && (memory_clock
<= 137500)) {
2643 tmp2
= (((0x36 * engine_clock
) / 137500) - 1) & 0xff;
2644 *dram_timimg2
&= ~0x00ff0000;
2645 *dram_timimg2
|= tmp2
<< 16;
2650 static int ci_populate_memory_timing_parameters(struct amdgpu_device
*adev
,
2653 SMU7_Discrete_MCArbDramTimingTableEntry
*arb_regs
)
2659 amdgpu_atombios_set_engine_dram_timings(adev
, sclk
, mclk
);
2661 dram_timing
= RREG32(mmMC_ARB_DRAM_TIMING
);
2662 dram_timing2
= RREG32(mmMC_ARB_DRAM_TIMING2
);
2663 burst_time
= RREG32(mmMC_ARB_BURST_TIME
) & MC_ARB_BURST_TIME__STATE0_MASK
;
2665 ci_register_patching_mc_arb(adev
, sclk
, mclk
, &dram_timing2
);
2667 arb_regs
->McArbDramTiming
= cpu_to_be32(dram_timing
);
2668 arb_regs
->McArbDramTiming2
= cpu_to_be32(dram_timing2
);
2669 arb_regs
->McArbBurstTime
= (u8
)burst_time
;
2674 static int ci_do_program_memory_timing_parameters(struct amdgpu_device
*adev
)
2676 struct ci_power_info
*pi
= ci_get_pi(adev
);
2677 SMU7_Discrete_MCArbDramTimingTable arb_regs
;
2681 memset(&arb_regs
, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable
));
2683 for (i
= 0; i
< pi
->dpm_table
.sclk_table
.count
; i
++) {
2684 for (j
= 0; j
< pi
->dpm_table
.mclk_table
.count
; j
++) {
2685 ret
= ci_populate_memory_timing_parameters(adev
,
2686 pi
->dpm_table
.sclk_table
.dpm_levels
[i
].value
,
2687 pi
->dpm_table
.mclk_table
.dpm_levels
[j
].value
,
2688 &arb_regs
.entries
[i
][j
]);
2695 ret
= amdgpu_ci_copy_bytes_to_smc(adev
,
2696 pi
->arb_table_start
,
2698 sizeof(SMU7_Discrete_MCArbDramTimingTable
),
2704 static int ci_program_memory_timing_parameters(struct amdgpu_device
*adev
)
2706 struct ci_power_info
*pi
= ci_get_pi(adev
);
2708 if (pi
->need_update_smu7_dpm_table
== 0)
2711 return ci_do_program_memory_timing_parameters(adev
);
2714 static void ci_populate_smc_initial_state(struct amdgpu_device
*adev
,
2715 struct amdgpu_ps
*amdgpu_boot_state
)
2717 struct ci_ps
*boot_state
= ci_get_ps(amdgpu_boot_state
);
2718 struct ci_power_info
*pi
= ci_get_pi(adev
);
2721 for (level
= 0; level
< adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.count
; level
++) {
2722 if (adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
[level
].clk
>=
2723 boot_state
->performance_levels
[0].sclk
) {
2724 pi
->smc_state_table
.GraphicsBootLevel
= level
;
2729 for (level
= 0; level
< adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_mclk
.count
; level
++) {
2730 if (adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_mclk
.entries
[level
].clk
>=
2731 boot_state
->performance_levels
[0].mclk
) {
2732 pi
->smc_state_table
.MemoryBootLevel
= level
;
2738 static u32
ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table
*dpm_table
)
2743 for (i
= dpm_table
->count
; i
> 0; i
--) {
2744 mask_value
= mask_value
<< 1;
2745 if (dpm_table
->dpm_levels
[i
-1].enabled
)
2748 mask_value
&= 0xFFFFFFFE;
2754 static void ci_populate_smc_link_level(struct amdgpu_device
*adev
,
2755 SMU7_Discrete_DpmTable
*table
)
2757 struct ci_power_info
*pi
= ci_get_pi(adev
);
2758 struct ci_dpm_table
*dpm_table
= &pi
->dpm_table
;
2761 for (i
= 0; i
< dpm_table
->pcie_speed_table
.count
; i
++) {
2762 table
->LinkLevel
[i
].PcieGenSpeed
=
2763 (u8
)dpm_table
->pcie_speed_table
.dpm_levels
[i
].value
;
2764 table
->LinkLevel
[i
].PcieLaneCount
=
2765 amdgpu_encode_pci_lane_width(dpm_table
->pcie_speed_table
.dpm_levels
[i
].param1
);
2766 table
->LinkLevel
[i
].EnabledForActivity
= 1;
2767 table
->LinkLevel
[i
].DownT
= cpu_to_be32(5);
2768 table
->LinkLevel
[i
].UpT
= cpu_to_be32(30);
2771 pi
->smc_state_table
.LinkLevelCount
= (u8
)dpm_table
->pcie_speed_table
.count
;
2772 pi
->dpm_level_enable_mask
.pcie_dpm_enable_mask
=
2773 ci_get_dpm_level_enable_mask_value(&dpm_table
->pcie_speed_table
);
2776 static int ci_populate_smc_uvd_level(struct amdgpu_device
*adev
,
2777 SMU7_Discrete_DpmTable
*table
)
2780 struct atom_clock_dividers dividers
;
2783 table
->UvdLevelCount
=
2784 adev
->pm
.dpm
.dyn_state
.uvd_clock_voltage_dependency_table
.count
;
2786 for (count
= 0; count
< table
->UvdLevelCount
; count
++) {
2787 table
->UvdLevel
[count
].VclkFrequency
=
2788 adev
->pm
.dpm
.dyn_state
.uvd_clock_voltage_dependency_table
.entries
[count
].vclk
;
2789 table
->UvdLevel
[count
].DclkFrequency
=
2790 adev
->pm
.dpm
.dyn_state
.uvd_clock_voltage_dependency_table
.entries
[count
].dclk
;
2791 table
->UvdLevel
[count
].MinVddc
=
2792 adev
->pm
.dpm
.dyn_state
.uvd_clock_voltage_dependency_table
.entries
[count
].v
* VOLTAGE_SCALE
;
2793 table
->UvdLevel
[count
].MinVddcPhases
= 1;
2795 ret
= amdgpu_atombios_get_clock_dividers(adev
,
2796 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK
,
2797 table
->UvdLevel
[count
].VclkFrequency
, false, ÷rs
);
2801 table
->UvdLevel
[count
].VclkDivider
= (u8
)dividers
.post_divider
;
2803 ret
= amdgpu_atombios_get_clock_dividers(adev
,
2804 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK
,
2805 table
->UvdLevel
[count
].DclkFrequency
, false, ÷rs
);
2809 table
->UvdLevel
[count
].DclkDivider
= (u8
)dividers
.post_divider
;
2811 table
->UvdLevel
[count
].VclkFrequency
= cpu_to_be32(table
->UvdLevel
[count
].VclkFrequency
);
2812 table
->UvdLevel
[count
].DclkFrequency
= cpu_to_be32(table
->UvdLevel
[count
].DclkFrequency
);
2813 table
->UvdLevel
[count
].MinVddc
= cpu_to_be16(table
->UvdLevel
[count
].MinVddc
);
2819 static int ci_populate_smc_vce_level(struct amdgpu_device
*adev
,
2820 SMU7_Discrete_DpmTable
*table
)
2823 struct atom_clock_dividers dividers
;
2826 table
->VceLevelCount
=
2827 adev
->pm
.dpm
.dyn_state
.vce_clock_voltage_dependency_table
.count
;
2829 for (count
= 0; count
< table
->VceLevelCount
; count
++) {
2830 table
->VceLevel
[count
].Frequency
=
2831 adev
->pm
.dpm
.dyn_state
.vce_clock_voltage_dependency_table
.entries
[count
].evclk
;
2832 table
->VceLevel
[count
].MinVoltage
=
2833 (u16
)adev
->pm
.dpm
.dyn_state
.vce_clock_voltage_dependency_table
.entries
[count
].v
* VOLTAGE_SCALE
;
2834 table
->VceLevel
[count
].MinPhases
= 1;
2836 ret
= amdgpu_atombios_get_clock_dividers(adev
,
2837 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK
,
2838 table
->VceLevel
[count
].Frequency
, false, ÷rs
);
2842 table
->VceLevel
[count
].Divider
= (u8
)dividers
.post_divider
;
2844 table
->VceLevel
[count
].Frequency
= cpu_to_be32(table
->VceLevel
[count
].Frequency
);
2845 table
->VceLevel
[count
].MinVoltage
= cpu_to_be16(table
->VceLevel
[count
].MinVoltage
);
2852 static int ci_populate_smc_acp_level(struct amdgpu_device
*adev
,
2853 SMU7_Discrete_DpmTable
*table
)
2856 struct atom_clock_dividers dividers
;
2859 table
->AcpLevelCount
= (u8
)
2860 (adev
->pm
.dpm
.dyn_state
.acp_clock_voltage_dependency_table
.count
);
2862 for (count
= 0; count
< table
->AcpLevelCount
; count
++) {
2863 table
->AcpLevel
[count
].Frequency
=
2864 adev
->pm
.dpm
.dyn_state
.acp_clock_voltage_dependency_table
.entries
[count
].clk
;
2865 table
->AcpLevel
[count
].MinVoltage
=
2866 adev
->pm
.dpm
.dyn_state
.acp_clock_voltage_dependency_table
.entries
[count
].v
;
2867 table
->AcpLevel
[count
].MinPhases
= 1;
2869 ret
= amdgpu_atombios_get_clock_dividers(adev
,
2870 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK
,
2871 table
->AcpLevel
[count
].Frequency
, false, ÷rs
);
2875 table
->AcpLevel
[count
].Divider
= (u8
)dividers
.post_divider
;
2877 table
->AcpLevel
[count
].Frequency
= cpu_to_be32(table
->AcpLevel
[count
].Frequency
);
2878 table
->AcpLevel
[count
].MinVoltage
= cpu_to_be16(table
->AcpLevel
[count
].MinVoltage
);
2884 static int ci_populate_smc_samu_level(struct amdgpu_device
*adev
,
2885 SMU7_Discrete_DpmTable
*table
)
2888 struct atom_clock_dividers dividers
;
2891 table
->SamuLevelCount
=
2892 adev
->pm
.dpm
.dyn_state
.samu_clock_voltage_dependency_table
.count
;
2894 for (count
= 0; count
< table
->SamuLevelCount
; count
++) {
2895 table
->SamuLevel
[count
].Frequency
=
2896 adev
->pm
.dpm
.dyn_state
.samu_clock_voltage_dependency_table
.entries
[count
].clk
;
2897 table
->SamuLevel
[count
].MinVoltage
=
2898 adev
->pm
.dpm
.dyn_state
.samu_clock_voltage_dependency_table
.entries
[count
].v
* VOLTAGE_SCALE
;
2899 table
->SamuLevel
[count
].MinPhases
= 1;
2901 ret
= amdgpu_atombios_get_clock_dividers(adev
,
2902 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK
,
2903 table
->SamuLevel
[count
].Frequency
, false, ÷rs
);
2907 table
->SamuLevel
[count
].Divider
= (u8
)dividers
.post_divider
;
2909 table
->SamuLevel
[count
].Frequency
= cpu_to_be32(table
->SamuLevel
[count
].Frequency
);
2910 table
->SamuLevel
[count
].MinVoltage
= cpu_to_be16(table
->SamuLevel
[count
].MinVoltage
);
2916 static int ci_calculate_mclk_params(struct amdgpu_device
*adev
,
2918 SMU7_Discrete_MemoryLevel
*mclk
,
2922 struct ci_power_info
*pi
= ci_get_pi(adev
);
2923 u32 dll_cntl
= pi
->clock_registers
.dll_cntl
;
2924 u32 mclk_pwrmgt_cntl
= pi
->clock_registers
.mclk_pwrmgt_cntl
;
2925 u32 mpll_ad_func_cntl
= pi
->clock_registers
.mpll_ad_func_cntl
;
2926 u32 mpll_dq_func_cntl
= pi
->clock_registers
.mpll_dq_func_cntl
;
2927 u32 mpll_func_cntl
= pi
->clock_registers
.mpll_func_cntl
;
2928 u32 mpll_func_cntl_1
= pi
->clock_registers
.mpll_func_cntl_1
;
2929 u32 mpll_func_cntl_2
= pi
->clock_registers
.mpll_func_cntl_2
;
2930 u32 mpll_ss1
= pi
->clock_registers
.mpll_ss1
;
2931 u32 mpll_ss2
= pi
->clock_registers
.mpll_ss2
;
2932 struct atom_mpll_param mpll_param
;
2935 ret
= amdgpu_atombios_get_memory_pll_dividers(adev
, memory_clock
, strobe_mode
, &mpll_param
);
2939 mpll_func_cntl
&= ~MPLL_FUNC_CNTL__BWCTRL_MASK
;
2940 mpll_func_cntl
|= (mpll_param
.bwcntl
<< MPLL_FUNC_CNTL__BWCTRL__SHIFT
);
2942 mpll_func_cntl_1
&= ~(MPLL_FUNC_CNTL_1__CLKF_MASK
| MPLL_FUNC_CNTL_1__CLKFRAC_MASK
|
2943 MPLL_FUNC_CNTL_1__VCO_MODE_MASK
);
2944 mpll_func_cntl_1
|= (mpll_param
.clkf
) << MPLL_FUNC_CNTL_1__CLKF__SHIFT
|
2945 (mpll_param
.clkfrac
<< MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT
) |
2946 (mpll_param
.vco_mode
<< MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT
);
2948 mpll_ad_func_cntl
&= ~MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK
;
2949 mpll_ad_func_cntl
|= (mpll_param
.post_div
<< MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT
);
2951 if (adev
->mc
.vram_type
== AMDGPU_VRAM_TYPE_GDDR5
) {
2952 mpll_dq_func_cntl
&= ~(MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK
|
2953 MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK
);
2954 mpll_dq_func_cntl
|= (mpll_param
.yclk_sel
<< MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT
) |
2955 (mpll_param
.post_div
<< MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT
);
2958 if (pi
->caps_mclk_ss_support
) {
2959 struct amdgpu_atom_ss ss
;
2962 u32 reference_clock
= adev
->clock
.mpll
.reference_freq
;
2964 if (mpll_param
.qdr
== 1)
2965 freq_nom
= memory_clock
* 4 * (1 << mpll_param
.post_div
);
2967 freq_nom
= memory_clock
* 2 * (1 << mpll_param
.post_div
);
2969 tmp
= (freq_nom
/ reference_clock
);
2971 if (amdgpu_atombios_get_asic_ss_info(adev
, &ss
,
2972 ASIC_INTERNAL_MEMORY_SS
, freq_nom
)) {
2973 u32 clks
= reference_clock
* 5 / ss
.rate
;
2974 u32 clkv
= (u32
)((((131 * ss
.percentage
* ss
.rate
) / 100) * tmp
) / freq_nom
);
2976 mpll_ss1
&= ~MPLL_SS1__CLKV_MASK
;
2977 mpll_ss1
|= (clkv
<< MPLL_SS1__CLKV__SHIFT
);
2979 mpll_ss2
&= ~MPLL_SS2__CLKS_MASK
;
2980 mpll_ss2
|= (clks
<< MPLL_SS2__CLKS__SHIFT
);
2984 mclk_pwrmgt_cntl
&= ~MCLK_PWRMGT_CNTL__DLL_SPEED_MASK
;
2985 mclk_pwrmgt_cntl
|= (mpll_param
.dll_speed
<< MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT
);
2988 mclk_pwrmgt_cntl
|= MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK
|
2989 MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK
;
2991 mclk_pwrmgt_cntl
&= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK
|
2992 MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK
);
2994 mclk
->MclkFrequency
= memory_clock
;
2995 mclk
->MpllFuncCntl
= mpll_func_cntl
;
2996 mclk
->MpllFuncCntl_1
= mpll_func_cntl_1
;
2997 mclk
->MpllFuncCntl_2
= mpll_func_cntl_2
;
2998 mclk
->MpllAdFuncCntl
= mpll_ad_func_cntl
;
2999 mclk
->MpllDqFuncCntl
= mpll_dq_func_cntl
;
3000 mclk
->MclkPwrmgtCntl
= mclk_pwrmgt_cntl
;
3001 mclk
->DllCntl
= dll_cntl
;
3002 mclk
->MpllSs1
= mpll_ss1
;
3003 mclk
->MpllSs2
= mpll_ss2
;
3008 static int ci_populate_single_memory_level(struct amdgpu_device
*adev
,
3010 SMU7_Discrete_MemoryLevel
*memory_level
)
3012 struct ci_power_info
*pi
= ci_get_pi(adev
);
3016 if (adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_mclk
.entries
) {
3017 ret
= ci_get_dependency_volt_by_clk(adev
,
3018 &adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_mclk
,
3019 memory_clock
, &memory_level
->MinVddc
);
3024 if (adev
->pm
.dpm
.dyn_state
.vddci_dependency_on_mclk
.entries
) {
3025 ret
= ci_get_dependency_volt_by_clk(adev
,
3026 &adev
->pm
.dpm
.dyn_state
.vddci_dependency_on_mclk
,
3027 memory_clock
, &memory_level
->MinVddci
);
3032 if (adev
->pm
.dpm
.dyn_state
.mvdd_dependency_on_mclk
.entries
) {
3033 ret
= ci_get_dependency_volt_by_clk(adev
,
3034 &adev
->pm
.dpm
.dyn_state
.mvdd_dependency_on_mclk
,
3035 memory_clock
, &memory_level
->MinMvdd
);
3040 memory_level
->MinVddcPhases
= 1;
3042 if (pi
->vddc_phase_shed_control
)
3043 ci_populate_phase_value_based_on_mclk(adev
,
3044 &adev
->pm
.dpm
.dyn_state
.phase_shedding_limits_table
,
3046 &memory_level
->MinVddcPhases
);
3048 memory_level
->EnabledForActivity
= 1;
3049 memory_level
->EnabledForThrottle
= 1;
3050 memory_level
->UpH
= 0;
3051 memory_level
->DownH
= 100;
3052 memory_level
->VoltageDownH
= 0;
3053 memory_level
->ActivityLevel
= (u16
)pi
->mclk_activity_target
;
3055 memory_level
->StutterEnable
= false;
3056 memory_level
->StrobeEnable
= false;
3057 memory_level
->EdcReadEnable
= false;
3058 memory_level
->EdcWriteEnable
= false;
3059 memory_level
->RttEnable
= false;
3061 memory_level
->DisplayWatermark
= PPSMC_DISPLAY_WATERMARK_LOW
;
3063 if (pi
->mclk_stutter_mode_threshold
&&
3064 (memory_clock
<= pi
->mclk_stutter_mode_threshold
) &&
3065 (!pi
->uvd_enabled
) &&
3066 (RREG32(mmDPG_PIPE_STUTTER_CONTROL
) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK
) &&
3067 (adev
->pm
.dpm
.new_active_crtc_count
<= 2))
3068 memory_level
->StutterEnable
= true;
3070 if (pi
->mclk_strobe_mode_threshold
&&
3071 (memory_clock
<= pi
->mclk_strobe_mode_threshold
))
3072 memory_level
->StrobeEnable
= 1;
3074 if (adev
->mc
.vram_type
== AMDGPU_VRAM_TYPE_GDDR5
) {
3075 memory_level
->StrobeRatio
=
3076 ci_get_mclk_frequency_ratio(memory_clock
, memory_level
->StrobeEnable
);
3077 if (pi
->mclk_edc_enable_threshold
&&
3078 (memory_clock
> pi
->mclk_edc_enable_threshold
))
3079 memory_level
->EdcReadEnable
= true;
3081 if (pi
->mclk_edc_wr_enable_threshold
&&
3082 (memory_clock
> pi
->mclk_edc_wr_enable_threshold
))
3083 memory_level
->EdcWriteEnable
= true;
3085 if (memory_level
->StrobeEnable
) {
3086 if (ci_get_mclk_frequency_ratio(memory_clock
, true) >=
3087 ((RREG32(mmMC_SEQ_MISC7
) >> 16) & 0xf))
3088 dll_state_on
= ((RREG32(mmMC_SEQ_MISC5
) >> 1) & 0x1) ? true : false;
3090 dll_state_on
= ((RREG32(mmMC_SEQ_MISC6
) >> 1) & 0x1) ? true : false;
3092 dll_state_on
= pi
->dll_default_on
;
3095 memory_level
->StrobeRatio
= ci_get_ddr3_mclk_frequency_ratio(memory_clock
);
3096 dll_state_on
= ((RREG32(mmMC_SEQ_MISC5
) >> 1) & 0x1) ? true : false;
3099 ret
= ci_calculate_mclk_params(adev
, memory_clock
, memory_level
, memory_level
->StrobeEnable
, dll_state_on
);
3103 memory_level
->MinVddc
= cpu_to_be32(memory_level
->MinVddc
* VOLTAGE_SCALE
);
3104 memory_level
->MinVddcPhases
= cpu_to_be32(memory_level
->MinVddcPhases
);
3105 memory_level
->MinVddci
= cpu_to_be32(memory_level
->MinVddci
* VOLTAGE_SCALE
);
3106 memory_level
->MinMvdd
= cpu_to_be32(memory_level
->MinMvdd
* VOLTAGE_SCALE
);
3108 memory_level
->MclkFrequency
= cpu_to_be32(memory_level
->MclkFrequency
);
3109 memory_level
->ActivityLevel
= cpu_to_be16(memory_level
->ActivityLevel
);
3110 memory_level
->MpllFuncCntl
= cpu_to_be32(memory_level
->MpllFuncCntl
);
3111 memory_level
->MpllFuncCntl_1
= cpu_to_be32(memory_level
->MpllFuncCntl_1
);
3112 memory_level
->MpllFuncCntl_2
= cpu_to_be32(memory_level
->MpllFuncCntl_2
);
3113 memory_level
->MpllAdFuncCntl
= cpu_to_be32(memory_level
->MpllAdFuncCntl
);
3114 memory_level
->MpllDqFuncCntl
= cpu_to_be32(memory_level
->MpllDqFuncCntl
);
3115 memory_level
->MclkPwrmgtCntl
= cpu_to_be32(memory_level
->MclkPwrmgtCntl
);
3116 memory_level
->DllCntl
= cpu_to_be32(memory_level
->DllCntl
);
3117 memory_level
->MpllSs1
= cpu_to_be32(memory_level
->MpllSs1
);
3118 memory_level
->MpllSs2
= cpu_to_be32(memory_level
->MpllSs2
);
3123 static int ci_populate_smc_acpi_level(struct amdgpu_device
*adev
,
3124 SMU7_Discrete_DpmTable
*table
)
3126 struct ci_power_info
*pi
= ci_get_pi(adev
);
3127 struct atom_clock_dividers dividers
;
3128 SMU7_Discrete_VoltageLevel voltage_level
;
3129 u32 spll_func_cntl
= pi
->clock_registers
.cg_spll_func_cntl
;
3130 u32 spll_func_cntl_2
= pi
->clock_registers
.cg_spll_func_cntl_2
;
3131 u32 dll_cntl
= pi
->clock_registers
.dll_cntl
;
3132 u32 mclk_pwrmgt_cntl
= pi
->clock_registers
.mclk_pwrmgt_cntl
;
3135 table
->ACPILevel
.Flags
&= ~PPSMC_SWSTATE_FLAG_DC
;
3138 table
->ACPILevel
.MinVddc
= cpu_to_be32(pi
->acpi_vddc
* VOLTAGE_SCALE
);
3140 table
->ACPILevel
.MinVddc
= cpu_to_be32(pi
->min_vddc_in_pp_table
* VOLTAGE_SCALE
);
3142 table
->ACPILevel
.MinVddcPhases
= pi
->vddc_phase_shed_control
? 0 : 1;
3144 table
->ACPILevel
.SclkFrequency
= adev
->clock
.spll
.reference_freq
;
3146 ret
= amdgpu_atombios_get_clock_dividers(adev
,
3147 COMPUTE_GPUCLK_INPUT_FLAG_SCLK
,
3148 table
->ACPILevel
.SclkFrequency
, false, ÷rs
);
3152 table
->ACPILevel
.SclkDid
= (u8
)dividers
.post_divider
;
3153 table
->ACPILevel
.DisplayWatermark
= PPSMC_DISPLAY_WATERMARK_LOW
;
3154 table
->ACPILevel
.DeepSleepDivId
= 0;
3156 spll_func_cntl
&= ~CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK
;
3157 spll_func_cntl
|= CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK
;
3159 spll_func_cntl_2
&= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK
;
3160 spll_func_cntl_2
|= (4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT
);
3162 table
->ACPILevel
.CgSpllFuncCntl
= spll_func_cntl
;
3163 table
->ACPILevel
.CgSpllFuncCntl2
= spll_func_cntl_2
;
3164 table
->ACPILevel
.CgSpllFuncCntl3
= pi
->clock_registers
.cg_spll_func_cntl_3
;
3165 table
->ACPILevel
.CgSpllFuncCntl4
= pi
->clock_registers
.cg_spll_func_cntl_4
;
3166 table
->ACPILevel
.SpllSpreadSpectrum
= pi
->clock_registers
.cg_spll_spread_spectrum
;
3167 table
->ACPILevel
.SpllSpreadSpectrum2
= pi
->clock_registers
.cg_spll_spread_spectrum_2
;
3168 table
->ACPILevel
.CcPwrDynRm
= 0;
3169 table
->ACPILevel
.CcPwrDynRm1
= 0;
3171 table
->ACPILevel
.Flags
= cpu_to_be32(table
->ACPILevel
.Flags
);
3172 table
->ACPILevel
.MinVddcPhases
= cpu_to_be32(table
->ACPILevel
.MinVddcPhases
);
3173 table
->ACPILevel
.SclkFrequency
= cpu_to_be32(table
->ACPILevel
.SclkFrequency
);
3174 table
->ACPILevel
.CgSpllFuncCntl
= cpu_to_be32(table
->ACPILevel
.CgSpllFuncCntl
);
3175 table
->ACPILevel
.CgSpllFuncCntl2
= cpu_to_be32(table
->ACPILevel
.CgSpllFuncCntl2
);
3176 table
->ACPILevel
.CgSpllFuncCntl3
= cpu_to_be32(table
->ACPILevel
.CgSpllFuncCntl3
);
3177 table
->ACPILevel
.CgSpllFuncCntl4
= cpu_to_be32(table
->ACPILevel
.CgSpllFuncCntl4
);
3178 table
->ACPILevel
.SpllSpreadSpectrum
= cpu_to_be32(table
->ACPILevel
.SpllSpreadSpectrum
);
3179 table
->ACPILevel
.SpllSpreadSpectrum2
= cpu_to_be32(table
->ACPILevel
.SpllSpreadSpectrum2
);
3180 table
->ACPILevel
.CcPwrDynRm
= cpu_to_be32(table
->ACPILevel
.CcPwrDynRm
);
3181 table
->ACPILevel
.CcPwrDynRm1
= cpu_to_be32(table
->ACPILevel
.CcPwrDynRm1
);
3183 table
->MemoryACPILevel
.MinVddc
= table
->ACPILevel
.MinVddc
;
3184 table
->MemoryACPILevel
.MinVddcPhases
= table
->ACPILevel
.MinVddcPhases
;
3186 if (pi
->vddci_control
!= CISLANDS_VOLTAGE_CONTROL_NONE
) {
3188 table
->MemoryACPILevel
.MinVddci
=
3189 cpu_to_be32(pi
->acpi_vddci
* VOLTAGE_SCALE
);
3191 table
->MemoryACPILevel
.MinVddci
=
3192 cpu_to_be32(pi
->min_vddci_in_pp_table
* VOLTAGE_SCALE
);
3195 if (ci_populate_mvdd_value(adev
, 0, &voltage_level
))
3196 table
->MemoryACPILevel
.MinMvdd
= 0;
3198 table
->MemoryACPILevel
.MinMvdd
=
3199 cpu_to_be32(voltage_level
.Voltage
* VOLTAGE_SCALE
);
3201 mclk_pwrmgt_cntl
|= MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK
|
3202 MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK
;
3203 mclk_pwrmgt_cntl
&= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK
|
3204 MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK
);
3206 dll_cntl
&= ~(DLL_CNTL__MRDCK0_BYPASS_MASK
| DLL_CNTL__MRDCK1_BYPASS_MASK
);
3208 table
->MemoryACPILevel
.DllCntl
= cpu_to_be32(dll_cntl
);
3209 table
->MemoryACPILevel
.MclkPwrmgtCntl
= cpu_to_be32(mclk_pwrmgt_cntl
);
3210 table
->MemoryACPILevel
.MpllAdFuncCntl
=
3211 cpu_to_be32(pi
->clock_registers
.mpll_ad_func_cntl
);
3212 table
->MemoryACPILevel
.MpllDqFuncCntl
=
3213 cpu_to_be32(pi
->clock_registers
.mpll_dq_func_cntl
);
3214 table
->MemoryACPILevel
.MpllFuncCntl
=
3215 cpu_to_be32(pi
->clock_registers
.mpll_func_cntl
);
3216 table
->MemoryACPILevel
.MpllFuncCntl_1
=
3217 cpu_to_be32(pi
->clock_registers
.mpll_func_cntl_1
);
3218 table
->MemoryACPILevel
.MpllFuncCntl_2
=
3219 cpu_to_be32(pi
->clock_registers
.mpll_func_cntl_2
);
3220 table
->MemoryACPILevel
.MpllSs1
= cpu_to_be32(pi
->clock_registers
.mpll_ss1
);
3221 table
->MemoryACPILevel
.MpllSs2
= cpu_to_be32(pi
->clock_registers
.mpll_ss2
);
3223 table
->MemoryACPILevel
.EnabledForThrottle
= 0;
3224 table
->MemoryACPILevel
.EnabledForActivity
= 0;
3225 table
->MemoryACPILevel
.UpH
= 0;
3226 table
->MemoryACPILevel
.DownH
= 100;
3227 table
->MemoryACPILevel
.VoltageDownH
= 0;
3228 table
->MemoryACPILevel
.ActivityLevel
=
3229 cpu_to_be16((u16
)pi
->mclk_activity_target
);
3231 table
->MemoryACPILevel
.StutterEnable
= false;
3232 table
->MemoryACPILevel
.StrobeEnable
= false;
3233 table
->MemoryACPILevel
.EdcReadEnable
= false;
3234 table
->MemoryACPILevel
.EdcWriteEnable
= false;
3235 table
->MemoryACPILevel
.RttEnable
= false;
3241 static int ci_enable_ulv(struct amdgpu_device
*adev
, bool enable
)
3243 struct ci_power_info
*pi
= ci_get_pi(adev
);
3244 struct ci_ulv_parm
*ulv
= &pi
->ulv
;
3246 if (ulv
->supported
) {
3248 return (amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_EnableULV
) == PPSMC_Result_OK
) ?
3251 return (amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_DisableULV
) == PPSMC_Result_OK
) ?
3258 static int ci_populate_ulv_level(struct amdgpu_device
*adev
,
3259 SMU7_Discrete_Ulv
*state
)
3261 struct ci_power_info
*pi
= ci_get_pi(adev
);
3262 u16 ulv_voltage
= adev
->pm
.dpm
.backbias_response_time
;
3264 state
->CcPwrDynRm
= 0;
3265 state
->CcPwrDynRm1
= 0;
3267 if (ulv_voltage
== 0) {
3268 pi
->ulv
.supported
= false;
3272 if (pi
->voltage_control
!= CISLANDS_VOLTAGE_CONTROL_BY_SVID2
) {
3273 if (ulv_voltage
> adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
[0].v
)
3274 state
->VddcOffset
= 0;
3277 adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
[0].v
- ulv_voltage
;
3279 if (ulv_voltage
> adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
[0].v
)
3280 state
->VddcOffsetVid
= 0;
3282 state
->VddcOffsetVid
= (u8
)
3283 ((adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
[0].v
- ulv_voltage
) *
3284 VOLTAGE_VID_OFFSET_SCALE2
/ VOLTAGE_VID_OFFSET_SCALE1
);
3286 state
->VddcPhase
= pi
->vddc_phase_shed_control
? 0 : 1;
3288 state
->CcPwrDynRm
= cpu_to_be32(state
->CcPwrDynRm
);
3289 state
->CcPwrDynRm1
= cpu_to_be32(state
->CcPwrDynRm1
);
3290 state
->VddcOffset
= cpu_to_be16(state
->VddcOffset
);
3295 static int ci_calculate_sclk_params(struct amdgpu_device
*adev
,
3297 SMU7_Discrete_GraphicsLevel
*sclk
)
3299 struct ci_power_info
*pi
= ci_get_pi(adev
);
3300 struct atom_clock_dividers dividers
;
3301 u32 spll_func_cntl_3
= pi
->clock_registers
.cg_spll_func_cntl_3
;
3302 u32 spll_func_cntl_4
= pi
->clock_registers
.cg_spll_func_cntl_4
;
3303 u32 cg_spll_spread_spectrum
= pi
->clock_registers
.cg_spll_spread_spectrum
;
3304 u32 cg_spll_spread_spectrum_2
= pi
->clock_registers
.cg_spll_spread_spectrum_2
;
3305 u32 reference_clock
= adev
->clock
.spll
.reference_freq
;
3306 u32 reference_divider
;
3310 ret
= amdgpu_atombios_get_clock_dividers(adev
,
3311 COMPUTE_GPUCLK_INPUT_FLAG_SCLK
,
3312 engine_clock
, false, ÷rs
);
3316 reference_divider
= 1 + dividers
.ref_div
;
3317 fbdiv
= dividers
.fb_div
& 0x3FFFFFF;
3319 spll_func_cntl_3
&= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK
;
3320 spll_func_cntl_3
|= (fbdiv
<< CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT
);
3321 spll_func_cntl_3
|= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK
;
3323 if (pi
->caps_sclk_ss_support
) {
3324 struct amdgpu_atom_ss ss
;
3325 u32 vco_freq
= engine_clock
* dividers
.post_div
;
3327 if (amdgpu_atombios_get_asic_ss_info(adev
, &ss
,
3328 ASIC_INTERNAL_ENGINE_SS
, vco_freq
)) {
3329 u32 clk_s
= reference_clock
* 5 / (reference_divider
* ss
.rate
);
3330 u32 clk_v
= 4 * ss
.percentage
* fbdiv
/ (clk_s
* 10000);
3332 cg_spll_spread_spectrum
&= ~(CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK
| CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK
);
3333 cg_spll_spread_spectrum
|= (clk_s
<< CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT
);
3334 cg_spll_spread_spectrum
|= (1 << CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT
);
3336 cg_spll_spread_spectrum_2
&= ~CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK
;
3337 cg_spll_spread_spectrum_2
|= (clk_v
<< CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT
);
3341 sclk
->SclkFrequency
= engine_clock
;
3342 sclk
->CgSpllFuncCntl3
= spll_func_cntl_3
;
3343 sclk
->CgSpllFuncCntl4
= spll_func_cntl_4
;
3344 sclk
->SpllSpreadSpectrum
= cg_spll_spread_spectrum
;
3345 sclk
->SpllSpreadSpectrum2
= cg_spll_spread_spectrum_2
;
3346 sclk
->SclkDid
= (u8
)dividers
.post_divider
;
3351 static int ci_populate_single_graphic_level(struct amdgpu_device
*adev
,
3353 u16 sclk_activity_level_t
,
3354 SMU7_Discrete_GraphicsLevel
*graphic_level
)
3356 struct ci_power_info
*pi
= ci_get_pi(adev
);
3359 ret
= ci_calculate_sclk_params(adev
, engine_clock
, graphic_level
);
3363 ret
= ci_get_dependency_volt_by_clk(adev
,
3364 &adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
,
3365 engine_clock
, &graphic_level
->MinVddc
);
3369 graphic_level
->SclkFrequency
= engine_clock
;
3371 graphic_level
->Flags
= 0;
3372 graphic_level
->MinVddcPhases
= 1;
3374 if (pi
->vddc_phase_shed_control
)
3375 ci_populate_phase_value_based_on_sclk(adev
,
3376 &adev
->pm
.dpm
.dyn_state
.phase_shedding_limits_table
,
3378 &graphic_level
->MinVddcPhases
);
3380 graphic_level
->ActivityLevel
= sclk_activity_level_t
;
3382 graphic_level
->CcPwrDynRm
= 0;
3383 graphic_level
->CcPwrDynRm1
= 0;
3384 graphic_level
->EnabledForThrottle
= 1;
3385 graphic_level
->UpH
= 0;
3386 graphic_level
->DownH
= 0;
3387 graphic_level
->VoltageDownH
= 0;
3388 graphic_level
->PowerThrottle
= 0;
3390 if (pi
->caps_sclk_ds
)
3391 graphic_level
->DeepSleepDivId
= ci_get_sleep_divider_id_from_clock(engine_clock
,
3392 CISLAND_MINIMUM_ENGINE_CLOCK
);
3394 graphic_level
->DisplayWatermark
= PPSMC_DISPLAY_WATERMARK_LOW
;
3396 graphic_level
->Flags
= cpu_to_be32(graphic_level
->Flags
);
3397 graphic_level
->MinVddc
= cpu_to_be32(graphic_level
->MinVddc
* VOLTAGE_SCALE
);
3398 graphic_level
->MinVddcPhases
= cpu_to_be32(graphic_level
->MinVddcPhases
);
3399 graphic_level
->SclkFrequency
= cpu_to_be32(graphic_level
->SclkFrequency
);
3400 graphic_level
->ActivityLevel
= cpu_to_be16(graphic_level
->ActivityLevel
);
3401 graphic_level
->CgSpllFuncCntl3
= cpu_to_be32(graphic_level
->CgSpllFuncCntl3
);
3402 graphic_level
->CgSpllFuncCntl4
= cpu_to_be32(graphic_level
->CgSpllFuncCntl4
);
3403 graphic_level
->SpllSpreadSpectrum
= cpu_to_be32(graphic_level
->SpllSpreadSpectrum
);
3404 graphic_level
->SpllSpreadSpectrum2
= cpu_to_be32(graphic_level
->SpllSpreadSpectrum2
);
3405 graphic_level
->CcPwrDynRm
= cpu_to_be32(graphic_level
->CcPwrDynRm
);
3406 graphic_level
->CcPwrDynRm1
= cpu_to_be32(graphic_level
->CcPwrDynRm1
);
3411 static int ci_populate_all_graphic_levels(struct amdgpu_device
*adev
)
3413 struct ci_power_info
*pi
= ci_get_pi(adev
);
3414 struct ci_dpm_table
*dpm_table
= &pi
->dpm_table
;
3415 u32 level_array_address
= pi
->dpm_table_start
+
3416 offsetof(SMU7_Discrete_DpmTable
, GraphicsLevel
);
3417 u32 level_array_size
= sizeof(SMU7_Discrete_GraphicsLevel
) *
3418 SMU7_MAX_LEVELS_GRAPHICS
;
3419 SMU7_Discrete_GraphicsLevel
*levels
= pi
->smc_state_table
.GraphicsLevel
;
3422 memset(levels
, 0, level_array_size
);
3424 for (i
= 0; i
< dpm_table
->sclk_table
.count
; i
++) {
3425 ret
= ci_populate_single_graphic_level(adev
,
3426 dpm_table
->sclk_table
.dpm_levels
[i
].value
,
3427 (u16
)pi
->activity_target
[i
],
3428 &pi
->smc_state_table
.GraphicsLevel
[i
]);
3432 pi
->smc_state_table
.GraphicsLevel
[i
].DeepSleepDivId
= 0;
3433 if (i
== (dpm_table
->sclk_table
.count
- 1))
3434 pi
->smc_state_table
.GraphicsLevel
[i
].DisplayWatermark
=
3435 PPSMC_DISPLAY_WATERMARK_HIGH
;
3437 pi
->smc_state_table
.GraphicsLevel
[0].EnabledForActivity
= 1;
3439 pi
->smc_state_table
.GraphicsDpmLevelCount
= (u8
)dpm_table
->sclk_table
.count
;
3440 pi
->dpm_level_enable_mask
.sclk_dpm_enable_mask
=
3441 ci_get_dpm_level_enable_mask_value(&dpm_table
->sclk_table
);
3443 ret
= amdgpu_ci_copy_bytes_to_smc(adev
, level_array_address
,
3444 (u8
*)levels
, level_array_size
,
3452 static int ci_populate_ulv_state(struct amdgpu_device
*adev
,
3453 SMU7_Discrete_Ulv
*ulv_level
)
3455 return ci_populate_ulv_level(adev
, ulv_level
);
3458 static int ci_populate_all_memory_levels(struct amdgpu_device
*adev
)
3460 struct ci_power_info
*pi
= ci_get_pi(adev
);
3461 struct ci_dpm_table
*dpm_table
= &pi
->dpm_table
;
3462 u32 level_array_address
= pi
->dpm_table_start
+
3463 offsetof(SMU7_Discrete_DpmTable
, MemoryLevel
);
3464 u32 level_array_size
= sizeof(SMU7_Discrete_MemoryLevel
) *
3465 SMU7_MAX_LEVELS_MEMORY
;
3466 SMU7_Discrete_MemoryLevel
*levels
= pi
->smc_state_table
.MemoryLevel
;
3469 memset(levels
, 0, level_array_size
);
3471 for (i
= 0; i
< dpm_table
->mclk_table
.count
; i
++) {
3472 if (dpm_table
->mclk_table
.dpm_levels
[i
].value
== 0)
3474 ret
= ci_populate_single_memory_level(adev
,
3475 dpm_table
->mclk_table
.dpm_levels
[i
].value
,
3476 &pi
->smc_state_table
.MemoryLevel
[i
]);
3481 if ((dpm_table
->mclk_table
.count
>= 2) &&
3482 ((adev
->pdev
->device
== 0x67B0) || (adev
->pdev
->device
== 0x67B1))) {
3483 pi
->smc_state_table
.MemoryLevel
[1].MinVddc
=
3484 pi
->smc_state_table
.MemoryLevel
[0].MinVddc
;
3485 pi
->smc_state_table
.MemoryLevel
[1].MinVddcPhases
=
3486 pi
->smc_state_table
.MemoryLevel
[0].MinVddcPhases
;
3489 pi
->smc_state_table
.MemoryLevel
[0].ActivityLevel
= cpu_to_be16(0x1F);
3491 pi
->smc_state_table
.MemoryDpmLevelCount
= (u8
)dpm_table
->mclk_table
.count
;
3492 pi
->dpm_level_enable_mask
.mclk_dpm_enable_mask
=
3493 ci_get_dpm_level_enable_mask_value(&dpm_table
->mclk_table
);
3495 pi
->smc_state_table
.MemoryLevel
[dpm_table
->mclk_table
.count
- 1].DisplayWatermark
=
3496 PPSMC_DISPLAY_WATERMARK_HIGH
;
3498 ret
= amdgpu_ci_copy_bytes_to_smc(adev
, level_array_address
,
3499 (u8
*)levels
, level_array_size
,
3507 static void ci_reset_single_dpm_table(struct amdgpu_device
*adev
,
3508 struct ci_single_dpm_table
* dpm_table
,
3513 dpm_table
->count
= count
;
3514 for (i
= 0; i
< MAX_REGULAR_DPM_NUMBER
; i
++)
3515 dpm_table
->dpm_levels
[i
].enabled
= false;
3518 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table
* dpm_table
,
3519 u32 index
, u32 pcie_gen
, u32 pcie_lanes
)
3521 dpm_table
->dpm_levels
[index
].value
= pcie_gen
;
3522 dpm_table
->dpm_levels
[index
].param1
= pcie_lanes
;
3523 dpm_table
->dpm_levels
[index
].enabled
= true;
3526 static int ci_setup_default_pcie_tables(struct amdgpu_device
*adev
)
3528 struct ci_power_info
*pi
= ci_get_pi(adev
);
3530 if (!pi
->use_pcie_performance_levels
&& !pi
->use_pcie_powersaving_levels
)
3533 if (pi
->use_pcie_performance_levels
&& !pi
->use_pcie_powersaving_levels
) {
3534 pi
->pcie_gen_powersaving
= pi
->pcie_gen_performance
;
3535 pi
->pcie_lane_powersaving
= pi
->pcie_lane_performance
;
3536 } else if (!pi
->use_pcie_performance_levels
&& pi
->use_pcie_powersaving_levels
) {
3537 pi
->pcie_gen_performance
= pi
->pcie_gen_powersaving
;
3538 pi
->pcie_lane_performance
= pi
->pcie_lane_powersaving
;
3541 ci_reset_single_dpm_table(adev
,
3542 &pi
->dpm_table
.pcie_speed_table
,
3543 SMU7_MAX_LEVELS_LINK
);
3545 if (adev
->asic_type
== CHIP_BONAIRE
)
3546 ci_setup_pcie_table_entry(&pi
->dpm_table
.pcie_speed_table
, 0,
3547 pi
->pcie_gen_powersaving
.min
,
3548 pi
->pcie_lane_powersaving
.max
);
3550 ci_setup_pcie_table_entry(&pi
->dpm_table
.pcie_speed_table
, 0,
3551 pi
->pcie_gen_powersaving
.min
,
3552 pi
->pcie_lane_powersaving
.min
);
3553 ci_setup_pcie_table_entry(&pi
->dpm_table
.pcie_speed_table
, 1,
3554 pi
->pcie_gen_performance
.min
,
3555 pi
->pcie_lane_performance
.min
);
3556 ci_setup_pcie_table_entry(&pi
->dpm_table
.pcie_speed_table
, 2,
3557 pi
->pcie_gen_powersaving
.min
,
3558 pi
->pcie_lane_powersaving
.max
);
3559 ci_setup_pcie_table_entry(&pi
->dpm_table
.pcie_speed_table
, 3,
3560 pi
->pcie_gen_performance
.min
,
3561 pi
->pcie_lane_performance
.max
);
3562 ci_setup_pcie_table_entry(&pi
->dpm_table
.pcie_speed_table
, 4,
3563 pi
->pcie_gen_powersaving
.max
,
3564 pi
->pcie_lane_powersaving
.max
);
3565 ci_setup_pcie_table_entry(&pi
->dpm_table
.pcie_speed_table
, 5,
3566 pi
->pcie_gen_performance
.max
,
3567 pi
->pcie_lane_performance
.max
);
3569 pi
->dpm_table
.pcie_speed_table
.count
= 6;
3574 static int ci_setup_default_dpm_tables(struct amdgpu_device
*adev
)
3576 struct ci_power_info
*pi
= ci_get_pi(adev
);
3577 struct amdgpu_clock_voltage_dependency_table
*allowed_sclk_vddc_table
=
3578 &adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
;
3579 struct amdgpu_clock_voltage_dependency_table
*allowed_mclk_table
=
3580 &adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_mclk
;
3581 struct amdgpu_cac_leakage_table
*std_voltage_table
=
3582 &adev
->pm
.dpm
.dyn_state
.cac_leakage_table
;
3585 if (allowed_sclk_vddc_table
== NULL
)
3587 if (allowed_sclk_vddc_table
->count
< 1)
3589 if (allowed_mclk_table
== NULL
)
3591 if (allowed_mclk_table
->count
< 1)
3594 memset(&pi
->dpm_table
, 0, sizeof(struct ci_dpm_table
));
3596 ci_reset_single_dpm_table(adev
,
3597 &pi
->dpm_table
.sclk_table
,
3598 SMU7_MAX_LEVELS_GRAPHICS
);
3599 ci_reset_single_dpm_table(adev
,
3600 &pi
->dpm_table
.mclk_table
,
3601 SMU7_MAX_LEVELS_MEMORY
);
3602 ci_reset_single_dpm_table(adev
,
3603 &pi
->dpm_table
.vddc_table
,
3604 SMU7_MAX_LEVELS_VDDC
);
3605 ci_reset_single_dpm_table(adev
,
3606 &pi
->dpm_table
.vddci_table
,
3607 SMU7_MAX_LEVELS_VDDCI
);
3608 ci_reset_single_dpm_table(adev
,
3609 &pi
->dpm_table
.mvdd_table
,
3610 SMU7_MAX_LEVELS_MVDD
);
3612 pi
->dpm_table
.sclk_table
.count
= 0;
3613 for (i
= 0; i
< allowed_sclk_vddc_table
->count
; i
++) {
3615 (pi
->dpm_table
.sclk_table
.dpm_levels
[pi
->dpm_table
.sclk_table
.count
-1].value
!=
3616 allowed_sclk_vddc_table
->entries
[i
].clk
)) {
3617 pi
->dpm_table
.sclk_table
.dpm_levels
[pi
->dpm_table
.sclk_table
.count
].value
=
3618 allowed_sclk_vddc_table
->entries
[i
].clk
;
3619 pi
->dpm_table
.sclk_table
.dpm_levels
[pi
->dpm_table
.sclk_table
.count
].enabled
=
3620 (i
== 0) ? true : false;
3621 pi
->dpm_table
.sclk_table
.count
++;
3625 pi
->dpm_table
.mclk_table
.count
= 0;
3626 for (i
= 0; i
< allowed_mclk_table
->count
; i
++) {
3628 (pi
->dpm_table
.mclk_table
.dpm_levels
[pi
->dpm_table
.mclk_table
.count
-1].value
!=
3629 allowed_mclk_table
->entries
[i
].clk
)) {
3630 pi
->dpm_table
.mclk_table
.dpm_levels
[pi
->dpm_table
.mclk_table
.count
].value
=
3631 allowed_mclk_table
->entries
[i
].clk
;
3632 pi
->dpm_table
.mclk_table
.dpm_levels
[pi
->dpm_table
.mclk_table
.count
].enabled
=
3633 (i
== 0) ? true : false;
3634 pi
->dpm_table
.mclk_table
.count
++;
3638 for (i
= 0; i
< allowed_sclk_vddc_table
->count
; i
++) {
3639 pi
->dpm_table
.vddc_table
.dpm_levels
[i
].value
=
3640 allowed_sclk_vddc_table
->entries
[i
].v
;
3641 pi
->dpm_table
.vddc_table
.dpm_levels
[i
].param1
=
3642 std_voltage_table
->entries
[i
].leakage
;
3643 pi
->dpm_table
.vddc_table
.dpm_levels
[i
].enabled
= true;
3645 pi
->dpm_table
.vddc_table
.count
= allowed_sclk_vddc_table
->count
;
3647 allowed_mclk_table
= &adev
->pm
.dpm
.dyn_state
.vddci_dependency_on_mclk
;
3648 if (allowed_mclk_table
) {
3649 for (i
= 0; i
< allowed_mclk_table
->count
; i
++) {
3650 pi
->dpm_table
.vddci_table
.dpm_levels
[i
].value
=
3651 allowed_mclk_table
->entries
[i
].v
;
3652 pi
->dpm_table
.vddci_table
.dpm_levels
[i
].enabled
= true;
3654 pi
->dpm_table
.vddci_table
.count
= allowed_mclk_table
->count
;
3657 allowed_mclk_table
= &adev
->pm
.dpm
.dyn_state
.mvdd_dependency_on_mclk
;
3658 if (allowed_mclk_table
) {
3659 for (i
= 0; i
< allowed_mclk_table
->count
; i
++) {
3660 pi
->dpm_table
.mvdd_table
.dpm_levels
[i
].value
=
3661 allowed_mclk_table
->entries
[i
].v
;
3662 pi
->dpm_table
.mvdd_table
.dpm_levels
[i
].enabled
= true;
3664 pi
->dpm_table
.mvdd_table
.count
= allowed_mclk_table
->count
;
3667 ci_setup_default_pcie_tables(adev
);
3669 /* save a copy of the default DPM table */
3670 memcpy(&(pi
->golden_dpm_table
), &(pi
->dpm_table
),
3671 sizeof(struct ci_dpm_table
));
3676 static int ci_find_boot_level(struct ci_single_dpm_table
*table
,
3677 u32 value
, u32
*boot_level
)
3682 for(i
= 0; i
< table
->count
; i
++) {
3683 if (value
== table
->dpm_levels
[i
].value
) {
3692 static void ci_save_default_power_profile(struct amdgpu_device
*adev
)
3694 struct ci_power_info
*pi
= ci_get_pi(adev
);
3695 struct SMU7_Discrete_GraphicsLevel
*levels
=
3696 pi
->smc_state_table
.GraphicsLevel
;
3697 uint32_t min_level
= 0;
3699 pi
->default_gfx_power_profile
.activity_threshold
=
3700 be16_to_cpu(levels
[0].ActivityLevel
);
3701 pi
->default_gfx_power_profile
.up_hyst
= levels
[0].UpH
;
3702 pi
->default_gfx_power_profile
.down_hyst
= levels
[0].DownH
;
3703 pi
->default_gfx_power_profile
.type
= AMD_PP_GFX_PROFILE
;
3705 pi
->default_compute_power_profile
= pi
->default_gfx_power_profile
;
3706 pi
->default_compute_power_profile
.type
= AMD_PP_COMPUTE_PROFILE
;
3708 /* Optimize compute power profile: Use only highest
3709 * 2 power levels (if more than 2 are available), Hysteresis:
3712 if (pi
->smc_state_table
.GraphicsDpmLevelCount
> 2)
3713 min_level
= pi
->smc_state_table
.GraphicsDpmLevelCount
- 2;
3714 else if (pi
->smc_state_table
.GraphicsDpmLevelCount
== 2)
3716 pi
->default_compute_power_profile
.min_sclk
=
3717 be32_to_cpu(levels
[min_level
].SclkFrequency
);
3719 pi
->default_compute_power_profile
.up_hyst
= 0;
3720 pi
->default_compute_power_profile
.down_hyst
= 5;
3722 pi
->gfx_power_profile
= pi
->default_gfx_power_profile
;
3723 pi
->compute_power_profile
= pi
->default_compute_power_profile
;
3726 static int ci_init_smc_table(struct amdgpu_device
*adev
)
3728 struct ci_power_info
*pi
= ci_get_pi(adev
);
3729 struct ci_ulv_parm
*ulv
= &pi
->ulv
;
3730 struct amdgpu_ps
*amdgpu_boot_state
= adev
->pm
.dpm
.boot_ps
;
3731 SMU7_Discrete_DpmTable
*table
= &pi
->smc_state_table
;
3734 ret
= ci_setup_default_dpm_tables(adev
);
3738 if (pi
->voltage_control
!= CISLANDS_VOLTAGE_CONTROL_NONE
)
3739 ci_populate_smc_voltage_tables(adev
, table
);
3741 ci_init_fps_limits(adev
);
3743 if (adev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_HARDWAREDC
)
3744 table
->SystemFlags
|= PPSMC_SYSTEMFLAG_GPIO_DC
;
3746 if (adev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_STEPVDDC
)
3747 table
->SystemFlags
|= PPSMC_SYSTEMFLAG_STEPVDDC
;
3749 if (adev
->mc
.vram_type
== AMDGPU_VRAM_TYPE_GDDR5
)
3750 table
->SystemFlags
|= PPSMC_SYSTEMFLAG_GDDR5
;
3752 if (ulv
->supported
) {
3753 ret
= ci_populate_ulv_state(adev
, &pi
->smc_state_table
.Ulv
);
3756 WREG32_SMC(ixCG_ULV_PARAMETER
, ulv
->cg_ulv_parameter
);
3759 ret
= ci_populate_all_graphic_levels(adev
);
3763 ret
= ci_populate_all_memory_levels(adev
);
3767 ci_populate_smc_link_level(adev
, table
);
3769 ret
= ci_populate_smc_acpi_level(adev
, table
);
3773 ret
= ci_populate_smc_vce_level(adev
, table
);
3777 ret
= ci_populate_smc_acp_level(adev
, table
);
3781 ret
= ci_populate_smc_samu_level(adev
, table
);
3785 ret
= ci_do_program_memory_timing_parameters(adev
);
3789 ret
= ci_populate_smc_uvd_level(adev
, table
);
3793 table
->UvdBootLevel
= 0;
3794 table
->VceBootLevel
= 0;
3795 table
->AcpBootLevel
= 0;
3796 table
->SamuBootLevel
= 0;
3797 table
->GraphicsBootLevel
= 0;
3798 table
->MemoryBootLevel
= 0;
3800 ret
= ci_find_boot_level(&pi
->dpm_table
.sclk_table
,
3801 pi
->vbios_boot_state
.sclk_bootup_value
,
3802 (u32
*)&pi
->smc_state_table
.GraphicsBootLevel
);
3804 ret
= ci_find_boot_level(&pi
->dpm_table
.mclk_table
,
3805 pi
->vbios_boot_state
.mclk_bootup_value
,
3806 (u32
*)&pi
->smc_state_table
.MemoryBootLevel
);
3808 table
->BootVddc
= pi
->vbios_boot_state
.vddc_bootup_value
;
3809 table
->BootVddci
= pi
->vbios_boot_state
.vddci_bootup_value
;
3810 table
->BootMVdd
= pi
->vbios_boot_state
.mvdd_bootup_value
;
3812 ci_populate_smc_initial_state(adev
, amdgpu_boot_state
);
3814 ret
= ci_populate_bapm_parameters_in_dpm_table(adev
);
3818 table
->UVDInterval
= 1;
3819 table
->VCEInterval
= 1;
3820 table
->ACPInterval
= 1;
3821 table
->SAMUInterval
= 1;
3822 table
->GraphicsVoltageChangeEnable
= 1;
3823 table
->GraphicsThermThrottleEnable
= 1;
3824 table
->GraphicsInterval
= 1;
3825 table
->VoltageInterval
= 1;
3826 table
->ThermalInterval
= 1;
3827 table
->TemperatureLimitHigh
= (u16
)((pi
->thermal_temp_setting
.temperature_high
*
3828 CISLANDS_Q88_FORMAT_CONVERSION_UNIT
) / 1000);
3829 table
->TemperatureLimitLow
= (u16
)((pi
->thermal_temp_setting
.temperature_low
*
3830 CISLANDS_Q88_FORMAT_CONVERSION_UNIT
) / 1000);
3831 table
->MemoryVoltageChangeEnable
= 1;
3832 table
->MemoryInterval
= 1;
3833 table
->VoltageResponseTime
= 0;
3834 table
->VddcVddciDelta
= 4000;
3835 table
->PhaseResponseTime
= 0;
3836 table
->MemoryThermThrottleEnable
= 1;
3837 table
->PCIeBootLinkLevel
= pi
->dpm_table
.pcie_speed_table
.count
- 1;
3838 table
->PCIeGenInterval
= 1;
3839 if (pi
->voltage_control
== CISLANDS_VOLTAGE_CONTROL_BY_SVID2
)
3840 table
->SVI2Enable
= 1;
3842 table
->SVI2Enable
= 0;
3844 table
->ThermGpio
= 17;
3845 table
->SclkStepSize
= 0x4000;
3847 table
->SystemFlags
= cpu_to_be32(table
->SystemFlags
);
3848 table
->SmioMaskVddcVid
= cpu_to_be32(table
->SmioMaskVddcVid
);
3849 table
->SmioMaskVddcPhase
= cpu_to_be32(table
->SmioMaskVddcPhase
);
3850 table
->SmioMaskVddciVid
= cpu_to_be32(table
->SmioMaskVddciVid
);
3851 table
->SmioMaskMvddVid
= cpu_to_be32(table
->SmioMaskMvddVid
);
3852 table
->SclkStepSize
= cpu_to_be32(table
->SclkStepSize
);
3853 table
->TemperatureLimitHigh
= cpu_to_be16(table
->TemperatureLimitHigh
);
3854 table
->TemperatureLimitLow
= cpu_to_be16(table
->TemperatureLimitLow
);
3855 table
->VddcVddciDelta
= cpu_to_be16(table
->VddcVddciDelta
);
3856 table
->VoltageResponseTime
= cpu_to_be16(table
->VoltageResponseTime
);
3857 table
->PhaseResponseTime
= cpu_to_be16(table
->PhaseResponseTime
);
3858 table
->BootVddc
= cpu_to_be16(table
->BootVddc
* VOLTAGE_SCALE
);
3859 table
->BootVddci
= cpu_to_be16(table
->BootVddci
* VOLTAGE_SCALE
);
3860 table
->BootMVdd
= cpu_to_be16(table
->BootMVdd
* VOLTAGE_SCALE
);
3862 ret
= amdgpu_ci_copy_bytes_to_smc(adev
,
3863 pi
->dpm_table_start
+
3864 offsetof(SMU7_Discrete_DpmTable
, SystemFlags
),
3865 (u8
*)&table
->SystemFlags
,
3866 sizeof(SMU7_Discrete_DpmTable
) - 3 * sizeof(SMU7_PIDController
),
3871 ci_save_default_power_profile(adev
);
3876 static void ci_trim_single_dpm_states(struct amdgpu_device
*adev
,
3877 struct ci_single_dpm_table
*dpm_table
,
3878 u32 low_limit
, u32 high_limit
)
3882 for (i
= 0; i
< dpm_table
->count
; i
++) {
3883 if ((dpm_table
->dpm_levels
[i
].value
< low_limit
) ||
3884 (dpm_table
->dpm_levels
[i
].value
> high_limit
))
3885 dpm_table
->dpm_levels
[i
].enabled
= false;
3887 dpm_table
->dpm_levels
[i
].enabled
= true;
3891 static void ci_trim_pcie_dpm_states(struct amdgpu_device
*adev
,
3892 u32 speed_low
, u32 lanes_low
,
3893 u32 speed_high
, u32 lanes_high
)
3895 struct ci_power_info
*pi
= ci_get_pi(adev
);
3896 struct ci_single_dpm_table
*pcie_table
= &pi
->dpm_table
.pcie_speed_table
;
3899 for (i
= 0; i
< pcie_table
->count
; i
++) {
3900 if ((pcie_table
->dpm_levels
[i
].value
< speed_low
) ||
3901 (pcie_table
->dpm_levels
[i
].param1
< lanes_low
) ||
3902 (pcie_table
->dpm_levels
[i
].value
> speed_high
) ||
3903 (pcie_table
->dpm_levels
[i
].param1
> lanes_high
))
3904 pcie_table
->dpm_levels
[i
].enabled
= false;
3906 pcie_table
->dpm_levels
[i
].enabled
= true;
3909 for (i
= 0; i
< pcie_table
->count
; i
++) {
3910 if (pcie_table
->dpm_levels
[i
].enabled
) {
3911 for (j
= i
+ 1; j
< pcie_table
->count
; j
++) {
3912 if (pcie_table
->dpm_levels
[j
].enabled
) {
3913 if ((pcie_table
->dpm_levels
[i
].value
== pcie_table
->dpm_levels
[j
].value
) &&
3914 (pcie_table
->dpm_levels
[i
].param1
== pcie_table
->dpm_levels
[j
].param1
))
3915 pcie_table
->dpm_levels
[j
].enabled
= false;
3922 static int ci_trim_dpm_states(struct amdgpu_device
*adev
,
3923 struct amdgpu_ps
*amdgpu_state
)
3925 struct ci_ps
*state
= ci_get_ps(amdgpu_state
);
3926 struct ci_power_info
*pi
= ci_get_pi(adev
);
3927 u32 high_limit_count
;
3929 if (state
->performance_level_count
< 1)
3932 if (state
->performance_level_count
== 1)
3933 high_limit_count
= 0;
3935 high_limit_count
= 1;
3937 ci_trim_single_dpm_states(adev
,
3938 &pi
->dpm_table
.sclk_table
,
3939 state
->performance_levels
[0].sclk
,
3940 state
->performance_levels
[high_limit_count
].sclk
);
3942 ci_trim_single_dpm_states(adev
,
3943 &pi
->dpm_table
.mclk_table
,
3944 state
->performance_levels
[0].mclk
,
3945 state
->performance_levels
[high_limit_count
].mclk
);
3947 ci_trim_pcie_dpm_states(adev
,
3948 state
->performance_levels
[0].pcie_gen
,
3949 state
->performance_levels
[0].pcie_lane
,
3950 state
->performance_levels
[high_limit_count
].pcie_gen
,
3951 state
->performance_levels
[high_limit_count
].pcie_lane
);
3956 static int ci_apply_disp_minimum_voltage_request(struct amdgpu_device
*adev
)
3958 struct amdgpu_clock_voltage_dependency_table
*disp_voltage_table
=
3959 &adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
;
3960 struct amdgpu_clock_voltage_dependency_table
*vddc_table
=
3961 &adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
;
3962 u32 requested_voltage
= 0;
3965 if (disp_voltage_table
== NULL
)
3967 if (!disp_voltage_table
->count
)
3970 for (i
= 0; i
< disp_voltage_table
->count
; i
++) {
3971 if (adev
->clock
.current_dispclk
== disp_voltage_table
->entries
[i
].clk
)
3972 requested_voltage
= disp_voltage_table
->entries
[i
].v
;
3975 for (i
= 0; i
< vddc_table
->count
; i
++) {
3976 if (requested_voltage
<= vddc_table
->entries
[i
].v
) {
3977 requested_voltage
= vddc_table
->entries
[i
].v
;
3978 return (amdgpu_ci_send_msg_to_smc_with_parameter(adev
,
3979 PPSMC_MSG_VddC_Request
,
3980 requested_voltage
* VOLTAGE_SCALE
) == PPSMC_Result_OK
) ?
3988 static int ci_upload_dpm_level_enable_mask(struct amdgpu_device
*adev
)
3990 struct ci_power_info
*pi
= ci_get_pi(adev
);
3991 PPSMC_Result result
;
3993 ci_apply_disp_minimum_voltage_request(adev
);
3995 if (!pi
->sclk_dpm_key_disabled
) {
3996 if (pi
->dpm_level_enable_mask
.sclk_dpm_enable_mask
) {
3997 result
= amdgpu_ci_send_msg_to_smc_with_parameter(adev
,
3998 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
3999 pi
->dpm_level_enable_mask
.sclk_dpm_enable_mask
);
4000 if (result
!= PPSMC_Result_OK
)
4005 if (!pi
->mclk_dpm_key_disabled
) {
4006 if (pi
->dpm_level_enable_mask
.mclk_dpm_enable_mask
) {
4007 result
= amdgpu_ci_send_msg_to_smc_with_parameter(adev
,
4008 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
4009 pi
->dpm_level_enable_mask
.mclk_dpm_enable_mask
);
4010 if (result
!= PPSMC_Result_OK
)
4016 if (!pi
->pcie_dpm_key_disabled
) {
4017 if (pi
->dpm_level_enable_mask
.pcie_dpm_enable_mask
) {
4018 result
= amdgpu_ci_send_msg_to_smc_with_parameter(adev
,
4019 PPSMC_MSG_PCIeDPM_SetEnabledMask
,
4020 pi
->dpm_level_enable_mask
.pcie_dpm_enable_mask
);
4021 if (result
!= PPSMC_Result_OK
)
4030 static void ci_find_dpm_states_clocks_in_dpm_table(struct amdgpu_device
*adev
,
4031 struct amdgpu_ps
*amdgpu_state
)
4033 struct ci_power_info
*pi
= ci_get_pi(adev
);
4034 struct ci_ps
*state
= ci_get_ps(amdgpu_state
);
4035 struct ci_single_dpm_table
*sclk_table
= &pi
->dpm_table
.sclk_table
;
4036 u32 sclk
= state
->performance_levels
[state
->performance_level_count
-1].sclk
;
4037 struct ci_single_dpm_table
*mclk_table
= &pi
->dpm_table
.mclk_table
;
4038 u32 mclk
= state
->performance_levels
[state
->performance_level_count
-1].mclk
;
4041 pi
->need_update_smu7_dpm_table
= 0;
4043 for (i
= 0; i
< sclk_table
->count
; i
++) {
4044 if (sclk
== sclk_table
->dpm_levels
[i
].value
)
4048 if (i
>= sclk_table
->count
) {
4049 pi
->need_update_smu7_dpm_table
|= DPMTABLE_OD_UPDATE_SCLK
;
4051 /* XXX check display min clock requirements */
4052 if (CISLAND_MINIMUM_ENGINE_CLOCK
!= CISLAND_MINIMUM_ENGINE_CLOCK
)
4053 pi
->need_update_smu7_dpm_table
|= DPMTABLE_UPDATE_SCLK
;
4056 for (i
= 0; i
< mclk_table
->count
; i
++) {
4057 if (mclk
== mclk_table
->dpm_levels
[i
].value
)
4061 if (i
>= mclk_table
->count
)
4062 pi
->need_update_smu7_dpm_table
|= DPMTABLE_OD_UPDATE_MCLK
;
4064 if (adev
->pm
.dpm
.current_active_crtc_count
!=
4065 adev
->pm
.dpm
.new_active_crtc_count
)
4066 pi
->need_update_smu7_dpm_table
|= DPMTABLE_UPDATE_MCLK
;
4069 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct amdgpu_device
*adev
,
4070 struct amdgpu_ps
*amdgpu_state
)
4072 struct ci_power_info
*pi
= ci_get_pi(adev
);
4073 struct ci_ps
*state
= ci_get_ps(amdgpu_state
);
4074 u32 sclk
= state
->performance_levels
[state
->performance_level_count
-1].sclk
;
4075 u32 mclk
= state
->performance_levels
[state
->performance_level_count
-1].mclk
;
4076 struct ci_dpm_table
*dpm_table
= &pi
->dpm_table
;
4079 if (!pi
->need_update_smu7_dpm_table
)
4082 if (pi
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_SCLK
)
4083 dpm_table
->sclk_table
.dpm_levels
[dpm_table
->sclk_table
.count
-1].value
= sclk
;
4085 if (pi
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_MCLK
)
4086 dpm_table
->mclk_table
.dpm_levels
[dpm_table
->mclk_table
.count
-1].value
= mclk
;
4088 if (pi
->need_update_smu7_dpm_table
& (DPMTABLE_OD_UPDATE_SCLK
| DPMTABLE_UPDATE_SCLK
)) {
4089 ret
= ci_populate_all_graphic_levels(adev
);
4094 if (pi
->need_update_smu7_dpm_table
& (DPMTABLE_OD_UPDATE_MCLK
| DPMTABLE_UPDATE_MCLK
)) {
4095 ret
= ci_populate_all_memory_levels(adev
);
4103 static int ci_enable_uvd_dpm(struct amdgpu_device
*adev
, bool enable
)
4105 struct ci_power_info
*pi
= ci_get_pi(adev
);
4106 const struct amdgpu_clock_and_voltage_limits
*max_limits
;
4109 if (adev
->pm
.dpm
.ac_power
)
4110 max_limits
= &adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
;
4112 max_limits
= &adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_dc
;
4115 pi
->dpm_level_enable_mask
.uvd_dpm_enable_mask
= 0;
4117 for (i
= adev
->pm
.dpm
.dyn_state
.uvd_clock_voltage_dependency_table
.count
- 1; i
>= 0; i
--) {
4118 if (adev
->pm
.dpm
.dyn_state
.uvd_clock_voltage_dependency_table
.entries
[i
].v
<= max_limits
->vddc
) {
4119 pi
->dpm_level_enable_mask
.uvd_dpm_enable_mask
|= 1 << i
;
4121 if (!pi
->caps_uvd_dpm
)
4126 amdgpu_ci_send_msg_to_smc_with_parameter(adev
,
4127 PPSMC_MSG_UVDDPM_SetEnabledMask
,
4128 pi
->dpm_level_enable_mask
.uvd_dpm_enable_mask
);
4130 if (pi
->last_mclk_dpm_enable_mask
& 0x1) {
4131 pi
->uvd_enabled
= true;
4132 pi
->dpm_level_enable_mask
.mclk_dpm_enable_mask
&= 0xFFFFFFFE;
4133 amdgpu_ci_send_msg_to_smc_with_parameter(adev
,
4134 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
4135 pi
->dpm_level_enable_mask
.mclk_dpm_enable_mask
);
4138 if (pi
->uvd_enabled
) {
4139 pi
->uvd_enabled
= false;
4140 pi
->dpm_level_enable_mask
.mclk_dpm_enable_mask
|= 1;
4141 amdgpu_ci_send_msg_to_smc_with_parameter(adev
,
4142 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
4143 pi
->dpm_level_enable_mask
.mclk_dpm_enable_mask
);
4147 return (amdgpu_ci_send_msg_to_smc(adev
, enable
?
4148 PPSMC_MSG_UVDDPM_Enable
: PPSMC_MSG_UVDDPM_Disable
) == PPSMC_Result_OK
) ?
4152 static int ci_enable_vce_dpm(struct amdgpu_device
*adev
, bool enable
)
4154 struct ci_power_info
*pi
= ci_get_pi(adev
);
4155 const struct amdgpu_clock_and_voltage_limits
*max_limits
;
4158 if (adev
->pm
.dpm
.ac_power
)
4159 max_limits
= &adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
;
4161 max_limits
= &adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_dc
;
4164 pi
->dpm_level_enable_mask
.vce_dpm_enable_mask
= 0;
4165 for (i
= adev
->pm
.dpm
.dyn_state
.vce_clock_voltage_dependency_table
.count
- 1; i
>= 0; i
--) {
4166 if (adev
->pm
.dpm
.dyn_state
.vce_clock_voltage_dependency_table
.entries
[i
].v
<= max_limits
->vddc
) {
4167 pi
->dpm_level_enable_mask
.vce_dpm_enable_mask
|= 1 << i
;
4169 if (!pi
->caps_vce_dpm
)
4174 amdgpu_ci_send_msg_to_smc_with_parameter(adev
,
4175 PPSMC_MSG_VCEDPM_SetEnabledMask
,
4176 pi
->dpm_level_enable_mask
.vce_dpm_enable_mask
);
4179 return (amdgpu_ci_send_msg_to_smc(adev
, enable
?
4180 PPSMC_MSG_VCEDPM_Enable
: PPSMC_MSG_VCEDPM_Disable
) == PPSMC_Result_OK
) ?
4185 static int ci_enable_samu_dpm(struct amdgpu_device
*adev
, bool enable
)
4187 struct ci_power_info
*pi
= ci_get_pi(adev
);
4188 const struct amdgpu_clock_and_voltage_limits
*max_limits
;
4191 if (adev
->pm
.dpm
.ac_power
)
4192 max_limits
= &adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
;
4194 max_limits
= &adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_dc
;
4197 pi
->dpm_level_enable_mask
.samu_dpm_enable_mask
= 0;
4198 for (i
= adev
->pm
.dpm
.dyn_state
.samu_clock_voltage_dependency_table
.count
- 1; i
>= 0; i
--) {
4199 if (adev
->pm
.dpm
.dyn_state
.samu_clock_voltage_dependency_table
.entries
[i
].v
<= max_limits
->vddc
) {
4200 pi
->dpm_level_enable_mask
.samu_dpm_enable_mask
|= 1 << i
;
4202 if (!pi
->caps_samu_dpm
)
4207 amdgpu_ci_send_msg_to_smc_with_parameter(adev
,
4208 PPSMC_MSG_SAMUDPM_SetEnabledMask
,
4209 pi
->dpm_level_enable_mask
.samu_dpm_enable_mask
);
4211 return (amdgpu_ci_send_msg_to_smc(adev
, enable
?
4212 PPSMC_MSG_SAMUDPM_Enable
: PPSMC_MSG_SAMUDPM_Disable
) == PPSMC_Result_OK
) ?
4216 static int ci_enable_acp_dpm(struct amdgpu_device
*adev
, bool enable
)
4218 struct ci_power_info
*pi
= ci_get_pi(adev
);
4219 const struct amdgpu_clock_and_voltage_limits
*max_limits
;
4222 if (adev
->pm
.dpm
.ac_power
)
4223 max_limits
= &adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
;
4225 max_limits
= &adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_dc
;
4228 pi
->dpm_level_enable_mask
.acp_dpm_enable_mask
= 0;
4229 for (i
= adev
->pm
.dpm
.dyn_state
.acp_clock_voltage_dependency_table
.count
- 1; i
>= 0; i
--) {
4230 if (adev
->pm
.dpm
.dyn_state
.acp_clock_voltage_dependency_table
.entries
[i
].v
<= max_limits
->vddc
) {
4231 pi
->dpm_level_enable_mask
.acp_dpm_enable_mask
|= 1 << i
;
4233 if (!pi
->caps_acp_dpm
)
4238 amdgpu_ci_send_msg_to_smc_with_parameter(adev
,
4239 PPSMC_MSG_ACPDPM_SetEnabledMask
,
4240 pi
->dpm_level_enable_mask
.acp_dpm_enable_mask
);
4243 return (amdgpu_ci_send_msg_to_smc(adev
, enable
?
4244 PPSMC_MSG_ACPDPM_Enable
: PPSMC_MSG_ACPDPM_Disable
) == PPSMC_Result_OK
) ?
4249 static int ci_update_uvd_dpm(struct amdgpu_device
*adev
, bool gate
)
4251 struct ci_power_info
*pi
= ci_get_pi(adev
);
4256 /* turn the clocks on when decoding */
4257 if (pi
->caps_uvd_dpm
||
4258 (adev
->pm
.dpm
.dyn_state
.uvd_clock_voltage_dependency_table
.count
<= 0))
4259 pi
->smc_state_table
.UvdBootLevel
= 0;
4261 pi
->smc_state_table
.UvdBootLevel
=
4262 adev
->pm
.dpm
.dyn_state
.uvd_clock_voltage_dependency_table
.count
- 1;
4264 tmp
= RREG32_SMC(ixDPM_TABLE_475
);
4265 tmp
&= ~DPM_TABLE_475__UvdBootLevel_MASK
;
4266 tmp
|= (pi
->smc_state_table
.UvdBootLevel
<< DPM_TABLE_475__UvdBootLevel__SHIFT
);
4267 WREG32_SMC(ixDPM_TABLE_475
, tmp
);
4268 ret
= ci_enable_uvd_dpm(adev
, true);
4270 ret
= ci_enable_uvd_dpm(adev
, false);
4278 static u8
ci_get_vce_boot_level(struct amdgpu_device
*adev
)
4281 u32 min_evclk
= 30000; /* ??? */
4282 struct amdgpu_vce_clock_voltage_dependency_table
*table
=
4283 &adev
->pm
.dpm
.dyn_state
.vce_clock_voltage_dependency_table
;
4285 for (i
= 0; i
< table
->count
; i
++) {
4286 if (table
->entries
[i
].evclk
>= min_evclk
)
4290 return table
->count
- 1;
4293 static int ci_update_vce_dpm(struct amdgpu_device
*adev
,
4294 struct amdgpu_ps
*amdgpu_new_state
,
4295 struct amdgpu_ps
*amdgpu_current_state
)
4297 struct ci_power_info
*pi
= ci_get_pi(adev
);
4301 if (amdgpu_current_state
->evclk
!= amdgpu_new_state
->evclk
) {
4302 if (amdgpu_new_state
->evclk
) {
4303 pi
->smc_state_table
.VceBootLevel
= ci_get_vce_boot_level(adev
);
4304 tmp
= RREG32_SMC(ixDPM_TABLE_475
);
4305 tmp
&= ~DPM_TABLE_475__VceBootLevel_MASK
;
4306 tmp
|= (pi
->smc_state_table
.VceBootLevel
<< DPM_TABLE_475__VceBootLevel__SHIFT
);
4307 WREG32_SMC(ixDPM_TABLE_475
, tmp
);
4309 ret
= ci_enable_vce_dpm(adev
, true);
4311 ret
= ci_enable_vce_dpm(adev
, false);
4320 static int ci_update_samu_dpm(struct amdgpu_device
*adev
, bool gate
)
4322 return ci_enable_samu_dpm(adev
, gate
);
4325 static int ci_update_acp_dpm(struct amdgpu_device
*adev
, bool gate
)
4327 struct ci_power_info
*pi
= ci_get_pi(adev
);
4331 pi
->smc_state_table
.AcpBootLevel
= 0;
4333 tmp
= RREG32_SMC(ixDPM_TABLE_475
);
4334 tmp
&= ~AcpBootLevel_MASK
;
4335 tmp
|= AcpBootLevel(pi
->smc_state_table
.AcpBootLevel
);
4336 WREG32_SMC(ixDPM_TABLE_475
, tmp
);
4339 return ci_enable_acp_dpm(adev
, !gate
);
4343 static int ci_generate_dpm_level_enable_mask(struct amdgpu_device
*adev
,
4344 struct amdgpu_ps
*amdgpu_state
)
4346 struct ci_power_info
*pi
= ci_get_pi(adev
);
4349 ret
= ci_trim_dpm_states(adev
, amdgpu_state
);
4353 pi
->dpm_level_enable_mask
.sclk_dpm_enable_mask
=
4354 ci_get_dpm_level_enable_mask_value(&pi
->dpm_table
.sclk_table
);
4355 pi
->dpm_level_enable_mask
.mclk_dpm_enable_mask
=
4356 ci_get_dpm_level_enable_mask_value(&pi
->dpm_table
.mclk_table
);
4357 pi
->last_mclk_dpm_enable_mask
=
4358 pi
->dpm_level_enable_mask
.mclk_dpm_enable_mask
;
4359 if (pi
->uvd_enabled
) {
4360 if (pi
->dpm_level_enable_mask
.mclk_dpm_enable_mask
& 1)
4361 pi
->dpm_level_enable_mask
.mclk_dpm_enable_mask
&= 0xFFFFFFFE;
4363 pi
->dpm_level_enable_mask
.pcie_dpm_enable_mask
=
4364 ci_get_dpm_level_enable_mask_value(&pi
->dpm_table
.pcie_speed_table
);
4369 static u32
ci_get_lowest_enabled_level(struct amdgpu_device
*adev
,
4374 while ((level_mask
& (1 << level
)) == 0)
4381 static int ci_dpm_force_performance_level(struct amdgpu_device
*adev
,
4382 enum amd_dpm_forced_level level
)
4384 struct ci_power_info
*pi
= ci_get_pi(adev
);
4388 if (level
== AMD_DPM_FORCED_LEVEL_HIGH
) {
4389 if ((!pi
->pcie_dpm_key_disabled
) &&
4390 pi
->dpm_level_enable_mask
.pcie_dpm_enable_mask
) {
4392 tmp
= pi
->dpm_level_enable_mask
.pcie_dpm_enable_mask
;
4396 ret
= ci_dpm_force_state_pcie(adev
, level
);
4399 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
4400 tmp
= (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1
) &
4401 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK
) >>
4402 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT
;
4409 if ((!pi
->sclk_dpm_key_disabled
) &&
4410 pi
->dpm_level_enable_mask
.sclk_dpm_enable_mask
) {
4412 tmp
= pi
->dpm_level_enable_mask
.sclk_dpm_enable_mask
;
4416 ret
= ci_dpm_force_state_sclk(adev
, levels
);
4419 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
4420 tmp
= (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX
) &
4421 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK
) >>
4422 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT
;
4429 if ((!pi
->mclk_dpm_key_disabled
) &&
4430 pi
->dpm_level_enable_mask
.mclk_dpm_enable_mask
) {
4432 tmp
= pi
->dpm_level_enable_mask
.mclk_dpm_enable_mask
;
4436 ret
= ci_dpm_force_state_mclk(adev
, levels
);
4439 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
4440 tmp
= (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX
) &
4441 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK
) >>
4442 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT
;
4449 } else if (level
== AMD_DPM_FORCED_LEVEL_LOW
) {
4450 if ((!pi
->sclk_dpm_key_disabled
) &&
4451 pi
->dpm_level_enable_mask
.sclk_dpm_enable_mask
) {
4452 levels
= ci_get_lowest_enabled_level(adev
,
4453 pi
->dpm_level_enable_mask
.sclk_dpm_enable_mask
);
4454 ret
= ci_dpm_force_state_sclk(adev
, levels
);
4457 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
4458 tmp
= (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX
) &
4459 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK
) >>
4460 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT
;
4466 if ((!pi
->mclk_dpm_key_disabled
) &&
4467 pi
->dpm_level_enable_mask
.mclk_dpm_enable_mask
) {
4468 levels
= ci_get_lowest_enabled_level(adev
,
4469 pi
->dpm_level_enable_mask
.mclk_dpm_enable_mask
);
4470 ret
= ci_dpm_force_state_mclk(adev
, levels
);
4473 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
4474 tmp
= (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX
) &
4475 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK
) >>
4476 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT
;
4482 if ((!pi
->pcie_dpm_key_disabled
) &&
4483 pi
->dpm_level_enable_mask
.pcie_dpm_enable_mask
) {
4484 levels
= ci_get_lowest_enabled_level(adev
,
4485 pi
->dpm_level_enable_mask
.pcie_dpm_enable_mask
);
4486 ret
= ci_dpm_force_state_pcie(adev
, levels
);
4489 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
4490 tmp
= (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1
) &
4491 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK
) >>
4492 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT
;
4498 } else if (level
== AMD_DPM_FORCED_LEVEL_AUTO
) {
4499 if (!pi
->pcie_dpm_key_disabled
) {
4500 PPSMC_Result smc_result
;
4502 smc_result
= amdgpu_ci_send_msg_to_smc(adev
,
4503 PPSMC_MSG_PCIeDPM_UnForceLevel
);
4504 if (smc_result
!= PPSMC_Result_OK
)
4507 ret
= ci_upload_dpm_level_enable_mask(adev
);
4512 adev
->pm
.dpm
.forced_level
= level
;
4517 static int ci_set_mc_special_registers(struct amdgpu_device
*adev
,
4518 struct ci_mc_reg_table
*table
)
4523 for (i
= 0, j
= table
->last
; i
< table
->last
; i
++) {
4524 if (j
>= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE
)
4526 switch(table
->mc_reg_address
[i
].s1
) {
4527 case mmMC_SEQ_MISC1
:
4528 temp_reg
= RREG32(mmMC_PMG_CMD_EMRS
);
4529 table
->mc_reg_address
[j
].s1
= mmMC_PMG_CMD_EMRS
;
4530 table
->mc_reg_address
[j
].s0
= mmMC_SEQ_PMG_CMD_EMRS_LP
;
4531 for (k
= 0; k
< table
->num_entries
; k
++) {
4532 table
->mc_reg_table_entry
[k
].mc_data
[j
] =
4533 ((temp_reg
& 0xffff0000)) | ((table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0xffff0000) >> 16);
4536 if (j
>= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE
)
4539 temp_reg
= RREG32(mmMC_PMG_CMD_MRS
);
4540 table
->mc_reg_address
[j
].s1
= mmMC_PMG_CMD_MRS
;
4541 table
->mc_reg_address
[j
].s0
= mmMC_SEQ_PMG_CMD_MRS_LP
;
4542 for (k
= 0; k
< table
->num_entries
; k
++) {
4543 table
->mc_reg_table_entry
[k
].mc_data
[j
] =
4544 (temp_reg
& 0xffff0000) | (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0x0000ffff);
4545 if (adev
->mc
.vram_type
!= AMDGPU_VRAM_TYPE_GDDR5
)
4546 table
->mc_reg_table_entry
[k
].mc_data
[j
] |= 0x100;
4549 if (j
> SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE
)
4552 if (adev
->mc
.vram_type
!= AMDGPU_VRAM_TYPE_GDDR5
) {
4553 table
->mc_reg_address
[j
].s1
= mmMC_PMG_AUTO_CMD
;
4554 table
->mc_reg_address
[j
].s0
= mmMC_PMG_AUTO_CMD
;
4555 for (k
= 0; k
< table
->num_entries
; k
++) {
4556 table
->mc_reg_table_entry
[k
].mc_data
[j
] =
4557 (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0xffff0000) >> 16;
4560 if (j
> SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE
)
4564 case mmMC_SEQ_RESERVE_M
:
4565 temp_reg
= RREG32(mmMC_PMG_CMD_MRS1
);
4566 table
->mc_reg_address
[j
].s1
= mmMC_PMG_CMD_MRS1
;
4567 table
->mc_reg_address
[j
].s0
= mmMC_SEQ_PMG_CMD_MRS1_LP
;
4568 for (k
= 0; k
< table
->num_entries
; k
++) {
4569 table
->mc_reg_table_entry
[k
].mc_data
[j
] =
4570 (temp_reg
& 0xffff0000) | (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0x0000ffff);
4573 if (j
> SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE
)
4587 static bool ci_check_s0_mc_reg_index(u16 in_reg
, u16
*out_reg
)
4592 case mmMC_SEQ_RAS_TIMING
:
4593 *out_reg
= mmMC_SEQ_RAS_TIMING_LP
;
4595 case mmMC_SEQ_DLL_STBY
:
4596 *out_reg
= mmMC_SEQ_DLL_STBY_LP
;
4598 case mmMC_SEQ_G5PDX_CMD0
:
4599 *out_reg
= mmMC_SEQ_G5PDX_CMD0_LP
;
4601 case mmMC_SEQ_G5PDX_CMD1
:
4602 *out_reg
= mmMC_SEQ_G5PDX_CMD1_LP
;
4604 case mmMC_SEQ_G5PDX_CTRL
:
4605 *out_reg
= mmMC_SEQ_G5PDX_CTRL_LP
;
4607 case mmMC_SEQ_CAS_TIMING
:
4608 *out_reg
= mmMC_SEQ_CAS_TIMING_LP
;
4610 case mmMC_SEQ_MISC_TIMING
:
4611 *out_reg
= mmMC_SEQ_MISC_TIMING_LP
;
4613 case mmMC_SEQ_MISC_TIMING2
:
4614 *out_reg
= mmMC_SEQ_MISC_TIMING2_LP
;
4616 case mmMC_SEQ_PMG_DVS_CMD
:
4617 *out_reg
= mmMC_SEQ_PMG_DVS_CMD_LP
;
4619 case mmMC_SEQ_PMG_DVS_CTL
:
4620 *out_reg
= mmMC_SEQ_PMG_DVS_CTL_LP
;
4622 case mmMC_SEQ_RD_CTL_D0
:
4623 *out_reg
= mmMC_SEQ_RD_CTL_D0_LP
;
4625 case mmMC_SEQ_RD_CTL_D1
:
4626 *out_reg
= mmMC_SEQ_RD_CTL_D1_LP
;
4628 case mmMC_SEQ_WR_CTL_D0
:
4629 *out_reg
= mmMC_SEQ_WR_CTL_D0_LP
;
4631 case mmMC_SEQ_WR_CTL_D1
:
4632 *out_reg
= mmMC_SEQ_WR_CTL_D1_LP
;
4634 case mmMC_PMG_CMD_EMRS
:
4635 *out_reg
= mmMC_SEQ_PMG_CMD_EMRS_LP
;
4637 case mmMC_PMG_CMD_MRS
:
4638 *out_reg
= mmMC_SEQ_PMG_CMD_MRS_LP
;
4640 case mmMC_PMG_CMD_MRS1
:
4641 *out_reg
= mmMC_SEQ_PMG_CMD_MRS1_LP
;
4643 case mmMC_SEQ_PMG_TIMING
:
4644 *out_reg
= mmMC_SEQ_PMG_TIMING_LP
;
4646 case mmMC_PMG_CMD_MRS2
:
4647 *out_reg
= mmMC_SEQ_PMG_CMD_MRS2_LP
;
4649 case mmMC_SEQ_WR_CTL_2
:
4650 *out_reg
= mmMC_SEQ_WR_CTL_2_LP
;
4660 static void ci_set_valid_flag(struct ci_mc_reg_table
*table
)
4664 for (i
= 0; i
< table
->last
; i
++) {
4665 for (j
= 1; j
< table
->num_entries
; j
++) {
4666 if (table
->mc_reg_table_entry
[j
-1].mc_data
[i
] !=
4667 table
->mc_reg_table_entry
[j
].mc_data
[i
]) {
4668 table
->valid_flag
|= 1 << i
;
4675 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table
*table
)
4680 for (i
= 0; i
< table
->last
; i
++) {
4681 table
->mc_reg_address
[i
].s0
=
4682 ci_check_s0_mc_reg_index(table
->mc_reg_address
[i
].s1
, &address
) ?
4683 address
: table
->mc_reg_address
[i
].s1
;
4687 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table
*table
,
4688 struct ci_mc_reg_table
*ci_table
)
4692 if (table
->last
> SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE
)
4694 if (table
->num_entries
> MAX_AC_TIMING_ENTRIES
)
4697 for (i
= 0; i
< table
->last
; i
++)
4698 ci_table
->mc_reg_address
[i
].s1
= table
->mc_reg_address
[i
].s1
;
4700 ci_table
->last
= table
->last
;
4702 for (i
= 0; i
< table
->num_entries
; i
++) {
4703 ci_table
->mc_reg_table_entry
[i
].mclk_max
=
4704 table
->mc_reg_table_entry
[i
].mclk_max
;
4705 for (j
= 0; j
< table
->last
; j
++)
4706 ci_table
->mc_reg_table_entry
[i
].mc_data
[j
] =
4707 table
->mc_reg_table_entry
[i
].mc_data
[j
];
4709 ci_table
->num_entries
= table
->num_entries
;
4714 static int ci_register_patching_mc_seq(struct amdgpu_device
*adev
,
4715 struct ci_mc_reg_table
*table
)
4721 tmp
= RREG32(mmMC_SEQ_MISC0
);
4722 patch
= ((tmp
& 0x0000f00) == 0x300) ? true : false;
4725 ((adev
->pdev
->device
== 0x67B0) ||
4726 (adev
->pdev
->device
== 0x67B1))) {
4727 for (i
= 0; i
< table
->last
; i
++) {
4728 if (table
->last
>= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE
)
4730 switch (table
->mc_reg_address
[i
].s1
) {
4731 case mmMC_SEQ_MISC1
:
4732 for (k
= 0; k
< table
->num_entries
; k
++) {
4733 if ((table
->mc_reg_table_entry
[k
].mclk_max
== 125000) ||
4734 (table
->mc_reg_table_entry
[k
].mclk_max
== 137500))
4735 table
->mc_reg_table_entry
[k
].mc_data
[i
] =
4736 (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0xFFFFFFF8) |
4740 case mmMC_SEQ_WR_CTL_D0
:
4741 for (k
= 0; k
< table
->num_entries
; k
++) {
4742 if ((table
->mc_reg_table_entry
[k
].mclk_max
== 125000) ||
4743 (table
->mc_reg_table_entry
[k
].mclk_max
== 137500))
4744 table
->mc_reg_table_entry
[k
].mc_data
[i
] =
4745 (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0xFFFF0F00) |
4749 case mmMC_SEQ_WR_CTL_D1
:
4750 for (k
= 0; k
< table
->num_entries
; k
++) {
4751 if ((table
->mc_reg_table_entry
[k
].mclk_max
== 125000) ||
4752 (table
->mc_reg_table_entry
[k
].mclk_max
== 137500))
4753 table
->mc_reg_table_entry
[k
].mc_data
[i
] =
4754 (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0xFFFF0F00) |
4758 case mmMC_SEQ_WR_CTL_2
:
4759 for (k
= 0; k
< table
->num_entries
; k
++) {
4760 if ((table
->mc_reg_table_entry
[k
].mclk_max
== 125000) ||
4761 (table
->mc_reg_table_entry
[k
].mclk_max
== 137500))
4762 table
->mc_reg_table_entry
[k
].mc_data
[i
] = 0;
4765 case mmMC_SEQ_CAS_TIMING
:
4766 for (k
= 0; k
< table
->num_entries
; k
++) {
4767 if (table
->mc_reg_table_entry
[k
].mclk_max
== 125000)
4768 table
->mc_reg_table_entry
[k
].mc_data
[i
] =
4769 (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0xFFE0FE0F) |
4771 else if (table
->mc_reg_table_entry
[k
].mclk_max
== 137500)
4772 table
->mc_reg_table_entry
[k
].mc_data
[i
] =
4773 (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0xFFE0FE0F) |
4777 case mmMC_SEQ_MISC_TIMING
:
4778 for (k
= 0; k
< table
->num_entries
; k
++) {
4779 if (table
->mc_reg_table_entry
[k
].mclk_max
== 125000)
4780 table
->mc_reg_table_entry
[k
].mc_data
[i
] =
4781 (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0xFFFFFFE0) |
4783 else if (table
->mc_reg_table_entry
[k
].mclk_max
== 137500)
4784 table
->mc_reg_table_entry
[k
].mc_data
[i
] =
4785 (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0xFFFFFFE0) |
4794 WREG32(mmMC_SEQ_IO_DEBUG_INDEX
, 3);
4795 tmp
= RREG32(mmMC_SEQ_IO_DEBUG_DATA
);
4796 tmp
= (tmp
& 0xFFF8FFFF) | (1 << 16);
4797 WREG32(mmMC_SEQ_IO_DEBUG_INDEX
, 3);
4798 WREG32(mmMC_SEQ_IO_DEBUG_DATA
, tmp
);
4804 static int ci_initialize_mc_reg_table(struct amdgpu_device
*adev
)
4806 struct ci_power_info
*pi
= ci_get_pi(adev
);
4807 struct atom_mc_reg_table
*table
;
4808 struct ci_mc_reg_table
*ci_table
= &pi
->mc_reg_table
;
4809 u8 module_index
= ci_get_memory_module_index(adev
);
4812 table
= kzalloc(sizeof(struct atom_mc_reg_table
), GFP_KERNEL
);
4816 WREG32(mmMC_SEQ_RAS_TIMING_LP
, RREG32(mmMC_SEQ_RAS_TIMING
));
4817 WREG32(mmMC_SEQ_CAS_TIMING_LP
, RREG32(mmMC_SEQ_CAS_TIMING
));
4818 WREG32(mmMC_SEQ_DLL_STBY_LP
, RREG32(mmMC_SEQ_DLL_STBY
));
4819 WREG32(mmMC_SEQ_G5PDX_CMD0_LP
, RREG32(mmMC_SEQ_G5PDX_CMD0
));
4820 WREG32(mmMC_SEQ_G5PDX_CMD1_LP
, RREG32(mmMC_SEQ_G5PDX_CMD1
));
4821 WREG32(mmMC_SEQ_G5PDX_CTRL_LP
, RREG32(mmMC_SEQ_G5PDX_CTRL
));
4822 WREG32(mmMC_SEQ_PMG_DVS_CMD_LP
, RREG32(mmMC_SEQ_PMG_DVS_CMD
));
4823 WREG32(mmMC_SEQ_PMG_DVS_CTL_LP
, RREG32(mmMC_SEQ_PMG_DVS_CTL
));
4824 WREG32(mmMC_SEQ_MISC_TIMING_LP
, RREG32(mmMC_SEQ_MISC_TIMING
));
4825 WREG32(mmMC_SEQ_MISC_TIMING2_LP
, RREG32(mmMC_SEQ_MISC_TIMING2
));
4826 WREG32(mmMC_SEQ_PMG_CMD_EMRS_LP
, RREG32(mmMC_PMG_CMD_EMRS
));
4827 WREG32(mmMC_SEQ_PMG_CMD_MRS_LP
, RREG32(mmMC_PMG_CMD_MRS
));
4828 WREG32(mmMC_SEQ_PMG_CMD_MRS1_LP
, RREG32(mmMC_PMG_CMD_MRS1
));
4829 WREG32(mmMC_SEQ_WR_CTL_D0_LP
, RREG32(mmMC_SEQ_WR_CTL_D0
));
4830 WREG32(mmMC_SEQ_WR_CTL_D1_LP
, RREG32(mmMC_SEQ_WR_CTL_D1
));
4831 WREG32(mmMC_SEQ_RD_CTL_D0_LP
, RREG32(mmMC_SEQ_RD_CTL_D0
));
4832 WREG32(mmMC_SEQ_RD_CTL_D1_LP
, RREG32(mmMC_SEQ_RD_CTL_D1
));
4833 WREG32(mmMC_SEQ_PMG_TIMING_LP
, RREG32(mmMC_SEQ_PMG_TIMING
));
4834 WREG32(mmMC_SEQ_PMG_CMD_MRS2_LP
, RREG32(mmMC_PMG_CMD_MRS2
));
4835 WREG32(mmMC_SEQ_WR_CTL_2_LP
, RREG32(mmMC_SEQ_WR_CTL_2
));
4837 ret
= amdgpu_atombios_init_mc_reg_table(adev
, module_index
, table
);
4841 ret
= ci_copy_vbios_mc_reg_table(table
, ci_table
);
4845 ci_set_s0_mc_reg_index(ci_table
);
4847 ret
= ci_register_patching_mc_seq(adev
, ci_table
);
4851 ret
= ci_set_mc_special_registers(adev
, ci_table
);
4855 ci_set_valid_flag(ci_table
);
4863 static int ci_populate_mc_reg_addresses(struct amdgpu_device
*adev
,
4864 SMU7_Discrete_MCRegisters
*mc_reg_table
)
4866 struct ci_power_info
*pi
= ci_get_pi(adev
);
4869 for (i
= 0, j
= 0; j
< pi
->mc_reg_table
.last
; j
++) {
4870 if (pi
->mc_reg_table
.valid_flag
& (1 << j
)) {
4871 if (i
>= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE
)
4873 mc_reg_table
->address
[i
].s0
= cpu_to_be16(pi
->mc_reg_table
.mc_reg_address
[j
].s0
);
4874 mc_reg_table
->address
[i
].s1
= cpu_to_be16(pi
->mc_reg_table
.mc_reg_address
[j
].s1
);
4879 mc_reg_table
->last
= (u8
)i
;
4884 static void ci_convert_mc_registers(const struct ci_mc_reg_entry
*entry
,
4885 SMU7_Discrete_MCRegisterSet
*data
,
4886 u32 num_entries
, u32 valid_flag
)
4890 for (i
= 0, j
= 0; j
< num_entries
; j
++) {
4891 if (valid_flag
& (1 << j
)) {
4892 data
->value
[i
] = cpu_to_be32(entry
->mc_data
[j
]);
4898 static void ci_convert_mc_reg_table_entry_to_smc(struct amdgpu_device
*adev
,
4899 const u32 memory_clock
,
4900 SMU7_Discrete_MCRegisterSet
*mc_reg_table_data
)
4902 struct ci_power_info
*pi
= ci_get_pi(adev
);
4905 for(i
= 0; i
< pi
->mc_reg_table
.num_entries
; i
++) {
4906 if (memory_clock
<= pi
->mc_reg_table
.mc_reg_table_entry
[i
].mclk_max
)
4910 if ((i
== pi
->mc_reg_table
.num_entries
) && (i
> 0))
4913 ci_convert_mc_registers(&pi
->mc_reg_table
.mc_reg_table_entry
[i
],
4914 mc_reg_table_data
, pi
->mc_reg_table
.last
,
4915 pi
->mc_reg_table
.valid_flag
);
4918 static void ci_convert_mc_reg_table_to_smc(struct amdgpu_device
*adev
,
4919 SMU7_Discrete_MCRegisters
*mc_reg_table
)
4921 struct ci_power_info
*pi
= ci_get_pi(adev
);
4924 for (i
= 0; i
< pi
->dpm_table
.mclk_table
.count
; i
++)
4925 ci_convert_mc_reg_table_entry_to_smc(adev
,
4926 pi
->dpm_table
.mclk_table
.dpm_levels
[i
].value
,
4927 &mc_reg_table
->data
[i
]);
4930 static int ci_populate_initial_mc_reg_table(struct amdgpu_device
*adev
)
4932 struct ci_power_info
*pi
= ci_get_pi(adev
);
4935 memset(&pi
->smc_mc_reg_table
, 0, sizeof(SMU7_Discrete_MCRegisters
));
4937 ret
= ci_populate_mc_reg_addresses(adev
, &pi
->smc_mc_reg_table
);
4940 ci_convert_mc_reg_table_to_smc(adev
, &pi
->smc_mc_reg_table
);
4942 return amdgpu_ci_copy_bytes_to_smc(adev
,
4943 pi
->mc_reg_table_start
,
4944 (u8
*)&pi
->smc_mc_reg_table
,
4945 sizeof(SMU7_Discrete_MCRegisters
),
4949 static int ci_update_and_upload_mc_reg_table(struct amdgpu_device
*adev
)
4951 struct ci_power_info
*pi
= ci_get_pi(adev
);
4953 if (!(pi
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_MCLK
))
4956 memset(&pi
->smc_mc_reg_table
, 0, sizeof(SMU7_Discrete_MCRegisters
));
4958 ci_convert_mc_reg_table_to_smc(adev
, &pi
->smc_mc_reg_table
);
4960 return amdgpu_ci_copy_bytes_to_smc(adev
,
4961 pi
->mc_reg_table_start
+
4962 offsetof(SMU7_Discrete_MCRegisters
, data
[0]),
4963 (u8
*)&pi
->smc_mc_reg_table
.data
[0],
4964 sizeof(SMU7_Discrete_MCRegisterSet
) *
4965 pi
->dpm_table
.mclk_table
.count
,
4969 static void ci_enable_voltage_control(struct amdgpu_device
*adev
)
4971 u32 tmp
= RREG32_SMC(ixGENERAL_PWRMGT
);
4973 tmp
|= GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK
;
4974 WREG32_SMC(ixGENERAL_PWRMGT
, tmp
);
4977 static enum amdgpu_pcie_gen
ci_get_maximum_link_speed(struct amdgpu_device
*adev
,
4978 struct amdgpu_ps
*amdgpu_state
)
4980 struct ci_ps
*state
= ci_get_ps(amdgpu_state
);
4982 u16 pcie_speed
, max_speed
= 0;
4984 for (i
= 0; i
< state
->performance_level_count
; i
++) {
4985 pcie_speed
= state
->performance_levels
[i
].pcie_gen
;
4986 if (max_speed
< pcie_speed
)
4987 max_speed
= pcie_speed
;
4993 static u16
ci_get_current_pcie_speed(struct amdgpu_device
*adev
)
4997 speed_cntl
= RREG32_PCIE(ixPCIE_LC_SPEED_CNTL
) &
4998 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK
;
4999 speed_cntl
>>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT
;
5001 return (u16
)speed_cntl
;
5004 static int ci_get_current_pcie_lane_number(struct amdgpu_device
*adev
)
5008 link_width
= RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL
) &
5009 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK
;
5010 link_width
>>= PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT
;
5012 switch (link_width
) {
5028 static void ci_request_link_speed_change_before_state_change(struct amdgpu_device
*adev
,
5029 struct amdgpu_ps
*amdgpu_new_state
,
5030 struct amdgpu_ps
*amdgpu_current_state
)
5032 struct ci_power_info
*pi
= ci_get_pi(adev
);
5033 enum amdgpu_pcie_gen target_link_speed
=
5034 ci_get_maximum_link_speed(adev
, amdgpu_new_state
);
5035 enum amdgpu_pcie_gen current_link_speed
;
5037 if (pi
->force_pcie_gen
== AMDGPU_PCIE_GEN_INVALID
)
5038 current_link_speed
= ci_get_maximum_link_speed(adev
, amdgpu_current_state
);
5040 current_link_speed
= pi
->force_pcie_gen
;
5042 pi
->force_pcie_gen
= AMDGPU_PCIE_GEN_INVALID
;
5043 pi
->pspp_notify_required
= false;
5044 if (target_link_speed
> current_link_speed
) {
5045 switch (target_link_speed
) {
5047 case AMDGPU_PCIE_GEN3
:
5048 if (amdgpu_acpi_pcie_performance_request(adev
, PCIE_PERF_REQ_PECI_GEN3
, false) == 0)
5050 pi
->force_pcie_gen
= AMDGPU_PCIE_GEN2
;
5051 if (current_link_speed
== AMDGPU_PCIE_GEN2
)
5053 case AMDGPU_PCIE_GEN2
:
5054 if (amdgpu_acpi_pcie_performance_request(adev
, PCIE_PERF_REQ_PECI_GEN2
, false) == 0)
5058 pi
->force_pcie_gen
= ci_get_current_pcie_speed(adev
);
5062 if (target_link_speed
< current_link_speed
)
5063 pi
->pspp_notify_required
= true;
5067 static void ci_notify_link_speed_change_after_state_change(struct amdgpu_device
*adev
,
5068 struct amdgpu_ps
*amdgpu_new_state
,
5069 struct amdgpu_ps
*amdgpu_current_state
)
5071 struct ci_power_info
*pi
= ci_get_pi(adev
);
5072 enum amdgpu_pcie_gen target_link_speed
=
5073 ci_get_maximum_link_speed(adev
, amdgpu_new_state
);
5076 if (pi
->pspp_notify_required
) {
5077 if (target_link_speed
== AMDGPU_PCIE_GEN3
)
5078 request
= PCIE_PERF_REQ_PECI_GEN3
;
5079 else if (target_link_speed
== AMDGPU_PCIE_GEN2
)
5080 request
= PCIE_PERF_REQ_PECI_GEN2
;
5082 request
= PCIE_PERF_REQ_PECI_GEN1
;
5084 if ((request
== PCIE_PERF_REQ_PECI_GEN1
) &&
5085 (ci_get_current_pcie_speed(adev
) > 0))
5089 amdgpu_acpi_pcie_performance_request(adev
, request
, false);
5094 static int ci_set_private_data_variables_based_on_pptable(struct amdgpu_device
*adev
)
5096 struct ci_power_info
*pi
= ci_get_pi(adev
);
5097 struct amdgpu_clock_voltage_dependency_table
*allowed_sclk_vddc_table
=
5098 &adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
;
5099 struct amdgpu_clock_voltage_dependency_table
*allowed_mclk_vddc_table
=
5100 &adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_mclk
;
5101 struct amdgpu_clock_voltage_dependency_table
*allowed_mclk_vddci_table
=
5102 &adev
->pm
.dpm
.dyn_state
.vddci_dependency_on_mclk
;
5104 if (allowed_sclk_vddc_table
== NULL
)
5106 if (allowed_sclk_vddc_table
->count
< 1)
5108 if (allowed_mclk_vddc_table
== NULL
)
5110 if (allowed_mclk_vddc_table
->count
< 1)
5112 if (allowed_mclk_vddci_table
== NULL
)
5114 if (allowed_mclk_vddci_table
->count
< 1)
5117 pi
->min_vddc_in_pp_table
= allowed_sclk_vddc_table
->entries
[0].v
;
5118 pi
->max_vddc_in_pp_table
=
5119 allowed_sclk_vddc_table
->entries
[allowed_sclk_vddc_table
->count
- 1].v
;
5121 pi
->min_vddci_in_pp_table
= allowed_mclk_vddci_table
->entries
[0].v
;
5122 pi
->max_vddci_in_pp_table
=
5123 allowed_mclk_vddci_table
->entries
[allowed_mclk_vddci_table
->count
- 1].v
;
5125 adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
.sclk
=
5126 allowed_sclk_vddc_table
->entries
[allowed_sclk_vddc_table
->count
- 1].clk
;
5127 adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
.mclk
=
5128 allowed_mclk_vddc_table
->entries
[allowed_sclk_vddc_table
->count
- 1].clk
;
5129 adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
.vddc
=
5130 allowed_sclk_vddc_table
->entries
[allowed_sclk_vddc_table
->count
- 1].v
;
5131 adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
.vddci
=
5132 allowed_mclk_vddci_table
->entries
[allowed_mclk_vddci_table
->count
- 1].v
;
5137 static void ci_patch_with_vddc_leakage(struct amdgpu_device
*adev
, u16
*vddc
)
5139 struct ci_power_info
*pi
= ci_get_pi(adev
);
5140 struct ci_leakage_voltage
*leakage_table
= &pi
->vddc_leakage
;
5143 for (leakage_index
= 0; leakage_index
< leakage_table
->count
; leakage_index
++) {
5144 if (leakage_table
->leakage_id
[leakage_index
] == *vddc
) {
5145 *vddc
= leakage_table
->actual_voltage
[leakage_index
];
5151 static void ci_patch_with_vddci_leakage(struct amdgpu_device
*adev
, u16
*vddci
)
5153 struct ci_power_info
*pi
= ci_get_pi(adev
);
5154 struct ci_leakage_voltage
*leakage_table
= &pi
->vddci_leakage
;
5157 for (leakage_index
= 0; leakage_index
< leakage_table
->count
; leakage_index
++) {
5158 if (leakage_table
->leakage_id
[leakage_index
] == *vddci
) {
5159 *vddci
= leakage_table
->actual_voltage
[leakage_index
];
5165 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device
*adev
,
5166 struct amdgpu_clock_voltage_dependency_table
*table
)
5171 for (i
= 0; i
< table
->count
; i
++)
5172 ci_patch_with_vddc_leakage(adev
, &table
->entries
[i
].v
);
5176 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct amdgpu_device
*adev
,
5177 struct amdgpu_clock_voltage_dependency_table
*table
)
5182 for (i
= 0; i
< table
->count
; i
++)
5183 ci_patch_with_vddci_leakage(adev
, &table
->entries
[i
].v
);
5187 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device
*adev
,
5188 struct amdgpu_vce_clock_voltage_dependency_table
*table
)
5193 for (i
= 0; i
< table
->count
; i
++)
5194 ci_patch_with_vddc_leakage(adev
, &table
->entries
[i
].v
);
5198 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device
*adev
,
5199 struct amdgpu_uvd_clock_voltage_dependency_table
*table
)
5204 for (i
= 0; i
< table
->count
; i
++)
5205 ci_patch_with_vddc_leakage(adev
, &table
->entries
[i
].v
);
5209 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct amdgpu_device
*adev
,
5210 struct amdgpu_phase_shedding_limits_table
*table
)
5215 for (i
= 0; i
< table
->count
; i
++)
5216 ci_patch_with_vddc_leakage(adev
, &table
->entries
[i
].voltage
);
5220 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct amdgpu_device
*adev
,
5221 struct amdgpu_clock_and_voltage_limits
*table
)
5224 ci_patch_with_vddc_leakage(adev
, (u16
*)&table
->vddc
);
5225 ci_patch_with_vddci_leakage(adev
, (u16
*)&table
->vddci
);
5229 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct amdgpu_device
*adev
,
5230 struct amdgpu_cac_leakage_table
*table
)
5235 for (i
= 0; i
< table
->count
; i
++)
5236 ci_patch_with_vddc_leakage(adev
, &table
->entries
[i
].vddc
);
5240 static void ci_patch_dependency_tables_with_leakage(struct amdgpu_device
*adev
)
5243 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev
,
5244 &adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
);
5245 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev
,
5246 &adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_mclk
);
5247 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev
,
5248 &adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
);
5249 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(adev
,
5250 &adev
->pm
.dpm
.dyn_state
.vddci_dependency_on_mclk
);
5251 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(adev
,
5252 &adev
->pm
.dpm
.dyn_state
.vce_clock_voltage_dependency_table
);
5253 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(adev
,
5254 &adev
->pm
.dpm
.dyn_state
.uvd_clock_voltage_dependency_table
);
5255 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev
,
5256 &adev
->pm
.dpm
.dyn_state
.samu_clock_voltage_dependency_table
);
5257 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev
,
5258 &adev
->pm
.dpm
.dyn_state
.acp_clock_voltage_dependency_table
);
5259 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(adev
,
5260 &adev
->pm
.dpm
.dyn_state
.phase_shedding_limits_table
);
5261 ci_patch_clock_voltage_limits_with_vddc_leakage(adev
,
5262 &adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
);
5263 ci_patch_clock_voltage_limits_with_vddc_leakage(adev
,
5264 &adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_dc
);
5265 ci_patch_cac_leakage_table_with_vddc_leakage(adev
,
5266 &adev
->pm
.dpm
.dyn_state
.cac_leakage_table
);
5270 static void ci_update_current_ps(struct amdgpu_device
*adev
,
5271 struct amdgpu_ps
*rps
)
5273 struct ci_ps
*new_ps
= ci_get_ps(rps
);
5274 struct ci_power_info
*pi
= ci_get_pi(adev
);
5276 pi
->current_rps
= *rps
;
5277 pi
->current_ps
= *new_ps
;
5278 pi
->current_rps
.ps_priv
= &pi
->current_ps
;
5279 adev
->pm
.dpm
.current_ps
= &pi
->current_rps
;
5282 static void ci_update_requested_ps(struct amdgpu_device
*adev
,
5283 struct amdgpu_ps
*rps
)
5285 struct ci_ps
*new_ps
= ci_get_ps(rps
);
5286 struct ci_power_info
*pi
= ci_get_pi(adev
);
5288 pi
->requested_rps
= *rps
;
5289 pi
->requested_ps
= *new_ps
;
5290 pi
->requested_rps
.ps_priv
= &pi
->requested_ps
;
5291 adev
->pm
.dpm
.requested_ps
= &pi
->requested_rps
;
5294 static int ci_dpm_pre_set_power_state(struct amdgpu_device
*adev
)
5296 struct ci_power_info
*pi
= ci_get_pi(adev
);
5297 struct amdgpu_ps requested_ps
= *adev
->pm
.dpm
.requested_ps
;
5298 struct amdgpu_ps
*new_ps
= &requested_ps
;
5300 ci_update_requested_ps(adev
, new_ps
);
5302 ci_apply_state_adjust_rules(adev
, &pi
->requested_rps
);
5307 static void ci_dpm_post_set_power_state(struct amdgpu_device
*adev
)
5309 struct ci_power_info
*pi
= ci_get_pi(adev
);
5310 struct amdgpu_ps
*new_ps
= &pi
->requested_rps
;
5312 ci_update_current_ps(adev
, new_ps
);
5316 static void ci_dpm_setup_asic(struct amdgpu_device
*adev
)
5318 ci_read_clock_registers(adev
);
5319 ci_enable_acpi_power_management(adev
);
5320 ci_init_sclk_t(adev
);
5323 static int ci_dpm_enable(struct amdgpu_device
*adev
)
5325 struct ci_power_info
*pi
= ci_get_pi(adev
);
5326 struct amdgpu_ps
*boot_ps
= adev
->pm
.dpm
.boot_ps
;
5329 if (pi
->voltage_control
!= CISLANDS_VOLTAGE_CONTROL_NONE
) {
5330 ci_enable_voltage_control(adev
);
5331 ret
= ci_construct_voltage_tables(adev
);
5333 DRM_ERROR("ci_construct_voltage_tables failed\n");
5337 if (pi
->caps_dynamic_ac_timing
) {
5338 ret
= ci_initialize_mc_reg_table(adev
);
5340 pi
->caps_dynamic_ac_timing
= false;
5343 ci_enable_spread_spectrum(adev
, true);
5344 if (pi
->thermal_protection
)
5345 ci_enable_thermal_protection(adev
, true);
5346 ci_program_sstp(adev
);
5347 ci_enable_display_gap(adev
);
5348 ci_program_vc(adev
);
5349 ret
= ci_upload_firmware(adev
);
5351 DRM_ERROR("ci_upload_firmware failed\n");
5354 ret
= ci_process_firmware_header(adev
);
5356 DRM_ERROR("ci_process_firmware_header failed\n");
5359 ret
= ci_initial_switch_from_arb_f0_to_f1(adev
);
5361 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
5364 ret
= ci_init_smc_table(adev
);
5366 DRM_ERROR("ci_init_smc_table failed\n");
5369 ret
= ci_init_arb_table_index(adev
);
5371 DRM_ERROR("ci_init_arb_table_index failed\n");
5374 if (pi
->caps_dynamic_ac_timing
) {
5375 ret
= ci_populate_initial_mc_reg_table(adev
);
5377 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
5381 ret
= ci_populate_pm_base(adev
);
5383 DRM_ERROR("ci_populate_pm_base failed\n");
5386 ci_dpm_start_smc(adev
);
5387 ci_enable_vr_hot_gpio_interrupt(adev
);
5388 ret
= ci_notify_smc_display_change(adev
, false);
5390 DRM_ERROR("ci_notify_smc_display_change failed\n");
5393 ci_enable_sclk_control(adev
, true);
5394 ret
= ci_enable_ulv(adev
, true);
5396 DRM_ERROR("ci_enable_ulv failed\n");
5399 ret
= ci_enable_ds_master_switch(adev
, true);
5401 DRM_ERROR("ci_enable_ds_master_switch failed\n");
5404 ret
= ci_start_dpm(adev
);
5406 DRM_ERROR("ci_start_dpm failed\n");
5409 ret
= ci_enable_didt(adev
, true);
5411 DRM_ERROR("ci_enable_didt failed\n");
5414 ret
= ci_enable_smc_cac(adev
, true);
5416 DRM_ERROR("ci_enable_smc_cac failed\n");
5419 ret
= ci_enable_power_containment(adev
, true);
5421 DRM_ERROR("ci_enable_power_containment failed\n");
5425 ret
= ci_power_control_set_level(adev
);
5427 DRM_ERROR("ci_power_control_set_level failed\n");
5431 ci_enable_auto_throttle_source(adev
, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL
, true);
5433 ret
= ci_enable_thermal_based_sclk_dpm(adev
, true);
5435 DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n");
5439 ci_thermal_start_thermal_controller(adev
);
5441 ci_update_current_ps(adev
, boot_ps
);
5446 static void ci_dpm_disable(struct amdgpu_device
*adev
)
5448 struct ci_power_info
*pi
= ci_get_pi(adev
);
5449 struct amdgpu_ps
*boot_ps
= adev
->pm
.dpm
.boot_ps
;
5451 amdgpu_irq_put(adev
, &adev
->pm
.dpm
.thermal
.irq
,
5452 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH
);
5453 amdgpu_irq_put(adev
, &adev
->pm
.dpm
.thermal
.irq
,
5454 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW
);
5456 ci_dpm_powergate_uvd(adev
, true);
5458 if (!amdgpu_ci_is_smc_running(adev
))
5461 ci_thermal_stop_thermal_controller(adev
);
5463 if (pi
->thermal_protection
)
5464 ci_enable_thermal_protection(adev
, false);
5465 ci_enable_power_containment(adev
, false);
5466 ci_enable_smc_cac(adev
, false);
5467 ci_enable_didt(adev
, false);
5468 ci_enable_spread_spectrum(adev
, false);
5469 ci_enable_auto_throttle_source(adev
, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL
, false);
5471 ci_enable_ds_master_switch(adev
, false);
5472 ci_enable_ulv(adev
, false);
5474 ci_reset_to_default(adev
);
5475 ci_dpm_stop_smc(adev
);
5476 ci_force_switch_to_arb_f0(adev
);
5477 ci_enable_thermal_based_sclk_dpm(adev
, false);
5479 ci_update_current_ps(adev
, boot_ps
);
5482 static int ci_dpm_set_power_state(struct amdgpu_device
*adev
)
5484 struct ci_power_info
*pi
= ci_get_pi(adev
);
5485 struct amdgpu_ps
*new_ps
= &pi
->requested_rps
;
5486 struct amdgpu_ps
*old_ps
= &pi
->current_rps
;
5489 ci_find_dpm_states_clocks_in_dpm_table(adev
, new_ps
);
5490 if (pi
->pcie_performance_request
)
5491 ci_request_link_speed_change_before_state_change(adev
, new_ps
, old_ps
);
5492 ret
= ci_freeze_sclk_mclk_dpm(adev
);
5494 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
5497 ret
= ci_populate_and_upload_sclk_mclk_dpm_levels(adev
, new_ps
);
5499 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
5502 ret
= ci_generate_dpm_level_enable_mask(adev
, new_ps
);
5504 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
5508 ret
= ci_update_vce_dpm(adev
, new_ps
, old_ps
);
5510 DRM_ERROR("ci_update_vce_dpm failed\n");
5514 ret
= ci_update_sclk_t(adev
);
5516 DRM_ERROR("ci_update_sclk_t failed\n");
5519 if (pi
->caps_dynamic_ac_timing
) {
5520 ret
= ci_update_and_upload_mc_reg_table(adev
);
5522 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
5526 ret
= ci_program_memory_timing_parameters(adev
);
5528 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
5531 ret
= ci_unfreeze_sclk_mclk_dpm(adev
);
5533 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
5536 ret
= ci_upload_dpm_level_enable_mask(adev
);
5538 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
5541 if (pi
->pcie_performance_request
)
5542 ci_notify_link_speed_change_after_state_change(adev
, new_ps
, old_ps
);
5548 static void ci_dpm_reset_asic(struct amdgpu_device
*adev
)
5550 ci_set_boot_state(adev
);
5554 static void ci_dpm_display_configuration_changed(struct amdgpu_device
*adev
)
5556 ci_program_display_gap(adev
);
5560 struct _ATOM_POWERPLAY_INFO info
;
5561 struct _ATOM_POWERPLAY_INFO_V2 info_2
;
5562 struct _ATOM_POWERPLAY_INFO_V3 info_3
;
5563 struct _ATOM_PPLIB_POWERPLAYTABLE pplib
;
5564 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2
;
5565 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3
;
5568 union pplib_clock_info
{
5569 struct _ATOM_PPLIB_R600_CLOCK_INFO r600
;
5570 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780
;
5571 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen
;
5572 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo
;
5573 struct _ATOM_PPLIB_SI_CLOCK_INFO si
;
5574 struct _ATOM_PPLIB_CI_CLOCK_INFO ci
;
5577 union pplib_power_state
{
5578 struct _ATOM_PPLIB_STATE v1
;
5579 struct _ATOM_PPLIB_STATE_V2 v2
;
5582 static void ci_parse_pplib_non_clock_info(struct amdgpu_device
*adev
,
5583 struct amdgpu_ps
*rps
,
5584 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
,
5587 rps
->caps
= le32_to_cpu(non_clock_info
->ulCapsAndSettings
);
5588 rps
->class = le16_to_cpu(non_clock_info
->usClassification
);
5589 rps
->class2
= le16_to_cpu(non_clock_info
->usClassification2
);
5591 if (ATOM_PPLIB_NONCLOCKINFO_VER1
< table_rev
) {
5592 rps
->vclk
= le32_to_cpu(non_clock_info
->ulVCLK
);
5593 rps
->dclk
= le32_to_cpu(non_clock_info
->ulDCLK
);
5599 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_BOOT
)
5600 adev
->pm
.dpm
.boot_ps
= rps
;
5601 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE
)
5602 adev
->pm
.dpm
.uvd_ps
= rps
;
5605 static void ci_parse_pplib_clock_info(struct amdgpu_device
*adev
,
5606 struct amdgpu_ps
*rps
, int index
,
5607 union pplib_clock_info
*clock_info
)
5609 struct ci_power_info
*pi
= ci_get_pi(adev
);
5610 struct ci_ps
*ps
= ci_get_ps(rps
);
5611 struct ci_pl
*pl
= &ps
->performance_levels
[index
];
5613 ps
->performance_level_count
= index
+ 1;
5615 pl
->sclk
= le16_to_cpu(clock_info
->ci
.usEngineClockLow
);
5616 pl
->sclk
|= clock_info
->ci
.ucEngineClockHigh
<< 16;
5617 pl
->mclk
= le16_to_cpu(clock_info
->ci
.usMemoryClockLow
);
5618 pl
->mclk
|= clock_info
->ci
.ucMemoryClockHigh
<< 16;
5620 pl
->pcie_gen
= amdgpu_get_pcie_gen_support(adev
,
5622 pi
->vbios_boot_state
.pcie_gen_bootup_value
,
5623 clock_info
->ci
.ucPCIEGen
);
5624 pl
->pcie_lane
= amdgpu_get_pcie_lane_support(adev
,
5625 pi
->vbios_boot_state
.pcie_lane_bootup_value
,
5626 le16_to_cpu(clock_info
->ci
.usPCIELane
));
5628 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_ACPI
) {
5629 pi
->acpi_pcie_gen
= pl
->pcie_gen
;
5632 if (rps
->class2
& ATOM_PPLIB_CLASSIFICATION2_ULV
) {
5633 pi
->ulv
.supported
= true;
5635 pi
->ulv
.cg_ulv_parameter
= CISLANDS_CGULVPARAMETER_DFLT
;
5638 /* patch up boot state */
5639 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_BOOT
) {
5640 pl
->mclk
= pi
->vbios_boot_state
.mclk_bootup_value
;
5641 pl
->sclk
= pi
->vbios_boot_state
.sclk_bootup_value
;
5642 pl
->pcie_gen
= pi
->vbios_boot_state
.pcie_gen_bootup_value
;
5643 pl
->pcie_lane
= pi
->vbios_boot_state
.pcie_lane_bootup_value
;
5646 switch (rps
->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK
) {
5647 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
:
5648 pi
->use_pcie_powersaving_levels
= true;
5649 if (pi
->pcie_gen_powersaving
.max
< pl
->pcie_gen
)
5650 pi
->pcie_gen_powersaving
.max
= pl
->pcie_gen
;
5651 if (pi
->pcie_gen_powersaving
.min
> pl
->pcie_gen
)
5652 pi
->pcie_gen_powersaving
.min
= pl
->pcie_gen
;
5653 if (pi
->pcie_lane_powersaving
.max
< pl
->pcie_lane
)
5654 pi
->pcie_lane_powersaving
.max
= pl
->pcie_lane
;
5655 if (pi
->pcie_lane_powersaving
.min
> pl
->pcie_lane
)
5656 pi
->pcie_lane_powersaving
.min
= pl
->pcie_lane
;
5658 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
:
5659 pi
->use_pcie_performance_levels
= true;
5660 if (pi
->pcie_gen_performance
.max
< pl
->pcie_gen
)
5661 pi
->pcie_gen_performance
.max
= pl
->pcie_gen
;
5662 if (pi
->pcie_gen_performance
.min
> pl
->pcie_gen
)
5663 pi
->pcie_gen_performance
.min
= pl
->pcie_gen
;
5664 if (pi
->pcie_lane_performance
.max
< pl
->pcie_lane
)
5665 pi
->pcie_lane_performance
.max
= pl
->pcie_lane
;
5666 if (pi
->pcie_lane_performance
.min
> pl
->pcie_lane
)
5667 pi
->pcie_lane_performance
.min
= pl
->pcie_lane
;
5674 static int ci_parse_power_table(struct amdgpu_device
*adev
)
5676 struct amdgpu_mode_info
*mode_info
= &adev
->mode_info
;
5677 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
;
5678 union pplib_power_state
*power_state
;
5679 int i
, j
, k
, non_clock_array_index
, clock_array_index
;
5680 union pplib_clock_info
*clock_info
;
5681 struct _StateArray
*state_array
;
5682 struct _ClockInfoArray
*clock_info_array
;
5683 struct _NonClockInfoArray
*non_clock_info_array
;
5684 union power_info
*power_info
;
5685 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
5688 u8
*power_state_offset
;
5691 if (!amdgpu_atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
5692 &frev
, &crev
, &data_offset
))
5694 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
5696 amdgpu_add_thermal_controller(adev
);
5698 state_array
= (struct _StateArray
*)
5699 (mode_info
->atom_context
->bios
+ data_offset
+
5700 le16_to_cpu(power_info
->pplib
.usStateArrayOffset
));
5701 clock_info_array
= (struct _ClockInfoArray
*)
5702 (mode_info
->atom_context
->bios
+ data_offset
+
5703 le16_to_cpu(power_info
->pplib
.usClockInfoArrayOffset
));
5704 non_clock_info_array
= (struct _NonClockInfoArray
*)
5705 (mode_info
->atom_context
->bios
+ data_offset
+
5706 le16_to_cpu(power_info
->pplib
.usNonClockInfoArrayOffset
));
5708 adev
->pm
.dpm
.ps
= kzalloc(sizeof(struct amdgpu_ps
) *
5709 state_array
->ucNumEntries
, GFP_KERNEL
);
5710 if (!adev
->pm
.dpm
.ps
)
5712 power_state_offset
= (u8
*)state_array
->states
;
5713 for (i
= 0; i
< state_array
->ucNumEntries
; i
++) {
5715 power_state
= (union pplib_power_state
*)power_state_offset
;
5716 non_clock_array_index
= power_state
->v2
.nonClockInfoIndex
;
5717 non_clock_info
= (struct _ATOM_PPLIB_NONCLOCK_INFO
*)
5718 &non_clock_info_array
->nonClockInfo
[non_clock_array_index
];
5719 ps
= kzalloc(sizeof(struct ci_ps
), GFP_KERNEL
);
5721 kfree(adev
->pm
.dpm
.ps
);
5724 adev
->pm
.dpm
.ps
[i
].ps_priv
= ps
;
5725 ci_parse_pplib_non_clock_info(adev
, &adev
->pm
.dpm
.ps
[i
],
5727 non_clock_info_array
->ucEntrySize
);
5729 idx
= (u8
*)&power_state
->v2
.clockInfoIndex
[0];
5730 for (j
= 0; j
< power_state
->v2
.ucNumDPMLevels
; j
++) {
5731 clock_array_index
= idx
[j
];
5732 if (clock_array_index
>= clock_info_array
->ucNumEntries
)
5734 if (k
>= CISLANDS_MAX_HARDWARE_POWERLEVELS
)
5736 clock_info
= (union pplib_clock_info
*)
5737 ((u8
*)&clock_info_array
->clockInfo
[0] +
5738 (clock_array_index
* clock_info_array
->ucEntrySize
));
5739 ci_parse_pplib_clock_info(adev
,
5740 &adev
->pm
.dpm
.ps
[i
], k
,
5744 power_state_offset
+= 2 + power_state
->v2
.ucNumDPMLevels
;
5746 adev
->pm
.dpm
.num_ps
= state_array
->ucNumEntries
;
5748 /* fill in the vce power states */
5749 for (i
= 0; i
< adev
->pm
.dpm
.num_of_vce_states
; i
++) {
5751 clock_array_index
= adev
->pm
.dpm
.vce_states
[i
].clk_idx
;
5752 clock_info
= (union pplib_clock_info
*)
5753 &clock_info_array
->clockInfo
[clock_array_index
* clock_info_array
->ucEntrySize
];
5754 sclk
= le16_to_cpu(clock_info
->ci
.usEngineClockLow
);
5755 sclk
|= clock_info
->ci
.ucEngineClockHigh
<< 16;
5756 mclk
= le16_to_cpu(clock_info
->ci
.usMemoryClockLow
);
5757 mclk
|= clock_info
->ci
.ucMemoryClockHigh
<< 16;
5758 adev
->pm
.dpm
.vce_states
[i
].sclk
= sclk
;
5759 adev
->pm
.dpm
.vce_states
[i
].mclk
= mclk
;
5765 static int ci_get_vbios_boot_values(struct amdgpu_device
*adev
,
5766 struct ci_vbios_boot_state
*boot_state
)
5768 struct amdgpu_mode_info
*mode_info
= &adev
->mode_info
;
5769 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
5770 ATOM_FIRMWARE_INFO_V2_2
*firmware_info
;
5774 if (amdgpu_atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
5775 &frev
, &crev
, &data_offset
)) {
5777 (ATOM_FIRMWARE_INFO_V2_2
*)(mode_info
->atom_context
->bios
+
5779 boot_state
->mvdd_bootup_value
= le16_to_cpu(firmware_info
->usBootUpMVDDCVoltage
);
5780 boot_state
->vddc_bootup_value
= le16_to_cpu(firmware_info
->usBootUpVDDCVoltage
);
5781 boot_state
->vddci_bootup_value
= le16_to_cpu(firmware_info
->usBootUpVDDCIVoltage
);
5782 boot_state
->pcie_gen_bootup_value
= ci_get_current_pcie_speed(adev
);
5783 boot_state
->pcie_lane_bootup_value
= ci_get_current_pcie_lane_number(adev
);
5784 boot_state
->sclk_bootup_value
= le32_to_cpu(firmware_info
->ulDefaultEngineClock
);
5785 boot_state
->mclk_bootup_value
= le32_to_cpu(firmware_info
->ulDefaultMemoryClock
);
5792 static void ci_dpm_fini(struct amdgpu_device
*adev
)
5796 for (i
= 0; i
< adev
->pm
.dpm
.num_ps
; i
++) {
5797 kfree(adev
->pm
.dpm
.ps
[i
].ps_priv
);
5799 kfree(adev
->pm
.dpm
.ps
);
5800 kfree(adev
->pm
.dpm
.priv
);
5801 kfree(adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
);
5802 amdgpu_free_extended_power_table(adev
);
5806 * ci_dpm_init_microcode - load ucode images from disk
5808 * @adev: amdgpu_device pointer
5810 * Use the firmware interface to load the ucode images into
5811 * the driver (not loaded into hw).
5812 * Returns 0 on success, error on failure.
5814 static int ci_dpm_init_microcode(struct amdgpu_device
*adev
)
5816 const char *chip_name
;
5822 switch (adev
->asic_type
) {
5824 if ((adev
->pdev
->revision
== 0x80) ||
5825 (adev
->pdev
->revision
== 0x81) ||
5826 (adev
->pdev
->device
== 0x665f))
5827 chip_name
= "bonaire_k";
5829 chip_name
= "bonaire";
5832 if (adev
->pdev
->revision
== 0x80)
5833 chip_name
= "hawaii_k";
5835 chip_name
= "hawaii";
5843 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_smc.bin", chip_name
);
5844 err
= request_firmware(&adev
->pm
.fw
, fw_name
, adev
->dev
);
5847 err
= amdgpu_ucode_validate(adev
->pm
.fw
);
5851 pr_err("cik_smc: Failed to load firmware \"%s\"\n", fw_name
);
5852 release_firmware(adev
->pm
.fw
);
5858 static int ci_dpm_init(struct amdgpu_device
*adev
)
5860 int index
= GetIndexIntoMasterTable(DATA
, ASIC_InternalSS_Info
);
5861 SMU7_Discrete_DpmTable
*dpm_table
;
5862 struct amdgpu_gpio_rec gpio
;
5863 u16 data_offset
, size
;
5865 struct ci_power_info
*pi
;
5868 pi
= kzalloc(sizeof(struct ci_power_info
), GFP_KERNEL
);
5871 adev
->pm
.dpm
.priv
= pi
;
5874 (adev
->pm
.pcie_gen_mask
& CAIL_PCIE_LINK_SPEED_SUPPORT_MASK
) >>
5875 CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT
;
5877 pi
->force_pcie_gen
= AMDGPU_PCIE_GEN_INVALID
;
5879 pi
->pcie_gen_performance
.max
= AMDGPU_PCIE_GEN1
;
5880 pi
->pcie_gen_performance
.min
= AMDGPU_PCIE_GEN3
;
5881 pi
->pcie_gen_powersaving
.max
= AMDGPU_PCIE_GEN1
;
5882 pi
->pcie_gen_powersaving
.min
= AMDGPU_PCIE_GEN3
;
5884 pi
->pcie_lane_performance
.max
= 0;
5885 pi
->pcie_lane_performance
.min
= 16;
5886 pi
->pcie_lane_powersaving
.max
= 0;
5887 pi
->pcie_lane_powersaving
.min
= 16;
5889 ret
= ci_get_vbios_boot_values(adev
, &pi
->vbios_boot_state
);
5895 ret
= amdgpu_get_platform_caps(adev
);
5901 ret
= amdgpu_parse_extended_power_table(adev
);
5907 ret
= ci_parse_power_table(adev
);
5913 pi
->dll_default_on
= false;
5914 pi
->sram_end
= SMC_RAM_END
;
5916 pi
->activity_target
[0] = CISLAND_TARGETACTIVITY_DFLT
;
5917 pi
->activity_target
[1] = CISLAND_TARGETACTIVITY_DFLT
;
5918 pi
->activity_target
[2] = CISLAND_TARGETACTIVITY_DFLT
;
5919 pi
->activity_target
[3] = CISLAND_TARGETACTIVITY_DFLT
;
5920 pi
->activity_target
[4] = CISLAND_TARGETACTIVITY_DFLT
;
5921 pi
->activity_target
[5] = CISLAND_TARGETACTIVITY_DFLT
;
5922 pi
->activity_target
[6] = CISLAND_TARGETACTIVITY_DFLT
;
5923 pi
->activity_target
[7] = CISLAND_TARGETACTIVITY_DFLT
;
5925 pi
->mclk_activity_target
= CISLAND_MCLK_TARGETACTIVITY_DFLT
;
5927 pi
->sclk_dpm_key_disabled
= 0;
5928 pi
->mclk_dpm_key_disabled
= 0;
5929 pi
->pcie_dpm_key_disabled
= 0;
5930 pi
->thermal_sclk_dpm_enabled
= 0;
5932 if (amdgpu_pp_feature_mask
& SCLK_DEEP_SLEEP_MASK
)
5933 pi
->caps_sclk_ds
= true;
5935 pi
->caps_sclk_ds
= false;
5937 pi
->mclk_strobe_mode_threshold
= 40000;
5938 pi
->mclk_stutter_mode_threshold
= 40000;
5939 pi
->mclk_edc_enable_threshold
= 40000;
5940 pi
->mclk_edc_wr_enable_threshold
= 40000;
5942 ci_initialize_powertune_defaults(adev
);
5944 pi
->caps_fps
= false;
5946 pi
->caps_sclk_throttle_low_notification
= false;
5948 pi
->caps_uvd_dpm
= true;
5949 pi
->caps_vce_dpm
= true;
5951 ci_get_leakage_voltages(adev
);
5952 ci_patch_dependency_tables_with_leakage(adev
);
5953 ci_set_private_data_variables_based_on_pptable(adev
);
5955 adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
=
5956 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry
), GFP_KERNEL
);
5957 if (!adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
) {
5961 adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.count
= 4;
5962 adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[0].clk
= 0;
5963 adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[0].v
= 0;
5964 adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[1].clk
= 36000;
5965 adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[1].v
= 720;
5966 adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[2].clk
= 54000;
5967 adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[2].v
= 810;
5968 adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[3].clk
= 72000;
5969 adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[3].v
= 900;
5971 adev
->pm
.dpm
.dyn_state
.mclk_sclk_ratio
= 4;
5972 adev
->pm
.dpm
.dyn_state
.sclk_mclk_delta
= 15000;
5973 adev
->pm
.dpm
.dyn_state
.vddc_vddci_delta
= 200;
5975 adev
->pm
.dpm
.dyn_state
.valid_sclk_values
.count
= 0;
5976 adev
->pm
.dpm
.dyn_state
.valid_sclk_values
.values
= NULL
;
5977 adev
->pm
.dpm
.dyn_state
.valid_mclk_values
.count
= 0;
5978 adev
->pm
.dpm
.dyn_state
.valid_mclk_values
.values
= NULL
;
5980 if (adev
->asic_type
== CHIP_HAWAII
) {
5981 pi
->thermal_temp_setting
.temperature_low
= 94500;
5982 pi
->thermal_temp_setting
.temperature_high
= 95000;
5983 pi
->thermal_temp_setting
.temperature_shutdown
= 104000;
5985 pi
->thermal_temp_setting
.temperature_low
= 99500;
5986 pi
->thermal_temp_setting
.temperature_high
= 100000;
5987 pi
->thermal_temp_setting
.temperature_shutdown
= 104000;
5990 pi
->uvd_enabled
= false;
5992 dpm_table
= &pi
->smc_state_table
;
5994 gpio
= amdgpu_atombios_lookup_gpio(adev
, VDDC_VRHOT_GPIO_PINID
);
5996 dpm_table
->VRHotGpio
= gpio
.shift
;
5997 adev
->pm
.dpm
.platform_caps
|= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT
;
5999 dpm_table
->VRHotGpio
= CISLANDS_UNUSED_GPIO_PIN
;
6000 adev
->pm
.dpm
.platform_caps
&= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT
;
6003 gpio
= amdgpu_atombios_lookup_gpio(adev
, PP_AC_DC_SWITCH_GPIO_PINID
);
6005 dpm_table
->AcDcGpio
= gpio
.shift
;
6006 adev
->pm
.dpm
.platform_caps
|= ATOM_PP_PLATFORM_CAP_HARDWAREDC
;
6008 dpm_table
->AcDcGpio
= CISLANDS_UNUSED_GPIO_PIN
;
6009 adev
->pm
.dpm
.platform_caps
&= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC
;
6012 gpio
= amdgpu_atombios_lookup_gpio(adev
, VDDC_PCC_GPIO_PINID
);
6014 u32 tmp
= RREG32_SMC(ixCNB_PWRMGT_CNTL
);
6016 switch (gpio
.shift
) {
6018 tmp
&= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK
;
6019 tmp
|= 1 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT
;
6022 tmp
&= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK
;
6023 tmp
|= 2 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT
;
6026 tmp
|= CNB_PWRMGT_CNTL__GNB_SLOW_MASK
;
6029 tmp
|= CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK
;
6032 tmp
|= CNB_PWRMGT_CNTL__DPM_ENABLED_MASK
;
6035 DRM_INFO("Invalid PCC GPIO: %u!\n", gpio
.shift
);
6038 WREG32_SMC(ixCNB_PWRMGT_CNTL
, tmp
);
6041 pi
->voltage_control
= CISLANDS_VOLTAGE_CONTROL_NONE
;
6042 pi
->vddci_control
= CISLANDS_VOLTAGE_CONTROL_NONE
;
6043 pi
->mvdd_control
= CISLANDS_VOLTAGE_CONTROL_NONE
;
6044 if (amdgpu_atombios_is_voltage_gpio(adev
, VOLTAGE_TYPE_VDDC
, VOLTAGE_OBJ_GPIO_LUT
))
6045 pi
->voltage_control
= CISLANDS_VOLTAGE_CONTROL_BY_GPIO
;
6046 else if (amdgpu_atombios_is_voltage_gpio(adev
, VOLTAGE_TYPE_VDDC
, VOLTAGE_OBJ_SVID2
))
6047 pi
->voltage_control
= CISLANDS_VOLTAGE_CONTROL_BY_SVID2
;
6049 if (adev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL
) {
6050 if (amdgpu_atombios_is_voltage_gpio(adev
, VOLTAGE_TYPE_VDDCI
, VOLTAGE_OBJ_GPIO_LUT
))
6051 pi
->vddci_control
= CISLANDS_VOLTAGE_CONTROL_BY_GPIO
;
6052 else if (amdgpu_atombios_is_voltage_gpio(adev
, VOLTAGE_TYPE_VDDCI
, VOLTAGE_OBJ_SVID2
))
6053 pi
->vddci_control
= CISLANDS_VOLTAGE_CONTROL_BY_SVID2
;
6055 adev
->pm
.dpm
.platform_caps
&= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL
;
6058 if (adev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_MVDDCONTROL
) {
6059 if (amdgpu_atombios_is_voltage_gpio(adev
, VOLTAGE_TYPE_MVDDC
, VOLTAGE_OBJ_GPIO_LUT
))
6060 pi
->mvdd_control
= CISLANDS_VOLTAGE_CONTROL_BY_GPIO
;
6061 else if (amdgpu_atombios_is_voltage_gpio(adev
, VOLTAGE_TYPE_MVDDC
, VOLTAGE_OBJ_SVID2
))
6062 pi
->mvdd_control
= CISLANDS_VOLTAGE_CONTROL_BY_SVID2
;
6064 adev
->pm
.dpm
.platform_caps
&= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL
;
6067 pi
->vddc_phase_shed_control
= true;
6069 #if defined(CONFIG_ACPI)
6070 pi
->pcie_performance_request
=
6071 amdgpu_acpi_is_pcie_performance_request_supported(adev
);
6073 pi
->pcie_performance_request
= false;
6076 if (amdgpu_atom_parse_data_header(adev
->mode_info
.atom_context
, index
, &size
,
6077 &frev
, &crev
, &data_offset
)) {
6078 pi
->caps_sclk_ss_support
= true;
6079 pi
->caps_mclk_ss_support
= true;
6080 pi
->dynamic_ss
= true;
6082 pi
->caps_sclk_ss_support
= false;
6083 pi
->caps_mclk_ss_support
= false;
6084 pi
->dynamic_ss
= true;
6087 if (adev
->pm
.int_thermal_type
!= THERMAL_TYPE_NONE
)
6088 pi
->thermal_protection
= true;
6090 pi
->thermal_protection
= false;
6092 pi
->caps_dynamic_ac_timing
= true;
6094 pi
->uvd_power_gated
= true;
6096 /* make sure dc limits are valid */
6097 if ((adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_dc
.sclk
== 0) ||
6098 (adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_dc
.mclk
== 0))
6099 adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_dc
=
6100 adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
;
6102 pi
->fan_ctrl_is_in_default_mode
= true;
6108 ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device
*adev
,
6111 struct ci_power_info
*pi
= ci_get_pi(adev
);
6112 struct amdgpu_ps
*rps
= &pi
->current_rps
;
6113 u32 sclk
= ci_get_average_sclk_freq(adev
);
6114 u32 mclk
= ci_get_average_mclk_freq(adev
);
6115 u32 activity_percent
= 50;
6118 ret
= ci_read_smc_soft_register(adev
, offsetof(SMU7_SoftRegisters
, AverageGraphicsA
),
6122 activity_percent
+= 0x80;
6123 activity_percent
>>= 8;
6124 activity_percent
= activity_percent
> 100 ? 100 : activity_percent
;
6127 seq_printf(m
, "uvd %sabled\n", pi
->uvd_power_gated
? "dis" : "en");
6128 seq_printf(m
, "vce %sabled\n", rps
->vce_active
? "en" : "dis");
6129 seq_printf(m
, "power level avg sclk: %u mclk: %u\n",
6131 seq_printf(m
, "GPU load: %u %%\n", activity_percent
);
6134 static void ci_dpm_print_power_state(struct amdgpu_device
*adev
,
6135 struct amdgpu_ps
*rps
)
6137 struct ci_ps
*ps
= ci_get_ps(rps
);
6141 amdgpu_dpm_print_class_info(rps
->class, rps
->class2
);
6142 amdgpu_dpm_print_cap_info(rps
->caps
);
6143 printk("\tuvd vclk: %d dclk: %d\n", rps
->vclk
, rps
->dclk
);
6144 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
6145 pl
= &ps
->performance_levels
[i
];
6146 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
6147 i
, pl
->sclk
, pl
->mclk
, pl
->pcie_gen
+ 1, pl
->pcie_lane
);
6149 amdgpu_dpm_print_ps_status(adev
, rps
);
6152 static inline bool ci_are_power_levels_equal(const struct ci_pl
*ci_cpl1
,
6153 const struct ci_pl
*ci_cpl2
)
6155 return ((ci_cpl1
->mclk
== ci_cpl2
->mclk
) &&
6156 (ci_cpl1
->sclk
== ci_cpl2
->sclk
) &&
6157 (ci_cpl1
->pcie_gen
== ci_cpl2
->pcie_gen
) &&
6158 (ci_cpl1
->pcie_lane
== ci_cpl2
->pcie_lane
));
6161 static int ci_check_state_equal(struct amdgpu_device
*adev
,
6162 struct amdgpu_ps
*cps
,
6163 struct amdgpu_ps
*rps
,
6166 struct ci_ps
*ci_cps
;
6167 struct ci_ps
*ci_rps
;
6170 if (adev
== NULL
|| cps
== NULL
|| rps
== NULL
|| equal
== NULL
)
6173 ci_cps
= ci_get_ps(cps
);
6174 ci_rps
= ci_get_ps(rps
);
6176 if (ci_cps
== NULL
) {
6181 if (ci_cps
->performance_level_count
!= ci_rps
->performance_level_count
) {
6187 for (i
= 0; i
< ci_cps
->performance_level_count
; i
++) {
6188 if (!ci_are_power_levels_equal(&(ci_cps
->performance_levels
[i
]),
6189 &(ci_rps
->performance_levels
[i
]))) {
6195 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
6196 *equal
= ((cps
->vclk
== rps
->vclk
) && (cps
->dclk
== rps
->dclk
));
6197 *equal
&= ((cps
->evclk
== rps
->evclk
) && (cps
->ecclk
== rps
->ecclk
));
6202 static u32
ci_dpm_get_sclk(struct amdgpu_device
*adev
, bool low
)
6204 struct ci_power_info
*pi
= ci_get_pi(adev
);
6205 struct ci_ps
*requested_state
= ci_get_ps(&pi
->requested_rps
);
6208 return requested_state
->performance_levels
[0].sclk
;
6210 return requested_state
->performance_levels
[requested_state
->performance_level_count
- 1].sclk
;
6213 static u32
ci_dpm_get_mclk(struct amdgpu_device
*adev
, bool low
)
6215 struct ci_power_info
*pi
= ci_get_pi(adev
);
6216 struct ci_ps
*requested_state
= ci_get_ps(&pi
->requested_rps
);
6219 return requested_state
->performance_levels
[0].mclk
;
6221 return requested_state
->performance_levels
[requested_state
->performance_level_count
- 1].mclk
;
6224 /* get temperature in millidegrees */
6225 static int ci_dpm_get_temp(struct amdgpu_device
*adev
)
6228 int actual_temp
= 0;
6230 temp
= (RREG32_SMC(ixCG_MULT_THERMAL_STATUS
) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK
) >>
6231 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT
;
6236 actual_temp
= temp
& 0x1ff;
6238 actual_temp
= actual_temp
* 1000;
6243 static int ci_set_temperature_range(struct amdgpu_device
*adev
)
6247 ret
= ci_thermal_enable_alert(adev
, false);
6250 ret
= ci_thermal_set_temperature_range(adev
, CISLANDS_TEMP_RANGE_MIN
,
6251 CISLANDS_TEMP_RANGE_MAX
);
6254 ret
= ci_thermal_enable_alert(adev
, true);
6260 static int ci_dpm_early_init(void *handle
)
6262 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
6264 ci_dpm_set_dpm_funcs(adev
);
6265 ci_dpm_set_irq_funcs(adev
);
6270 static int ci_dpm_late_init(void *handle
)
6273 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
6278 /* init the sysfs and debugfs files late */
6279 ret
= amdgpu_pm_sysfs_init(adev
);
6283 ret
= ci_set_temperature_range(adev
);
6290 static int ci_dpm_sw_init(void *handle
)
6293 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
6295 ret
= amdgpu_irq_add_id(adev
, AMDGPU_IH_CLIENTID_LEGACY
, 230,
6296 &adev
->pm
.dpm
.thermal
.irq
);
6300 ret
= amdgpu_irq_add_id(adev
, AMDGPU_IH_CLIENTID_LEGACY
, 231,
6301 &adev
->pm
.dpm
.thermal
.irq
);
6305 /* default to balanced state */
6306 adev
->pm
.dpm
.state
= POWER_STATE_TYPE_BALANCED
;
6307 adev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_BALANCED
;
6308 adev
->pm
.dpm
.forced_level
= AMD_DPM_FORCED_LEVEL_AUTO
;
6309 adev
->pm
.default_sclk
= adev
->clock
.default_sclk
;
6310 adev
->pm
.default_mclk
= adev
->clock
.default_mclk
;
6311 adev
->pm
.current_sclk
= adev
->clock
.default_sclk
;
6312 adev
->pm
.current_mclk
= adev
->clock
.default_mclk
;
6313 adev
->pm
.int_thermal_type
= THERMAL_TYPE_NONE
;
6315 ret
= ci_dpm_init_microcode(adev
);
6319 if (amdgpu_dpm
== 0)
6322 INIT_WORK(&adev
->pm
.dpm
.thermal
.work
, amdgpu_dpm_thermal_work_handler
);
6323 mutex_lock(&adev
->pm
.mutex
);
6324 ret
= ci_dpm_init(adev
);
6327 adev
->pm
.dpm
.current_ps
= adev
->pm
.dpm
.requested_ps
= adev
->pm
.dpm
.boot_ps
;
6328 if (amdgpu_dpm
== 1)
6329 amdgpu_pm_print_power_states(adev
);
6330 mutex_unlock(&adev
->pm
.mutex
);
6331 DRM_INFO("amdgpu: dpm initialized\n");
6337 mutex_unlock(&adev
->pm
.mutex
);
6338 DRM_ERROR("amdgpu: dpm initialization failed\n");
6342 static int ci_dpm_sw_fini(void *handle
)
6344 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
6346 flush_work(&adev
->pm
.dpm
.thermal
.work
);
6348 mutex_lock(&adev
->pm
.mutex
);
6349 amdgpu_pm_sysfs_fini(adev
);
6351 mutex_unlock(&adev
->pm
.mutex
);
6353 release_firmware(adev
->pm
.fw
);
6359 static int ci_dpm_hw_init(void *handle
)
6363 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
6366 ret
= ci_upload_firmware(adev
);
6368 DRM_ERROR("ci_upload_firmware failed\n");
6371 ci_dpm_start_smc(adev
);
6375 mutex_lock(&adev
->pm
.mutex
);
6376 ci_dpm_setup_asic(adev
);
6377 ret
= ci_dpm_enable(adev
);
6379 adev
->pm
.dpm_enabled
= false;
6381 adev
->pm
.dpm_enabled
= true;
6382 mutex_unlock(&adev
->pm
.mutex
);
6387 static int ci_dpm_hw_fini(void *handle
)
6389 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
6391 if (adev
->pm
.dpm_enabled
) {
6392 mutex_lock(&adev
->pm
.mutex
);
6393 ci_dpm_disable(adev
);
6394 mutex_unlock(&adev
->pm
.mutex
);
6396 ci_dpm_stop_smc(adev
);
6402 static int ci_dpm_suspend(void *handle
)
6404 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
6406 if (adev
->pm
.dpm_enabled
) {
6407 mutex_lock(&adev
->pm
.mutex
);
6408 amdgpu_irq_put(adev
, &adev
->pm
.dpm
.thermal
.irq
,
6409 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH
);
6410 amdgpu_irq_put(adev
, &adev
->pm
.dpm
.thermal
.irq
,
6411 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW
);
6412 adev
->pm
.dpm
.last_user_state
= adev
->pm
.dpm
.user_state
;
6413 adev
->pm
.dpm
.last_state
= adev
->pm
.dpm
.state
;
6414 adev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_INTERNAL_BOOT
;
6415 adev
->pm
.dpm
.state
= POWER_STATE_TYPE_INTERNAL_BOOT
;
6416 mutex_unlock(&adev
->pm
.mutex
);
6417 amdgpu_pm_compute_clocks(adev
);
6424 static int ci_dpm_resume(void *handle
)
6427 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
6429 if (adev
->pm
.dpm_enabled
) {
6430 /* asic init will reset to the boot state */
6431 mutex_lock(&adev
->pm
.mutex
);
6432 ci_dpm_setup_asic(adev
);
6433 ret
= ci_dpm_enable(adev
);
6435 adev
->pm
.dpm_enabled
= false;
6437 adev
->pm
.dpm_enabled
= true;
6438 adev
->pm
.dpm
.user_state
= adev
->pm
.dpm
.last_user_state
;
6439 adev
->pm
.dpm
.state
= adev
->pm
.dpm
.last_state
;
6440 mutex_unlock(&adev
->pm
.mutex
);
6441 if (adev
->pm
.dpm_enabled
)
6442 amdgpu_pm_compute_clocks(adev
);
6447 static bool ci_dpm_is_idle(void *handle
)
6453 static int ci_dpm_wait_for_idle(void *handle
)
6459 static int ci_dpm_soft_reset(void *handle
)
6464 static int ci_dpm_set_interrupt_state(struct amdgpu_device
*adev
,
6465 struct amdgpu_irq_src
*source
,
6467 enum amdgpu_interrupt_state state
)
6472 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH
:
6474 case AMDGPU_IRQ_STATE_DISABLE
:
6475 cg_thermal_int
= RREG32_SMC(ixCG_THERMAL_INT
);
6476 cg_thermal_int
|= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK
;
6477 WREG32_SMC(ixCG_THERMAL_INT
, cg_thermal_int
);
6479 case AMDGPU_IRQ_STATE_ENABLE
:
6480 cg_thermal_int
= RREG32_SMC(ixCG_THERMAL_INT
);
6481 cg_thermal_int
&= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK
;
6482 WREG32_SMC(ixCG_THERMAL_INT
, cg_thermal_int
);
6489 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW
:
6491 case AMDGPU_IRQ_STATE_DISABLE
:
6492 cg_thermal_int
= RREG32_SMC(ixCG_THERMAL_INT
);
6493 cg_thermal_int
|= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK
;
6494 WREG32_SMC(ixCG_THERMAL_INT
, cg_thermal_int
);
6496 case AMDGPU_IRQ_STATE_ENABLE
:
6497 cg_thermal_int
= RREG32_SMC(ixCG_THERMAL_INT
);
6498 cg_thermal_int
&= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK
;
6499 WREG32_SMC(ixCG_THERMAL_INT
, cg_thermal_int
);
6512 static int ci_dpm_process_interrupt(struct amdgpu_device
*adev
,
6513 struct amdgpu_irq_src
*source
,
6514 struct amdgpu_iv_entry
*entry
)
6516 bool queue_thermal
= false;
6521 switch (entry
->src_id
) {
6522 case 230: /* thermal low to high */
6523 DRM_DEBUG("IH: thermal low to high\n");
6524 adev
->pm
.dpm
.thermal
.high_to_low
= false;
6525 queue_thermal
= true;
6527 case 231: /* thermal high to low */
6528 DRM_DEBUG("IH: thermal high to low\n");
6529 adev
->pm
.dpm
.thermal
.high_to_low
= true;
6530 queue_thermal
= true;
6537 schedule_work(&adev
->pm
.dpm
.thermal
.work
);
6542 static int ci_dpm_set_clockgating_state(void *handle
,
6543 enum amd_clockgating_state state
)
6548 static int ci_dpm_set_powergating_state(void *handle
,
6549 enum amd_powergating_state state
)
6554 static int ci_dpm_print_clock_levels(struct amdgpu_device
*adev
,
6555 enum pp_clock_type type
, char *buf
)
6557 struct ci_power_info
*pi
= ci_get_pi(adev
);
6558 struct ci_single_dpm_table
*sclk_table
= &pi
->dpm_table
.sclk_table
;
6559 struct ci_single_dpm_table
*mclk_table
= &pi
->dpm_table
.mclk_table
;
6560 struct ci_single_dpm_table
*pcie_table
= &pi
->dpm_table
.pcie_speed_table
;
6562 int i
, now
, size
= 0;
6563 uint32_t clock
, pcie_speed
;
6567 amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_API_GetSclkFrequency
);
6568 clock
= RREG32(mmSMC_MSG_ARG_0
);
6570 for (i
= 0; i
< sclk_table
->count
; i
++) {
6571 if (clock
> sclk_table
->dpm_levels
[i
].value
)
6577 for (i
= 0; i
< sclk_table
->count
; i
++)
6578 size
+= sprintf(buf
+ size
, "%d: %uMhz %s\n",
6579 i
, sclk_table
->dpm_levels
[i
].value
/ 100,
6580 (i
== now
) ? "*" : "");
6583 amdgpu_ci_send_msg_to_smc(adev
, PPSMC_MSG_API_GetMclkFrequency
);
6584 clock
= RREG32(mmSMC_MSG_ARG_0
);
6586 for (i
= 0; i
< mclk_table
->count
; i
++) {
6587 if (clock
> mclk_table
->dpm_levels
[i
].value
)
6593 for (i
= 0; i
< mclk_table
->count
; i
++)
6594 size
+= sprintf(buf
+ size
, "%d: %uMhz %s\n",
6595 i
, mclk_table
->dpm_levels
[i
].value
/ 100,
6596 (i
== now
) ? "*" : "");
6599 pcie_speed
= ci_get_current_pcie_speed(adev
);
6600 for (i
= 0; i
< pcie_table
->count
; i
++) {
6601 if (pcie_speed
!= pcie_table
->dpm_levels
[i
].value
)
6607 for (i
= 0; i
< pcie_table
->count
; i
++)
6608 size
+= sprintf(buf
+ size
, "%d: %s %s\n", i
,
6609 (pcie_table
->dpm_levels
[i
].value
== 0) ? "2.5GB, x1" :
6610 (pcie_table
->dpm_levels
[i
].value
== 1) ? "5.0GB, x16" :
6611 (pcie_table
->dpm_levels
[i
].value
== 2) ? "8.0GB, x16" : "",
6612 (i
== now
) ? "*" : "");
6621 static int ci_dpm_force_clock_level(struct amdgpu_device
*adev
,
6622 enum pp_clock_type type
, uint32_t mask
)
6624 struct ci_power_info
*pi
= ci_get_pi(adev
);
6626 if (adev
->pm
.dpm
.forced_level
& (AMD_DPM_FORCED_LEVEL_AUTO
|
6627 AMD_DPM_FORCED_LEVEL_LOW
|
6628 AMD_DPM_FORCED_LEVEL_HIGH
))
6633 if (!pi
->sclk_dpm_key_disabled
)
6634 amdgpu_ci_send_msg_to_smc_with_parameter(adev
,
6635 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
6636 pi
->dpm_level_enable_mask
.sclk_dpm_enable_mask
& mask
);
6640 if (!pi
->mclk_dpm_key_disabled
)
6641 amdgpu_ci_send_msg_to_smc_with_parameter(adev
,
6642 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
6643 pi
->dpm_level_enable_mask
.mclk_dpm_enable_mask
& mask
);
6648 uint32_t tmp
= mask
& pi
->dpm_level_enable_mask
.pcie_dpm_enable_mask
;
6654 if (!pi
->pcie_dpm_key_disabled
)
6655 amdgpu_ci_send_msg_to_smc_with_parameter(adev
,
6656 PPSMC_MSG_PCIeDPM_ForceLevel
,
6667 static int ci_dpm_get_sclk_od(struct amdgpu_device
*adev
)
6669 struct ci_power_info
*pi
= ci_get_pi(adev
);
6670 struct ci_single_dpm_table
*sclk_table
= &(pi
->dpm_table
.sclk_table
);
6671 struct ci_single_dpm_table
*golden_sclk_table
=
6672 &(pi
->golden_dpm_table
.sclk_table
);
6675 value
= (sclk_table
->dpm_levels
[sclk_table
->count
- 1].value
-
6676 golden_sclk_table
->dpm_levels
[golden_sclk_table
->count
- 1].value
) *
6678 golden_sclk_table
->dpm_levels
[golden_sclk_table
->count
- 1].value
;
6683 static int ci_dpm_set_sclk_od(struct amdgpu_device
*adev
, uint32_t value
)
6685 struct ci_power_info
*pi
= ci_get_pi(adev
);
6686 struct ci_ps
*ps
= ci_get_ps(adev
->pm
.dpm
.requested_ps
);
6687 struct ci_single_dpm_table
*golden_sclk_table
=
6688 &(pi
->golden_dpm_table
.sclk_table
);
6693 ps
->performance_levels
[ps
->performance_level_count
- 1].sclk
=
6694 golden_sclk_table
->dpm_levels
[golden_sclk_table
->count
- 1].value
*
6696 golden_sclk_table
->dpm_levels
[golden_sclk_table
->count
- 1].value
;
6701 static int ci_dpm_get_mclk_od(struct amdgpu_device
*adev
)
6703 struct ci_power_info
*pi
= ci_get_pi(adev
);
6704 struct ci_single_dpm_table
*mclk_table
= &(pi
->dpm_table
.mclk_table
);
6705 struct ci_single_dpm_table
*golden_mclk_table
=
6706 &(pi
->golden_dpm_table
.mclk_table
);
6709 value
= (mclk_table
->dpm_levels
[mclk_table
->count
- 1].value
-
6710 golden_mclk_table
->dpm_levels
[golden_mclk_table
->count
- 1].value
) *
6712 golden_mclk_table
->dpm_levels
[golden_mclk_table
->count
- 1].value
;
6717 static int ci_dpm_set_mclk_od(struct amdgpu_device
*adev
, uint32_t value
)
6719 struct ci_power_info
*pi
= ci_get_pi(adev
);
6720 struct ci_ps
*ps
= ci_get_ps(adev
->pm
.dpm
.requested_ps
);
6721 struct ci_single_dpm_table
*golden_mclk_table
=
6722 &(pi
->golden_dpm_table
.mclk_table
);
6727 ps
->performance_levels
[ps
->performance_level_count
- 1].mclk
=
6728 golden_mclk_table
->dpm_levels
[golden_mclk_table
->count
- 1].value
*
6730 golden_mclk_table
->dpm_levels
[golden_mclk_table
->count
- 1].value
;
6735 static int ci_dpm_get_power_profile_state(struct amdgpu_device
*adev
,
6736 struct amd_pp_profile
*query
)
6738 struct ci_power_info
*pi
= ci_get_pi(adev
);
6743 if (query
->type
== AMD_PP_GFX_PROFILE
)
6744 memcpy(query
, &pi
->gfx_power_profile
,
6745 sizeof(struct amd_pp_profile
));
6746 else if (query
->type
== AMD_PP_COMPUTE_PROFILE
)
6747 memcpy(query
, &pi
->compute_power_profile
,
6748 sizeof(struct amd_pp_profile
));
6755 static int ci_populate_requested_graphic_levels(struct amdgpu_device
*adev
,
6756 struct amd_pp_profile
*request
)
6758 struct ci_power_info
*pi
= ci_get_pi(adev
);
6759 struct ci_dpm_table
*dpm_table
= &(pi
->dpm_table
);
6760 struct SMU7_Discrete_GraphicsLevel
*levels
=
6761 pi
->smc_state_table
.GraphicsLevel
;
6762 uint32_t array
= pi
->dpm_table_start
+
6763 offsetof(SMU7_Discrete_DpmTable
, GraphicsLevel
);
6764 uint32_t array_size
= sizeof(struct SMU7_Discrete_GraphicsLevel
) *
6765 SMU7_MAX_LEVELS_GRAPHICS
;
6768 for (i
= 0; i
< dpm_table
->sclk_table
.count
; i
++) {
6769 levels
[i
].ActivityLevel
=
6770 cpu_to_be16(request
->activity_threshold
);
6771 levels
[i
].EnabledForActivity
= 1;
6772 levels
[i
].UpH
= request
->up_hyst
;
6773 levels
[i
].DownH
= request
->down_hyst
;
6776 return amdgpu_ci_copy_bytes_to_smc(adev
, array
, (uint8_t *)levels
,
6777 array_size
, pi
->sram_end
);
6780 static void ci_find_min_clock_masks(struct amdgpu_device
*adev
,
6781 uint32_t *sclk_mask
, uint32_t *mclk_mask
,
6782 uint32_t min_sclk
, uint32_t min_mclk
)
6784 struct ci_power_info
*pi
= ci_get_pi(adev
);
6785 struct ci_dpm_table
*dpm_table
= &(pi
->dpm_table
);
6788 for (i
= 0; i
< dpm_table
->sclk_table
.count
; i
++) {
6789 if (dpm_table
->sclk_table
.dpm_levels
[i
].enabled
&&
6790 dpm_table
->sclk_table
.dpm_levels
[i
].value
>= min_sclk
)
6791 *sclk_mask
|= 1 << i
;
6794 for (i
= 0; i
< dpm_table
->mclk_table
.count
; i
++) {
6795 if (dpm_table
->mclk_table
.dpm_levels
[i
].enabled
&&
6796 dpm_table
->mclk_table
.dpm_levels
[i
].value
>= min_mclk
)
6797 *mclk_mask
|= 1 << i
;
6801 static int ci_set_power_profile_state(struct amdgpu_device
*adev
,
6802 struct amd_pp_profile
*request
)
6804 struct ci_power_info
*pi
= ci_get_pi(adev
);
6805 int tmp_result
, result
= 0;
6806 uint32_t sclk_mask
= 0, mclk_mask
= 0;
6808 tmp_result
= ci_freeze_sclk_mclk_dpm(adev
);
6810 DRM_ERROR("Failed to freeze SCLK MCLK DPM!");
6811 result
= tmp_result
;
6814 tmp_result
= ci_populate_requested_graphic_levels(adev
,
6817 DRM_ERROR("Failed to populate requested graphic levels!");
6818 result
= tmp_result
;
6821 tmp_result
= ci_unfreeze_sclk_mclk_dpm(adev
);
6823 DRM_ERROR("Failed to unfreeze SCLK MCLK DPM!");
6824 result
= tmp_result
;
6827 ci_find_min_clock_masks(adev
, &sclk_mask
, &mclk_mask
,
6828 request
->min_sclk
, request
->min_mclk
);
6831 if (!pi
->sclk_dpm_key_disabled
)
6832 amdgpu_ci_send_msg_to_smc_with_parameter(
6834 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
6835 pi
->dpm_level_enable_mask
.
6836 sclk_dpm_enable_mask
&
6841 if (!pi
->mclk_dpm_key_disabled
)
6842 amdgpu_ci_send_msg_to_smc_with_parameter(
6844 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
6845 pi
->dpm_level_enable_mask
.
6846 mclk_dpm_enable_mask
&
6854 static int ci_dpm_set_power_profile_state(struct amdgpu_device
*adev
,
6855 struct amd_pp_profile
*request
)
6857 struct ci_power_info
*pi
= ci_get_pi(adev
);
6860 if (!pi
|| !request
)
6863 if (adev
->pm
.dpm
.forced_level
!=
6864 AMD_DPM_FORCED_LEVEL_AUTO
)
6867 if (request
->min_sclk
||
6868 request
->min_mclk
||
6869 request
->activity_threshold
||
6871 request
->down_hyst
) {
6872 if (request
->type
== AMD_PP_GFX_PROFILE
)
6873 memcpy(&pi
->gfx_power_profile
, request
,
6874 sizeof(struct amd_pp_profile
));
6875 else if (request
->type
== AMD_PP_COMPUTE_PROFILE
)
6876 memcpy(&pi
->compute_power_profile
, request
,
6877 sizeof(struct amd_pp_profile
));
6881 if (request
->type
== pi
->current_power_profile
)
6882 ret
= ci_set_power_profile_state(
6886 /* set power profile if it exists */
6887 switch (request
->type
) {
6888 case AMD_PP_GFX_PROFILE
:
6889 ret
= ci_set_power_profile_state(
6891 &pi
->gfx_power_profile
);
6893 case AMD_PP_COMPUTE_PROFILE
:
6894 ret
= ci_set_power_profile_state(
6896 &pi
->compute_power_profile
);
6904 pi
->current_power_profile
= request
->type
;
6909 static int ci_dpm_reset_power_profile_state(struct amdgpu_device
*adev
,
6910 struct amd_pp_profile
*request
)
6912 struct ci_power_info
*pi
= ci_get_pi(adev
);
6914 if (!pi
|| !request
)
6917 if (request
->type
== AMD_PP_GFX_PROFILE
) {
6918 pi
->gfx_power_profile
= pi
->default_gfx_power_profile
;
6919 return ci_dpm_set_power_profile_state(adev
,
6920 &pi
->gfx_power_profile
);
6921 } else if (request
->type
== AMD_PP_COMPUTE_PROFILE
) {
6922 pi
->compute_power_profile
=
6923 pi
->default_compute_power_profile
;
6924 return ci_dpm_set_power_profile_state(adev
,
6925 &pi
->compute_power_profile
);
6930 static int ci_dpm_switch_power_profile(struct amdgpu_device
*adev
,
6931 enum amd_pp_profile_type type
)
6933 struct ci_power_info
*pi
= ci_get_pi(adev
);
6934 struct amd_pp_profile request
= {0};
6939 if (pi
->current_power_profile
!= type
) {
6940 request
.type
= type
;
6941 return ci_dpm_set_power_profile_state(adev
, &request
);
6947 static int ci_dpm_read_sensor(struct amdgpu_device
*adev
, int idx
,
6948 void *value
, int *size
)
6950 u32 activity_percent
= 50;
6953 /* size must be at least 4 bytes for all sensors */
6958 case AMDGPU_PP_SENSOR_GFX_SCLK
:
6959 *((uint32_t *)value
) = ci_get_average_sclk_freq(adev
);
6962 case AMDGPU_PP_SENSOR_GFX_MCLK
:
6963 *((uint32_t *)value
) = ci_get_average_mclk_freq(adev
);
6966 case AMDGPU_PP_SENSOR_GPU_TEMP
:
6967 *((uint32_t *)value
) = ci_dpm_get_temp(adev
);
6970 case AMDGPU_PP_SENSOR_GPU_LOAD
:
6971 ret
= ci_read_smc_soft_register(adev
,
6972 offsetof(SMU7_SoftRegisters
,
6976 activity_percent
+= 0x80;
6977 activity_percent
>>= 8;
6979 activity_percent
> 100 ? 100 : activity_percent
;
6981 *((uint32_t *)value
) = activity_percent
;
6989 const struct amd_ip_funcs ci_dpm_ip_funcs
= {
6991 .early_init
= ci_dpm_early_init
,
6992 .late_init
= ci_dpm_late_init
,
6993 .sw_init
= ci_dpm_sw_init
,
6994 .sw_fini
= ci_dpm_sw_fini
,
6995 .hw_init
= ci_dpm_hw_init
,
6996 .hw_fini
= ci_dpm_hw_fini
,
6997 .suspend
= ci_dpm_suspend
,
6998 .resume
= ci_dpm_resume
,
6999 .is_idle
= ci_dpm_is_idle
,
7000 .wait_for_idle
= ci_dpm_wait_for_idle
,
7001 .soft_reset
= ci_dpm_soft_reset
,
7002 .set_clockgating_state
= ci_dpm_set_clockgating_state
,
7003 .set_powergating_state
= ci_dpm_set_powergating_state
,
7006 static const struct amdgpu_dpm_funcs ci_dpm_funcs
= {
7007 .get_temperature
= &ci_dpm_get_temp
,
7008 .pre_set_power_state
= &ci_dpm_pre_set_power_state
,
7009 .set_power_state
= &ci_dpm_set_power_state
,
7010 .post_set_power_state
= &ci_dpm_post_set_power_state
,
7011 .display_configuration_changed
= &ci_dpm_display_configuration_changed
,
7012 .get_sclk
= &ci_dpm_get_sclk
,
7013 .get_mclk
= &ci_dpm_get_mclk
,
7014 .print_power_state
= &ci_dpm_print_power_state
,
7015 .debugfs_print_current_performance_level
= &ci_dpm_debugfs_print_current_performance_level
,
7016 .force_performance_level
= &ci_dpm_force_performance_level
,
7017 .vblank_too_short
= &ci_dpm_vblank_too_short
,
7018 .powergate_uvd
= &ci_dpm_powergate_uvd
,
7019 .set_fan_control_mode
= &ci_dpm_set_fan_control_mode
,
7020 .get_fan_control_mode
= &ci_dpm_get_fan_control_mode
,
7021 .set_fan_speed_percent
= &ci_dpm_set_fan_speed_percent
,
7022 .get_fan_speed_percent
= &ci_dpm_get_fan_speed_percent
,
7023 .print_clock_levels
= ci_dpm_print_clock_levels
,
7024 .force_clock_level
= ci_dpm_force_clock_level
,
7025 .get_sclk_od
= ci_dpm_get_sclk_od
,
7026 .set_sclk_od
= ci_dpm_set_sclk_od
,
7027 .get_mclk_od
= ci_dpm_get_mclk_od
,
7028 .set_mclk_od
= ci_dpm_set_mclk_od
,
7029 .check_state_equal
= ci_check_state_equal
,
7030 .get_vce_clock_state
= amdgpu_get_vce_clock_state
,
7031 .get_power_profile_state
= ci_dpm_get_power_profile_state
,
7032 .set_power_profile_state
= ci_dpm_set_power_profile_state
,
7033 .reset_power_profile_state
= ci_dpm_reset_power_profile_state
,
7034 .switch_power_profile
= ci_dpm_switch_power_profile
,
7035 .read_sensor
= ci_dpm_read_sensor
,
7038 static void ci_dpm_set_dpm_funcs(struct amdgpu_device
*adev
)
7040 if (adev
->pm
.funcs
== NULL
)
7041 adev
->pm
.funcs
= &ci_dpm_funcs
;
7044 static const struct amdgpu_irq_src_funcs ci_dpm_irq_funcs
= {
7045 .set
= ci_dpm_set_interrupt_state
,
7046 .process
= ci_dpm_process_interrupt
,
7049 static void ci_dpm_set_irq_funcs(struct amdgpu_device
*adev
)
7051 adev
->pm
.dpm
.thermal
.irq
.num_types
= AMDGPU_THERMAL_IRQ_LAST
;
7052 adev
->pm
.dpm
.thermal
.irq
.funcs
= &ci_dpm_irq_funcs
;