2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "bif/bif_4_1_d.h"
33 #include "bif/bif_4_1_sh_mask.h"
35 #include "gca/gfx_7_2_d.h"
36 #include "gca/gfx_7_2_enum.h"
37 #include "gca/gfx_7_2_sh_mask.h"
39 #include "gmc/gmc_7_1_d.h"
40 #include "gmc/gmc_7_1_sh_mask.h"
42 #include "oss/oss_2_0_d.h"
43 #include "oss/oss_2_0_sh_mask.h"
45 static const u32 sdma_offsets
[SDMA_MAX_INSTANCE
] =
47 SDMA0_REGISTER_OFFSET
,
51 static void cik_sdma_set_ring_funcs(struct amdgpu_device
*adev
);
52 static void cik_sdma_set_irq_funcs(struct amdgpu_device
*adev
);
53 static void cik_sdma_set_buffer_funcs(struct amdgpu_device
*adev
);
54 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device
*adev
);
55 static int cik_sdma_soft_reset(void *handle
);
57 MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
58 MODULE_FIRMWARE("radeon/bonaire_sdma1.bin");
59 MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
60 MODULE_FIRMWARE("radeon/hawaii_sdma1.bin");
61 MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
62 MODULE_FIRMWARE("radeon/kaveri_sdma1.bin");
63 MODULE_FIRMWARE("radeon/kabini_sdma.bin");
64 MODULE_FIRMWARE("radeon/kabini_sdma1.bin");
65 MODULE_FIRMWARE("radeon/mullins_sdma.bin");
66 MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
68 u32
amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device
*adev
);
71 static void cik_sdma_free_microcode(struct amdgpu_device
*adev
)
74 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
75 release_firmware(adev
->sdma
.instance
[i
].fw
);
76 adev
->sdma
.instance
[i
].fw
= NULL
;
82 * Starting with CIK, the GPU has new asynchronous
83 * DMA engines. These engines are used for compute
84 * and gfx. There are two DMA engines (SDMA0, SDMA1)
85 * and each one supports 1 ring buffer used for gfx
86 * and 2 queues used for compute.
88 * The programming model is very similar to the CP
89 * (ring buffer, IBs, etc.), but sDMA has it's own
90 * packet format that is different from the PM4 format
91 * used by the CP. sDMA supports copying data, writing
92 * embedded data, solid fills, and a number of other
93 * things. It also has support for tiling/detiling of
98 * cik_sdma_init_microcode - load ucode images from disk
100 * @adev: amdgpu_device pointer
102 * Use the firmware interface to load the ucode images into
103 * the driver (not loaded into hw).
104 * Returns 0 on success, error on failure.
106 static int cik_sdma_init_microcode(struct amdgpu_device
*adev
)
108 const char *chip_name
;
114 switch (adev
->asic_type
) {
116 chip_name
= "bonaire";
119 chip_name
= "hawaii";
122 chip_name
= "kaveri";
125 chip_name
= "kabini";
128 chip_name
= "mullins";
133 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
135 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_sdma.bin", chip_name
);
137 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_sdma1.bin", chip_name
);
138 err
= request_firmware(&adev
->sdma
.instance
[i
].fw
, fw_name
, adev
->dev
);
141 err
= amdgpu_ucode_validate(adev
->sdma
.instance
[i
].fw
);
146 "cik_sdma: Failed to load firmware \"%s\"\n",
148 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
149 release_firmware(adev
->sdma
.instance
[i
].fw
);
150 adev
->sdma
.instance
[i
].fw
= NULL
;
157 * cik_sdma_ring_get_rptr - get the current read pointer
159 * @ring: amdgpu ring pointer
161 * Get the current rptr from the hardware (CIK+).
163 static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring
*ring
)
167 rptr
= ring
->adev
->wb
.wb
[ring
->rptr_offs
];
169 return (rptr
& 0x3fffc) >> 2;
173 * cik_sdma_ring_get_wptr - get the current write pointer
175 * @ring: amdgpu ring pointer
177 * Get the current wptr from the hardware (CIK+).
179 static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring
*ring
)
181 struct amdgpu_device
*adev
= ring
->adev
;
182 u32 me
= (ring
== &adev
->sdma
.instance
[0].ring
) ? 0 : 1;
184 return (RREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[me
]) & 0x3fffc) >> 2;
188 * cik_sdma_ring_set_wptr - commit the write pointer
190 * @ring: amdgpu ring pointer
192 * Write the wptr back to the hardware (CIK+).
194 static void cik_sdma_ring_set_wptr(struct amdgpu_ring
*ring
)
196 struct amdgpu_device
*adev
= ring
->adev
;
197 u32 me
= (ring
== &adev
->sdma
.instance
[0].ring
) ? 0 : 1;
199 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[me
], (ring
->wptr
<< 2) & 0x3fffc);
202 static void cik_sdma_ring_insert_nop(struct amdgpu_ring
*ring
, uint32_t count
)
204 struct amdgpu_sdma_instance
*sdma
= amdgpu_get_sdma_instance(ring
);
207 for (i
= 0; i
< count
; i
++)
208 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
209 amdgpu_ring_write(ring
, ring
->nop
|
210 SDMA_NOP_COUNT(count
- 1));
212 amdgpu_ring_write(ring
, ring
->nop
);
216 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
218 * @ring: amdgpu ring pointer
219 * @ib: IB object to schedule
221 * Schedule an IB in the DMA ring (CIK).
223 static void cik_sdma_ring_emit_ib(struct amdgpu_ring
*ring
,
224 struct amdgpu_ib
*ib
,
225 unsigned vm_id
, bool ctx_switch
)
227 u32 extra_bits
= vm_id
& 0xf;
229 /* IB packet must end on a 8 DW boundary */
230 cik_sdma_ring_insert_nop(ring
, (12 - (ring
->wptr
& 7)) % 8);
232 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER
, 0, extra_bits
));
233 amdgpu_ring_write(ring
, ib
->gpu_addr
& 0xffffffe0); /* base must be 32 byte aligned */
234 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
) & 0xffffffff);
235 amdgpu_ring_write(ring
, ib
->length_dw
);
240 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
242 * @ring: amdgpu ring pointer
244 * Emit an hdp flush packet on the requested DMA ring.
246 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring
*ring
)
248 u32 extra_bits
= (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
249 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
252 if (ring
== &ring
->adev
->sdma
.instance
[0].ring
)
253 ref_and_mask
= GPU_HDP_FLUSH_DONE__SDMA0_MASK
;
255 ref_and_mask
= GPU_HDP_FLUSH_DONE__SDMA1_MASK
;
257 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM
, 0, extra_bits
));
258 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_DONE
<< 2);
259 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_REQ
<< 2);
260 amdgpu_ring_write(ring
, ref_and_mask
); /* reference */
261 amdgpu_ring_write(ring
, ref_and_mask
); /* mask */
262 amdgpu_ring_write(ring
, (0xfff << 16) | 10); /* retry count, poll interval */
265 static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring
*ring
)
267 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE
, 0, 0xf000));
268 amdgpu_ring_write(ring
, mmHDP_DEBUG0
);
269 amdgpu_ring_write(ring
, 1);
273 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
275 * @ring: amdgpu ring pointer
276 * @fence: amdgpu fence object
278 * Add a DMA fence packet to the ring to write
279 * the fence seq number and DMA trap packet to generate
280 * an interrupt if needed (CIK).
282 static void cik_sdma_ring_emit_fence(struct amdgpu_ring
*ring
, u64 addr
, u64 seq
,
285 bool write64bit
= flags
& AMDGPU_FENCE_FLAG_64BIT
;
286 /* write the fence */
287 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_FENCE
, 0, 0));
288 amdgpu_ring_write(ring
, lower_32_bits(addr
));
289 amdgpu_ring_write(ring
, upper_32_bits(addr
));
290 amdgpu_ring_write(ring
, lower_32_bits(seq
));
292 /* optionally write high bits as well */
295 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_FENCE
, 0, 0));
296 amdgpu_ring_write(ring
, lower_32_bits(addr
));
297 amdgpu_ring_write(ring
, upper_32_bits(addr
));
298 amdgpu_ring_write(ring
, upper_32_bits(seq
));
301 /* generate an interrupt */
302 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_TRAP
, 0, 0));
306 * cik_sdma_gfx_stop - stop the gfx async dma engines
308 * @adev: amdgpu_device pointer
310 * Stop the gfx async dma ring buffers (CIK).
312 static void cik_sdma_gfx_stop(struct amdgpu_device
*adev
)
314 struct amdgpu_ring
*sdma0
= &adev
->sdma
.instance
[0].ring
;
315 struct amdgpu_ring
*sdma1
= &adev
->sdma
.instance
[1].ring
;
319 if ((adev
->mman
.buffer_funcs_ring
== sdma0
) ||
320 (adev
->mman
.buffer_funcs_ring
== sdma1
))
321 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.visible_vram_size
);
323 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
324 rb_cntl
= RREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
]);
325 rb_cntl
&= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK
;
326 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
327 WREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
], 0);
329 sdma0
->ready
= false;
330 sdma1
->ready
= false;
334 * cik_sdma_rlc_stop - stop the compute async dma engines
336 * @adev: amdgpu_device pointer
338 * Stop the compute async dma queues (CIK).
340 static void cik_sdma_rlc_stop(struct amdgpu_device
*adev
)
346 * cik_sdma_enable - stop the async dma engines
348 * @adev: amdgpu_device pointer
349 * @enable: enable/disable the DMA MEs.
351 * Halt or unhalt the async dma engines (CIK).
353 static void cik_sdma_enable(struct amdgpu_device
*adev
, bool enable
)
359 cik_sdma_gfx_stop(adev
);
360 cik_sdma_rlc_stop(adev
);
363 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
364 me_cntl
= RREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
]);
366 me_cntl
&= ~SDMA0_F32_CNTL__HALT_MASK
;
368 me_cntl
|= SDMA0_F32_CNTL__HALT_MASK
;
369 WREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
], me_cntl
);
374 * cik_sdma_gfx_resume - setup and start the async dma engines
376 * @adev: amdgpu_device pointer
378 * Set up the gfx DMA ring buffers and enable them (CIK).
379 * Returns 0 for success, error for failure.
381 static int cik_sdma_gfx_resume(struct amdgpu_device
*adev
)
383 struct amdgpu_ring
*ring
;
384 u32 rb_cntl
, ib_cntl
;
389 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
390 ring
= &adev
->sdma
.instance
[i
].ring
;
391 wb_offset
= (ring
->rptr_offs
* 4);
393 mutex_lock(&adev
->srbm_mutex
);
394 for (j
= 0; j
< 16; j
++) {
395 cik_srbm_select(adev
, 0, 0, 0, j
);
397 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR
+ sdma_offsets
[i
], 0);
398 WREG32(mmSDMA0_GFX_APE1_CNTL
+ sdma_offsets
[i
], 0);
399 /* XXX SDMA RLC - todo */
401 cik_srbm_select(adev
, 0, 0, 0, 0);
402 mutex_unlock(&adev
->srbm_mutex
);
404 WREG32(mmSDMA0_TILING_CONFIG
+ sdma_offsets
[i
],
405 adev
->gfx
.config
.gb_addr_config
& 0x70);
407 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL
+ sdma_offsets
[i
], 0);
408 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
+ sdma_offsets
[i
], 0);
410 /* Set ring buffer size in dwords */
411 rb_bufsz
= order_base_2(ring
->ring_size
/ 4);
412 rb_cntl
= rb_bufsz
<< 1;
414 rb_cntl
|= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK
|
415 SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK
;
417 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
419 /* Initialize the ring buffer's read and write pointers */
420 WREG32(mmSDMA0_GFX_RB_RPTR
+ sdma_offsets
[i
], 0);
421 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
], 0);
422 WREG32(mmSDMA0_GFX_IB_RPTR
+ sdma_offsets
[i
], 0);
423 WREG32(mmSDMA0_GFX_IB_OFFSET
+ sdma_offsets
[i
], 0);
425 /* set the wb address whether it's enabled or not */
426 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI
+ sdma_offsets
[i
],
427 upper_32_bits(adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFF);
428 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO
+ sdma_offsets
[i
],
429 ((adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFC));
431 rb_cntl
|= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK
;
433 WREG32(mmSDMA0_GFX_RB_BASE
+ sdma_offsets
[i
], ring
->gpu_addr
>> 8);
434 WREG32(mmSDMA0_GFX_RB_BASE_HI
+ sdma_offsets
[i
], ring
->gpu_addr
>> 40);
437 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
], ring
->wptr
<< 2);
440 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
],
441 rb_cntl
| SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK
);
443 ib_cntl
= SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK
;
445 ib_cntl
|= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK
;
448 WREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
], ib_cntl
);
453 cik_sdma_enable(adev
, true);
455 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
456 ring
= &adev
->sdma
.instance
[i
].ring
;
457 r
= amdgpu_ring_test_ring(ring
);
463 if (adev
->mman
.buffer_funcs_ring
== ring
)
464 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.real_vram_size
);
471 * cik_sdma_rlc_resume - setup and start the async dma engines
473 * @adev: amdgpu_device pointer
475 * Set up the compute DMA queues and enable them (CIK).
476 * Returns 0 for success, error for failure.
478 static int cik_sdma_rlc_resume(struct amdgpu_device
*adev
)
485 * cik_sdma_load_microcode - load the sDMA ME ucode
487 * @adev: amdgpu_device pointer
489 * Loads the sDMA0/1 ucode.
490 * Returns 0 for success, -EINVAL if the ucode is not available.
492 static int cik_sdma_load_microcode(struct amdgpu_device
*adev
)
494 const struct sdma_firmware_header_v1_0
*hdr
;
495 const __le32
*fw_data
;
500 cik_sdma_enable(adev
, false);
502 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
503 if (!adev
->sdma
.instance
[i
].fw
)
505 hdr
= (const struct sdma_firmware_header_v1_0
*)adev
->sdma
.instance
[i
].fw
->data
;
506 amdgpu_ucode_print_sdma_hdr(&hdr
->header
);
507 fw_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
) / 4;
508 adev
->sdma
.instance
[i
].fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
509 adev
->sdma
.instance
[i
].feature_version
= le32_to_cpu(hdr
->ucode_feature_version
);
510 if (adev
->sdma
.instance
[i
].feature_version
>= 20)
511 adev
->sdma
.instance
[i
].burst_nop
= true;
512 fw_data
= (const __le32
*)
513 (adev
->sdma
.instance
[i
].fw
->data
+ le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
514 WREG32(mmSDMA0_UCODE_ADDR
+ sdma_offsets
[i
], 0);
515 for (j
= 0; j
< fw_size
; j
++)
516 WREG32(mmSDMA0_UCODE_DATA
+ sdma_offsets
[i
], le32_to_cpup(fw_data
++));
517 WREG32(mmSDMA0_UCODE_ADDR
+ sdma_offsets
[i
], adev
->sdma
.instance
[i
].fw_version
);
524 * cik_sdma_start - setup and start the async dma engines
526 * @adev: amdgpu_device pointer
528 * Set up the DMA engines and enable them (CIK).
529 * Returns 0 for success, error for failure.
531 static int cik_sdma_start(struct amdgpu_device
*adev
)
535 r
= cik_sdma_load_microcode(adev
);
539 /* halt the engine before programing */
540 cik_sdma_enable(adev
, false);
542 /* start the gfx rings and rlc compute queues */
543 r
= cik_sdma_gfx_resume(adev
);
546 r
= cik_sdma_rlc_resume(adev
);
554 * cik_sdma_ring_test_ring - simple async dma engine test
556 * @ring: amdgpu_ring structure holding ring information
558 * Test the DMA engine by writing using it to write an
559 * value to memory. (CIK).
560 * Returns 0 for success, error for failure.
562 static int cik_sdma_ring_test_ring(struct amdgpu_ring
*ring
)
564 struct amdgpu_device
*adev
= ring
->adev
;
571 r
= amdgpu_wb_get(adev
, &index
);
573 dev_err(adev
->dev
, "(%d) failed to allocate wb slot\n", r
);
577 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
579 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
581 r
= amdgpu_ring_alloc(ring
, 5);
583 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring
->idx
, r
);
584 amdgpu_wb_free(adev
, index
);
587 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_WRITE
, SDMA_WRITE_SUB_OPCODE_LINEAR
, 0));
588 amdgpu_ring_write(ring
, lower_32_bits(gpu_addr
));
589 amdgpu_ring_write(ring
, upper_32_bits(gpu_addr
));
590 amdgpu_ring_write(ring
, 1); /* number of DWs to follow */
591 amdgpu_ring_write(ring
, 0xDEADBEEF);
592 amdgpu_ring_commit(ring
);
594 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
595 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
596 if (tmp
== 0xDEADBEEF)
601 if (i
< adev
->usec_timeout
) {
602 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring
->idx
, i
);
604 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
608 amdgpu_wb_free(adev
, index
);
614 * cik_sdma_ring_test_ib - test an IB on the DMA engine
616 * @ring: amdgpu_ring structure holding ring information
618 * Test a simple IB in the DMA ring (CIK).
619 * Returns 0 on success, error on failure.
621 static int cik_sdma_ring_test_ib(struct amdgpu_ring
*ring
, long timeout
)
623 struct amdgpu_device
*adev
= ring
->adev
;
625 struct fence
*f
= NULL
;
631 r
= amdgpu_wb_get(adev
, &index
);
633 dev_err(adev
->dev
, "(%ld) failed to allocate wb slot\n", r
);
637 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
639 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
640 memset(&ib
, 0, sizeof(ib
));
641 r
= amdgpu_ib_get(adev
, NULL
, 256, &ib
);
643 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r
);
647 ib
.ptr
[0] = SDMA_PACKET(SDMA_OPCODE_WRITE
,
648 SDMA_WRITE_SUB_OPCODE_LINEAR
, 0);
649 ib
.ptr
[1] = lower_32_bits(gpu_addr
);
650 ib
.ptr
[2] = upper_32_bits(gpu_addr
);
652 ib
.ptr
[4] = 0xDEADBEEF;
654 r
= amdgpu_ib_schedule(ring
, 1, &ib
, NULL
, NULL
, &f
);
658 r
= fence_wait_timeout(f
, false, timeout
);
660 DRM_ERROR("amdgpu: IB test timed out\n");
664 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r
);
667 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
668 if (tmp
== 0xDEADBEEF) {
669 DRM_INFO("ib test on ring %d succeeded\n", ring
->idx
);
672 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp
);
677 amdgpu_ib_free(adev
, &ib
, NULL
);
680 amdgpu_wb_free(adev
, index
);
685 * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
687 * @ib: indirect buffer to fill with commands
688 * @pe: addr of the page entry
689 * @src: src addr to copy from
690 * @count: number of page entries to update
692 * Update PTEs by copying them from the GART using sDMA (CIK).
694 static void cik_sdma_vm_copy_pte(struct amdgpu_ib
*ib
,
695 uint64_t pe
, uint64_t src
,
699 unsigned bytes
= count
* 8;
700 if (bytes
> 0x1FFFF8)
703 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_COPY
,
704 SDMA_WRITE_SUB_OPCODE_LINEAR
, 0);
705 ib
->ptr
[ib
->length_dw
++] = bytes
;
706 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
707 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src
);
708 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src
);
709 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(pe
);
710 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
719 * cik_sdma_vm_write_pages - update PTEs by writing them manually
721 * @ib: indirect buffer to fill with commands
722 * @pe: addr of the page entry
723 * @addr: dst addr to write into pe
724 * @count: number of page entries to update
725 * @incr: increase next addr by incr bytes
726 * @flags: access flags
728 * Update PTEs by writing them manually using sDMA (CIK).
730 static void cik_sdma_vm_write_pte(struct amdgpu_ib
*ib
,
731 const dma_addr_t
*pages_addr
, uint64_t pe
,
732 uint64_t addr
, unsigned count
,
733 uint32_t incr
, uint32_t flags
)
743 /* for non-physically contiguous pages (system) */
744 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_WRITE
,
745 SDMA_WRITE_SUB_OPCODE_LINEAR
, 0);
746 ib
->ptr
[ib
->length_dw
++] = pe
;
747 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
748 ib
->ptr
[ib
->length_dw
++] = ndw
;
749 for (; ndw
> 0; ndw
-= 2, --count
, pe
+= 8) {
750 value
= amdgpu_vm_map_gart(pages_addr
, addr
);
753 ib
->ptr
[ib
->length_dw
++] = value
;
754 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
760 * cik_sdma_vm_set_pages - update the page tables using sDMA
762 * @ib: indirect buffer to fill with commands
763 * @pe: addr of the page entry
764 * @addr: dst addr to write into pe
765 * @count: number of page entries to update
766 * @incr: increase next addr by incr bytes
767 * @flags: access flags
769 * Update the page tables using sDMA (CIK).
771 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib
*ib
,
773 uint64_t addr
, unsigned count
,
774 uint32_t incr
, uint32_t flags
)
784 if (flags
& AMDGPU_PTE_VALID
)
789 /* for physically contiguous pages (vram) */
790 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE
, 0, 0);
791 ib
->ptr
[ib
->length_dw
++] = pe
; /* dst addr */
792 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
793 ib
->ptr
[ib
->length_dw
++] = flags
; /* mask */
794 ib
->ptr
[ib
->length_dw
++] = 0;
795 ib
->ptr
[ib
->length_dw
++] = value
; /* value */
796 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
797 ib
->ptr
[ib
->length_dw
++] = incr
; /* increment size */
798 ib
->ptr
[ib
->length_dw
++] = 0;
799 ib
->ptr
[ib
->length_dw
++] = ndw
; /* number of entries */
808 * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
810 * @ib: indirect buffer to fill with padding
813 static void cik_sdma_ring_pad_ib(struct amdgpu_ring
*ring
, struct amdgpu_ib
*ib
)
815 struct amdgpu_sdma_instance
*sdma
= amdgpu_get_sdma_instance(ring
);
819 pad_count
= (8 - (ib
->length_dw
& 0x7)) % 8;
820 for (i
= 0; i
< pad_count
; i
++)
821 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
822 ib
->ptr
[ib
->length_dw
++] =
823 SDMA_PACKET(SDMA_OPCODE_NOP
, 0, 0) |
824 SDMA_NOP_COUNT(pad_count
- 1);
826 ib
->ptr
[ib
->length_dw
++] =
827 SDMA_PACKET(SDMA_OPCODE_NOP
, 0, 0);
831 * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
833 * @ring: amdgpu_ring pointer
835 * Make sure all previous operations are completed (CIK).
837 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring
*ring
)
839 uint32_t seq
= ring
->fence_drv
.sync_seq
;
840 uint64_t addr
= ring
->fence_drv
.gpu_addr
;
843 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM
, 0,
844 SDMA_POLL_REG_MEM_EXTRA_OP(0) |
845 SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
846 SDMA_POLL_REG_MEM_EXTRA_M
));
847 amdgpu_ring_write(ring
, addr
& 0xfffffffc);
848 amdgpu_ring_write(ring
, upper_32_bits(addr
) & 0xffffffff);
849 amdgpu_ring_write(ring
, seq
); /* reference */
850 amdgpu_ring_write(ring
, 0xfffffff); /* mask */
851 amdgpu_ring_write(ring
, (0xfff << 16) | 4); /* retry count, poll interval */
855 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
857 * @ring: amdgpu_ring pointer
858 * @vm: amdgpu_vm pointer
860 * Update the page table base and flush the VM TLB
863 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring
*ring
,
864 unsigned vm_id
, uint64_t pd_addr
)
866 u32 extra_bits
= (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
867 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
869 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE
, 0, 0xf000));
871 amdgpu_ring_write(ring
, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ vm_id
));
873 amdgpu_ring_write(ring
, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
+ vm_id
- 8));
875 amdgpu_ring_write(ring
, pd_addr
>> 12);
878 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE
, 0, 0xf000));
879 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
);
880 amdgpu_ring_write(ring
, 1 << vm_id
);
882 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM
, 0, extra_bits
));
883 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
<< 2);
884 amdgpu_ring_write(ring
, 0);
885 amdgpu_ring_write(ring
, 0); /* reference */
886 amdgpu_ring_write(ring
, 0); /* mask */
887 amdgpu_ring_write(ring
, (0xfff << 16) | 10); /* retry count, poll interval */
890 static void cik_enable_sdma_mgcg(struct amdgpu_device
*adev
,
895 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_SDMA_MGCG
)) {
896 WREG32(mmSDMA0_CLK_CTRL
+ SDMA0_REGISTER_OFFSET
, 0x00000100);
897 WREG32(mmSDMA0_CLK_CTRL
+ SDMA1_REGISTER_OFFSET
, 0x00000100);
899 orig
= data
= RREG32(mmSDMA0_CLK_CTRL
+ SDMA0_REGISTER_OFFSET
);
902 WREG32(mmSDMA0_CLK_CTRL
+ SDMA0_REGISTER_OFFSET
, data
);
904 orig
= data
= RREG32(mmSDMA0_CLK_CTRL
+ SDMA1_REGISTER_OFFSET
);
907 WREG32(mmSDMA0_CLK_CTRL
+ SDMA1_REGISTER_OFFSET
, data
);
911 static void cik_enable_sdma_mgls(struct amdgpu_device
*adev
,
916 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_SDMA_LS
)) {
917 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
);
920 WREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
, data
);
922 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
);
925 WREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
, data
);
927 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
);
930 WREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
, data
);
932 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
);
935 WREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
, data
);
939 static int cik_sdma_early_init(void *handle
)
941 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
943 adev
->sdma
.num_instances
= SDMA_MAX_INSTANCE
;
945 cik_sdma_set_ring_funcs(adev
);
946 cik_sdma_set_irq_funcs(adev
);
947 cik_sdma_set_buffer_funcs(adev
);
948 cik_sdma_set_vm_pte_funcs(adev
);
953 static int cik_sdma_sw_init(void *handle
)
955 struct amdgpu_ring
*ring
;
956 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
959 r
= cik_sdma_init_microcode(adev
);
961 DRM_ERROR("Failed to load sdma firmware!\n");
965 /* SDMA trap event */
966 r
= amdgpu_irq_add_id(adev
, 224, &adev
->sdma
.trap_irq
);
970 /* SDMA Privileged inst */
971 r
= amdgpu_irq_add_id(adev
, 241, &adev
->sdma
.illegal_inst_irq
);
975 /* SDMA Privileged inst */
976 r
= amdgpu_irq_add_id(adev
, 247, &adev
->sdma
.illegal_inst_irq
);
980 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
981 ring
= &adev
->sdma
.instance
[i
].ring
;
982 ring
->ring_obj
= NULL
;
983 sprintf(ring
->name
, "sdma%d", i
);
984 r
= amdgpu_ring_init(adev
, ring
, 1024,
985 SDMA_PACKET(SDMA_OPCODE_NOP
, 0, 0), 0xf,
986 &adev
->sdma
.trap_irq
,
988 AMDGPU_SDMA_IRQ_TRAP0
: AMDGPU_SDMA_IRQ_TRAP1
,
989 AMDGPU_RING_TYPE_SDMA
);
997 static int cik_sdma_sw_fini(void *handle
)
999 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1002 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1003 amdgpu_ring_fini(&adev
->sdma
.instance
[i
].ring
);
1005 cik_sdma_free_microcode(adev
);
1009 static int cik_sdma_hw_init(void *handle
)
1012 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1014 r
= cik_sdma_start(adev
);
1021 static int cik_sdma_hw_fini(void *handle
)
1023 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1025 cik_sdma_enable(adev
, false);
1030 static int cik_sdma_suspend(void *handle
)
1032 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1034 return cik_sdma_hw_fini(adev
);
1037 static int cik_sdma_resume(void *handle
)
1039 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1041 cik_sdma_soft_reset(handle
);
1043 return cik_sdma_hw_init(adev
);
1046 static bool cik_sdma_is_idle(void *handle
)
1048 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1049 u32 tmp
= RREG32(mmSRBM_STATUS2
);
1051 if (tmp
& (SRBM_STATUS2__SDMA_BUSY_MASK
|
1052 SRBM_STATUS2__SDMA1_BUSY_MASK
))
1058 static int cik_sdma_wait_for_idle(void *handle
)
1062 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1064 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
1065 tmp
= RREG32(mmSRBM_STATUS2
) & (SRBM_STATUS2__SDMA_BUSY_MASK
|
1066 SRBM_STATUS2__SDMA1_BUSY_MASK
);
1075 static int cik_sdma_soft_reset(void *handle
)
1077 u32 srbm_soft_reset
= 0;
1078 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1079 u32 tmp
= RREG32(mmSRBM_STATUS2
);
1081 if (tmp
& SRBM_STATUS2__SDMA_BUSY_MASK
) {
1083 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
);
1084 tmp
|= SDMA0_F32_CNTL__HALT_MASK
;
1085 WREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
, tmp
);
1086 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK
;
1088 if (tmp
& SRBM_STATUS2__SDMA1_BUSY_MASK
) {
1090 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
);
1091 tmp
|= SDMA0_F32_CNTL__HALT_MASK
;
1092 WREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
, tmp
);
1093 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK
;
1096 if (srbm_soft_reset
) {
1097 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1098 tmp
|= srbm_soft_reset
;
1099 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
1100 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1101 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1105 tmp
&= ~srbm_soft_reset
;
1106 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1107 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1109 /* Wait a little for things to settle down */
1116 static int cik_sdma_set_trap_irq_state(struct amdgpu_device
*adev
,
1117 struct amdgpu_irq_src
*src
,
1119 enum amdgpu_interrupt_state state
)
1124 case AMDGPU_SDMA_IRQ_TRAP0
:
1126 case AMDGPU_IRQ_STATE_DISABLE
:
1127 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
);
1128 sdma_cntl
&= ~SDMA0_CNTL__TRAP_ENABLE_MASK
;
1129 WREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
, sdma_cntl
);
1131 case AMDGPU_IRQ_STATE_ENABLE
:
1132 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
);
1133 sdma_cntl
|= SDMA0_CNTL__TRAP_ENABLE_MASK
;
1134 WREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
, sdma_cntl
);
1140 case AMDGPU_SDMA_IRQ_TRAP1
:
1142 case AMDGPU_IRQ_STATE_DISABLE
:
1143 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
);
1144 sdma_cntl
&= ~SDMA0_CNTL__TRAP_ENABLE_MASK
;
1145 WREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
, sdma_cntl
);
1147 case AMDGPU_IRQ_STATE_ENABLE
:
1148 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
);
1149 sdma_cntl
|= SDMA0_CNTL__TRAP_ENABLE_MASK
;
1150 WREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
, sdma_cntl
);
1162 static int cik_sdma_process_trap_irq(struct amdgpu_device
*adev
,
1163 struct amdgpu_irq_src
*source
,
1164 struct amdgpu_iv_entry
*entry
)
1166 u8 instance_id
, queue_id
;
1168 instance_id
= (entry
->ring_id
& 0x3) >> 0;
1169 queue_id
= (entry
->ring_id
& 0xc) >> 2;
1170 DRM_DEBUG("IH: SDMA trap\n");
1171 switch (instance_id
) {
1175 amdgpu_fence_process(&adev
->sdma
.instance
[0].ring
);
1188 amdgpu_fence_process(&adev
->sdma
.instance
[1].ring
);
1203 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device
*adev
,
1204 struct amdgpu_irq_src
*source
,
1205 struct amdgpu_iv_entry
*entry
)
1207 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1208 schedule_work(&adev
->reset_work
);
1212 static int cik_sdma_set_clockgating_state(void *handle
,
1213 enum amd_clockgating_state state
)
1216 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1218 if (state
== AMD_CG_STATE_GATE
)
1221 cik_enable_sdma_mgcg(adev
, gate
);
1222 cik_enable_sdma_mgls(adev
, gate
);
1227 static int cik_sdma_set_powergating_state(void *handle
,
1228 enum amd_powergating_state state
)
1233 const struct amd_ip_funcs cik_sdma_ip_funcs
= {
1235 .early_init
= cik_sdma_early_init
,
1237 .sw_init
= cik_sdma_sw_init
,
1238 .sw_fini
= cik_sdma_sw_fini
,
1239 .hw_init
= cik_sdma_hw_init
,
1240 .hw_fini
= cik_sdma_hw_fini
,
1241 .suspend
= cik_sdma_suspend
,
1242 .resume
= cik_sdma_resume
,
1243 .is_idle
= cik_sdma_is_idle
,
1244 .wait_for_idle
= cik_sdma_wait_for_idle
,
1245 .soft_reset
= cik_sdma_soft_reset
,
1246 .set_clockgating_state
= cik_sdma_set_clockgating_state
,
1247 .set_powergating_state
= cik_sdma_set_powergating_state
,
1250 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs
= {
1251 .get_rptr
= cik_sdma_ring_get_rptr
,
1252 .get_wptr
= cik_sdma_ring_get_wptr
,
1253 .set_wptr
= cik_sdma_ring_set_wptr
,
1255 .emit_ib
= cik_sdma_ring_emit_ib
,
1256 .emit_fence
= cik_sdma_ring_emit_fence
,
1257 .emit_pipeline_sync
= cik_sdma_ring_emit_pipeline_sync
,
1258 .emit_vm_flush
= cik_sdma_ring_emit_vm_flush
,
1259 .emit_hdp_flush
= cik_sdma_ring_emit_hdp_flush
,
1260 .emit_hdp_invalidate
= cik_sdma_ring_emit_hdp_invalidate
,
1261 .test_ring
= cik_sdma_ring_test_ring
,
1262 .test_ib
= cik_sdma_ring_test_ib
,
1263 .insert_nop
= cik_sdma_ring_insert_nop
,
1264 .pad_ib
= cik_sdma_ring_pad_ib
,
1267 static void cik_sdma_set_ring_funcs(struct amdgpu_device
*adev
)
1271 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1272 adev
->sdma
.instance
[i
].ring
.funcs
= &cik_sdma_ring_funcs
;
1275 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs
= {
1276 .set
= cik_sdma_set_trap_irq_state
,
1277 .process
= cik_sdma_process_trap_irq
,
1280 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs
= {
1281 .process
= cik_sdma_process_illegal_inst_irq
,
1284 static void cik_sdma_set_irq_funcs(struct amdgpu_device
*adev
)
1286 adev
->sdma
.trap_irq
.num_types
= AMDGPU_SDMA_IRQ_LAST
;
1287 adev
->sdma
.trap_irq
.funcs
= &cik_sdma_trap_irq_funcs
;
1288 adev
->sdma
.illegal_inst_irq
.funcs
= &cik_sdma_illegal_inst_irq_funcs
;
1292 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1294 * @ring: amdgpu_ring structure holding ring information
1295 * @src_offset: src GPU address
1296 * @dst_offset: dst GPU address
1297 * @byte_count: number of bytes to xfer
1299 * Copy GPU buffers using the DMA engine (CIK).
1300 * Used by the amdgpu ttm implementation to move pages if
1301 * registered as the asic copy callback.
1303 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib
*ib
,
1304 uint64_t src_offset
,
1305 uint64_t dst_offset
,
1306 uint32_t byte_count
)
1308 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_COPY
, SDMA_COPY_SUB_OPCODE_LINEAR
, 0);
1309 ib
->ptr
[ib
->length_dw
++] = byte_count
;
1310 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
1311 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src_offset
);
1312 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src_offset
);
1313 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1314 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1318 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1320 * @ring: amdgpu_ring structure holding ring information
1321 * @src_data: value to write to buffer
1322 * @dst_offset: dst GPU address
1323 * @byte_count: number of bytes to xfer
1325 * Fill GPU buffers using the DMA engine (CIK).
1327 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib
*ib
,
1329 uint64_t dst_offset
,
1330 uint32_t byte_count
)
1332 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL
, 0, 0);
1333 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1334 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1335 ib
->ptr
[ib
->length_dw
++] = src_data
;
1336 ib
->ptr
[ib
->length_dw
++] = byte_count
;
1339 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs
= {
1340 .copy_max_bytes
= 0x1fffff,
1342 .emit_copy_buffer
= cik_sdma_emit_copy_buffer
,
1344 .fill_max_bytes
= 0x1fffff,
1346 .emit_fill_buffer
= cik_sdma_emit_fill_buffer
,
1349 static void cik_sdma_set_buffer_funcs(struct amdgpu_device
*adev
)
1351 if (adev
->mman
.buffer_funcs
== NULL
) {
1352 adev
->mman
.buffer_funcs
= &cik_sdma_buffer_funcs
;
1353 adev
->mman
.buffer_funcs_ring
= &adev
->sdma
.instance
[0].ring
;
1357 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs
= {
1358 .copy_pte
= cik_sdma_vm_copy_pte
,
1359 .write_pte
= cik_sdma_vm_write_pte
,
1360 .set_pte_pde
= cik_sdma_vm_set_pte_pde
,
1363 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device
*adev
)
1367 if (adev
->vm_manager
.vm_pte_funcs
== NULL
) {
1368 adev
->vm_manager
.vm_pte_funcs
= &cik_sdma_vm_pte_funcs
;
1369 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1370 adev
->vm_manager
.vm_pte_rings
[i
] =
1371 &adev
->sdma
.instance
[i
].ring
;
1373 adev
->vm_manager
.vm_pte_num_rings
= adev
->sdma
.num_instances
;