2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "bif/bif_4_1_d.h"
33 #include "bif/bif_4_1_sh_mask.h"
35 #include "gca/gfx_7_2_d.h"
36 #include "gca/gfx_7_2_enum.h"
37 #include "gca/gfx_7_2_sh_mask.h"
39 #include "gmc/gmc_7_1_d.h"
40 #include "gmc/gmc_7_1_sh_mask.h"
42 #include "oss/oss_2_0_d.h"
43 #include "oss/oss_2_0_sh_mask.h"
45 static const u32 sdma_offsets
[SDMA_MAX_INSTANCE
] =
47 SDMA0_REGISTER_OFFSET
,
51 static void cik_sdma_set_ring_funcs(struct amdgpu_device
*adev
);
52 static void cik_sdma_set_irq_funcs(struct amdgpu_device
*adev
);
53 static void cik_sdma_set_buffer_funcs(struct amdgpu_device
*adev
);
54 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device
*adev
);
56 MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
57 MODULE_FIRMWARE("radeon/bonaire_sdma1.bin");
58 MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
59 MODULE_FIRMWARE("radeon/hawaii_sdma1.bin");
60 MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
61 MODULE_FIRMWARE("radeon/kaveri_sdma1.bin");
62 MODULE_FIRMWARE("radeon/kabini_sdma.bin");
63 MODULE_FIRMWARE("radeon/kabini_sdma1.bin");
64 MODULE_FIRMWARE("radeon/mullins_sdma.bin");
65 MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
67 u32
amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device
*adev
);
71 * Starting with CIK, the GPU has new asynchronous
72 * DMA engines. These engines are used for compute
73 * and gfx. There are two DMA engines (SDMA0, SDMA1)
74 * and each one supports 1 ring buffer used for gfx
75 * and 2 queues used for compute.
77 * The programming model is very similar to the CP
78 * (ring buffer, IBs, etc.), but sDMA has it's own
79 * packet format that is different from the PM4 format
80 * used by the CP. sDMA supports copying data, writing
81 * embedded data, solid fills, and a number of other
82 * things. It also has support for tiling/detiling of
87 * cik_sdma_init_microcode - load ucode images from disk
89 * @adev: amdgpu_device pointer
91 * Use the firmware interface to load the ucode images into
92 * the driver (not loaded into hw).
93 * Returns 0 on success, error on failure.
95 static int cik_sdma_init_microcode(struct amdgpu_device
*adev
)
97 const char *chip_name
;
103 switch (adev
->asic_type
) {
105 chip_name
= "bonaire";
108 chip_name
= "hawaii";
111 chip_name
= "kaveri";
114 chip_name
= "kabini";
117 chip_name
= "mullins";
122 for (i
= 0; i
< SDMA_MAX_INSTANCE
; i
++) {
124 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_sdma.bin", chip_name
);
126 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_sdma1.bin", chip_name
);
127 err
= request_firmware(&adev
->sdma
[i
].fw
, fw_name
, adev
->dev
);
130 err
= amdgpu_ucode_validate(adev
->sdma
[i
].fw
);
135 "cik_sdma: Failed to load firmware \"%s\"\n",
137 for (i
= 0; i
< SDMA_MAX_INSTANCE
; i
++) {
138 release_firmware(adev
->sdma
[i
].fw
);
139 adev
->sdma
[i
].fw
= NULL
;
146 * cik_sdma_ring_get_rptr - get the current read pointer
148 * @ring: amdgpu ring pointer
150 * Get the current rptr from the hardware (CIK+).
152 static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring
*ring
)
156 rptr
= ring
->adev
->wb
.wb
[ring
->rptr_offs
];
158 return (rptr
& 0x3fffc) >> 2;
162 * cik_sdma_ring_get_wptr - get the current write pointer
164 * @ring: amdgpu ring pointer
166 * Get the current wptr from the hardware (CIK+).
168 static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring
*ring
)
170 struct amdgpu_device
*adev
= ring
->adev
;
171 u32 me
= (ring
== &adev
->sdma
[0].ring
) ? 0 : 1;
173 return (RREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[me
]) & 0x3fffc) >> 2;
177 * cik_sdma_ring_set_wptr - commit the write pointer
179 * @ring: amdgpu ring pointer
181 * Write the wptr back to the hardware (CIK+).
183 static void cik_sdma_ring_set_wptr(struct amdgpu_ring
*ring
)
185 struct amdgpu_device
*adev
= ring
->adev
;
186 u32 me
= (ring
== &adev
->sdma
[0].ring
) ? 0 : 1;
188 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[me
], (ring
->wptr
<< 2) & 0x3fffc);
191 static void cik_sdma_ring_insert_nop(struct amdgpu_ring
*ring
, uint32_t count
)
193 struct amdgpu_sdma
*sdma
= amdgpu_get_sdma_instance(ring
);
196 for (i
= 0; i
< count
; i
++)
197 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
198 amdgpu_ring_write(ring
, ring
->nop
|
199 SDMA_NOP_COUNT(count
- 1));
201 amdgpu_ring_write(ring
, ring
->nop
);
205 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
207 * @ring: amdgpu ring pointer
208 * @ib: IB object to schedule
210 * Schedule an IB in the DMA ring (CIK).
212 static void cik_sdma_ring_emit_ib(struct amdgpu_ring
*ring
,
213 struct amdgpu_ib
*ib
)
215 u32 extra_bits
= (ib
->vm
? ib
->vm
->ids
[ring
->idx
].id
: 0) & 0xf;
216 u32 next_rptr
= ring
->wptr
+ 5;
218 while ((next_rptr
& 7) != 4)
222 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_WRITE
, SDMA_WRITE_SUB_OPCODE_LINEAR
, 0));
223 amdgpu_ring_write(ring
, ring
->next_rptr_gpu_addr
& 0xfffffffc);
224 amdgpu_ring_write(ring
, upper_32_bits(ring
->next_rptr_gpu_addr
) & 0xffffffff);
225 amdgpu_ring_write(ring
, 1); /* number of DWs to follow */
226 amdgpu_ring_write(ring
, next_rptr
);
228 /* IB packet must end on a 8 DW boundary */
229 cik_sdma_ring_insert_nop(ring
, (12 - (ring
->wptr
& 7)) % 8);
231 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER
, 0, extra_bits
));
232 amdgpu_ring_write(ring
, ib
->gpu_addr
& 0xffffffe0); /* base must be 32 byte aligned */
233 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
) & 0xffffffff);
234 amdgpu_ring_write(ring
, ib
->length_dw
);
239 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
241 * @ring: amdgpu ring pointer
243 * Emit an hdp flush packet on the requested DMA ring.
245 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring
*ring
)
247 u32 extra_bits
= (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
248 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
251 if (ring
== &ring
->adev
->sdma
[0].ring
)
252 ref_and_mask
= GPU_HDP_FLUSH_DONE__SDMA0_MASK
;
254 ref_and_mask
= GPU_HDP_FLUSH_DONE__SDMA1_MASK
;
256 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM
, 0, extra_bits
));
257 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_DONE
<< 2);
258 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_REQ
<< 2);
259 amdgpu_ring_write(ring
, ref_and_mask
); /* reference */
260 amdgpu_ring_write(ring
, ref_and_mask
); /* mask */
261 amdgpu_ring_write(ring
, (0xfff << 16) | 10); /* retry count, poll interval */
265 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
267 * @ring: amdgpu ring pointer
268 * @fence: amdgpu fence object
270 * Add a DMA fence packet to the ring to write
271 * the fence seq number and DMA trap packet to generate
272 * an interrupt if needed (CIK).
274 static void cik_sdma_ring_emit_fence(struct amdgpu_ring
*ring
, u64 addr
, u64 seq
,
277 bool write64bit
= flags
& AMDGPU_FENCE_FLAG_64BIT
;
278 /* write the fence */
279 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_FENCE
, 0, 0));
280 amdgpu_ring_write(ring
, lower_32_bits(addr
));
281 amdgpu_ring_write(ring
, upper_32_bits(addr
));
282 amdgpu_ring_write(ring
, lower_32_bits(seq
));
284 /* optionally write high bits as well */
287 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_FENCE
, 0, 0));
288 amdgpu_ring_write(ring
, lower_32_bits(addr
));
289 amdgpu_ring_write(ring
, upper_32_bits(addr
));
290 amdgpu_ring_write(ring
, upper_32_bits(seq
));
293 /* generate an interrupt */
294 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_TRAP
, 0, 0));
298 * cik_sdma_ring_emit_semaphore - emit a semaphore on the dma ring
300 * @ring: amdgpu_ring structure holding ring information
301 * @semaphore: amdgpu semaphore object
302 * @emit_wait: wait or signal semaphore
304 * Add a DMA semaphore packet to the ring wait on or signal
307 static bool cik_sdma_ring_emit_semaphore(struct amdgpu_ring
*ring
,
308 struct amdgpu_semaphore
*semaphore
,
311 u64 addr
= semaphore
->gpu_addr
;
312 u32 extra_bits
= emit_wait
? 0 : SDMA_SEMAPHORE_EXTRA_S
;
314 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE
, 0, extra_bits
));
315 amdgpu_ring_write(ring
, addr
& 0xfffffff8);
316 amdgpu_ring_write(ring
, upper_32_bits(addr
) & 0xffffffff);
322 * cik_sdma_gfx_stop - stop the gfx async dma engines
324 * @adev: amdgpu_device pointer
326 * Stop the gfx async dma ring buffers (CIK).
328 static void cik_sdma_gfx_stop(struct amdgpu_device
*adev
)
330 struct amdgpu_ring
*sdma0
= &adev
->sdma
[0].ring
;
331 struct amdgpu_ring
*sdma1
= &adev
->sdma
[1].ring
;
335 if ((adev
->mman
.buffer_funcs_ring
== sdma0
) ||
336 (adev
->mman
.buffer_funcs_ring
== sdma1
))
337 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.visible_vram_size
);
339 for (i
= 0; i
< SDMA_MAX_INSTANCE
; i
++) {
340 rb_cntl
= RREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
]);
341 rb_cntl
&= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK
;
342 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
343 WREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
], 0);
345 sdma0
->ready
= false;
346 sdma1
->ready
= false;
350 * cik_sdma_rlc_stop - stop the compute async dma engines
352 * @adev: amdgpu_device pointer
354 * Stop the compute async dma queues (CIK).
356 static void cik_sdma_rlc_stop(struct amdgpu_device
*adev
)
362 * cik_sdma_enable - stop the async dma engines
364 * @adev: amdgpu_device pointer
365 * @enable: enable/disable the DMA MEs.
367 * Halt or unhalt the async dma engines (CIK).
369 static void cik_sdma_enable(struct amdgpu_device
*adev
, bool enable
)
374 if (enable
== false) {
375 cik_sdma_gfx_stop(adev
);
376 cik_sdma_rlc_stop(adev
);
379 for (i
= 0; i
< SDMA_MAX_INSTANCE
; i
++) {
380 me_cntl
= RREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
]);
382 me_cntl
&= ~SDMA0_F32_CNTL__HALT_MASK
;
384 me_cntl
|= SDMA0_F32_CNTL__HALT_MASK
;
385 WREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
], me_cntl
);
390 * cik_sdma_gfx_resume - setup and start the async dma engines
392 * @adev: amdgpu_device pointer
394 * Set up the gfx DMA ring buffers and enable them (CIK).
395 * Returns 0 for success, error for failure.
397 static int cik_sdma_gfx_resume(struct amdgpu_device
*adev
)
399 struct amdgpu_ring
*ring
;
400 u32 rb_cntl
, ib_cntl
;
405 for (i
= 0; i
< SDMA_MAX_INSTANCE
; i
++) {
406 ring
= &adev
->sdma
[i
].ring
;
407 wb_offset
= (ring
->rptr_offs
* 4);
409 mutex_lock(&adev
->srbm_mutex
);
410 for (j
= 0; j
< 16; j
++) {
411 cik_srbm_select(adev
, 0, 0, 0, j
);
413 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR
+ sdma_offsets
[i
], 0);
414 WREG32(mmSDMA0_GFX_APE1_CNTL
+ sdma_offsets
[i
], 0);
415 /* XXX SDMA RLC - todo */
417 cik_srbm_select(adev
, 0, 0, 0, 0);
418 mutex_unlock(&adev
->srbm_mutex
);
420 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL
+ sdma_offsets
[i
], 0);
421 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
+ sdma_offsets
[i
], 0);
423 /* Set ring buffer size in dwords */
424 rb_bufsz
= order_base_2(ring
->ring_size
/ 4);
425 rb_cntl
= rb_bufsz
<< 1;
427 rb_cntl
|= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK
|
428 SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK
;
430 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
432 /* Initialize the ring buffer's read and write pointers */
433 WREG32(mmSDMA0_GFX_RB_RPTR
+ sdma_offsets
[i
], 0);
434 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
], 0);
436 /* set the wb address whether it's enabled or not */
437 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI
+ sdma_offsets
[i
],
438 upper_32_bits(adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFF);
439 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO
+ sdma_offsets
[i
],
440 ((adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFC));
442 rb_cntl
|= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK
;
444 WREG32(mmSDMA0_GFX_RB_BASE
+ sdma_offsets
[i
], ring
->gpu_addr
>> 8);
445 WREG32(mmSDMA0_GFX_RB_BASE_HI
+ sdma_offsets
[i
], ring
->gpu_addr
>> 40);
448 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
], ring
->wptr
<< 2);
451 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
],
452 rb_cntl
| SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK
);
454 ib_cntl
= SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK
;
456 ib_cntl
|= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK
;
459 WREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
], ib_cntl
);
463 r
= amdgpu_ring_test_ring(ring
);
469 if (adev
->mman
.buffer_funcs_ring
== ring
)
470 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.real_vram_size
);
477 * cik_sdma_rlc_resume - setup and start the async dma engines
479 * @adev: amdgpu_device pointer
481 * Set up the compute DMA queues and enable them (CIK).
482 * Returns 0 for success, error for failure.
484 static int cik_sdma_rlc_resume(struct amdgpu_device
*adev
)
491 * cik_sdma_load_microcode - load the sDMA ME ucode
493 * @adev: amdgpu_device pointer
495 * Loads the sDMA0/1 ucode.
496 * Returns 0 for success, -EINVAL if the ucode is not available.
498 static int cik_sdma_load_microcode(struct amdgpu_device
*adev
)
500 const struct sdma_firmware_header_v1_0
*hdr
;
501 const __le32
*fw_data
;
505 if (!adev
->sdma
[0].fw
|| !adev
->sdma
[1].fw
)
509 cik_sdma_enable(adev
, false);
511 for (i
= 0; i
< SDMA_MAX_INSTANCE
; i
++) {
512 hdr
= (const struct sdma_firmware_header_v1_0
*)adev
->sdma
[i
].fw
->data
;
513 amdgpu_ucode_print_sdma_hdr(&hdr
->header
);
514 fw_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
) / 4;
515 adev
->sdma
[i
].fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
516 adev
->sdma
[i
].feature_version
= le32_to_cpu(hdr
->ucode_feature_version
);
517 if (adev
->sdma
[i
].feature_version
>= 20)
518 adev
->sdma
[i
].burst_nop
= true;
519 fw_data
= (const __le32
*)
520 (adev
->sdma
[i
].fw
->data
+ le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
521 WREG32(mmSDMA0_UCODE_ADDR
+ sdma_offsets
[i
], 0);
522 for (j
= 0; j
< fw_size
; j
++)
523 WREG32(mmSDMA0_UCODE_DATA
+ sdma_offsets
[i
], le32_to_cpup(fw_data
++));
524 WREG32(mmSDMA0_UCODE_ADDR
+ sdma_offsets
[i
], adev
->sdma
[i
].fw_version
);
531 * cik_sdma_start - setup and start the async dma engines
533 * @adev: amdgpu_device pointer
535 * Set up the DMA engines and enable them (CIK).
536 * Returns 0 for success, error for failure.
538 static int cik_sdma_start(struct amdgpu_device
*adev
)
542 r
= cik_sdma_load_microcode(adev
);
547 cik_sdma_enable(adev
, true);
549 /* start the gfx rings and rlc compute queues */
550 r
= cik_sdma_gfx_resume(adev
);
553 r
= cik_sdma_rlc_resume(adev
);
561 * cik_sdma_ring_test_ring - simple async dma engine test
563 * @ring: amdgpu_ring structure holding ring information
565 * Test the DMA engine by writing using it to write an
566 * value to memory. (CIK).
567 * Returns 0 for success, error for failure.
569 static int cik_sdma_ring_test_ring(struct amdgpu_ring
*ring
)
571 struct amdgpu_device
*adev
= ring
->adev
;
578 r
= amdgpu_wb_get(adev
, &index
);
580 dev_err(adev
->dev
, "(%d) failed to allocate wb slot\n", r
);
584 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
586 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
588 r
= amdgpu_ring_lock(ring
, 5);
590 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring
->idx
, r
);
591 amdgpu_wb_free(adev
, index
);
594 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_WRITE
, SDMA_WRITE_SUB_OPCODE_LINEAR
, 0));
595 amdgpu_ring_write(ring
, lower_32_bits(gpu_addr
));
596 amdgpu_ring_write(ring
, upper_32_bits(gpu_addr
));
597 amdgpu_ring_write(ring
, 1); /* number of DWs to follow */
598 amdgpu_ring_write(ring
, 0xDEADBEEF);
599 amdgpu_ring_unlock_commit(ring
);
601 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
602 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
603 if (tmp
== 0xDEADBEEF)
608 if (i
< adev
->usec_timeout
) {
609 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring
->idx
, i
);
611 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
615 amdgpu_wb_free(adev
, index
);
621 * cik_sdma_ring_test_ib - test an IB on the DMA engine
623 * @ring: amdgpu_ring structure holding ring information
625 * Test a simple IB in the DMA ring (CIK).
626 * Returns 0 on success, error on failure.
628 static int cik_sdma_ring_test_ib(struct amdgpu_ring
*ring
)
630 struct amdgpu_device
*adev
= ring
->adev
;
632 struct fence
*f
= NULL
;
639 r
= amdgpu_wb_get(adev
, &index
);
641 dev_err(adev
->dev
, "(%d) failed to allocate wb slot\n", r
);
645 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
647 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
648 memset(&ib
, 0, sizeof(ib
));
649 r
= amdgpu_ib_get(ring
, NULL
, 256, &ib
);
651 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r
);
655 ib
.ptr
[0] = SDMA_PACKET(SDMA_OPCODE_WRITE
, SDMA_WRITE_SUB_OPCODE_LINEAR
, 0);
656 ib
.ptr
[1] = lower_32_bits(gpu_addr
);
657 ib
.ptr
[2] = upper_32_bits(gpu_addr
);
659 ib
.ptr
[4] = 0xDEADBEEF;
661 r
= amdgpu_sched_ib_submit_kernel_helper(adev
, ring
, &ib
, 1, NULL
,
662 AMDGPU_FENCE_OWNER_UNDEFINED
,
667 r
= fence_wait(f
, false);
669 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r
);
672 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
673 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
674 if (tmp
== 0xDEADBEEF)
678 if (i
< adev
->usec_timeout
) {
679 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
683 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp
);
689 amdgpu_ib_free(adev
, &ib
);
691 amdgpu_wb_free(adev
, index
);
696 * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
698 * @ib: indirect buffer to fill with commands
699 * @pe: addr of the page entry
700 * @src: src addr to copy from
701 * @count: number of page entries to update
703 * Update PTEs by copying them from the GART using sDMA (CIK).
705 static void cik_sdma_vm_copy_pte(struct amdgpu_ib
*ib
,
706 uint64_t pe
, uint64_t src
,
710 unsigned bytes
= count
* 8;
711 if (bytes
> 0x1FFFF8)
714 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_COPY
,
715 SDMA_WRITE_SUB_OPCODE_LINEAR
, 0);
716 ib
->ptr
[ib
->length_dw
++] = bytes
;
717 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
718 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src
);
719 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src
);
720 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(pe
);
721 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
730 * cik_sdma_vm_write_pages - update PTEs by writing them manually
732 * @ib: indirect buffer to fill with commands
733 * @pe: addr of the page entry
734 * @addr: dst addr to write into pe
735 * @count: number of page entries to update
736 * @incr: increase next addr by incr bytes
737 * @flags: access flags
739 * Update PTEs by writing them manually using sDMA (CIK).
741 static void cik_sdma_vm_write_pte(struct amdgpu_ib
*ib
,
743 uint64_t addr
, unsigned count
,
744 uint32_t incr
, uint32_t flags
)
754 /* for non-physically contiguous pages (system) */
755 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_WRITE
,
756 SDMA_WRITE_SUB_OPCODE_LINEAR
, 0);
757 ib
->ptr
[ib
->length_dw
++] = pe
;
758 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
759 ib
->ptr
[ib
->length_dw
++] = ndw
;
760 for (; ndw
> 0; ndw
-= 2, --count
, pe
+= 8) {
761 if (flags
& AMDGPU_PTE_SYSTEM
) {
762 value
= amdgpu_vm_map_gart(ib
->ring
->adev
, addr
);
763 value
&= 0xFFFFFFFFFFFFF000ULL
;
764 } else if (flags
& AMDGPU_PTE_VALID
) {
771 ib
->ptr
[ib
->length_dw
++] = value
;
772 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
778 * cik_sdma_vm_set_pages - update the page tables using sDMA
780 * @ib: indirect buffer to fill with commands
781 * @pe: addr of the page entry
782 * @addr: dst addr to write into pe
783 * @count: number of page entries to update
784 * @incr: increase next addr by incr bytes
785 * @flags: access flags
787 * Update the page tables using sDMA (CIK).
789 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib
*ib
,
791 uint64_t addr
, unsigned count
,
792 uint32_t incr
, uint32_t flags
)
802 if (flags
& AMDGPU_PTE_VALID
)
807 /* for physically contiguous pages (vram) */
808 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE
, 0, 0);
809 ib
->ptr
[ib
->length_dw
++] = pe
; /* dst addr */
810 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
811 ib
->ptr
[ib
->length_dw
++] = flags
; /* mask */
812 ib
->ptr
[ib
->length_dw
++] = 0;
813 ib
->ptr
[ib
->length_dw
++] = value
; /* value */
814 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
815 ib
->ptr
[ib
->length_dw
++] = incr
; /* increment size */
816 ib
->ptr
[ib
->length_dw
++] = 0;
817 ib
->ptr
[ib
->length_dw
++] = ndw
; /* number of entries */
826 * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
828 * @ib: indirect buffer to fill with padding
831 static void cik_sdma_vm_pad_ib(struct amdgpu_ib
*ib
)
833 struct amdgpu_sdma
*sdma
= amdgpu_get_sdma_instance(ib
->ring
);
837 pad_count
= (8 - (ib
->length_dw
& 0x7)) % 8;
838 for (i
= 0; i
< pad_count
; i
++)
839 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
840 ib
->ptr
[ib
->length_dw
++] =
841 SDMA_PACKET(SDMA_OPCODE_NOP
, 0, 0) |
842 SDMA_NOP_COUNT(pad_count
- 1);
844 ib
->ptr
[ib
->length_dw
++] =
845 SDMA_PACKET(SDMA_OPCODE_NOP
, 0, 0);
849 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
851 * @ring: amdgpu_ring pointer
852 * @vm: amdgpu_vm pointer
854 * Update the page table base and flush the VM TLB
857 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring
*ring
,
858 unsigned vm_id
, uint64_t pd_addr
)
860 u32 extra_bits
= (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
861 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
863 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE
, 0, 0xf000));
865 amdgpu_ring_write(ring
, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ vm_id
));
867 amdgpu_ring_write(ring
, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
+ vm_id
- 8));
869 amdgpu_ring_write(ring
, pd_addr
>> 12);
872 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE
, 0, 0xf000));
873 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
);
874 amdgpu_ring_write(ring
, 1 << vm_id
);
876 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM
, 0, extra_bits
));
877 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
<< 2);
878 amdgpu_ring_write(ring
, 0);
879 amdgpu_ring_write(ring
, 0); /* reference */
880 amdgpu_ring_write(ring
, 0); /* mask */
881 amdgpu_ring_write(ring
, (0xfff << 16) | 10); /* retry count, poll interval */
884 static void cik_enable_sdma_mgcg(struct amdgpu_device
*adev
,
889 if (enable
&& (adev
->cg_flags
& AMDGPU_CG_SUPPORT_SDMA_MGCG
)) {
890 WREG32(mmSDMA0_CLK_CTRL
+ SDMA0_REGISTER_OFFSET
, 0x00000100);
891 WREG32(mmSDMA0_CLK_CTRL
+ SDMA1_REGISTER_OFFSET
, 0x00000100);
893 orig
= data
= RREG32(mmSDMA0_CLK_CTRL
+ SDMA0_REGISTER_OFFSET
);
896 WREG32(mmSDMA0_CLK_CTRL
+ SDMA0_REGISTER_OFFSET
, data
);
898 orig
= data
= RREG32(mmSDMA0_CLK_CTRL
+ SDMA1_REGISTER_OFFSET
);
901 WREG32(mmSDMA0_CLK_CTRL
+ SDMA1_REGISTER_OFFSET
, data
);
905 static void cik_enable_sdma_mgls(struct amdgpu_device
*adev
,
910 if (enable
&& (adev
->cg_flags
& AMDGPU_CG_SUPPORT_SDMA_LS
)) {
911 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
);
914 WREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
, data
);
916 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
);
919 WREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
, data
);
921 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
);
924 WREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
, data
);
926 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
);
929 WREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
, data
);
933 static int cik_sdma_early_init(void *handle
)
935 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
937 cik_sdma_set_ring_funcs(adev
);
938 cik_sdma_set_irq_funcs(adev
);
939 cik_sdma_set_buffer_funcs(adev
);
940 cik_sdma_set_vm_pte_funcs(adev
);
945 static int cik_sdma_sw_init(void *handle
)
947 struct amdgpu_ring
*ring
;
948 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
951 r
= cik_sdma_init_microcode(adev
);
953 DRM_ERROR("Failed to load sdma firmware!\n");
957 /* SDMA trap event */
958 r
= amdgpu_irq_add_id(adev
, 224, &adev
->sdma_trap_irq
);
962 /* SDMA Privileged inst */
963 r
= amdgpu_irq_add_id(adev
, 241, &adev
->sdma_illegal_inst_irq
);
967 /* SDMA Privileged inst */
968 r
= amdgpu_irq_add_id(adev
, 247, &adev
->sdma_illegal_inst_irq
);
972 ring
= &adev
->sdma
[0].ring
;
973 ring
->ring_obj
= NULL
;
975 ring
= &adev
->sdma
[1].ring
;
976 ring
->ring_obj
= NULL
;
978 ring
= &adev
->sdma
[0].ring
;
979 sprintf(ring
->name
, "sdma0");
980 r
= amdgpu_ring_init(adev
, ring
, 256 * 1024,
981 SDMA_PACKET(SDMA_OPCODE_NOP
, 0, 0), 0xf,
982 &adev
->sdma_trap_irq
, AMDGPU_SDMA_IRQ_TRAP0
,
983 AMDGPU_RING_TYPE_SDMA
);
987 ring
= &adev
->sdma
[1].ring
;
988 sprintf(ring
->name
, "sdma1");
989 r
= amdgpu_ring_init(adev
, ring
, 256 * 1024,
990 SDMA_PACKET(SDMA_OPCODE_NOP
, 0, 0), 0xf,
991 &adev
->sdma_trap_irq
, AMDGPU_SDMA_IRQ_TRAP1
,
992 AMDGPU_RING_TYPE_SDMA
);
999 static int cik_sdma_sw_fini(void *handle
)
1001 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1003 amdgpu_ring_fini(&adev
->sdma
[0].ring
);
1004 amdgpu_ring_fini(&adev
->sdma
[1].ring
);
1009 static int cik_sdma_hw_init(void *handle
)
1012 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1014 r
= cik_sdma_start(adev
);
1021 static int cik_sdma_hw_fini(void *handle
)
1023 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1025 cik_sdma_enable(adev
, false);
1030 static int cik_sdma_suspend(void *handle
)
1032 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1034 return cik_sdma_hw_fini(adev
);
1037 static int cik_sdma_resume(void *handle
)
1039 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1041 return cik_sdma_hw_init(adev
);
1044 static bool cik_sdma_is_idle(void *handle
)
1046 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1047 u32 tmp
= RREG32(mmSRBM_STATUS2
);
1049 if (tmp
& (SRBM_STATUS2__SDMA_BUSY_MASK
|
1050 SRBM_STATUS2__SDMA1_BUSY_MASK
))
1056 static int cik_sdma_wait_for_idle(void *handle
)
1060 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1062 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
1063 tmp
= RREG32(mmSRBM_STATUS2
) & (SRBM_STATUS2__SDMA_BUSY_MASK
|
1064 SRBM_STATUS2__SDMA1_BUSY_MASK
);
1073 static void cik_sdma_print_status(void *handle
)
1076 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1078 dev_info(adev
->dev
, "CIK SDMA registers\n");
1079 dev_info(adev
->dev
, " SRBM_STATUS2=0x%08X\n",
1080 RREG32(mmSRBM_STATUS2
));
1081 for (i
= 0; i
< SDMA_MAX_INSTANCE
; i
++) {
1082 dev_info(adev
->dev
, " SDMA%d_STATUS_REG=0x%08X\n",
1083 i
, RREG32(mmSDMA0_STATUS_REG
+ sdma_offsets
[i
]));
1084 dev_info(adev
->dev
, " SDMA%d_ME_CNTL=0x%08X\n",
1085 i
, RREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
]));
1086 dev_info(adev
->dev
, " SDMA%d_CNTL=0x%08X\n",
1087 i
, RREG32(mmSDMA0_CNTL
+ sdma_offsets
[i
]));
1088 dev_info(adev
->dev
, " SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
1089 i
, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL
+ sdma_offsets
[i
]));
1090 dev_info(adev
->dev
, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1091 i
, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
+ sdma_offsets
[i
]));
1092 dev_info(adev
->dev
, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
1093 i
, RREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
]));
1094 dev_info(adev
->dev
, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
1095 i
, RREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
]));
1096 dev_info(adev
->dev
, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
1097 i
, RREG32(mmSDMA0_GFX_RB_RPTR
+ sdma_offsets
[i
]));
1098 dev_info(adev
->dev
, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
1099 i
, RREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
]));
1100 dev_info(adev
->dev
, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1101 i
, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI
+ sdma_offsets
[i
]));
1102 dev_info(adev
->dev
, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1103 i
, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO
+ sdma_offsets
[i
]));
1104 dev_info(adev
->dev
, " SDMA%d_GFX_RB_BASE=0x%08X\n",
1105 i
, RREG32(mmSDMA0_GFX_RB_BASE
+ sdma_offsets
[i
]));
1106 dev_info(adev
->dev
, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1107 i
, RREG32(mmSDMA0_GFX_RB_BASE_HI
+ sdma_offsets
[i
]));
1108 mutex_lock(&adev
->srbm_mutex
);
1109 for (j
= 0; j
< 16; j
++) {
1110 cik_srbm_select(adev
, 0, 0, 0, j
);
1111 dev_info(adev
->dev
, " VM %d:\n", j
);
1112 dev_info(adev
->dev
, " SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n",
1113 RREG32(mmSDMA0_GFX_VIRTUAL_ADDR
+ sdma_offsets
[i
]));
1114 dev_info(adev
->dev
, " SDMA0_GFX_APE1_CNTL=0x%08X\n",
1115 RREG32(mmSDMA0_GFX_APE1_CNTL
+ sdma_offsets
[i
]));
1117 cik_srbm_select(adev
, 0, 0, 0, 0);
1118 mutex_unlock(&adev
->srbm_mutex
);
1122 static int cik_sdma_soft_reset(void *handle
)
1124 u32 srbm_soft_reset
= 0;
1125 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1126 u32 tmp
= RREG32(mmSRBM_STATUS2
);
1128 if (tmp
& SRBM_STATUS2__SDMA_BUSY_MASK
) {
1130 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
);
1131 tmp
|= SDMA0_F32_CNTL__HALT_MASK
;
1132 WREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
, tmp
);
1133 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK
;
1135 if (tmp
& SRBM_STATUS2__SDMA1_BUSY_MASK
) {
1137 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
);
1138 tmp
|= SDMA0_F32_CNTL__HALT_MASK
;
1139 WREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
, tmp
);
1140 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK
;
1143 if (srbm_soft_reset
) {
1144 cik_sdma_print_status((void *)adev
);
1146 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1147 tmp
|= srbm_soft_reset
;
1148 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
1149 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1150 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1154 tmp
&= ~srbm_soft_reset
;
1155 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1156 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1158 /* Wait a little for things to settle down */
1161 cik_sdma_print_status((void *)adev
);
1167 static int cik_sdma_set_trap_irq_state(struct amdgpu_device
*adev
,
1168 struct amdgpu_irq_src
*src
,
1170 enum amdgpu_interrupt_state state
)
1175 case AMDGPU_SDMA_IRQ_TRAP0
:
1177 case AMDGPU_IRQ_STATE_DISABLE
:
1178 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
);
1179 sdma_cntl
&= ~SDMA0_CNTL__TRAP_ENABLE_MASK
;
1180 WREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
, sdma_cntl
);
1182 case AMDGPU_IRQ_STATE_ENABLE
:
1183 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
);
1184 sdma_cntl
|= SDMA0_CNTL__TRAP_ENABLE_MASK
;
1185 WREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
, sdma_cntl
);
1191 case AMDGPU_SDMA_IRQ_TRAP1
:
1193 case AMDGPU_IRQ_STATE_DISABLE
:
1194 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
);
1195 sdma_cntl
&= ~SDMA0_CNTL__TRAP_ENABLE_MASK
;
1196 WREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
, sdma_cntl
);
1198 case AMDGPU_IRQ_STATE_ENABLE
:
1199 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
);
1200 sdma_cntl
|= SDMA0_CNTL__TRAP_ENABLE_MASK
;
1201 WREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
, sdma_cntl
);
1213 static int cik_sdma_process_trap_irq(struct amdgpu_device
*adev
,
1214 struct amdgpu_irq_src
*source
,
1215 struct amdgpu_iv_entry
*entry
)
1217 u8 instance_id
, queue_id
;
1219 instance_id
= (entry
->ring_id
& 0x3) >> 0;
1220 queue_id
= (entry
->ring_id
& 0xc) >> 2;
1221 DRM_DEBUG("IH: SDMA trap\n");
1222 switch (instance_id
) {
1226 amdgpu_fence_process(&adev
->sdma
[0].ring
);
1239 amdgpu_fence_process(&adev
->sdma
[1].ring
);
1254 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device
*adev
,
1255 struct amdgpu_irq_src
*source
,
1256 struct amdgpu_iv_entry
*entry
)
1258 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1259 schedule_work(&adev
->reset_work
);
1263 static int cik_sdma_set_clockgating_state(void *handle
,
1264 enum amd_clockgating_state state
)
1267 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1269 if (state
== AMD_CG_STATE_GATE
)
1272 cik_enable_sdma_mgcg(adev
, gate
);
1273 cik_enable_sdma_mgls(adev
, gate
);
1278 static int cik_sdma_set_powergating_state(void *handle
,
1279 enum amd_powergating_state state
)
1284 const struct amd_ip_funcs cik_sdma_ip_funcs
= {
1285 .early_init
= cik_sdma_early_init
,
1287 .sw_init
= cik_sdma_sw_init
,
1288 .sw_fini
= cik_sdma_sw_fini
,
1289 .hw_init
= cik_sdma_hw_init
,
1290 .hw_fini
= cik_sdma_hw_fini
,
1291 .suspend
= cik_sdma_suspend
,
1292 .resume
= cik_sdma_resume
,
1293 .is_idle
= cik_sdma_is_idle
,
1294 .wait_for_idle
= cik_sdma_wait_for_idle
,
1295 .soft_reset
= cik_sdma_soft_reset
,
1296 .print_status
= cik_sdma_print_status
,
1297 .set_clockgating_state
= cik_sdma_set_clockgating_state
,
1298 .set_powergating_state
= cik_sdma_set_powergating_state
,
1302 * cik_sdma_ring_is_lockup - Check if the DMA engine is locked up
1304 * @ring: amdgpu_ring structure holding ring information
1306 * Check if the async DMA engine is locked up (CIK).
1307 * Returns true if the engine appears to be locked up, false if not.
1309 static bool cik_sdma_ring_is_lockup(struct amdgpu_ring
*ring
)
1312 if (cik_sdma_is_idle(ring
->adev
)) {
1313 amdgpu_ring_lockup_update(ring
);
1316 return amdgpu_ring_test_lockup(ring
);
1319 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs
= {
1320 .get_rptr
= cik_sdma_ring_get_rptr
,
1321 .get_wptr
= cik_sdma_ring_get_wptr
,
1322 .set_wptr
= cik_sdma_ring_set_wptr
,
1324 .emit_ib
= cik_sdma_ring_emit_ib
,
1325 .emit_fence
= cik_sdma_ring_emit_fence
,
1326 .emit_semaphore
= cik_sdma_ring_emit_semaphore
,
1327 .emit_vm_flush
= cik_sdma_ring_emit_vm_flush
,
1328 .emit_hdp_flush
= cik_sdma_ring_emit_hdp_flush
,
1329 .test_ring
= cik_sdma_ring_test_ring
,
1330 .test_ib
= cik_sdma_ring_test_ib
,
1331 .is_lockup
= cik_sdma_ring_is_lockup
,
1332 .insert_nop
= cik_sdma_ring_insert_nop
,
1335 static void cik_sdma_set_ring_funcs(struct amdgpu_device
*adev
)
1337 adev
->sdma
[0].ring
.funcs
= &cik_sdma_ring_funcs
;
1338 adev
->sdma
[1].ring
.funcs
= &cik_sdma_ring_funcs
;
1341 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs
= {
1342 .set
= cik_sdma_set_trap_irq_state
,
1343 .process
= cik_sdma_process_trap_irq
,
1346 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs
= {
1347 .process
= cik_sdma_process_illegal_inst_irq
,
1350 static void cik_sdma_set_irq_funcs(struct amdgpu_device
*adev
)
1352 adev
->sdma_trap_irq
.num_types
= AMDGPU_SDMA_IRQ_LAST
;
1353 adev
->sdma_trap_irq
.funcs
= &cik_sdma_trap_irq_funcs
;
1354 adev
->sdma_illegal_inst_irq
.funcs
= &cik_sdma_illegal_inst_irq_funcs
;
1358 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1360 * @ring: amdgpu_ring structure holding ring information
1361 * @src_offset: src GPU address
1362 * @dst_offset: dst GPU address
1363 * @byte_count: number of bytes to xfer
1365 * Copy GPU buffers using the DMA engine (CIK).
1366 * Used by the amdgpu ttm implementation to move pages if
1367 * registered as the asic copy callback.
1369 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib
*ib
,
1370 uint64_t src_offset
,
1371 uint64_t dst_offset
,
1372 uint32_t byte_count
)
1374 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_COPY
, SDMA_COPY_SUB_OPCODE_LINEAR
, 0);
1375 ib
->ptr
[ib
->length_dw
++] = byte_count
;
1376 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
1377 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src_offset
);
1378 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src_offset
);
1379 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1380 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1384 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1386 * @ring: amdgpu_ring structure holding ring information
1387 * @src_data: value to write to buffer
1388 * @dst_offset: dst GPU address
1389 * @byte_count: number of bytes to xfer
1391 * Fill GPU buffers using the DMA engine (CIK).
1393 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib
*ib
,
1395 uint64_t dst_offset
,
1396 uint32_t byte_count
)
1398 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL
, 0, 0);
1399 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1400 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1401 ib
->ptr
[ib
->length_dw
++] = src_data
;
1402 ib
->ptr
[ib
->length_dw
++] = byte_count
;
1405 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs
= {
1406 .copy_max_bytes
= 0x1fffff,
1408 .emit_copy_buffer
= cik_sdma_emit_copy_buffer
,
1410 .fill_max_bytes
= 0x1fffff,
1412 .emit_fill_buffer
= cik_sdma_emit_fill_buffer
,
1415 static void cik_sdma_set_buffer_funcs(struct amdgpu_device
*adev
)
1417 if (adev
->mman
.buffer_funcs
== NULL
) {
1418 adev
->mman
.buffer_funcs
= &cik_sdma_buffer_funcs
;
1419 adev
->mman
.buffer_funcs_ring
= &adev
->sdma
[0].ring
;
1423 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs
= {
1424 .copy_pte
= cik_sdma_vm_copy_pte
,
1425 .write_pte
= cik_sdma_vm_write_pte
,
1426 .set_pte_pde
= cik_sdma_vm_set_pte_pde
,
1427 .pad_ib
= cik_sdma_vm_pad_ib
,
1430 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device
*adev
)
1432 if (adev
->vm_manager
.vm_pte_funcs
== NULL
) {
1433 adev
->vm_manager
.vm_pte_funcs
= &cik_sdma_vm_pte_funcs
;
1434 adev
->vm_manager
.vm_pte_funcs_ring
= &adev
->sdma
[0].ring
;
1435 adev
->vm_manager
.vm_pte_funcs_ring
->is_pte_ring
= true;